unsigned char pal; // 08 1=PAL 0=NTSC\r
unsigned char sram_reg; // 09 SRAM reg. See SRR_* below\r
unsigned short z80_bank68k; // 0a\r
- unsigned short z80_lastaddr; // this is for Z80 faking\r
- unsigned char pad0;\r
+ unsigned short pad0;\r
+ unsigned char pad1;\r
unsigned char z80_reset; // z80 reset held\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
unsigned short eeprom_addr; // EEPROM address register\r
unsigned char eeprom_cycle; // EEPROM cycle number\r
unsigned char eeprom_slave; // EEPROM slave word for X24C02 and better SRAMs\r
unsigned char eeprom_status;\r
- unsigned char pad1;\r
+ unsigned char pad2;\r
unsigned short dma_xfers; // 18\r
unsigned char eeprom_wb[2]; // EEPROM latch/write buffer\r
unsigned int frame_count; // 1c for movies and idle det\r
Rot_Comp rot_comp;\r
} mcd_state;\r
\r
+// XXX: this will need to be reworked for cart+cd support.\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
+// 32X\r
+#define P32XV_nPAL (1<<15)\r
+#define P32XV_PRI (1<< 7)\r
+#define P32XV_Mx (3<< 0)\r
+\r
+#define P32XV_VBLK (1<<15)\r
+#define P32XV_HBLK (1<<14)\r
+#define P32XV_PEN (1<<13)\r
+#define P32XV_nFEN (1<< 1)\r
+#define P32XV_FS (1<< 0)\r
+\r
+struct Pico32x\r
+{\r
+ unsigned short regs[0x20];\r
+ unsigned short vdp_regs[0x10];\r
+ unsigned char pending_fb;\r
+ unsigned char dirty_pal;\r
+ unsigned char pad[2];\r
+};\r
+\r
+struct Pico32xMem\r
+{\r
+ unsigned char sdram[0x40000];\r
+ unsigned short dram[2][0x20000/2]; // AKA fb\r
+ unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
+ unsigned short pal[0x100];\r
+ unsigned short pal_native[0x100]; // converted to native (for renderer)\r
+};\r
\r
// area.c\r
PICO_INTERNAL void PicoAreaPackCpu(unsigned char *cpu, int is_sub);\r
PICO_INTERNAL void PicoFrameStart(void);\r
void PicoDrawSync(int to, int blank_last_line);\r
void BackFill(int reg7, int sh);\r
-void FinalizeLineRGB555(int sh);\r
+void FinalizeLineRGB555(int sh, int line);\r
extern int DrawScanline;\r
#define MAX_LINE_SPRITES 29\r
extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
void PicoFrameMS(void);\r
void PicoFrameDrawOnlyMS(void);\r
\r
+// 32x/32x.c\r
+extern struct Pico32x Pico32x;\r
+void Pico32xInit(void);\r
+void PicoPower32x(void);\r
+void PicoReset32x(void);\r
+void Pico32xStartup(void);\r
+void PicoUnload32x(void);\r
+void PicoFrame32x(void);\r
+\r
+// 32x/memory.c\r
+struct Pico32xMem *Pico32xMem;\r
+unsigned int PicoRead8_32x(unsigned int a);\r
+unsigned int PicoRead16_32x(unsigned int a);\r
+void PicoWrite8_32x(unsigned int a, unsigned int d);\r
+void PicoWrite16_32x(unsigned int a, unsigned int d);\r
+void PicoMemSetup32x(void);\r
+void Pico32xSwapDRAM(int b);\r
+\r
+// 32x/draw.c\r
+void FinalizeLine32xRGB555(int sh, int line);\r
+\r
/* avoid dependency on newer glibc */\r
static __inline int isspace_(int c)\r
{\r
#define EL_IDLE 0x00010000 /* idle loop det. */\r
#define EL_CDREGS 0x00020000 /* MCD: register access */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
+#define EL_32X 0x00080000\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r