\r
// ----------------------- SH2 CPU -----------------------\r
\r
-#include "cpu/sh2mame/sh2.h"\r
+#include "cpu/sh2/sh2.h"\r
\r
extern SH2 sh2s[2];\r
#define msh2 sh2s[0]\r
#define ssh2 sh2s[1]\r
\r
-#define ash2_end_run(after) if (sh2_icount > (after)) sh2_icount = after\r
-#define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r
+#define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
+#define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r
\r
#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
#define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r
\r
+#define sh2_set_gbr(c, v) \\r
+ { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
+#define sh2_set_vbr(c, v) \\r
+ { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
\r
// 32X\r
#define P32XS_FM (1<<15)\r
+#define P32XS_REN (1<< 7)\r
+#define P32XS_nRES (1<< 1)\r
+#define P32XS_ADEN (1<< 0)\r
#define P32XS2_ADEN (1<< 9)\r
#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
#define P32XS_68S (1<< 2)\r
extern areaclose *areaClose;\r
\r
// cart.c\r
+void Byteswap(void *dst, const void *src, int len);\r
extern void (*PicoCartMemSetup)(void);\r
extern void (*PicoCartUnloadHook)(void);\r
\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
void p32x_update_irls(void);\r
+void p32x_reset_sh2s(void);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r