#ifndef DRC_SH2\r
# define sh2_end_run(sh2, after_) do { \\r
if ((sh2)->icount > (after_)) { \\r
- (sh2)->cycles_timeslice -= (sh2)->icount; \\r
+ (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
(sh2)->icount = after_; \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
-# define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
int left_ = (signed int)(sh2)->sr >> 12; \\r
if (left_ > (after_)) { \\r
- (sh2)->cycles_timeslice -= left_; \\r
+ (sh2)->cycles_timeslice -= left_ - (after_); \\r
(sh2)->sr &= 0xfff; \\r
(sh2)->sr |= (after_) << 12; \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
-# define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
+# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
+#define sh2_cycles_done_t(sh2) \\r
+ ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
#define sh2_cycles_done_m68k(sh2) \\r
((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
\r
#define P32XV_nFEN (1<< 1)\r
#define P32XV_FS (1<< 0)\r
\r
-#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_RTP (1<<7) // PWM control\r
+#define P32XP_FULL (1<<15) // PWM pulse\r
#define P32XP_EMPTY (1<<14)\r
\r
#define P32XF_68KCPOLL (1 << 0)\r
#define P32XF_68KVPOLL (1 << 1)\r
-#define P32XF_PWM_PEND (1 << 6)\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
#define SH2_DRCBLK_DA_SHIFT 1\r
\r
+#define SH2_READ_SHIFT 25\r
#define SH2_WRITE_SHIFT 25\r
\r
struct Pico32x\r
unsigned char sh2irqi[2]; // individual\r
unsigned int sh2irqs; // common irqs\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
- unsigned int dmac_ptr;\r
- unsigned int pwm_irq_sample_cnt;\r
+ unsigned int dmac0_fifo_ptr;\r
+ unsigned int pad;\r
unsigned char comm_dirty_68k;\r
unsigned char comm_dirty_sh2;\r
- unsigned short pad;\r
- unsigned int reserved[8];\r
+ unsigned char pwm_irq_cnt;\r
+ unsigned char pad1;\r
+ unsigned short pwm_p[2]; // pwm pos in fifo\r
+ unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
+ unsigned int reserved[6];\r
};\r
\r
struct Pico32xMem\r
unsigned char m68k_rom[0x100];\r
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
};\r
- unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
#ifdef DRC_SH2\r
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
#endif\r
unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
- unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
+ signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
};\r
\r
// area.c\r
unsigned int PicoRead16_io(unsigned int a);\r
void PicoWrite8_io(unsigned int a, unsigned int d);\r
void PicoWrite16_io(unsigned int a, unsigned int d);\r
+void p32x_dreq1_trigger(void);\r
\r
// pico/memory.c\r
PICO_INTERNAL void PicoMemSetupPico(void);\r
void Pico32xStateLoaded(int is_early);\r
void p32x_sync_sh2s(unsigned int m68k_target);\r
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
-void p32x_update_irls(SH2 *active_sh2);\r
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
void p32x_reset_sh2s(void);\r
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
extern int Pico32xDrawMode;\r
\r
// 32x/pwm.c\r
-unsigned int p32x_pwm_read16(unsigned int a);\r
-void p32x_pwm_write16(unsigned int a, unsigned int d);\r
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
+ unsigned int m68k_cycles);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d,\r
+ SH2 *sh2, unsigned int m68k_cycles);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
-void p32x_timers_do(unsigned int cycles);\r
-void p32x_timers_recalc(void);\r
-void p32x_pwm_schedule(unsigned int now);\r
+void p32x_pwm_ctl_changed(void);\r
+void p32x_pwm_schedule(unsigned int m68k_now);\r
void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_irq_event(unsigned int m68k_now);\r
+void p32x_pwm_state_loaded(void);\r
+\r
+// 32x/sh2soc.c\r
+void p32x_dreq0_trigger(void);\r
+void p32x_dreq1_trigger(void);\r
+void p32x_timers_recalc(void);\r
+void p32x_timers_do(unsigned int m68k_slice);\r
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
+void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
#else\r
#define Pico32xInit()\r
#define PicoPower32x()\r
\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
-#define EL_LOGMASK 0\r
+# ifdef __x86_64__ // HACK\r
+# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
+# else\r
+# define EL_LOGMASK (EL_STATUS)\r
+# endif\r
#endif\r
\r
#define EL_HVCNT 0x00000001 /* hv counter reads */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
+#define EL_32XP 0x00200000 /* 32X peripherals */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
notaz.gp2x.de / picodrive.git / blobdiff