// Pico Library - Internal Header File\r
\r
// (c) Copyright 2004 Dave, All rights reserved.\r
-// (c) Copyright 2006-2008 Grazvydas "notaz" Ignotas, all rights reserved.\r
+// (c) Copyright 2006-2009 Grazvydas "notaz" Ignotas, all rights reserved.\r
// Free for non-commercial use.\r
\r
// For commercial use, separate licencing terms must be obtained.\r
typedef unsigned char (z80_read_f)(unsigned short a);\r
typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
\r
+// ----------------------- SH2 CPU -----------------------\r
+\r
+#include "cpu/sh2mame/sh2.h"\r
+\r
+SH2 msh2, ssh2;\r
+#define ash2_end_run(after) sh2_icount = after\r
+#define ash2_cycles_done() (10000 - sh2_icount) // HACK\r
+\r
+#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
+#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
+#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
+#define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
unsigned short z80_bank68k; // 0a\r
unsigned short pad0;\r
unsigned char pad1;\r
- unsigned char z80_reset; // z80 reset held\r
+ unsigned char z80_reset; // 0f z80 reset held\r
unsigned char padDelay[2]; // 10 gamepad phase time outs, so we count a delay\r
unsigned short eeprom_addr; // EEPROM address register\r
unsigned char eeprom_cycle; // EEPROM cycle number\r
#define Pico_mcd ((mcd_state *)Pico.rom)\r
\r
// 32X\r
-#define P32XV_nPAL (1<<15)\r
-#define P32XV_PRI (1<< 7)\r
-#define P32XV_Mx (3<< 0)\r
-\r
-#define P32XV_VBLK (1<<15)\r
-#define P32XV_HBLK (1<<14)\r
-#define P32XV_PEN (1<<13)\r
-#define P32XV_nFEN (1<< 1)\r
-#define P32XV_FS (1<< 0)\r
+#define P32XS_FM (1<<15)\r
+#define P32XS2_ADEN (1<< 9)\r
+#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
+#define P32XS_68S (1<< 2)\r
+#define P32XS_DMA (1<< 1)\r
+#define P32XS_RV (1<< 0)\r
+\r
+#define P32XV_nPAL (1<<15) // VDP\r
+#define P32XV_PRI (1<< 7)\r
+#define P32XV_Mx (3<< 0) // display mode mask\r
+\r
+#define P32XV_VBLK (1<<15)\r
+#define P32XV_HBLK (1<<14)\r
+#define P32XV_PEN (1<<13)\r
+#define P32XV_nFEN (1<< 1)\r
+#define P32XV_FS (1<< 0)\r
+\r
+#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_EMPTY (1<<14)\r
+\r
+#define P32XF_68KPOLL (1 << 0)\r
+#define P32XF_MSH2POLL (1 << 1)\r
+#define P32XF_SSH2POLL (1 << 2)\r
+#define P32XF_68KVPOLL (1 << 3)\r
+#define P32XF_MSH2VPOLL (1 << 4)\r
+#define P32XF_SSH2VPOLL (1 << 5)\r
+\r
+#define P32XI_VRES (1 << 14/2) // IRL/2\r
+#define P32XI_VINT (1 << 12/2)\r
+#define P32XI_HINT (1 << 10/2)\r
+#define P32XI_CMD (1 << 8/2)\r
+#define P32XI_PWM (1 << 6/2)\r
+\r
+// real one is 4*2, but we use more because we don't lockstep\r
+#define DMAC_FIFO_LEN (4*4)\r
+#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
struct Pico32x\r
{\r
unsigned short regs[0x20];\r
unsigned short vdp_regs[0x10];\r
+ unsigned short sh2_regs[3];\r
unsigned char pending_fb;\r
unsigned char dirty_pal;\r
- unsigned char pad[2];\r
+ unsigned int emu_flags;\r
+ unsigned char sh2irq_mask[2];\r
+ unsigned char sh2irqi[2]; // individual\r
+ unsigned int sh2irqs; // common irqs\r
+ unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
+ unsigned int dmac_ptr;\r
+ unsigned int pwm_irq_sample_cnt;\r
};\r
\r
struct Pico32xMem\r
{\r
unsigned char sdram[0x40000];\r
- unsigned short dram[2][0x20000/2]; // AKA fb\r
- unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
+ unsigned short dram[2][0x20000/2]; // AKA fb\r
+ unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
+ unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
+ unsigned char sh2_rom_m[0x800];\r
+ unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
- unsigned short pal_native[0x100]; // converted to native (for renderer)\r
+ unsigned short pal_native[0x100]; // converted to native (for renderer)\r
+ unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
+ signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
};\r
\r
// area.c\r
\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
-PICO_INTERNAL_ASM void PicoMemRemapCD(int r3);\r
-PICO_INTERNAL_ASM void PicoMemResetCDdecode(int r3);\r
+void PicoMemStateLoaded(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
extern struct PicoSRAM SRam;\r
extern int PicoPadInt[2];\r
extern int emustatus;\r
+extern int scanlines_total;\r
extern void (*PicoResetHook)(void);\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int CheckDMA(void);\r
void Pico32xStartup(void);\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
+void p32x_update_irls(void);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
void PicoWrite16_32x(unsigned int a, unsigned int d);\r
void PicoMemSetup32x(void);\r
void Pico32xSwapDRAM(int b);\r
+void p32x_poll_event(int cpu_mask, int is_vdp);\r
\r
// 32x/draw.c\r
void FinalizeLine32xRGB555(int sh, int line);\r
\r
+// 32x/pwm.c\r
+unsigned int p32x_pwm_read16(unsigned int a);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d);\r
+void p32x_pwm_refresh(void);\r
+void p32x_pwm_irq_check(int new_line);\r
+void p32x_pwm_update(int *buf32, int length, int stereo);\r
+extern int pwm_frame_smp_cnt;\r
+\r
/* avoid dependency on newer glibc */\r
static __inline int isspace_(int c)\r
{\r
#define EL_CDREGS 0x00020000 /* MCD: register access */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
+#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
notaz.gp2x.de / picodrive.git / blobdiff