revive GP2X build, update

[picodrive.git] / pico / pico_int.h

diff --git a/pico/pico_int.h b/pico/pico_int.h
index 53c6f4e..6e4917b 100644 (file)
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -251,6 +251,7 @@ extern SH2 sh2s[2];
   } \\r
 } while (0)\r
 # define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
 # define sh2_pc(sh2) (sh2)->ppc\r
 #else\r
 # define sh2_end_run(sh2, after_) do { \\r
@@ -262,6 +263,7 @@ extern SH2 sh2s[2];
   } \\r
 } while (0)\r
 # define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
 # define sh2_pc(sh2) (sh2)->pc\r
 #endif\r
 \r
@@ -281,6 +283,9 @@ extern SH2 sh2s[2];
 #define sh2_set_vbr(c, v) \\r
   { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
 \r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+       elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
+\r
 // ---------------------------------------------------------\r
 \r
 // main oscillator clock which controls timing\r
@@ -348,7 +353,7 @@ struct Pico
   unsigned short vsram[0x40];  // 0x22180\r
 \r
   unsigned char *rom;          // 0x22200\r
-  unsigned int romsize;        // 0x22204\r
+  unsigned int romsize;        // 0x22204 (on 32bits)\r
 \r
   struct PicoMisc m;\r
   struct PicoVideo video;\r
@@ -436,6 +441,7 @@ typedef struct
                unsigned char pcm_ram[0x10000];\r
                unsigned char pcm_ram_b[0x10][0x1000];\r
        };\r
+       // FIXME: should be short\r
        unsigned char s68k_regs[0x200];                 // 110000: GA, not CPU regs\r
        unsigned char bram[0x2000];                     // 110200: 8K\r
        struct mcd_misc m;                              // 112200: misc\r
@@ -477,8 +483,9 @@ typedef struct
 #define P32XP_FULL  (1<<15) // PWM pulse\r
 #define P32XP_EMPTY (1<<14)\r
 \r
-#define P32XF_68KCPOLL  (1 << 0)\r
-#define P32XF_68KVPOLL  (1 << 1)\r
+#define P32XF_68KCPOLL   (1 << 0)\r
+#define P32XF_68KVPOLL   (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
 \r
 #define P32XI_VRES (1 << 14/2) // IRL/2\r
 #define P32XI_VINT (1 << 12/2)\r
@@ -489,8 +496,7 @@ typedef struct
 // peripheral reg access\r
 #define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
 \r
-// real one is 4*2, but we use more because we don't lockstep\r
-#define DMAC_FIFO_LEN (4*4)\r
+#define DMAC_FIFO_LEN (4*2)\r
 #define PWM_BUFF_LEN 1024 // in one channel samples\r
 \r
 #define SH2_DRCBLK_RAM_SHIFT 1\r
@@ -511,9 +517,10 @@ struct Pico32x
   unsigned char sh2irqi[2];      // individual\r
   unsigned int sh2irqs;          // common irqs\r
   unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
+  unsigned int pad[4];\r
   unsigned int dmac0_fifo_ptr;\r
   unsigned short vdp_fbcr_fake;\r
-  unsigned short pad;\r
+  unsigned short pad2;\r
   unsigned char comm_dirty_68k;\r
   unsigned char comm_dirty_sh2;\r
   unsigned char pwm_irq_cnt;\r
@@ -537,12 +544,19 @@ struct Pico32xMem
 #ifdef DRC_SH2\r
   unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
 #endif\r
-  unsigned char  sh2_rom_m[0x800];\r
-  unsigned char  sh2_rom_s[0x400];\r
+  union {\r
+    unsigned char  b[0x800];\r
+    unsigned short w[0x800/2];\r
+  } sh2_rom_m;\r
+  union {\r
+    unsigned char  b[0x400];\r
+    unsigned short w[0x400/2];\r
+  } sh2_rom_s;\r
   unsigned short pal[0x100];\r
   unsigned short pal_native[0x100];     // converted to native (for renderer)\r
   signed short   pwm[2*PWM_BUFF_LEN];   // PWM buffer for current frame\r
-  signed short   pwm_fifo[2][4];        // [0] - current, others - fifo entries\r
+  signed short   pwm_current[2];        // current converted samples\r
+  unsigned short pwm_fifo[2][4];        // [0] - current raw, others - fifo entries\r
 };\r
 \r
 // area.c\r
@@ -593,7 +607,6 @@ unsigned int PicoRead8_io(unsigned int a);
 unsigned int PicoRead16_io(unsigned int a);\r
 void PicoWrite8_io(unsigned int a, unsigned int d);\r
 void PicoWrite16_io(unsigned int a, unsigned int d);\r
-void p32x_dreq1_trigger(void);\r
 \r
 // pico/memory.c\r
 PICO_INTERNAL void PicoMemSetupPico(void);\r
@@ -744,6 +757,7 @@ extern struct Pico32x Pico32x;
 enum p32x_event {\r
   P32X_EVENT_PWM,\r
   P32X_EVENT_FILLEND,\r
+  P32X_EVENT_HINT,\r
   P32X_EVENT_COUNT,\r
 };\r
 extern unsigned int event_times[P32X_EVENT_COUNT];\r
@@ -758,9 +772,12 @@ void Pico32xStateLoaded(int is_early);
 void p32x_sync_sh2s(unsigned int m68k_target);\r
 void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
 void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
 void p32x_reset_sh2s(void);\r
 void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
 void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
 \r
 // 32x/memory.c\r
 struct Pico32xMem *Pico32xMem;\r
@@ -797,6 +814,7 @@ void p32x_pwm_update(int *buf32, int length, int stereo);
 void p32x_pwm_ctl_changed(void);\r
 void p32x_pwm_schedule(unsigned int m68k_now);\r
 void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
 void p32x_pwm_irq_event(unsigned int m68k_now);\r
 void p32x_pwm_state_loaded(void);\r
 \r