#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
-#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
+#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
+#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
-#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
+#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
#define SekSr PicoCpuFM68k.sr\r
+#define SekSrS68k PicoCpuFS68k.sr\r
#define SekSetStop(x) { \\r
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
-#define SekDar(x) PicoCpuMM68k.dar[x]\r
-#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
+#define SekDar(x) PicoCpuMM68k.dar[x]\r
+#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
+#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMM68k.stopped=0; \\r
#ifndef DRC_SH2\r
# define sh2_end_run(sh2, after_) do { \\r
if ((sh2)->icount > (after_)) { \\r
- (sh2)->cycles_timeslice -= (sh2)->icount; \\r
+ (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
(sh2)->icount = after_; \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
-# define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
+# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
int left_ = (signed int)(sh2)->sr >> 12; \\r
if (left_ > (after_)) { \\r
- (sh2)->cycles_timeslice -= left_; \\r
+ (sh2)->cycles_timeslice -= left_ - (after_); \\r
(sh2)->sr &= 0xfff; \\r
(sh2)->sr |= (after_) << 12; \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
-# define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
+# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
+#define sh2_cycles_done_t(sh2) \\r
+ ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
#define sh2_cycles_done_m68k(sh2) \\r
((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
\r
#define sh2_set_vbr(c, v) \\r
{ if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+ elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
unsigned short vsram[0x40]; // 0x22180\r
\r
unsigned char *rom; // 0x22200\r
- unsigned int romsize; // 0x22204\r
+ unsigned int romsize; // 0x22204 (on 32bits)\r
\r
struct PicoMisc m;\r
struct PicoVideo video;\r
unsigned char pcm_ram[0x10000];\r
unsigned char pcm_ram_b[0x10][0x1000];\r
};\r
+ // FIXME: should be short\r
unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
unsigned char bram[0x2000]; // 110200: 8K\r
struct mcd_misc m; // 112200: misc\r
#define P32XV_nFEN (1<< 1)\r
#define P32XV_FS (1<< 0)\r
\r
-#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_RTP (1<<7) // PWM control\r
+#define P32XP_FULL (1<<15) // PWM pulse\r
#define P32XP_EMPTY (1<<14)\r
\r
-#define P32XF_68KCPOLL (1 << 0)\r
-#define P32XF_68KVPOLL (1 << 1)\r
-#define P32XF_PWM_PEND (1 << 6)\r
+#define P32XF_68KCPOLL (1 << 0)\r
+#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
// peripheral reg access\r
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
\r
-// real one is 4*2, but we use more because we don't lockstep\r
-#define DMAC_FIFO_LEN (4*4)\r
+#define DMAC_FIFO_LEN (4*2)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
#define SH2_DRCBLK_DA_SHIFT 1\r
\r
+#define SH2_READ_SHIFT 25\r
#define SH2_WRITE_SHIFT 25\r
\r
struct Pico32x\r
unsigned char sh2irqi[2]; // individual\r
unsigned int sh2irqs; // common irqs\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
- unsigned int dmac_ptr;\r
- unsigned int pwm_irq_sample_cnt;\r
+ unsigned int pad[4];\r
+ unsigned int dmac0_fifo_ptr;\r
+ unsigned short vdp_fbcr_fake;\r
+ unsigned short pad2;\r
unsigned char comm_dirty_68k;\r
unsigned char comm_dirty_sh2;\r
- unsigned short pad;\r
- unsigned int reserved[8];\r
+ unsigned char pwm_irq_cnt;\r
+ unsigned char pad1;\r
+ unsigned short pwm_p[2]; // pwm pos in fifo\r
+ unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
+ unsigned int reserved[6];\r
};\r
\r
struct Pico32xMem\r
unsigned char m68k_rom[0x100];\r
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
};\r
- unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
#ifdef DRC_SH2\r
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
#endif\r
- unsigned char sh2_rom_m[0x800];\r
- unsigned char sh2_rom_s[0x400];\r
+ union {\r
+ unsigned char b[0x800];\r
+ unsigned short w[0x800/2];\r
+ } sh2_rom_m;\r
+ union {\r
+ unsigned char b[0x400];\r
+ unsigned short w[0x400/2];\r
+ } sh2_rom_s;\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
- unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
+ signed short pwm_current[2]; // current converted samples\r
+ unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
};\r
\r
// area.c\r
void SekStepM68k(void);\r
void SekInitIdleDet(void);\r
void SekFinishIdleDet(void);\r
+#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
+void SekTrace(int is_s68k);\r
+#else\r
+#define SekTrace(x)\r
+#endif\r
\r
// cd/sek.c\r
PICO_INTERNAL void SekInitS68k(void);\r
enum p32x_event {\r
P32X_EVENT_PWM,\r
P32X_EVENT_FILLEND,\r
+ P32X_EVENT_HINT,\r
P32X_EVENT_COUNT,\r
};\r
extern unsigned int event_times[P32X_EVENT_COUNT];\r
void Pico32xStateLoaded(int is_early);\r
void p32x_sync_sh2s(unsigned int m68k_target);\r
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
-void p32x_update_irls(SH2 *active_sh2);\r
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
void p32x_reset_sh2s(void);\r
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
extern int Pico32xDrawMode;\r
\r
// 32x/pwm.c\r
-unsigned int p32x_pwm_read16(unsigned int a);\r
-void p32x_pwm_write16(unsigned int a, unsigned int d);\r
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
+ unsigned int m68k_cycles);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d,\r
+ SH2 *sh2, unsigned int m68k_cycles);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
-void p32x_timers_do(unsigned int cycles);\r
-void p32x_timers_recalc(void);\r
-void p32x_pwm_schedule(unsigned int now);\r
+void p32x_pwm_ctl_changed(void);\r
+void p32x_pwm_schedule(unsigned int m68k_now);\r
void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
+void p32x_pwm_irq_event(unsigned int m68k_now);\r
+void p32x_pwm_state_loaded(void);\r
+\r
+// 32x/sh2soc.c\r
+void p32x_dreq0_trigger(void);\r
+void p32x_dreq1_trigger(void);\r
+void p32x_timers_recalc(void);\r
+void p32x_timers_do(unsigned int m68k_slice);\r
+void sh2_peripheral_reset(SH2 *sh2);\r
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
+void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
#else\r
#define Pico32xInit()\r
#define PicoPower32x()\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
+#define EL_32XP 0x00200000 /* 32X peripherals */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r