32x drc functional on ARM, random adjustments

[picodrive.git] / pico / pico_int.h

diff --git a/pico/pico_int.h b/pico/pico_int.h
index b84b131..838af54 100644 (file)
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -237,20 +237,34 @@ typedef void (z80_write_f)(unsigned int a, unsigned char data);
 \r
 // ----------------------- SH2 CPU -----------------------\r
 \r
-#include "cpu/sh2mame/sh2.h"\r
+#include "cpu/sh2/sh2.h"\r
 \r
 extern SH2 sh2s[2];\r
 #define msh2 sh2s[0]\r
 #define ssh2 sh2s[1]\r
 \r
-#define ash2_end_run(after) if (sh2_icount > (after)) sh2_icount = after\r
-#define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r
+#ifndef DRC_SH2\r
+# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
+# define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r
+#else\r
+# define ash2_end_run(after) { \\r
+   if ((sh2->sr >> 12) > (after)) \\r
+     { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r
+}\r
+# define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))\r
+#endif\r
 \r
-#define sh2_pc(c)     (c) ? ssh2.ppc : msh2.ppc\r
+//#define sh2_pc(c)     (c) ? ssh2.ppc : msh2.ppc\r
+#define sh2_pc(c)     (c) ? ssh2.pc : msh2.pc\r
 #define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
 #define sh2_gbr(c)    (c) ? ssh2.gbr : msh2.gbr\r
 #define sh2_vbr(c)    (c) ? ssh2.vbr : msh2.vbr\r
-#define sh2_sr(c)     (c) ? ssh2.sr : msh2.sr\r
+#define sh2_sr(c)   (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
+\r
+#define sh2_set_gbr(c, v) \\r
+  { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
+#define sh2_set_vbr(c, v) \\r
+  { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
 \r
 // ---------------------------------------------------------\r
 \r
@@ -416,6 +430,9 @@ typedef struct
 \r
 // 32X\r
 #define P32XS_FM    (1<<15)\r
+#define P32XS_REN   (1<< 7)\r
+#define P32XS_nRES  (1<< 1)\r
+#define P32XS_ADEN  (1<< 0)\r
 #define P32XS2_ADEN (1<< 9)\r
 #define P32XS_FULL  (1<< 7) // DREQ FIFO full\r
 #define P32XS_68S   (1<< 2)\r
@@ -455,6 +472,9 @@ typedef struct
 #define DMAC_FIFO_LEN (4*4)\r
 #define PWM_BUFF_LEN 1024 // in one channel samples\r
 \r
+#define SH2_DRCBLK_RAM_SHIFT 1\r
+#define SH2_DRCBLK_DA_SHIFT  1\r
+\r
 struct Pico32x\r
 {\r
   unsigned short regs[0x20];\r
@@ -474,9 +494,15 @@ struct Pico32x
 struct Pico32xMem\r
 {\r
   unsigned char  sdram[0x40000];\r
+#ifdef DRC_SH2\r
+  unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
+#endif\r
   unsigned short dram[2][0x20000/2];    // AKA fb\r
   unsigned char  m68k_rom[0x10000];     // 0x100; using M68K_BANK_SIZE\r
   unsigned char  data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
+#ifdef DRC_SH2\r
+  unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
+#endif\r
   unsigned char  sh2_rom_m[0x800];\r
   unsigned char  sh2_rom_s[0x400];\r
   unsigned short pal[0x100];\r
@@ -514,6 +540,7 @@ extern areaseek *areaSeek;
 extern areaclose *areaClose;\r
 \r
 // cart.c\r
+void Byteswap(void *dst, const void *src, int len);\r
 extern void (*PicoCartMemSetup)(void);\r
 extern void (*PicoCartUnloadHook)(void);\r
 \r
@@ -680,6 +707,7 @@ void Pico32xStartup(void);
 void PicoUnload32x(void);\r
 void PicoFrame32x(void);\r
 void p32x_update_irls(void);\r
+void p32x_reset_sh2s(void);\r
 \r
 // 32x/memory.c\r
 struct Pico32xMem *Pico32xMem;\r
@@ -708,6 +736,10 @@ static __inline int isspace_(int c)
        return (0x09 <= c && c <= 0x0d) || c == ' ';\r
 }\r
 \r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
+#endif\r
+\r
 // emulation event logging\r
 #ifndef EL_LOGMASK\r
 #define EL_LOGMASK 0\r
@@ -757,10 +789,10 @@ extern void lprintf(const char *fmt, ...);
 #define cdprintf(x...)\r
 #endif\r
 \r
-#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r
-#define MEMH_FUNC __attribute__((aligned(4)))\r
+#ifdef __i386__\r
+#define REGPARM(x) __attribute__((regparm(x)))\r
 #else\r
-#define MEMH_FUNC\r
+#define REGPARM(x)\r
 #endif\r
 \r
 #ifdef __GNUC__\r