#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
+#define SekDar(x) PicoCpuCM68k.d[x]\r
+#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
+#define SekIrqLevel PicoCpuCM68k.irq\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
+#define SekDar(x) PicoCpuFM68k.dreg[x].D\r
+#define SekSr PicoCpuFM68k.sr\r
#define SekSetStop(x) { \\r
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
#define SekShouldInterrupt fm68k_would_interrupt()\r
\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
+#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
+#define SekDar(x) PicoCpuMM68k.dar[x]\r
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMM68k.stopped=0; \\r
m68k_set_irq(irq); \\r
m68k_set_context(oldcontext); \\r
}\r
+#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
\r
#endif\r
#endif // EMU_M68K\r
\r
#include "cpu/sh2mame/sh2.h"\r
\r
-SH2 msh2, ssh2;\r
+extern SH2 sh2s[2];\r
+#define msh2 sh2s[0]\r
+#define ssh2 sh2s[1]\r
+\r
#define ash2_end_run(after) if (sh2_icount > (after)) sh2_icount = after\r
#define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r
\r
#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
#define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r
\r
+#define sh2_set_gbr(c, v) \\r
+ { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
+#define sh2_set_vbr(c, v) \\r
+ { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
\r
// 32X\r
#define P32XS_FM (1<<15)\r
+#define P32XS_REN (1<< 7)\r
+#define P32XS_nRES (1<< 1)\r
+#define P32XS_ADEN (1<< 0)\r
#define P32XS2_ADEN (1<< 9)\r
#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
#define P32XS_68S (1<< 2)\r
#define P32XI_CMD (1 << 8/2)\r
#define P32XI_PWM (1 << 6/2)\r
\r
+// peripheral reg access\r
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
+\r
// real one is 4*2, but we use more because we don't lockstep\r
#define DMAC_FIFO_LEN (4*4)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
extern areaclose *areaClose;\r
\r
// cart.c\r
+void Byteswap(void *dst, const void *src, int len);\r
extern void (*PicoCartMemSetup)(void);\r
extern void (*PicoCartUnloadHook)(void);\r
\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
void p32x_update_irls(void);\r
+void p32x_reset_sh2s(void);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
// 32x/pwm.c\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
-void p32x_pwm_refresh(void);\r
-void p32x_pwm_irq_check(int new_line);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
+void p32x_timers_do(int new_line);\r
+void p32x_timers_recalc(void);\r
extern int pwm_frame_smp_cnt;\r
\r
/* avoid dependency on newer glibc */\r