} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
#define sh2_set_vbr(c, v) \\r
{ if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+ elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
unsigned short vsram[0x40]; // 0x22180\r
\r
unsigned char *rom; // 0x22200\r
- unsigned int romsize; // 0x22204\r
+ unsigned int romsize; // 0x22204 (on 32bits)\r
\r
struct PicoMisc m;\r
struct PicoVideo video;\r
#define P32XP_FULL (1<<15) // PWM pulse\r
#define P32XP_EMPTY (1<<14)\r
\r
-#define P32XF_68KCPOLL (1 << 0)\r
-#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_68KCPOLL (1 << 0)\r
+#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
unsigned int PicoRead16_io(unsigned int a);\r
void PicoWrite8_io(unsigned int a, unsigned int d);\r
void PicoWrite16_io(unsigned int a, unsigned int d);\r
-void p32x_dreq1_trigger(void);\r
\r
// pico/memory.c\r
PICO_INTERNAL void PicoMemSetupPico(void);\r
enum p32x_event {\r
P32X_EVENT_PWM,\r
P32X_EVENT_FILLEND,\r
+ P32X_EVENT_HINT,\r
P32X_EVENT_COUNT,\r
};\r
extern unsigned int event_times[P32X_EVENT_COUNT];\r
void p32x_sync_sh2s(unsigned int m68k_target);\r
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
void p32x_reset_sh2s(void);\r
void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
void p32x_pwm_ctl_changed(void);\r
void p32x_pwm_schedule(unsigned int m68k_now);\r
void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
void p32x_pwm_irq_event(unsigned int m68k_now);\r
void p32x_pwm_state_loaded(void);\r
\r