#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
+#define SekDar(x) PicoCpuCM68k.d[x]\r
+#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
#define SekShouldInterrupt (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
+#define SekIrqLevel PicoCpuCM68k.irq\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
+#define SekDar(x) PicoCpuFM68k.dreg[x].D\r
+#define SekSr PicoCpuFM68k.sr\r
#define SekSetStop(x) { \\r
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
#define SekShouldInterrupt fm68k_would_interrupt()\r
\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
+#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
#ifdef EMU_M68K\r
#define EMU_CORE_DEBUG\r
#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
+#define SekDar(x) PicoCpuMM68k.dar[x]\r
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMM68k.stopped=0; \\r
m68k_set_irq(irq); \\r
m68k_set_context(oldcontext); \\r
}\r
+#define SekIrqLevel (PicoCpuMM68k.int_level >> 8)\r
\r
#endif\r
#endif // EMU_M68K\r
\r
#define cycles_68k_to_z80(x) ((x)*957 >> 11)\r
\r
-#define Z80_MEM_SHIFT 13\r
-extern unsigned long z80_read_map [0x10000 >> Z80_MEM_SHIFT];\r
-extern unsigned long z80_write_map[0x10000 >> Z80_MEM_SHIFT];\r
-typedef unsigned char (z80_read_f)(unsigned short a);\r
-typedef void (z80_write_f)(unsigned int a, unsigned char data);\r
-\r
// ----------------------- SH2 CPU -----------------------\r
\r
-#include "cpu/sh2mame/sh2.h"\r
+#include "cpu/sh2/sh2.h"\r
+\r
+extern SH2 sh2s[2];\r
+#define msh2 sh2s[0]\r
+#define ssh2 sh2s[1]\r
\r
-SH2 msh2, ssh2;\r
-#define ash2_end_run(after) sh2_icount = after\r
+#ifndef DRC_SH2\r
+# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
+# define ash2_cycles_done() (sh2->cycles_aim - sh2->icount)\r
+#else\r
+# define ash2_end_run(after) { \\r
+ if ((sh2->sr >> 12) > (after)) \\r
+ { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r
+}\r
+# define ash2_cycles_done() (sh2->cycles_aim - (sh2->sr >> 12))\r
+#endif\r
\r
-#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+#define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
-#define sh2_sr(c) (c) ? ssh2.sr : msh2.sr\r
+#define sh2_sr(c) (((c) ? ssh2.sr : msh2.sr) & 0xfff)\r
+\r
+#define sh2_set_gbr(c, v) \\r
+ { if (c) ssh2.gbr = v; else msh2.gbr = v; }\r
+#define sh2_set_vbr(c, v) \\r
+ { if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
// ---------------------------------------------------------\r
\r
\r
// 32X\r
#define P32XS_FM (1<<15)\r
+#define P32XS_REN (1<< 7)\r
+#define P32XS_nRES (1<< 1)\r
+#define P32XS_ADEN (1<< 0)\r
#define P32XS2_ADEN (1<< 9)\r
#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
#define P32XS_68S (1<< 2)\r
+#define P32XS_DMA (1<< 1)\r
#define P32XS_RV (1<< 0)\r
\r
#define P32XV_nPAL (1<<15) // VDP\r
#define P32XV_PRI (1<< 7)\r
#define P32XV_Mx (3<< 0) // display mode mask\r
\r
+#define P32XV_SFT (1<< 0)\r
+\r
#define P32XV_VBLK (1<<15)\r
#define P32XV_HBLK (1<<14)\r
#define P32XV_PEN (1<<13)\r
#define P32XI_CMD (1 << 8/2)\r
#define P32XI_PWM (1 << 6/2)\r
\r
+// peripheral reg access\r
+#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
+\r
// real one is 4*2, but we use more because we don't lockstep\r
#define DMAC_FIFO_LEN (4*4)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
+#define SH2_DRCBLK_RAM_SHIFT 1\r
+#define SH2_DRCBLK_DA_SHIFT 1\r
+\r
+#define SH2_WRITE_SHIFT 25\r
+\r
struct Pico32x\r
{\r
unsigned short regs[0x20];\r
- unsigned short vdp_regs[0x10];\r
+ unsigned short vdp_regs[0x10]; // 0x40\r
+ unsigned short sh2_regs[3]; // 0x60\r
unsigned char pending_fb;\r
unsigned char dirty_pal;\r
- unsigned char pad[2];\r
unsigned int emu_flags;\r
unsigned char sh2irq_mask[2];\r
unsigned char sh2irqi[2]; // individual\r
struct Pico32xMem\r
{\r
unsigned char sdram[0x40000];\r
+#ifdef DRC_SH2\r
+ unsigned short drcblk_ram[1 << (18 - SH2_DRCBLK_RAM_SHIFT)];\r
+#endif\r
unsigned short dram[2][0x20000/2]; // AKA fb\r
unsigned char m68k_rom[0x10000]; // 0x100; using M68K_BANK_SIZE\r
unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
+#ifdef DRC_SH2\r
+ unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
+#endif\r
unsigned char sh2_rom_m[0x800];\r
unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
extern areaclose *areaClose;\r
\r
// cart.c\r
+void Byteswap(void *dst, const void *src, int len);\r
extern void (*PicoCartMemSetup)(void);\r
extern void (*PicoCartUnloadHook)(void);\r
\r
PICO_INTERNAL void PicoFrameStart(void);\r
void PicoDrawSync(int to, int blank_last_line);\r
void BackFill(int reg7, int sh);\r
-void FinalizeLineRGB555(int sh, int line);\r
+void FinalizeLine555(int sh, int line);\r
extern int DrawScanline;\r
#define MAX_LINE_SPRITES 29\r
extern unsigned char HighLnSpr[240][3 + MAX_LINE_SPRITES];\r
+extern void *DrawLineDestBase;\r
+extern int DrawLineDestIncrement;\r
\r
// draw2.c\r
PICO_INTERNAL void PicoFrameFull();\r
void PicoFrameStartMode4(void);\r
void PicoLineMode4(int line);\r
void PicoDoHighPal555M4(void);\r
-void PicoDrawSetColorFormatMode4(int which);\r
+void PicoDrawSetOutputMode4(pdso_t which);\r
\r
// memory.c\r
PICO_INTERNAL void PicoMemSetup(void);\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
void p32x_update_irls(void);\r
+void p32x_reset_sh2s(void);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
void PicoWrite16_32x(unsigned int a, unsigned int d);\r
void PicoMemSetup32x(void);\r
void Pico32xSwapDRAM(int b);\r
-void p32x_poll_event(int is_vdp);\r
+void p32x_poll_event(int cpu_mask, int is_vdp);\r
\r
// 32x/draw.c\r
void FinalizeLine32xRGB555(int sh, int line);\r
+void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
+void PicoDraw32xLayerMdOnly(int offs, int lines);\r
+enum {\r
+ PDM32X_OFF,\r
+ PDM32X_32X_ONLY,\r
+ PDM32X_BOTH,\r
+};\r
+extern int Pico32xDrawMode;\r
\r
// 32x/pwm.c\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
-void p32x_pwm_refresh(void);\r
-void p32x_pwm_irq_check(void);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
+void p32x_timers_do(int new_line);\r
+void p32x_timers_recalc(void);\r
extern int pwm_frame_smp_cnt;\r
\r
/* avoid dependency on newer glibc */\r
return (0x09 <= c && c <= 0x0d) || c == ' ';\r
}\r
\r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))\r
+#endif\r
+\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
#define EL_LOGMASK 0\r
#define EL_CDREGS 0x00020000 /* MCD: register access */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
+#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
#define elprintf(w,f,...)\r
#endif\r
\r
+// profiling\r
+#ifdef PPROF\r
+#include <platform/linux/pprof.h>\r
+#else\r
+#define pprof_init()\r
+#define pprof_finish()\r
+#define pprof_start(x)\r
+#define pprof_end(...)\r
+#define pprof_end_sub(...)\r
+#endif\r
+\r
+// misc\r
#ifdef _MSC_VER\r
#define cdprintf\r
#else\r
#define cdprintf(x...)\r
#endif\r
\r
-#if defined(__GNUC__) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 3\r
-#define MEMH_FUNC __attribute__((aligned(4)))\r
+#ifdef __i386__\r
+#define REGPARM(x) __attribute__((regparm(x)))\r
#else\r
-#define MEMH_FUNC\r
+#define REGPARM(x)\r
#endif\r
\r
#ifdef __GNUC__\r