} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
#define sh2_set_vbr(c, v) \\r
{ if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+ elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
// peripheral reg access\r
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
\r
-// real one is 4*2, but we use more because we don't lockstep\r
-#define DMAC_FIFO_LEN (4*4)\r
+#define DMAC_FIFO_LEN (4*2)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
unsigned char sh2irqi[2]; // individual\r
unsigned int sh2irqs; // common irqs\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
+ unsigned int pad[4];\r
unsigned int dmac0_fifo_ptr;\r
- unsigned int pad;\r
+ unsigned short vdp_fbcr_fake;\r
+ unsigned short pad2;\r
unsigned char comm_dirty_68k;\r
unsigned char comm_dirty_sh2;\r
unsigned char pwm_irq_cnt;\r
void p32x_dreq1_trigger(void);\r
void p32x_timers_recalc(void);\r
void p32x_timers_do(unsigned int m68k_slice);\r
+void sh2_peripheral_reset(SH2 *sh2);\r
unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r