#ifdef EMU_C68K\r
#include "../cpu/cyclone/Cyclone.h"\r
extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuCM68k.cycles // cycles left for this run\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuCS68k.cycles)\r
-#define SekEndTimeslice(after) PicoCpuCM68k.cycles=after\r
-#define SekEndTimesliceS68k(after) PicoCpuCS68k.cycles=after\r
+#define SekCyclesLeft PicoCpuCM68k.cycles // cycles left for this run\r
+#define SekCyclesLeftS68k PicoCpuCS68k.cycles\r
#define SekPc (PicoCpuCM68k.pc-PicoCpuCM68k.membase)\r
#define SekPcS68k (PicoCpuCS68k.pc-PicoCpuCS68k.membase)\r
-#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
+#define SekDar(x) (x < 8 ? PicoCpuCM68k.d[x] : PicoCpuCM68k.a[x - 8])\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuCS68k.d[x] : PicoCpuCS68k.a[x - 8])\r
#define SekSr CycloneGetSr(&PicoCpuCM68k)\r
+#define SekSrS68k CycloneGetSr(&PicoCpuCS68k)\r
#define SekSetStop(x) { PicoCpuCM68k.state_flags&=~1; if (x) { PicoCpuCM68k.state_flags|=1; PicoCpuCM68k.cycles=0; } }\r
#define SekSetStopS68k(x) { PicoCpuCS68k.state_flags&=~1; if (x) { PicoCpuCS68k.state_flags|=1; PicoCpuCS68k.cycles=0; } }\r
#define SekIsStoppedM68k() (PicoCpuCM68k.state_flags&1)\r
#define SekInterrupt(i) PicoCpuCM68k.irq=i\r
#define SekIrqLevel PicoCpuCM68k.irq\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_F68K\r
#include "../cpu/fame/fame.h"\r
extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;\r
-#define SekCyclesLeftNoMCD PicoCpuFM68k.io_cycle_counter\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuFS68k.io_cycle_counter)\r
-#define SekEndTimeslice(after) PicoCpuFM68k.io_cycle_counter=after\r
-#define SekEndTimesliceS68k(after) PicoCpuFS68k.io_cycle_counter=after\r
+#define SekCyclesLeft PicoCpuFM68k.io_cycle_counter\r
+#define SekCyclesLeftS68k PicoCpuFS68k.io_cycle_counter\r
#define SekPc fm68k_get_pc(&PicoCpuFM68k)\r
#define SekPcS68k fm68k_get_pc(&PicoCpuFS68k)\r
-#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
+#define SekDar(x) (x < 8 ? PicoCpuFM68k.dreg[x].D : PicoCpuFM68k.areg[x - 8].D)\r
+#define SekDarS68k(x) (x < 8 ? PicoCpuFS68k.dreg[x].D : PicoCpuFS68k.areg[x - 8].D)\r
#define SekSr PicoCpuFM68k.sr\r
+#define SekSrS68k PicoCpuFS68k.sr\r
#define SekSetStop(x) { \\r
PicoCpuFM68k.execinfo &= ~FM68K_HALTED; \\r
if (x) { PicoCpuFM68k.execinfo |= FM68K_HALTED; PicoCpuFM68k.io_cycle_counter = 0; } \\r
#define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
#define SekIrqLevel PicoCpuFM68k.interrupts[0]\r
\r
-#ifdef EMU_M68K\r
-#define EMU_CORE_DEBUG\r
-#endif\r
#endif\r
\r
#ifdef EMU_M68K\r
#include "../cpu/musashi/m68kcpu.h"\r
extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;\r
#ifndef SekCyclesLeft\r
-#define SekCyclesLeftNoMCD PicoCpuMM68k.cyc_remaining_cycles\r
-#define SekCyclesLeft \\r
- (((PicoAHW&1) && (PicoOpt & POPT_EN_MCD_PSYNC)) ? (SekCycleAim-SekCycleCnt) : SekCyclesLeftNoMCD)\r
-#define SekCyclesLeftS68k \\r
- ((PicoOpt & POPT_EN_MCD_PSYNC) ? (SekCycleAimS68k-SekCycleCntS68k) : PicoCpuMS68k.cyc_remaining_cycles)\r
-#define SekEndTimeslice(after) SET_CYCLES(after)\r
-#define SekEndTimesliceS68k(after) PicoCpuMS68k.cyc_remaining_cycles=after\r
+#define SekCyclesLeft PicoCpuMM68k.cyc_remaining_cycles\r
+#define SekCyclesLeftS68k PicoCpuMS68k.cyc_remaining_cycles\r
#define SekPc m68k_get_reg(&PicoCpuMM68k, M68K_REG_PC)\r
#define SekPcS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_PC)\r
-#define SekDar(x) PicoCpuMM68k.dar[x]\r
-#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
+#define SekDar(x) PicoCpuMM68k.dar[x]\r
+#define SekDarS68k(x) PicoCpuMS68k.dar[x]\r
+#define SekSr m68k_get_reg(&PicoCpuMM68k, M68K_REG_SR)\r
+#define SekSrS68k m68k_get_reg(&PicoCpuMS68k, M68K_REG_SR)\r
#define SekSetStop(x) { \\r
if(x) { SET_CYCLES(0); PicoCpuMM68k.stopped=STOP_LEVEL_STOP; } \\r
else PicoCpuMM68k.stopped=0; \\r
#endif\r
#endif // EMU_M68K\r
\r
-extern int SekCycleCnt; // cycles done in this frame\r
-extern int SekCycleAim; // cycle aim\r
-extern unsigned int SekCycleCntT; // total cycle counter, updated once per frame\r
-\r
-#define SekCyclesReset() { \\r
- SekCycleCntT+=SekCycleAim; \\r
- SekCycleCnt-=SekCycleAim; \\r
- SekCycleAim=0; \\r
+// while running, cnt represents target of current timeslice\r
+// while not in SekRun(), it's actual cycles done\r
+// (but always use SekCyclesDone() if you need current position)\r
+// cnt may change if timeslice is ended prematurely or extended,\r
+// so we use SekCycleAim for the actual target\r
+extern unsigned int SekCycleCnt;\r
+extern unsigned int SekCycleAim;\r
+\r
+// number of cycles done (can be checked anywhere)\r
+#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
+\r
+// burn cycles while not in SekRun() and while in\r
+#define SekCyclesBurn(c) SekCycleCnt += c\r
+#define SekCyclesBurnRun(c) { \\r
+ SekCyclesLeft -= c; \\r
+ if (SekCyclesLeft < 0) \\r
+ SekCyclesLeft = 0; \\r
}\r
-#define SekCyclesBurn(c) SekCycleCnt+=c\r
-#define SekCyclesDone() (SekCycleAim-SekCyclesLeft) // number of cycles done in this frame (can be checked anywhere)\r
-#define SekCyclesDoneT() (SekCycleCntT+SekCyclesDone()) // total nuber of cycles done for this rom\r
\r
+// note: sometimes may extend timeslice to delay an irq\r
#define SekEndRun(after) { \\r
- SekCycleCnt -= SekCyclesLeft - (after); \\r
- if (SekCycleCnt < 0) SekCycleCnt = 0; \\r
- SekEndTimeslice(after); \\r
+ SekCycleCnt -= SekCyclesLeft - (after); \\r
+ SekCyclesLeft = after; \\r
}\r
\r
+extern unsigned int SekCycleCntS68k;\r
+extern unsigned int SekCycleAimS68k;\r
+\r
#define SekEndRunS68k(after) { \\r
- SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
- if (SekCycleCntS68k < 0) SekCycleCntS68k = 0; \\r
- SekEndTimesliceS68k(after); \\r
+ if (SekCyclesLeftS68k > (after)) { \\r
+ SekCycleCntS68k -= SekCyclesLeftS68k - (after); \\r
+ SekCyclesLeftS68k = after; \\r
+ } \\r
}\r
\r
-extern int SekCycleCntS68k;\r
-extern int SekCycleAimS68k;\r
+#define SekCyclesDoneS68k() (SekCycleCntS68k - SekCyclesLeftS68k)\r
\r
-#define SekCyclesResetS68k() { \\r
- SekCycleCntS68k-=SekCycleAimS68k; \\r
- SekCycleAimS68k=0; \\r
-}\r
-#define SekCyclesDoneS68k() (SekCycleAimS68k-SekCyclesLeftS68k)\r
-\r
-#ifdef EMU_CORE_DEBUG\r
-extern int dbg_irq_level;\r
-#undef SekEndTimeslice\r
-#undef SekCyclesBurn\r
-#undef SekEndRun\r
-#undef SekInterrupt\r
-#define SekEndTimeslice(c)\r
-#define SekCyclesBurn(c) c\r
-#define SekEndRun(c)\r
-#define SekInterrupt(irq) dbg_irq_level=irq\r
-#endif\r
+// compare cycles, handling overflows\r
+// check if a > b\r
+#define CYCLES_GT(a, b) \\r
+ ((int)((a) - (b)) > 0)\r
+// check if a >= b\r
+#define CYCLES_GE(a, b) \\r
+ ((int)((a) - (b)) >= 0)\r
\r
// ----------------------- Z80 CPU -----------------------\r
\r
\r
#define Z80_STATE_SIZE 0x60\r
\r
-extern int z80stopCycle; /* in 68k cycles */\r
+extern unsigned int last_z80_sync;\r
extern int z80_cycle_cnt; /* 'done' z80 cycles before z80_run() */\r
extern int z80_cycle_aim;\r
extern int z80_scanline;\r
extern int z80_scanline_cycles; /* cycles done until z80_scanline */\r
\r
#define z80_resetCycles() \\r
+ last_z80_sync = SekCyclesDone(); \\r
z80_cycle_cnt = z80_cycle_aim = z80_scanline = z80_scanline_cycles = 0;\r
\r
#define z80_cyclesDone() \\r
#define ssh2 sh2s[1]\r
\r
#ifndef DRC_SH2\r
-# define ash2_end_run(sh2, after) do { \\r
- if ((sh2)->icount > (after)) { \\r
- (sh2)->cycles_timeslice -= (sh2)->icount; \\r
- (sh2)->icount = after; \\r
+# define sh2_end_run(sh2, after_) do { \\r
+ if ((sh2)->icount > (after_)) { \\r
+ (sh2)->cycles_timeslice -= (sh2)->icount - (after_); \\r
+ (sh2)->icount = after_; \\r
} \\r
} while (0)\r
-# define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - (sh2)->icount)\r
+# define sh2_cycles_left(sh2) (sh2)->icount\r
+# define sh2_burn_cycles(sh2, n) (sh2)->icount -= n\r
+# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
-# define ash2_end_run(sh2, after) do { \\r
- int left = (sh2)->sr >> 12; \\r
- if (left > (after)) { \\r
- (sh2)->cycles_timeslice -= left; \\r
+# define sh2_end_run(sh2, after_) do { \\r
+ int left_ = (signed int)(sh2)->sr >> 12; \\r
+ if (left_ > (after_)) { \\r
+ (sh2)->cycles_timeslice -= left_ - (after_); \\r
(sh2)->sr &= 0xfff; \\r
- (sh2)->sr |= (after) << 12; \\r
+ (sh2)->sr |= (after_) << 12; \\r
} \\r
} while (0)\r
-# define ash2_cycles_done(sh2) ((sh2)->cycles_timeslice - ((sh2)->sr >> 12))\r
+# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
+# define sh2_burn_cycles(sh2, n) (sh2)->sr -= ((n) << 12)\r
+# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
-//#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
-#define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
+#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
+#define sh2_cycles_done_t(sh2) \\r
+ ((sh2)->m68krcycles_done * 3 + sh2_cycles_done(sh2))\r
+#define sh2_cycles_done_m68k(sh2) \\r
+ ((sh2)->m68krcycles_done + (sh2_cycles_done(sh2) / 3))\r
+\r
#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
#define sh2_gbr(c) (c) ? ssh2.gbr : msh2.gbr\r
#define sh2_vbr(c) (c) ? ssh2.vbr : msh2.vbr\r
#define sh2_set_vbr(c, v) \\r
{ if (c) ssh2.vbr = v; else msh2.vbr = v; }\r
\r
+#define elprintf_sh2(sh2, w, f, ...) \\r
+ elprintf(w,"%csh2 "f,(sh2)->is_slave?'s':'m',##__VA_ARGS__)\r
+\r
// ---------------------------------------------------------\r
\r
// main oscillator clock which controls timing\r
unsigned short vsram[0x40]; // 0x22180\r
\r
unsigned char *rom; // 0x22200\r
- unsigned int romsize; // 0x22204\r
+ unsigned int romsize; // 0x22204 (on 32bits)\r
\r
struct PicoMisc m;\r
struct PicoVideo video;\r
unsigned short hint_vector;\r
unsigned char busreq;\r
unsigned char s68k_pend_ints;\r
- unsigned int state_flags; // 04: emu state: reset_pending\r
- unsigned int counter75hz;\r
- unsigned int pad0;\r
- int timer_int3; // 10\r
- unsigned int timer_stopwatch;\r
+ unsigned int state_flags; // 04\r
+ unsigned int stopwatch_base_c;\r
+ unsigned int m68k_comm_dirty;\r
+ unsigned short m68k_poll_a;\r
+ unsigned short m68k_poll_cnt;\r
+ unsigned int pad;\r
unsigned char bcram_reg; // 18: battery-backed RAM cart register\r
unsigned char pad2;\r
unsigned short pad3;\r
- int pad[9];\r
+ int pad4[9];\r
};\r
\r
typedef struct\r
unsigned char pcm_ram[0x10000];\r
unsigned char pcm_ram_b[0x10][0x1000];\r
};\r
+ // FIXME: should be short\r
unsigned char s68k_regs[0x200]; // 110000: GA, not CPU regs\r
unsigned char bram[0x2000]; // 110200: 8K\r
struct mcd_misc m; // 112200: misc\r
#define P32XV_nFEN (1<< 1)\r
#define P32XV_FS (1<< 0)\r
\r
-#define P32XP_FULL (1<<15) // PWM\r
+#define P32XP_RTP (1<<7) // PWM control\r
+#define P32XP_FULL (1<<15) // PWM pulse\r
#define P32XP_EMPTY (1<<14)\r
\r
-#define P32XF_68KPOLL (1 << 0)\r
-#define P32XF_MSH2POLL (1 << 1)\r
-#define P32XF_SSH2POLL (1 << 2)\r
-#define P32XF_68KVPOLL (1 << 3)\r
-#define P32XF_MSH2VPOLL (1 << 4)\r
-#define P32XF_SSH2VPOLL (1 << 5)\r
-#define P32XF_PWM_PEND (1 << 6)\r
+#define P32XF_68KCPOLL (1 << 0)\r
+#define P32XF_68KVPOLL (1 << 1)\r
+#define P32XF_Z80_32X_IO (1 << 7) // z80 does 32x io\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
// peripheral reg access\r
#define PREG8(regs,offs) ((unsigned char *)regs)[offs ^ 3]\r
\r
-// real one is 4*2, but we use more because we don't lockstep\r
-#define DMAC_FIFO_LEN (4*4)\r
+#define DMAC_FIFO_LEN (4*2)\r
#define PWM_BUFF_LEN 1024 // in one channel samples\r
\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
#define SH2_DRCBLK_DA_SHIFT 1\r
\r
+#define SH2_READ_SHIFT 25\r
#define SH2_WRITE_SHIFT 25\r
\r
struct Pico32x\r
unsigned char sh2irqi[2]; // individual\r
unsigned int sh2irqs; // common irqs\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
- unsigned int dmac_ptr;\r
- unsigned int pwm_irq_sample_cnt;\r
+ unsigned int pad[4];\r
+ unsigned int dmac0_fifo_ptr;\r
+ unsigned short vdp_fbcr_fake;\r
+ unsigned short pad2;\r
unsigned char comm_dirty_68k;\r
unsigned char comm_dirty_sh2;\r
- unsigned short pad;\r
- unsigned int reserved[8];\r
+ unsigned char pwm_irq_cnt;\r
+ unsigned char pad1;\r
+ unsigned short pwm_p[2]; // pwm pos in fifo\r
+ unsigned int pwm_cycle_p; // pwm play cursor (32x cycles)\r
+ unsigned int reserved[6];\r
};\r
\r
struct Pico32xMem\r
unsigned char m68k_rom[0x100];\r
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
};\r
- unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
#ifdef DRC_SH2\r
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
#endif\r
- unsigned char sh2_rom_m[0x800];\r
- unsigned char sh2_rom_s[0x400];\r
+ union {\r
+ unsigned char b[0x800];\r
+ unsigned short w[0x800/2];\r
+ } sh2_rom_m;\r
+ union {\r
+ unsigned char b[0x400];\r
+ unsigned short w[0x400/2];\r
+ } sh2_rom_s;\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
- unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
+ signed short pwm_current[2]; // current converted samples\r
+ unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
};\r
\r
// area.c\r
\r
// cd/memory.c\r
PICO_INTERNAL void PicoMemSetupCD(void);\r
-void PicoMemStateLoaded(void);\r
+void pcd_state_loaded_mem(void);\r
\r
// pico.c\r
extern struct Pico Pico;\r
extern void (*PicoLineHook)(void);\r
PICO_INTERNAL int CheckDMA(void);\r
PICO_INTERNAL void PicoDetectRegion(void);\r
-PICO_INTERNAL void PicoSyncZ80(int m68k_cycles_done);\r
+PICO_INTERNAL void PicoSyncZ80(unsigned int m68k_cycles_done);\r
\r
// cd/pico.c\r
+#define PCDS_IEN1 (1<<1)\r
+#define PCDS_IEN2 (1<<2)\r
+#define PCDS_IEN3 (1<<3)\r
+#define PCDS_IEN4 (1<<4)\r
+#define PCDS_IEN5 (1<<5)\r
+#define PCDS_IEN6 (1<<6)\r
+\r
PICO_INTERNAL void PicoInitMCD(void);\r
PICO_INTERNAL void PicoExitMCD(void);\r
PICO_INTERNAL void PicoPowerMCD(void);\r
PICO_INTERNAL int PicoResetMCD(void);\r
PICO_INTERNAL void PicoFrameMCD(void);\r
\r
+enum pcd_event {\r
+ PCD_EVENT_CDC,\r
+ PCD_EVENT_TIMER3,\r
+ PCD_EVENT_GFX,\r
+ PCD_EVENT_DMA,\r
+ PCD_EVENT_COUNT,\r
+};\r
+extern unsigned int pcd_event_times[PCD_EVENT_COUNT];\r
+void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);\r
+void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
+unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
+void pcd_sync_s68k(unsigned int m68k_target);\r
+void pcd_state_loaded(void);\r
+\r
// pico/pico.c\r
PICO_INTERNAL void PicoInitPico(void);\r
PICO_INTERNAL void PicoReratePico(void);\r
void SekStepM68k(void);\r
void SekInitIdleDet(void);\r
void SekFinishIdleDet(void);\r
+#if defined(CPU_CMP_R) || defined(CPU_CMP_W)\r
+void SekTrace(int is_s68k);\r
+#else\r
+#define SekTrace(x)\r
+#endif\r
\r
// cd/sek.c\r
PICO_INTERNAL void SekInitS68k(void);\r
enum p32x_event {\r
P32X_EVENT_PWM,\r
P32X_EVENT_FILLEND,\r
+ P32X_EVENT_HINT,\r
P32X_EVENT_COUNT,\r
};\r
-extern unsigned int event_times[P32X_EVENT_COUNT];\r
+extern unsigned int p32x_event_times[P32X_EVENT_COUNT];\r
\r
void Pico32xInit(void);\r
void PicoPower32x(void);\r
void Pico32xStartup(void);\r
void PicoUnload32x(void);\r
void PicoFrame32x(void);\r
+void Pico32xStateLoaded(int is_early);\r
void p32x_sync_sh2s(unsigned int m68k_target);\r
-void p32x_update_irls(int nested_call);\r
+void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target);\r
+void p32x_update_irls(SH2 *active_sh2, int m68k_cycles);\r
+void p32x_trigger_irq(SH2 *sh2, int m68k_cycles, unsigned int mask);\r
+void p32x_update_cmd_irq(SH2 *sh2, int m68k_cycles);\r
void p32x_reset_sh2s(void);\r
-void p32x_event_schedule(enum p32x_event event, unsigned int now, int after);\r
+void p32x_event_schedule(unsigned int now, enum p32x_event event, int after);\r
+void p32x_event_schedule_sh2(SH2 *sh2, enum p32x_event event, int after);\r
+void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
void PicoWrite16_32x(unsigned int a, unsigned int d);\r
void PicoMemSetup32x(void);\r
void Pico32xSwapDRAM(int b);\r
-void Pico32xStateLoaded(void);\r
-void p32x_poll_event(int cpu_mask, int is_vdp);\r
+void Pico32xMemStateLoaded(void);\r
+void p32x_m68k_poll_event(unsigned int flags);\r
+void p32x_sh2_poll_event(SH2 *sh2, unsigned int flags, unsigned int m68k_cycles);\r
\r
// 32x/draw.c\r
+void PicoDrawSetOutFormat32x(pdso_t which, int use_32x_line_mode);\r
void FinalizeLine32xRGB555(int sh, int line);\r
void PicoDraw32xLayer(int offs, int lines, int mdbg);\r
void PicoDraw32xLayerMdOnly(int offs, int lines);\r
extern int Pico32xDrawMode;\r
\r
// 32x/pwm.c\r
-unsigned int p32x_pwm_read16(unsigned int a);\r
-void p32x_pwm_write16(unsigned int a, unsigned int d);\r
+unsigned int p32x_pwm_read16(unsigned int a, SH2 *sh2,\r
+ unsigned int m68k_cycles);\r
+void p32x_pwm_write16(unsigned int a, unsigned int d,\r
+ SH2 *sh2, unsigned int m68k_cycles);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
-void p32x_timers_do(unsigned int cycles);\r
+void p32x_pwm_ctl_changed(void);\r
+void p32x_pwm_schedule(unsigned int m68k_now);\r
+void p32x_pwm_schedule_sh2(SH2 *sh2);\r
+void p32x_pwm_sync_to_sh2(SH2 *sh2);\r
+void p32x_pwm_irq_event(unsigned int m68k_now);\r
+void p32x_pwm_state_loaded(void);\r
+\r
+// 32x/sh2soc.c\r
+void p32x_dreq0_trigger(void);\r
+void p32x_dreq1_trigger(void);\r
void p32x_timers_recalc(void);\r
-void p32x_pwm_schedule(unsigned int now);\r
+void p32x_timers_do(unsigned int m68k_slice);\r
+void sh2_peripheral_reset(SH2 *sh2);\r
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
+void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+\r
#else\r
#define Pico32xInit()\r
#define PicoPower32x()\r
#define PicoFrame32x()\r
#define PicoUnload32x()\r
#define Pico32xStateLoaded()\r
-#define PicoDraw32xSetFrameMode(...)\r
#define FinalizeLine32xRGB555 NULL\r
#define p32x_pwm_update(...)\r
#define p32x_timers_recalc()\r
\r
// emulation event logging\r
#ifndef EL_LOGMASK\r
-#define EL_LOGMASK 0\r
+# ifdef __x86_64__ // HACK\r
+# define EL_LOGMASK (EL_STATUS|EL_IDLE|EL_ANOMALY)\r
+# else\r
+# define EL_LOGMASK (EL_STATUS)\r
+# endif\r
#endif\r
\r
#define EL_HVCNT 0x00000001 /* hv counter reads */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
+#define EL_32XP 0x00200000 /* 32X peripherals */\r
+#define EL_CD 0x00400000 /* MCD */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r
#define pprof_end_sub(...)\r
#endif\r
\r
+#ifdef EVT_LOG\r
+enum evt {\r
+ EVT_FRAME_START,\r
+ EVT_NEXT_LINE,\r
+ EVT_RUN_START,\r
+ EVT_RUN_END,\r
+ EVT_POLL_START,\r
+ EVT_POLL_END,\r
+ EVT_CNT\r
+};\r
+\r
+enum evt_cpu {\r
+ EVT_M68K,\r
+ EVT_S68K,\r
+ EVT_MSH2,\r
+ EVT_SSH2,\r
+ EVT_CPU_CNT\r
+};\r
+\r
+void pevt_log(unsigned int cycles, enum evt_cpu c, enum evt e);\r
+void pevt_dump(void);\r
+\r
+#define pevt_log_m68k(e) \\r
+ pevt_log(SekCyclesDoneT(), EVT_M68K, e)\r
+#define pevt_log_m68k_o(e) \\r
+ pevt_log(SekCyclesDoneT2(), EVT_M68K, e)\r
+#define pevt_log_sh2(sh2, e) \\r
+ pevt_log(sh2_cycles_done_m68k(sh2), EVT_MSH2 + (sh2)->is_slave, e)\r
+#define pevt_log_sh2_o(sh2, e) \\r
+ pevt_log((sh2)->m68krcycles_done, EVT_MSH2 + (sh2)->is_slave, e)\r
+#else\r
+#define pevt_log(c, e)\r
+#define pevt_log_m68k(e)\r
+#define pevt_log_m68k_o(e)\r
+#define pevt_log_sh2(sh2, e)\r
+#define pevt_log_sh2_o(sh2, e)\r
+#define pevt_dump()\r
+#endif\r
+\r
// misc\r
#ifdef _MSC_VER\r
#define cdprintf\r
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