cd: rewrite pcm

[picodrive.git] / pico / pico_int.h

diff --git a/pico/pico_int.h b/pico/pico_int.h
index 2053ac6..ccc1a9b 100644 (file)
--- a/pico/pico_int.h
+++ b/pico/pico_int.h
@@ -51,6 +51,9 @@ extern struct Cyclone PicoCpuCM68k, PicoCpuCS68k;
 #define SekIsStoppedS68k() (PicoCpuCS68k.state_flags&1)\r
 #define SekShouldInterrupt() (PicoCpuCM68k.irq > (PicoCpuCM68k.srh&7))\r
 \r
+#define SekNotPolling     PicoCpuCM68k.not_pol\r
+#define SekNotPollingS68k PicoCpuCS68k.not_pol\r
+\r
 #define SekInterrupt(i) PicoCpuCM68k.irq=i\r
 #define SekIrqLevel     PicoCpuCM68k.irq\r
 \r
@@ -79,6 +82,9 @@ extern M68K_CONTEXT PicoCpuFM68k, PicoCpuFS68k;
 #define SekIsStoppedS68k() (PicoCpuFS68k.execinfo&FM68K_HALTED)\r
 #define SekShouldInterrupt() fm68k_would_interrupt()\r
 \r
+#define SekNotPolling     PicoCpuFM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuFS68k.not_polling\r
+\r
 #define SekInterrupt(irq) PicoCpuFM68k.interrupts[0]=irq\r
 #define SekIrqLevel       PicoCpuFM68k.interrupts[0]\r
 \r
@@ -108,6 +114,9 @@ extern m68ki_cpu_core PicoCpuMM68k, PicoCpuMS68k;
 #define SekIsStoppedS68k() (PicoCpuMS68k.stopped==STOP_LEVEL_STOP)\r
 #define SekShouldInterrupt() (CPU_INT_LEVEL > FLAG_INT_MASK)\r
 \r
+#define SekNotPolling     PicoCpuMM68k.not_polling\r
+#define SekNotPollingS68k PicoCpuMS68k.not_polling\r
+\r
 #define SekInterrupt(irq) { \\r
        void *oldcontext = m68ki_cpu_p; \\r
        m68k_set_context(&PicoCpuMM68k); \\r
@@ -134,8 +143,6 @@ extern unsigned int SekCycleAim;
 #define SekCyclesBurn(c)    SekCycleCnt += c\r
 #define SekCyclesBurnRun(c) { \\r
   SekCyclesLeft -= c; \\r
-  if (SekCyclesLeft < 0) \\r
-    SekCyclesLeft = 0; \\r
 }\r
 \r
 // note: sometimes may extend timeslice to delay an irq\r
@@ -174,6 +181,8 @@ extern struct DrZ80 drZ80;
 #define z80_run(cycles)    ((cycles) - DrZ80Run(&drZ80, cycles))\r
 #define z80_run_nr(cycles) DrZ80Run(&drZ80, cycles)\r
 #define z80_int()          drZ80.Z80_IRQ = 1\r
+#define z80_int()          drZ80.Z80_IRQ = 1\r
+#define z80_nmi()          drZ80.Z80IF |= 8\r
 \r
 #define z80_cyclesLeft     drZ80.cycles\r
 #define z80_pc()           (drZ80.Z80PC - drZ80.Z80PC_BASE)\r
@@ -184,6 +193,7 @@ extern struct DrZ80 drZ80;
 #define z80_run(cycles)    Cz80_Exec(&CZ80, cycles)\r
 #define z80_run_nr(cycles) Cz80_Exec(&CZ80, cycles)\r
 #define z80_int()          Cz80_Set_IRQ(&CZ80, 0, HOLD_LINE)\r
+#define z80_nmi()          Cz80_Set_IRQ(&CZ80, IRQ_LINE_NMI, 0)\r
 \r
 #define z80_cyclesLeft     (CZ80.ICount - CZ80.ExtraCycles)\r
 #define z80_pc()           Cz80_Get_Reg(&CZ80, CZ80_PC)\r
@@ -193,6 +203,7 @@ extern struct DrZ80 drZ80;
 #define z80_run(cycles)    (cycles)\r
 #define z80_run_nr(cycles)\r
 #define z80_int()\r
+#define z80_nmi()\r
 \r
 #endif\r
 \r
@@ -296,7 +307,7 @@ struct PicoMisc
   unsigned char sram_reg;      // 09 SRAM reg. See SRR_* below\r
   unsigned short z80_bank68k;  // 0a\r
   unsigned short pad0;\r
-  unsigned char  pad1;\r
+  unsigned char  ncart_in;     // 0e !cart_in\r
   unsigned char  z80_reset;    // 0f z80 reset held\r
   unsigned char  padDelay[2];  // 10 gamepad phase time outs, so we count a delay\r
   unsigned short eeprom_addr;  // EEPROM address register\r
@@ -313,7 +324,8 @@ struct PicoMS
 {\r
   unsigned char carthw[0x10];\r
   unsigned char io_ctl;\r
-  unsigned char pad[0x4f];\r
+  unsigned char nmi_state;\r
+  unsigned char pad[0x4e];\r
 };\r
 \r
 // some assembly stuff depend on these, do not touch!\r
@@ -366,13 +378,15 @@ struct PicoSRAM
 #include "cd/LC89510.h"\r
 #include "cd/gfx_cd.h"\r
 \r
+#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
+\r
 struct mcd_pcm\r
 {\r
        unsigned char control; // reg7\r
        unsigned char enabled; // reg8\r
        unsigned char cur_ch;\r
        unsigned char bank;\r
-       int pad1;\r
+       unsigned int update_cycles;\r
 \r
        struct pcm_chan                 // 08, size 0x10\r
        {\r
@@ -382,10 +396,12 @@ struct mcd_pcm
        } ch[8];\r
 };\r
 \r
+#define PCD_ST_S68K_RST 1\r
+\r
 struct mcd_misc\r
 {\r
        unsigned short hint_vector;\r
-       unsigned char  busreq;\r
+       unsigned char  busreq;          // not s68k_regs[1]\r
        unsigned char  s68k_pend_ints;\r
        unsigned int   state_flags;     // 04\r
        unsigned int   stopwatch_base_c;\r
@@ -431,6 +447,9 @@ typedef struct
        CDC  cdc;\r
        _scd scd;\r
        Rot_Comp rot_comp;\r
+       int pcm_mixbuf[PCM_MIXBUF_LEN * 2];\r
+       int pcm_mixpos;\r
+       int pcm_mixbuf_dirty;\r
 } mcd_state;\r
 \r
 // XXX: this will need to be reworked for cart+cd support.\r
@@ -438,6 +457,7 @@ typedef struct
 \r
 // 32X\r
 #define P32XS_FM    (1<<15)\r
+#define P32XS_nCART (1<< 8)\r
 #define P32XS_REN   (1<< 7)\r
 #define P32XS_nRES  (1<< 1)\r
 #define P32XS_ADEN  (1<< 0)\r
@@ -593,6 +613,10 @@ PICO_INTERNAL void PicoMemSetupPico(void);
 \r
 // cd/memory.c\r
 PICO_INTERNAL void PicoMemSetupCD(void);\r
+unsigned int PicoRead8_mcd_io(unsigned int a);\r
+unsigned int PicoRead16_mcd_io(unsigned int a);\r
+void PicoWrite8_mcd_io(unsigned int a, unsigned int d);\r
+void PicoWrite16_mcd_io(unsigned int a, unsigned int d);\r
 void pcd_state_loaded_mem(void);\r
 \r
 // pico.c\r
@@ -633,8 +657,16 @@ void pcd_event_schedule(unsigned int now, enum pcd_event event, int after);
 void pcd_event_schedule_s68k(enum pcd_event event, int after);\r
 unsigned int pcd_cycles_m68k_to_s68k(unsigned int c);\r
 int  pcd_sync_s68k(unsigned int m68k_target, int m68k_poll_sync);\r
+void pcd_run_cpus(int m68k_cycles);\r
+void pcd_soft_reset(void);\r
 void pcd_state_loaded(void);\r
 \r
+// cd/pcm.c\r
+void pcd_pcm_sync(unsigned int to);\r
+void pcd_pcm_update(int *buffer, int length, int stereo);\r
+void pcd_pcm_write(unsigned int a, unsigned int d);\r
+unsigned int pcd_pcm_read(unsigned int a);\r
+\r
 // pico/pico.c\r
 PICO_INTERNAL void PicoInitPico(void);\r
 PICO_INTERNAL void PicoReratePico(void);\r
@@ -697,6 +729,7 @@ void ym2612_unpack_state(void);
 \r
 \r
 // videoport.c\r
+extern int line_base_cycles;\r
 PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
 PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
 PICO_INTERNAL_ASM unsigned int PicoVideoRead8(unsigned int a);\r
@@ -828,9 +861,9 @@ void sh2_peripheral_reset(SH2 *sh2);
 unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
 unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
 unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
-void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
-void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
-void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
 \r
 #else\r
 #define Pico32xInit()\r
@@ -959,7 +992,7 @@ void pevt_dump(void);
 #define cdprintf(x...)\r
 #endif\r
 \r
-#ifdef __i386__\r
+#if defined(__GNUC__) && defined(__i386__)\r
 #define REGPARM(x) __attribute__((regparm(x)))\r
 #else\r
 #define REGPARM(x)\r