\r
SH2 msh2, ssh2;\r
#define ash2_end_run(after) sh2_icount = after\r
+#define ash2_cycles_done() (sh2->cycles_aim - sh2_icount)\r
\r
#define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
#define sh2_reg(c, x) (c) ? ssh2.r[x] : msh2.r[x]\r
#define P32XS2_ADEN (1<< 9)\r
#define P32XS_FULL (1<< 7) // DREQ FIFO full\r
#define P32XS_68S (1<< 2)\r
+#define P32XS_DMA (1<< 1)\r
#define P32XS_RV (1<< 0)\r
\r
#define P32XV_nPAL (1<<15) // VDP\r
{\r
unsigned short regs[0x20];\r
unsigned short vdp_regs[0x10];\r
+ unsigned short sh2_regs[3];\r
unsigned char pending_fb;\r
unsigned char dirty_pal;\r
- unsigned char pad[2];\r
unsigned int emu_flags;\r
unsigned char sh2irq_mask[2];\r
unsigned char sh2irqi[2]; // individual\r
void PicoWrite16_32x(unsigned int a, unsigned int d);\r
void PicoMemSetup32x(void);\r
void Pico32xSwapDRAM(int b);\r
-void p32x_poll_event(int is_vdp);\r
+void p32x_poll_event(int cpu_mask, int is_vdp);\r
\r
// 32x/draw.c\r
void FinalizeLine32xRGB555(int sh, int line);\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
void p32x_pwm_refresh(void);\r
-void p32x_pwm_irq_check(void);\r
+void p32x_pwm_irq_check(int new_line);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
extern int pwm_frame_smp_cnt;\r
\r
#define EL_CDREGS 0x00020000 /* MCD: register access */\r
#define EL_CDREG3 0x00040000 /* MCD: register 3 only */\r
#define EL_32X 0x00080000\r
+#define EL_PWM 0x00100000 /* 32X PWM stuff (LOTS of output) */\r
\r
#define EL_STATUS 0x40000000 /* status messages */\r
#define EL_ANOMALY 0x80000000 /* some unexpected conditions (during emulation) */\r