.global code940\r
\r
+.equ mmsp2_regs, (0xc0000000-0x02000000) @ assume we live @ 0x2000000 bank\r
+\r
code940: @ interrupt table:\r
b .b_reset @ reset\r
b .b_undef @ undefined instructions\r
mov r12, #6\r
mov sp, #0x100000 @ reset stack\r
sub sp, sp, #4\r
- mov r1, #0xbe000000 @ assume we live @ 0x2000000 bank\r
+ mov r1, #mmsp2_regs\r
orr r2, r1, #0x3B00\r
orr r2, r2, #0x0046\r
mvn r3, #0\r
\r
@ set up region 3: 64k 0xbe000000-0xbe010000 (hw control registers)\r
mov r0, #(0x0f<<1)|1\r
- orr r0, r0, #0xbe000000\r
+ orr r0, r0, #mmsp2_regs\r
mcr p15, 0, r0, c6, c3, 0\r
mcr p15, 0, r0, c6, c3, 1\r
\r
mov r0, #(1<<1)\r
mcr p15, 0, r0, c3, c0, 0\r
\r
- @ set protection, allow accsess only to regions 1 and 2\r
+ @ set protection, allow access only to regions 1 and 2\r
mov r0, #(3<<8)|(3<<6)|(3<<4)|(3<<2)|(0) @ data: [full, full, full, full, no access] for regions [4 3 2 1 0]\r
mcr p15, 0, r0, c5, c0, 0\r
mov r0, #(0<<8)|(0<<6)|(0<<4)|(3<<2)|(0) @ instructions: [no access, no, no, full, no]\r
orr r0, r0, #1 @ 0x00000001: enable protection unit\r
orr r0, r0, #4 @ 0x00000004: enable D cache\r
orr r0, r0, #0x1000 @ 0x00001000: enable I cache\r
- bic r0, r0, #0xC0000000\r
- orr r0, r0, #0x40000000 @ 0x40000000: synchronous, faster?\r
-@ orr r0, r0, #0xC0000000 @ 0xC0000000: async\r
+@ bic r0, r0, #0xC0000000\r
+@ orr r0, r0, #0x40000000 @ 0x40000000: synchronous, faster?\r
+ orr r0, r0, #0xC0000000 @ 0xC0000000: async\r
mcr p15, 0, r0, c1, c0, 0 @ set control reg\r
\r
@ flush (invalidate) the cache (just in case)\r
\r
.Enter:\r
mov r0, r12\r
+ mov r1, lr\r
bl Main940\r
\r
@ we should never get here\r
-.b_deadloop:\r
- b .b_deadloop\r
+@.b_deadloop:\r
+@ b .b_deadloop\r
+ b .b_reserved\r
\r
\r
\r
.global wait_irq\r
\r
wait_irq:\r
+ mov r0, #mmsp2_regs\r
+ orr r0, r0, #0x3B00\r
+ orr r1, r0, #0x0042\r
+ mov r3, #0\r
+ strh r3, [r1] @ disable interrupts\r
+ orr r2, r0, #0x003E\r
+ strh r3, [r2] @ remove busy flag\r
+ mov r3, #1\r
+ strh r3, [r1] @ enable interrupts\r
+\r
mrs r0, cpsr\r
bic r0, r0, #0x80\r
- msr cpsr_c, r0 @ enable interrupts\r
+ msr cpsr_c, r0 @ enable interrupts\r
\r
mov r0, #0\r
mcr p15, 0, r0, c7, c0, 4 @ wait for IRQ\r
@ mcr p15, 0, r0, c15, c8, 2\r
+ nop\r
+ nop\r
b .b_reserved\r
\r
.pool\r