sub r14, r14, #(62 - 12) @ r14 = shift - (62 - FIXED_BITS)
vshll.u16 uvrg_base, uvrg0, #16 @ uvrg_base = uvrg0 << 16
- vdup.u32 r_shift, r14 @ r_shift = { shift, shift, shift, shift }
-
+ vdup.u32 r_shift, r14 @ r_shift = { shift, shift*, shift, shift* }
+ @ * - vshl.u64: ignored by hw
vadd.u32 uvrg_base, uvrgb_phase
vabs.s32 ga_uvrg_x, ga_uvrg_x @ ga_uvrg_x = abs(ga_uvrg_x)
vpush { texture_mask }; \
vpush { uvrg_dx4 }; \
\
- stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
+ stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12 }; /* r14=num_blocks */ \
bl flush_render_block_buffer; \
- ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
+ ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12 }; \
\
vpop { uvrg_dx4 }; \
vpop { texture_mask }; \
vpush { texture_mask }; \
vpush { uvrg_dx4 }; \
\
- stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
+ stmdb sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12 }; /* r14=num_blocks */ \
bl flush_render_block_buffer; \
- ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12, r14 }; \
+ ldmia sp!, { r0 - r3, EXTRA_UNSAVED_REGS r12 }; \
\
vpop { uvrg_dx4 }; \
vpop { texture_mask }; \
.align 3; \
\
function(shade_blocks_##shading##_textured_modulated_##dithering##_##target) \
+ save_abi_regs(); \
shade_blocks_textured_modulated_prologue_##shading(dithering, target); \
stmdb sp!, { r4 - r5, lr }; \
- save_abi_regs(); \
ldrh num_blocks, [psx_gpu, #psx_gpu_num_blocks_offset]; \
\
vld1.u32 { test_mask }, [psx_gpu, :128]; \
shade_blocks_textured_modulated_store_draw_mask_##target(28); \
shade_blocks_textured_modulated_store_pixels_##target(); \
\
+ ldmia sp!, { r4 - r5, lr }; \
restore_abi_regs(); \
- ldmia sp!, { r4 - r5, pc } \
+ bx lr \
shade_blocks_textured_modulated_builder(shaded, dithered, direct);
#define texel_block_expanded_b q2
#define texel_block_expanded_ab q2
#define texel_block_expanded_c q3
-#define texel_block_expanded_d q4
+#define texel_block_expanded_d q0
#define texel_block_expanded_cd q3
function(update_texture_4bpp_cache)