move.l (4 + \arg * 4 + \stacksz)(%sp), \reg
.endm
+# args are always 4 bytes in stack, caller restores sp
.macro ldargw arg, stacksz, reg
move.w (4 + \arg * 4 + 2 + \stacksz)(%sp), \reg
.endm
.global burn10 /* u16 val */
burn10:
- ldarg 0, 0, d0
+ ldargw 0, 0, d0
subq.l #1, d0
0:
- dbra d0, 0b
- rts
+ dbra d0, 0b /* 10|14 */
+ rts /* 16 */
.global write16_x16 /* u32 a, u16 count, u16 d */
write16_x16:
# destroys d1
.global get_input
get_input:
+.global get_input_s
+get_input_s:
move.b #0x40,(0xa10003)
moveq.l #0,d0
nop
and.w d0,d1 /* what changed now */
.endif
rts
+.global get_input_end
+get_input_end:
+
+.global get_line
+get_line:
+ movea.l #0xc00008, a0
+ moveq.l #0, d0
+0:
+ move.b (a0), d0 /* 8 d2 = vcnt */
+ cmp.b (a0), d0 /* 8 reread for super-rare corruption (torn read) */
+ bne 0b
+ rts
.global write_and_read1 /* u32 a, u16 d, void *dst */
write_and_read1:
.global x32x_disable
x32x_disable:
movea.l #0xa15100, a0
+ move.w #0, 6(a0) /* RV=0 */
move.w #1, (a0) /* ADEN (reset sh2) */
move.w #0, (a0) /* adapter disable, reset sh2 */
move.w #1, d0
ymwrite a0, a1, #0x27, #0x30 /* 30 disable, clear */
ymwrite a0, a1, #0x24, #0xfc /* 30 timer a */
- ymwrite a0, a1, #0x25, #0x01 /* 30 =15 - why 15? expected 16 */
+ ymwrite a0, a1, #0x25, #0x01 /* 30 =15 */
ymwrite a0, a1, #0x26, #0xff /* 30 timer b shortest interval */
move.b #0x27, (a0) /* 12 addr prep */
nop
move.b (a0), d0 /* 8 */
and.b d1, d0 /* 4 */
beq 0b /* 10|8 */
-0:
+
move.b #0x3f, (a1) /* 12 start a, clear */
- moveq.l #3, d1 /* 12 cycles for old flag to clear itself */
- nop
- nop
+
+ move.w #(488/10), d0 /* waste cycles */
+0: dbra d0, 0b
+
+ ymwrite a0, a1, #0x24, #0xf0 /* 30 show that rewriting count */
+ ymwrite a0, a1, #0x25, #0x00 /* 30 does nothing until timer expires */
+
+ move.w #(488*2/10), d0 /* waste cycles */
+0: dbra d0, 0b
+
+ ymwrite a0, a1, #0x26, #0xfc /* 30 same for timer b */
+ ymwrite a0, a1, #0x27, #0x0f /* 30 setting already set bits too */
+ moveq.l #0, d0
+ moveq.l #3, d1
0:
move.b (a0), d0
and.b d1, d0
move.b (a0), d0 /* re-read, else very occasionally get 1 */
rts
+.global test_ym_ab_sync2
+test_ym_ab_sync2:
+ movea.l #0xa04000, a0
+ movea.l #0xa04001, a1
+
+ move.b #0x0f, (a1) /* 12 enable */
+ moveq.l #0, d0
+ moveq.l #3, d1
+ nop /* 4 need ~12c to clear */
+0:
+ move.b (a0), d0 /* 8 */
+ and.b d1, d0 /* 4 */
+ beq 0b /* 10|8 */
+ move.b (a0), d0 /* re-read */
+ move.b #0x3c, (a1) /* 12 clear, disable */
+ rts
+
+.global x32x_switch_rv
+x32x_switch_rv:
+ ldargw 0, 0, d0
+ move.l (sp)+, d1
+ movea.l #0xa15106, a0
+ btst #0, d0
+ bne 0f
+ move.w #0, (a0)
+ or.l #0x880000, d1
+ bra 1f
+0:
+ move.w #1, (a0)
+ and.l #0x07ffff, d1
+1:
+ movea.l d1, a1
+ jmp (a1)
+.global x32x_switch_rv_end
+x32x_switch_rv_end:
+
# vim:filetype=asmM68k:ts=4:sw=4:expandtab