move.w (a0), d0
rts
+.global read_sr
+read_sr:
+ move.w sr, d0
+ rts
+
.global memcpy_ /* void *dst, const void *src, u16 size */
memcpy_:
ldarg 0, 0, a0
0:
move.w d0, (0xf004).w /* 12 */
move.w (sp)+, d0 /* 8 */
- rte /* 20 114 */
+ rte /* 20 114+44 */
.global test_hint_end
test_hint_end:
.global x32x_enable
x32x_enable:
movea.l #0xa15100, a0
- movea.l #0xa15120, a1
+ movea.l #0xa15122, a1
+ move.w #1, (a0) /* ADEN */
+# wait for min(20_sh2_cycles, pll_setup_time)
+# pll time is unclear, icd_mars.prg mentions 10ms which sounds
+# way too much. Hope 40 68k cycles is enough
+ move.w #40/10, d0
+0:
+ dbra d0, 0b
move.w #3, (a0) /* ADEN, nRES */
0:
- nop
- nop
+ move.w #0xffff, d0 /* waste some cycles */
tst.w (a1)
- beq 0b /* BIOS busy */
+ beq 0b /* master BIOS busy */
+
+0: /* for slave, use a limit, as it */
+ tst.w 4(a1) /* won't respond on master error. */
+ dbne d0, 0b /* slave BIOS busy */
+
or.w #1, 6(a0) /* RV */
rts
.global x32x_enable_end
x32x_enable_end:
+.global test_32x_b_c0
+test_32x_b_c0:
+ ldarg 0, 0, a1
+ ldargw 1, 0, d0
+ jsr (0xc0).l /* move.b d0, (a1); RV=0 */
+ bset #0, (0xa15107).l
+ rts
+.global test_32x_b_c0_end
+test_32x_b_c0_end:
+
# some nastyness from Fatal Rewind
.global test_h_v_2
test_h_v_2: