2 // This file is part of the Cyclone 68000 Emulator
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4 // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
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5 // Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)
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7 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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8 // You can choose the license that has the most advantages for you.
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10 // SVN repository can be found at http://code.google.com/p/cyclone68000/
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15 static FILE *AsmFile=NULL;
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17 static int CycloneVer=0x0099; // Version number of library
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18 int *CyJump=NULL; // Jump table
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19 int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format
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20 const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2
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21 const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2
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22 int Cycles; // Current cycles for opcode
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23 int pc_dirty; // something changed PC during processing
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26 // opcodes often used by games
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27 static const unsigned short hot_opcodes[] = {
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30 0x51c8, // dbra Dn, $2
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31 0x4a38, // tst.b $0.w
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32 0xd040, // add.w Dn, Dn
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33 0x4a79, // tst.w $0.l
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34 0x0240, // andi.w #$0, D0
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35 0x2038, // move.l $0.w, D0
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36 0xb0b8, // cmp.l $0.w, D0
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38 0x30c0, // move.w D0, (A0)+
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39 0x3028, // move.w ($0,A0), D0
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40 0x0c40, // cmpi.w #$0, D0
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41 0x0c79, // cmpi.w #$0, $0.l
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44 0x3000, // move.w D0, D0
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45 0x0839, // btst #$0, $0.l
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46 0x7000, // moveq #$0, D0
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47 0x3040, // movea.w D0, A0
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48 0x0838, // btst #$0, $0.w
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49 0x4a39, // tst.b $0.l
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50 0x33d8, // move.w (A0)+, $0.l
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52 0xb038, // cmp.b $0.w, D0
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53 0x3039, // move.w $0.l, D0
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57 0x5e40, // addq.w #7, D0
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58 0x1039, // move.b $0.l, D0
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59 0x20c0, // move.l D0, (A0)+
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60 0x1018, // move.b (A0)+, D0
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61 0x30d0, // move.w (A0), (A0)+
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62 0x3080, // move.w D0, (A0)
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63 0x3018, // move.w (A0)+, D0
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64 0xc040, // and.w D0, D0
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65 0x3180, // move.w D0, (A0,D0.w)
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66 0x1198, // move.b (A0)+, (A0,D0.w)
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71 0x41f0, // lea (A0,D0.w), A0
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72 0x4a28, // tst.b ($0,A0)
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73 0x0828, // btst #$0, ($0,A0)
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74 0x0640, // addi.w #$0, D0
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75 0x10c0, // move.b D0, (A0)+
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76 0x10d8, // move.b (A0)+, (A0)+
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78 #define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))
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80 static int is_op_hot(int op)
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83 for (i = 0; i < hot_opcode_count; i++)
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84 if (op == hot_opcodes[i])
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89 void ot(const char *format, ...)
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94 // notaz: stop me from leaving newlines in the middle of format string
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95 // and generating bad code
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96 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);
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97 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);
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99 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')
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102 va_start(valist,format);
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103 if (AsmFile) vfprintf(AsmFile,format,valist);
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109 if (ms) ot(" LTORG\n");
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110 else ot(" .ltorg\n");
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113 #if (CYCLONE_FOR_GENESIS == 2)
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114 static const char *tas_ops[] = {
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115 "Op4ad0", "Op4ad8", "Op4adf",
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116 "Op4ae0", "Op4ae7", "Op4ae8",
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117 "Op4af0", "Op4af8", "Op4af9",
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120 // get handler address in r0, OT (offset table) in r2
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121 static void ChangeTASGet(unsigned int i)
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123 if (i >= sizeof(tas_ops) / sizeof(tas_ops[0]))
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125 ot(" ldr r0,[r2,#%d*4] ;@ %s\n",i,tas_ops[i]);
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126 ot(" add r0,r0,r2\n");
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130 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
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131 static void AddressErrorWrapper(char rw, const char *dataprg, int iw)
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133 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");
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134 ot(" ldr r1,[r7,#0x44]\n");
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135 ot(" mov r6,#0x%02x\n", iw);
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136 ot(" mov r11,r0\n");
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137 ot(" tst r1,#0x20\n");
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138 ot(" orrne r6,r6,#4\n");
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139 ot(" b ExceptionAddressError\n");
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144 void FlushPC(int force)
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146 #if MEMHANDLERS_NEED_PC
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151 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
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154 static void PrintFramework()
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156 int state_flags_to_check = 1; // stopped
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158 state_flags_to_check |= 2; // tracing
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161 state_flags_to_check |= 0x10; // halted
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164 ot(";@ --------------------------- Framework --------------------------\n");
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165 if (ms) ot("CycloneRun\n");
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166 else ot("CycloneRun:\n");
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168 ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");
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170 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");
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171 ot(" ;@ r0-3 = Temporary registers\n");
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172 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
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173 ot(" ldr r6,[r7,#0x54] ;@ r6 = Opcode Jump table (from reset)\n");
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174 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");
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175 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
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176 ot(" ;@ r8 = Current Opcode\n");
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177 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");
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178 ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");
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179 ot(" ;@ r11 = Source value / Memory Base\n");
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181 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
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182 ot(" mov r2,#0\n");
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183 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");
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185 ot(";@ CheckInterrupt:\n");
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186 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
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187 ot(" beq NoInts0\n");
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188 ot(" cmp r0,#6 ;@ irq>6 ?\n");
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189 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
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190 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
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191 ot(" bgt CycloneDoInterrupt\n");
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192 ot("NoInts0%s\n", ms?"":":");
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194 ot(";@ Check if our processor is in special state\n");
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195 ot(";@ and jump to opcode handler if not\n");
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196 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");
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197 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");
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198 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);
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199 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
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201 ot("CycloneSpecial%s\n", ms?"":":");
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203 ot(" tst r0,#2 ;@ tracing?\n");
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204 ot(" bne CycloneDoTrace\n");
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206 ot(";@ stopped or halted\n");
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207 ot(" mov r5,#0\n");
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208 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");
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209 ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");
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213 ot(";@ We come back here after execution\n");
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214 ot("CycloneEnd%s\n", ms?"":":");
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215 ot(" sub r4,r4,#2\n");
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216 ot("CycloneEndNoBack%s\n", ms?"":":");
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217 #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE
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218 ot(" ldr r1,[r7,#0x98]\n");
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219 ot(" mov r10,r10,lsr #28\n");
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220 ot(" tst r1,r1\n");
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221 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");
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223 ot(" mov r10,r10,lsr #28\n");
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225 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
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226 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
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227 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
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228 ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");
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233 ot("CycloneInitJT%s\n", ms?"":":");
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234 #if COMPRESS_JUMPTABLE
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235 ot(";@ decompress jump table\n");
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236 ot(" mov r12,r0 ;@ jump table\n");
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237 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");
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238 ot(" ldr r1,[r0,#-4]\n");
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239 ot(" tst r1,r1\n");
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240 ot(" movne pc,lr ;@ already uncompressed\n");
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241 ot(" stmfd sp!,{r7,lr}\n");
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242 ot(" mov r7,r12 ;@ jump table\n");
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243 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");
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244 ot("unc_loop%s\n", ms?"":":");
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245 ot(" ldrh r1,[r0],#2\n");
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246 ot(" and r2,r1,#0xf\n");
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247 ot(" bic r1,r1,#0xf\n");
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248 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");
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249 ot(" cmp r2,#0xf\n");
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250 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");
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251 ot(" tst r2,r2\n");
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252 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");
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253 ot(" tst r2,r2\n");
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254 ot(" beq unc_finish ;@ done decompressing\n");
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255 ot(" tst r1,r1\n");
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256 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");
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257 ot(" beq unc_loop\n");
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258 ot("unc_loop_in%s\n", ms?"":":");
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259 ot(" subs r2,r2,#1\n");
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260 ot(" str r1,[r12],#4\n");
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261 ot(" bgt unc_loop_in\n");
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262 ot(" b unc_loop\n");
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263 ot("unc_finish%s\n", ms?"":":");
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264 ot(" ;@ set a-line and f-line handlers\n");
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265 ot(" add r0,r7,#0xa000*4\n");
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266 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");
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267 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");
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268 ot(" mov r2,#0x1000\n");
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269 ot("unc_fill3%s\n", ms?"":":");
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270 ot(" subs r2,r2,#1\n");
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271 ot(" str r1,[r0],#4\n");
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272 ot(" bgt unc_fill3\n");
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273 ot(" add r0,r7,#0xf000*4\n");
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274 ot(" mov r2,#0x1000\n");
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275 ot("unc_fill4%s\n", ms?"":":");
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276 ot(" subs r2,r2,#1\n");
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277 ot(" str r3,[r0],#4\n");
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278 ot(" bgt unc_fill4\n");
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279 ot(" ldmfd sp!,{r7,pc}\n");
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282 ot(";@ fix final jumptable entries\n");
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283 ot(" add r0,r0,#0x10000*4\n");
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284 ot(" ldr r1,[r0,#-3*4]\n");
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285 ot(" str r1,[r0,#-2*4]\n");
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286 ot(" str r1,[r0,#-1*4]\n");
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292 ot("CycloneResetJT%s\n", ms?"":":");
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293 ot(" stmfd sp!,{r7,lr}\n");
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294 ot(" mov r7,r0\n");
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295 ot(" str r1,[r7,#0x54] ;@ save CycloneJumpTab avoid literal pools\n");
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296 ot(" mov r0,#0\n");
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297 ot(" str r0,[r7,#0x58] ;@ state_flags\n");
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298 ot(" str r0,[r7,#0x48] ;@ OSP\n");
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299 ot(" mov r1,#0x27 ;@ Supervisor mode\n");
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300 ot(" strb r1,[r7,#0x44] ;@ set SR high\n");
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301 ot(" strb r0,[r7,#0x47] ;@ IRQ\n");
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303 ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");
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304 ot(" mov r0,#0\n");
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305 ot(" str r0,[r7,#0x60] ;@ Membase\n");
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306 ot(" mov r0,#4\n");
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308 #ifdef MEMHANDLERS_DIRECT_PREFIX
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309 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
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311 ot(" mov lr,pc\n");
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312 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
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314 ot(" str r0,[r7,#0x40] ;@ PC + base\n");
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315 ot(" ldmfd sp!,{r7,pc}\n");
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319 ot("CycloneSetRealTAS_JT%s\n", ms?"":":");
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320 #if (CYCLONE_FOR_GENESIS == 2)
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321 ot(" tst r0,r0\n");
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322 ot(" add r12,r1,#0x4a00*4\n");
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323 ot(" add r12,r12,#0x00d0*4\n");
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324 ot(" adr r2,CycloneOT_TAS_\n");
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325 ot(" addeq r2,r2,#%lu*4\n", sizeof(tas_ops) / sizeof(tas_ops[0]));
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328 ot(" mov r1,#8\n");
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329 ot("setrtas_loop0%s ;@ 4ad0-4ad7\n",ms?"":":");
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330 ot(" subs r1,r1,#1\n");
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331 ot(" str r0,[r12],#4\n");
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332 ot(" bne setrtas_loop0\n");
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335 ot(" mov r1,#7\n");
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336 ot("setrtas_loop1%s ;@ 4ad8-4ade\n",ms?"":":");
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337 ot(" subs r1,r1,#1\n");
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338 ot(" str r0,[r12],#4\n");
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339 ot(" bne setrtas_loop1\n");
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342 ot(" str r0,[r12],#4\n");
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344 ot(" mov r1,#7\n");
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345 ot("setrtas_loop2%s ;@ 4ae0-4ae6\n",ms?"":":");
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346 ot(" subs r1,r1,#1\n");
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347 ot(" str r0,[r12],#4\n");
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348 ot(" bne setrtas_loop2\n");
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351 ot(" str r0,[r12],#4\n");
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353 ot(" mov r1,#8\n");
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354 ot("setrtas_loop3%s ;@ 4ae8-4aef\n",ms?"":":");
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355 ot(" subs r1,r1,#1\n");
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356 ot(" str r0,[r12],#4\n");
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357 ot(" bne setrtas_loop3\n");
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360 ot(" mov r1,#8\n");
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361 ot("setrtas_loop4%s ;@ 4af0-4af7\n",ms?"":":");
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362 ot(" subs r1,r1,#1\n");
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363 ot(" str r0,[r12],#4\n");
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364 ot(" bne setrtas_loop4\n");
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367 ot(" str r0,[r12],#4\n");
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369 ot(" str r0,[r12],#4\n");
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375 // offset table to avoid .text relocations (forbidden by Android and iOS)
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376 #if (CYCLONE_FOR_GENESIS == 2)
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377 ot("CycloneOT_TAS_%s\n", ms?"":":"); // working TAS (no MD bug)
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378 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)
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379 ot(" %s %s_-CycloneOT_TAS_\n", ms?"dcd":".long", tas_ops[i]);
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380 ot("CycloneOT_TAS%s\n", ms?"":":"); // broken TAS
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381 for (size_t i = 0; i < sizeof(tas_ops) / sizeof(tas_ops[0]); i++)
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382 ot(" %s %s-CycloneOT_TAS\n", ms?"dcd":".long", tas_ops[i]);
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387 // 68k: XNZVC, ARM: NZCV
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388 ot("CycloneSetSr%s\n", ms?"":":");
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389 ot(" mov r2,r1,lsr #8\n");
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390 // ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");
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391 // ot(" eor r3,r3,r2\n");
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392 // ot(" tst r3,#0x20\n");
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394 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");
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396 ot(" and r2,r2,#0x27 ;@ only defined bits\n");
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398 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");
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399 ot(" mov r2,r1,lsl #25\n");
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400 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");
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401 ot(" bic r2,r1,#0xf3\n");
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402 ot(" tst r1,#1\n");
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403 ot(" orrne r2,r2,#2\n");
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404 ot(" tst r1,#2\n");
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405 ot(" orrne r2,r2,#1\n");
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406 ot(" strb r2,[r0,#0x46] ;@ flags\n");
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411 ot("CycloneGetSr%s\n", ms?"":":");
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412 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");
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413 ot(" bic r2,r1,#0xf3\n");
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414 ot(" tst r1,#1\n");
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415 ot(" orrne r2,r2,#2\n");
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416 ot(" tst r1,#2\n");
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417 ot(" orrne r2,r2,#1\n");
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418 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");
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419 ot(" tst r1,#0x20000000\n");
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420 ot(" orrne r2,r2,#0x10\n");
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421 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");
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422 ot(" orr r0,r2,r1,lsl #8\n");
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427 ot("CyclonePack%s\n", ms?"":":");
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428 ot(" stmfd sp!,{r4,r5,lr}\n");
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429 ot(" mov r4,r0\n");
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430 ot(" mov r5,r1\n");
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431 ot(" mov r3,#16\n");
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432 ot(";@ 0x00-0x3f: DA registers\n");
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433 ot("c_pack_loop%s\n",ms?"":":");
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434 ot(" ldr r1,[r0],#4\n");
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435 ot(" subs r3,r3,#1\n");
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436 ot(" str r1,[r5],#4\n");
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437 ot(" bne c_pack_loop\n");
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438 ot(";@ 0x40: PC\n");
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439 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");
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440 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");
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441 ot(" sub r0,r0,r1\n");
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442 ot(" str r0,[r5],#4\n");
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443 ot(";@ 0x44: SR\n");
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444 ot(" mov r0,r4\n");
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445 ot(" bl CycloneGetSr\n");
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446 ot(" strh r0,[r5],#2\n");
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447 ot(";@ 0x46: IRQ level\n");
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448 ot(" ldrb r0,[r4,#0x47]\n");
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449 ot(" strb r0,[r5],#2\n");
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450 ot(";@ 0x48: other SP\n");
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451 ot(" ldr r0,[r4,#0x48]\n");
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452 ot(" str r0,[r5],#4\n");
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453 ot(";@ 0x4c: CPU state flags\n");
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454 ot(" ldr r0,[r4,#0x58]\n");
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455 ot(" str r0,[r5],#4\n");
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456 ot(" ldmfd sp!,{r4,r5,pc}\n");
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460 ot("CycloneUnpack%s\n", ms?"":":");
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461 ot(" stmfd sp!,{r5,r7,lr}\n");
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462 ot(" mov r7,r0\n");
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463 ot(" movs r5,r1\n");
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464 ot(" beq c_unpack_do_pc\n");
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465 ot(" mov r3,#16\n");
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466 ot(";@ 0x00-0x3f: DA registers\n");
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467 ot("c_unpack_loop%s\n",ms?"":":");
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468 ot(" ldr r1,[r5],#4\n");
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469 ot(" subs r3,r3,#1\n");
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470 ot(" str r1,[r0],#4\n");
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471 ot(" bne c_unpack_loop\n");
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472 ot(";@ 0x40: PC\n");
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473 ot(" ldr r0,[r5],#4 ;@ PC\n");
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474 ot(" str r0,[r7,#0x40] ;@ handle later\n");
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475 ot(";@ 0x44: SR\n");
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476 ot(" ldrh r1,[r5],#2\n");
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477 ot(" mov r0,r7\n");
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478 ot(" bl CycloneSetSr\n");
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479 ot(";@ 0x46: IRQ level\n");
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480 ot(" ldrb r0,[r5],#2\n");
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481 ot(" strb r0,[r7,#0x47]\n");
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482 ot(";@ 0x48: other SP\n");
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483 ot(" ldr r0,[r5],#4\n");
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484 ot(" str r0,[r7,#0x48]\n");
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485 ot(";@ 0x4c: CPU state flags\n");
\r
486 ot(" ldr r0,[r5],#4\n");
\r
487 ot(" str r0,[r7,#0x58]\n");
\r
488 ot("c_unpack_do_pc%s\n",ms?"":":");
\r
489 ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");
\r
490 #if USE_CHECKPC_CALLBACK
\r
491 ot(" mov r1,#0\n");
\r
492 ot(" str r1,[r7,#0x60] ;@ Memory base\n");
\r
493 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
494 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
496 ot(" mov lr,pc\n");
\r
497 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
500 ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");
\r
501 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");
\r
503 ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");
\r
504 ot(" ldmfd sp!,{r5,r7,pc}\n");
\r
508 ot("CycloneFlushIrq%s\n", ms?"":":");
\r
509 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");
\r
510 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]
\r
511 ot(" cmp r2,#6 ;@ irq>6 ?\n");
\r
512 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
513 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
514 ot(" movle r0,#0\n");
\r
515 ot(" bxle lr ;@ no ints\n");
\r
517 ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
518 ot(" mov r7,r0\n");
\r
519 ot(" mov r0,r2\n");
\r
520 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");
\r
521 ot(" mov r5,#0\n");
\r
522 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");
\r
523 ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");
\r
524 ot(" adr r2,CycloneFlushIrqEnd\n");
\r
525 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");
\r
526 ot(" b CycloneDoInterrupt\n");
\r
528 ot("CycloneFlushIrqEnd%s\n", ms?"":":");
\r
529 ot(" rsb r0,r5,#0\n");
\r
530 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");
\r
531 ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
532 ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");
\r
538 ot(";@ DoInterrupt - r0=IRQ level\n");
\r
539 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");
\r
540 ot(" sub r4,r4,#2\n");
\r
541 ot("CycloneDoInterrupt%s\n", ms?"":":");
\r
542 ot(" bic r8,r8,#0xff000000\n");
\r
543 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");
\r
545 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4
\r
546 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html
\r
547 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
548 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
549 ot(" and r0,r0,#7\n");
\r
550 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");
\r
551 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
552 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
553 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
555 ot(" str r2,[r7,#0x58]\n");
\r
556 ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
557 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
560 // 3. Save the current processor context.
\r
561 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
562 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");
\r
563 ot(" tst r6,#0x20\n");
\r
564 ot(";@ get our SP:\n");
\r
565 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
566 ot(" streq r11,[r7,#0x48]\n");
\r
567 ot(" moveq r11,r2\n");
\r
568 ot(";@ Push old PC onto stack\n");
\r
569 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");
\r
570 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
572 ot(";@ Push old SR:\n");
\r
573 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
574 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
575 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
576 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
577 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
578 ot(" and r0,r0,#0x20000000\n");
\r
579 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
580 ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");
\r
581 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");
\r
582 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
583 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler
\r
586 // 2. Obtain the exception vector.
\r
587 ot(" mov r11,r8,lsr #29\n");
\r
588 ot(" mov r0,r11\n");
\r
589 #if USE_INT_ACK_CALLBACK
\r
590 ot(";@ call IrqCallback if it is defined\n");
\r
591 #if INT_ACK_NEEDS_STUFF
\r
592 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
593 ot(" mov r1,r10,lsr #28\n");
\r
594 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
595 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
597 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");
\r
598 ot(" add lr,pc,#4*3\n");
\r
599 ot(" tst r3,r3\n");
\r
600 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");
\r
601 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");
\r
603 #if INT_ACK_CHANGES_CYCLES
\r
604 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
606 ot(";@ get IRQ vector address:\n");
\r
607 ot(" cmn r0,#1 ;@ returned -1?\n");
\r
608 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");
\r
609 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2
\r
610 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");
\r
611 #else // !USE_INT_ACK_CALLBACK
\r
612 ot(";@ Clear irq:\n");
\r
613 ot(" mov r2,#0\n");
\r
614 ot(" strb r2,[r7,#0x47]\n");
\r
615 ot(" add r0,r0,#0x18 ;@ use autovector\n");
\r
617 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");
\r
619 ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");
\r
620 ot(";@ Read IRQ Vector:\n");
\r
621 MemHandler(0,2,0,0);
\r
622 ot(" tst r0,r0 ;@ uninitialized int vector?\n");
\r
623 ot(" moveq r0,#0x3c\n");
\r
624 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
625 ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);
\r
627 ot(" moveq lr,pc\n");
\r
628 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");
\r
630 #if USE_CHECKPC_CALLBACK
\r
631 ot(" add lr,pc,#4\n");
\r
632 ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");
\r
633 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
634 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
636 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
638 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
639 ot(" mov r4,r0\n");
\r
641 ot(" bic r4,r0,#1\n");
\r
644 ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");
\r
645 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
646 ot(" bic r4,r4,#1\n");
\r
651 // 4. Obtain a new context and resume instruction processing.
\r
652 // note: the obtain part was already done in previous steps
\r
653 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
654 ot(" tst r4,#1\n");
\r
655 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
657 ot(" ldr r6,[r7,#0x54]\n");
\r
658 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
659 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");
\r
660 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
661 ot(" b CycloneEnd\n");
\r
665 // trashes all temp regs
\r
666 ot("Exception%s\n", ms?"":":");
\r
667 ot(" ;@ Cause an Exception - Vector number in r0\n");
\r
668 ot(" mov r11,lr ;@ Preserve ARM return address\n");
\r
669 ot(" bic r8,r8,#0xff000000\n");
\r
670 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");
\r
672 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
673 ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");
\r
674 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
675 ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");
\r
676 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
677 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
678 ot(" str r2,[r7,#0x58]\n");
\r
679 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
682 // 3. Save the current processor context.
\r
683 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
684 ot(" tst r6,#0x20\n");
\r
685 ot(";@ get our SP:\n");
\r
686 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
687 ot(" streq r0,[r7,#0x48]\n");
\r
688 ot(" moveq r0,r2\n");
\r
689 ot(";@ Push old PC onto stack\n");
\r
690 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
691 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
692 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
693 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
695 ot(";@ Push old SR:\n");
\r
696 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
697 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");
\r
698 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
699 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
700 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
701 ot(" and r0,r0,#0x20000000\n");
\r
702 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
703 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
704 ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");
\r
705 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
706 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
707 MemHandler(1,1,0,0);
\r
710 // 2. Obtain the exception vector
\r
711 ot(";@ Read Exception Vector:\n");
\r
712 ot(" mov r0,r8,lsr #24\n");
\r
713 ot(" mov r0,r0,lsl #2\n");
\r
714 MemHandler(0,2,0,0);
\r
715 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
716 #if USE_CHECKPC_CALLBACK
\r
717 ot(" add lr,pc,#4\n");
\r
718 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
719 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
720 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
722 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
724 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
725 ot(" mov r4,r0\n");
\r
727 ot(" bic r4,r0,#1\n");
\r
730 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
731 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
732 ot(" bic r4,r4,#1\n");
\r
737 // 4. Resume execution.
\r
738 #if EMULATE_ADDRESS_ERRORS_JUMP
\r
739 ot(" tst r4,#1\n");
\r
740 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
742 ot(" ldr r6,[r7,#0x54]\n");
\r
743 ot(" bx r11 ;@ Return\n");
\r
747 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
748 // first some wrappers: I see no point inlining this code,
\r
749 // as it will be executed in really rare cases.
\r
750 AddressErrorWrapper('r', "data", 0x11);
\r
751 AddressErrorWrapper('r', "prg", 0x12);
\r
752 AddressErrorWrapper('w', "data", 0x01);
\r
753 // there are no program writes
\r
754 // cpu space is only for bus errors?
\r
755 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");
\r
756 ot(" ldr r1,[r7,#0x44]\n");
\r
757 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
758 ot(" mov r6,#0x12\n");
\r
759 ot(" sub r11,r4,r3\n");
\r
760 ot(" tst r1,#0x20\n");
\r
761 ot(" orrne r6,r6,#4\n");
\r
764 ot("ExceptionAddressError%s\n", ms?"":":");
\r
765 ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");
\r
767 // 1. Make a temporary copy of the status register and set the status register for exception processing.
\r
768 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");
\r
769 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");
\r
770 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");
\r
771 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");
\r
772 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");
\r
773 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");
\r
774 ot(" tst r2,#4\n");
\r
775 ot(" orrne r6,r6,#8 ;@ complete info word\n");
\r
776 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
778 ot(" tst r2,#8\n");
\r
779 ot(" orrne r2,r2,#0x10 ;@ HALT\n");
\r
780 ot(" orr r2,r2,#8 ;@ processing address error\n");
\r
781 ot(" str r2,[r7,#0x58]\n");
\r
782 ot(" movne r5,#0\n");
\r
783 ot(" bne CycloneEndNoBack ;@ bye bye\n");
\r
785 ot(" str r2,[r7,#0x58]\n");
\r
787 ot(" and r10,r10,#0xf0000000\n");
\r
788 ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");
\r
791 // 3. Save the current processor context + additional information.
\r
792 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");
\r
793 ot(" tst r10,#0x200\n");
\r
794 ot(";@ get our SP:\n");
\r
795 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");
\r
796 ot(" streq r0,[r7,#0x48]\n");
\r
797 ot(" moveq r0,r2\n");
\r
799 ot(";@ Push old PC onto stack\n");
\r
800 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");
\r
801 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");
\r
802 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");
\r
803 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
804 MemHandler(1,2,0,EMULATE_HALT);
\r
806 ot(";@ Push old SR:\n");
\r
807 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");
\r
808 ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");
\r
809 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");
\r
810 ot(" tst r2,#1 ;@ 1 if C!=V\n");
\r
811 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");
\r
812 ot(" and r0,r0,#0x20000000\n");
\r
813 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");
\r
814 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
815 ot(" and r10,r10,#0xf0000000\n");
\r
816 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
817 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
818 MemHandler(1,1,0,0);
\r
819 // IR (instruction register)
\r
820 ot(";@ Push IR:\n");
\r
821 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
822 ot(" mov r1,r8\n");
\r
823 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
824 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
825 MemHandler(1,1,0,0);
\r
827 ot(";@ Push address:\n");
\r
828 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
829 ot(" mov r1,r11\n");
\r
830 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");
\r
831 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
832 MemHandler(1,2,0,0);
\r
833 // information word
\r
834 ot(";@ Push info word:\n");
\r
835 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");
\r
836 ot(" mov r1,r6\n");
\r
837 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");
\r
838 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");
\r
839 MemHandler(1,1,0,0);
\r
842 // 2. Obtain the exception vector
\r
843 ot(";@ Read Exception Vector:\n");
\r
844 ot(" mov r0,#0x0c\n");
\r
845 MemHandler(0,2,0,0);
\r
846 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");
\r
847 #if USE_CHECKPC_CALLBACK
\r
848 ot(" add lr,pc,#4\n");
\r
849 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");
\r
850 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
851 ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);
\r
853 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");
\r
855 ot(" mov r4,r0\n");
\r
857 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");
\r
861 #if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT
\r
862 ot(" tst r4,#1\n");
\r
863 ot(" bne ExceptionAddressError_r_prg_r4\n");
\r
865 ot(" bic r4,r4,#1\n");
\r
868 // 4. Resume execution.
\r
869 ot(" ldr r6,[r7,#0x54]\n");
\r
870 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
871 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");
\r
872 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
873 ot(" b CycloneEnd\n");
\r
879 // expects srh and irq level in r1, next opcode already fetched to r8
\r
880 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");
\r
881 ot(" ldr r0,[r7,#0x58]\n");
\r
882 ot(" cmp r5,#0\n");
\r
883 ot(" orr r0,r0,#2 ;@ go to trace mode\n");
\r
884 ot(" str r0,[r7,#0x58]\n");
\r
885 ot(" ble CycloneEnd\n"); // should take care of situation where we come here when already tracing
\r
886 ot(";@ CheckInterrupt:\n");
\r
887 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");
\r
888 ot(" beq CycloneDoTrace\n");
\r
889 ot(" cmp r0,#6 ;@ irq>6 ?\n");
\r
890 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");
\r
891 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");
\r
892 ot(" bgt CycloneDoInterruptGoBack\n");
\r
895 // expects next opcode to be already fetched to r8
\r
896 ot("CycloneDoTrace%s\n", ms?"":":");
\r
897 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");
\r
898 ot(" ldr r1,[r7,#0x98]\n");
\r
899 ot(" mov r5,#0\n");
\r
900 ot(" str r1,[r7,#0xa0]\n");
\r
901 ot(" adr r0,TraceEnd\n");
\r
902 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");
\r
903 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
906 ot("TraceEnd%s\n", ms?"":":");
\r
907 ot(" ldr r2,[r7,#0x58]\n");
\r
908 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");
\r
909 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");
\r
910 ot(" mov r10,r10,lsl #28\n");
\r
911 ot(" add r5,r0,r5\n");
\r
912 ot(" str r1,[r7,#0x98]\n");
\r
913 ot(";@ still tracing?\n"); // exception might have happend
\r
914 ot(" tst r2,#2\n");
\r
915 ot(" beq TraceDisabled\n");
\r
916 ot(";@ trace exception\n");
\r
917 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
918 ot(" ldr r1,[r7,#0x58]\n");
\r
919 ot(" mov r0,#9\n");
\r
920 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
921 ot(" str r1,[r7,#0x58]\n");
\r
923 ot(" mov r0,#9\n");
\r
925 ot(" bl Exception\n");
\r
926 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
927 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");
\r
928 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
929 ot(" b CycloneEnd\n");
\r
931 ot("TraceDisabled%s\n", ms?"":":");
\r
932 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");
\r
933 ot(" cmp r5,#0\n");
\r
934 ot(" ldrgt pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");
\r
935 ot(" b CycloneEnd\n");
\r
940 // ---------------------------------------------------------------------------
\r
941 // Call Read(r0), Write(r0,r1) or Fetch(r0)
\r
942 // Trashes r0-r3,r12,lr
\r
943 int MemHandler(int type,int size,int addrreg,int need_addrerr_check)
\r
945 int func=0x68+type*0xc+(size<<2); // Find correct offset
\r
948 #if MEMHANDLERS_NEED_FLAGS
\r
949 ot(" mov r3,r10,lsr #28\n");
\r
950 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
954 #if (MEMHANDLERS_ADDR_MASK & 0xff000000)
\r
955 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);
\r
958 #if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)
\r
959 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);
\r
962 #if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)
\r
963 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);
\r
966 #if (MEMHANDLERS_ADDR_MASK & 0x000000ff)
\r
967 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);
\r
971 #if EMULATE_ADDRESS_ERRORS_IO
\r
972 if (size > 0 && need_addrerr_check)
\r
974 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks
\r
975 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);
\r
976 ot(" tst r0,#1 ;@ address error?\n");
\r
978 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;
\r
979 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;
\r
980 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;
\r
986 sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);
\r
987 #ifdef MEMHANDLERS_DIRECT_PREFIX
\r
989 ot(" mov r0,r%i\n", addrreg);
\r
990 ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);
\r
991 (void)func; // avoid warning
\r
995 ot(" add lr,pc,#4\n");
\r
996 ot(" mov r0,r%i\n", addrreg);
\r
999 ot(" mov lr,pc\n");
\r
1000 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);
\r
1003 // Document what we are calling:
\r
1004 if (type==1) ot("%s(r0,r1)",what);
\r
1005 else ot("%s(r0)", what);
\r
1008 #if MEMHANDLERS_CHANGE_FLAGS
\r
1009 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1010 ot(" mov r10,r10,lsl #28\n");
\r
1012 #if MEMHANDLERS_CHANGE_PC
\r
1013 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1019 static void PrintOpcodes()
\r
1023 printf("Creating Opcodes: [");
\r
1025 ot(";@ ---------------------------- Opcodes ---------------------------\n");
\r
1027 // Emit null opcode:
\r
1028 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");
\r
1029 #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO
\r
1030 ot(" ldr r1,[r7,#0x58]\n");
\r
1031 ot(" sub r4,r4,#2\n");
\r
1032 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");
\r
1033 ot(" str r1,[r7,#0x58]\n");
\r
1035 ot(" sub r4,r4,#2\n");
\r
1037 #if USE_UNRECOGNIZED_CALLBACK
\r
1038 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1039 ot(" mov r1,r10,lsr #28\n");
\r
1040 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1041 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1042 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1043 ot(" tst r11,r11\n");
\r
1044 ot(" movne lr,pc\n");
\r
1045 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1046 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1047 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1048 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1049 ot(" mov r10,r10,lsl #28\n");
\r
1050 ot(" tst r0,r0\n");
\r
1051 ot(" moveq r0,#4\n");
\r
1052 ot(" bleq Exception\n");
\r
1054 ot(" mov r0,#4\n");
\r
1055 ot(" bl Exception\n");
\r
1061 // Unrecognised a-line and f-line opcodes throw an exception:
\r
1062 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");
\r
1063 ot(" sub r4,r4,#2\n");
\r
1064 #if USE_AFLINE_CALLBACK
\r
1065 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1066 ot(" mov r1,r10,lsr #28\n");
\r
1067 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1068 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1069 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1070 ot(" tst r11,r11\n");
\r
1071 ot(" movne lr,pc\n");
\r
1072 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1073 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1074 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1075 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1076 ot(" mov r10,r10,lsl #28\n");
\r
1077 ot(" tst r0,r0\n");
\r
1078 ot(" moveq r0,#0x0a\n");
\r
1079 ot(" bleq Exception\n");
\r
1081 ot(" mov r0,#0x0a\n");
\r
1082 ot(" bl Exception\n");
\r
1088 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");
\r
1089 ot(" sub r4,r4,#2\n");
\r
1090 #if USE_AFLINE_CALLBACK
\r
1091 ot(" str r4,[r7,#0x40] ;@ Save PC\n");
\r
1092 ot(" mov r1,r10,lsr #28\n");
\r
1093 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");
\r
1094 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");
\r
1095 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");
\r
1096 ot(" tst r11,r11\n");
\r
1097 ot(" movne lr,pc\n");
\r
1098 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");
\r
1099 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");
\r
1100 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
\r
1101 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");
\r
1102 ot(" mov r10,r10,lsl #28\n");
\r
1103 ot(" tst r0,r0\n");
\r
1104 ot(" moveq r0,#0x0b\n");
\r
1105 ot(" bleq Exception\n");
\r
1107 ot(" mov r0,#0x0b\n");
\r
1108 ot(" bl Exception\n");
\r
1115 for (op=0;op<hot_opcode_count;op++)
\r
1116 OpAny(hot_opcodes[op]);
\r
1118 for (op=0;op<0x10000;op++)
\r
1120 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress
\r
1122 if (!is_op_hot(op))
\r
1132 static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)
\r
1135 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;
\r
1136 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;
\r
1137 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;
\r
1140 if((counter&7)==7) ot(nl,nlp); else ot(",");
\r
1143 static void PrintJumpTable()
\r
1145 int i=0,op=0,len=0;
\r
1147 ot(";@ -------------------------- Jump Table --------------------------\n");
\r
1149 // space for decompressed table
\r
1150 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");
\r
1152 #if COMPRESS_JUMPTABLE
\r
1153 int handlers=0,reps=0,*indexes,ip,u,out;
\r
1154 // use some weird compression on the jump table
\r
1155 indexes=(int *)malloc(0x10000*4);
\r
1156 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }
\r
1159 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1161 for(i = 0; i < 0xa000/8; i++)
\r
1162 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1164 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);
\r
1166 // hanlers live in "a-line" part of the table
\r
1167 // first output nop,a-line,f-line handlers
\r
1168 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");
\r
1171 for(i=0;i<len;i++)
\r
1175 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?
\r
1176 if(u==-1 && op >= 0) {
\r
1177 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);
\r
1178 indexes[op] = handlers;
\r
1183 fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1184 for(i = 8-(handlers&7); i > 0; i--)
\r
1189 for(i = (0x4000-handlers)/8; i > 0; i--)
\r
1190 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1192 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);
\r
1194 printf("total distinct hanlers: %i\n",handlers);
\r
1196 for(i=0,ip=0; i < 0xf000; i++, ip++) {
\r
1199 // it must skip a-line area, because we keep our data there
\r
1200 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);
\r
1201 ott("0x%.4x", 0x1000, "\n",0,ip,1);
\r
1205 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;
\r
1206 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised
\r
1207 if(reps <= 0xe || reps==0x10) {
\r
1208 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)
\r
1209 ott("0x%.4x", out, "\n",0,ip,1);
\r
1211 ott("0x%.4x", out, "\n",0,ip++,1);
\r
1212 ott("0x%.4x", reps,"\n",0,ip,1);
\r
1215 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);
\r
1216 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1218 for(i = 8-(ip&7); i > 0; i--)
\r
1223 for(i = (0x2000-ip/2)/8+1; i > 0; i--)
\r
1224 ot(" dcd 0,0,0,0,0,0,0,0\n");
\r
1226 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);
\r
1231 ot("CycloneJumpTab%s\n", ms?"":":");
\r
1232 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table
\r
1233 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)
\r
1234 // this is due to COFF objects using only 2 bytes for reloc count
\r
1236 for (i=0;i<len;i++)
\r
1240 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);
\r
1241 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);
\r
1242 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);
\r
1243 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);
\r
1245 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma
\r
1248 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");
\r
1249 ot(";@ so we leave this pattern to patch it later\n");
\r
1250 ot("%s 0x78563412\n", ms?" dcd":" .long");
\r
1251 ot("%s 0x56341290\n", ms?" dcd":" .long");
\r
1255 static int CycloneMake()
\r
1258 const char *name="Cyclone.s";
\r
1259 const char *globl=ms?"export":".global";
\r
1261 // Open the assembly file
\r
1262 if (ms) name="Cyclone.asm";
\r
1263 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;
\r
1265 printf("Making %s...\n",name);
\r
1267 ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1269 ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");
\r
1270 ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");
\r
1272 ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");
\r
1273 ot(";@ You can choose the license that has the most advantages for you.\n\n");
\r
1274 ot(";@ SVN repository can be found at http://code.google.com/p/cyclone68000/\n\n");
\r
1276 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;
\r
1277 memset(CyJump,0xff,0x40000); // Init to -1
\r
1278 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation
\r
1279 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation
\r
1281 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");
\r
1282 ot(" %s CycloneInitJT\n",globl);
\r
1283 ot(" %s CycloneResetJT\n",globl);
\r
1284 ot(" %s CycloneRun\n",globl);
\r
1285 ot(" %s CycloneSetSr\n",globl);
\r
1286 ot(" %s CycloneGetSr\n",globl);
\r
1287 ot(" %s CycloneFlushIrq\n",globl);
\r
1288 ot(" %s CyclonePack\n",globl);
\r
1289 ot(" %s CycloneUnpack\n",globl);
\r
1290 ot(" %s CycloneVer\n",globl);
\r
1291 ot(" %s CycloneJumpTab\n",globl);
\r
1292 #if (CYCLONE_FOR_GENESIS == 2)
\r
1293 ot(" %s CycloneSetRealTAS_JT\n",globl);
\r
1294 ot(" %s CycloneDoInterrupt\n",globl);
\r
1295 ot(" %s CycloneDoTrace\n",globl);
\r
1296 ot(" %s Op____\n",globl);
\r
1297 ot(" %s Op6002\n",globl);
\r
1298 ot(" %s Op6602\n",globl);
\r
1299 ot(" %s Op6702\n",globl);
\r
1302 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");
\r
1303 ot("%.4x\n",CycloneVer);
\r
1309 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);
\r
1312 if (ms) ot(" END\n");
\r
1314 ot("\n\n;@ vim:filetype=armasm\n");
\r
1316 fclose(AsmFile); AsmFile=NULL;
\r
1319 printf("Assembling...\n");
\r
1320 // Assemble the file
\r
1321 if (ms) system("armasm Cyclone.asm");
\r
1322 else system("as -o Cyclone.o Cyclone.s");
\r
1323 printf("Done!\n\n");
\r
1332 printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);
\r
1334 // Make GAS or ARMASM version
\r