2 // This file is part of the Cyclone 68000 Emulator
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4 // Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)
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5 // Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)
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7 // This code is licensed under the GNU General Public License version 2.0 and the MAME License.
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8 // You can choose the license that has the most advantages for you.
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10 // SVN repository can be found at http://code.google.com/p/cyclone68000/
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16 const char *TestCond(int m68k_cc, int invert)
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18 const char *cond="";
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19 const char *icond="";
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28 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");
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29 cond="eq", icond="ne";
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32 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");
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33 cond="ne", icond="eq";
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36 ot(" tst r10,#0x20000000 ;@ cc: !C\n");
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37 cond="eq", icond="ne";
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40 ot(" tst r10,#0x20000000 ;@ cs: C\n");
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41 cond="ne", icond="eq";
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44 ot(" tst r10,#0x40000000 ;@ ne: !Z\n");
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45 cond="eq", icond="ne";
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48 ot(" tst r10,#0x40000000 ;@ eq: Z\n");
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49 cond="ne", icond="eq";
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52 ot(" tst r10,#0x10000000 ;@ vc: !V\n");
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53 cond="eq", icond="ne";
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56 ot(" tst r10,#0x10000000 ;@ vs: V\n");
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57 cond="ne", icond="eq";
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60 ot(" tst r10,r10 ;@ pl: !N\n");
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61 cond="pl", icond="mi";
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64 ot(" tst r10,r10 ;@ mi: N\n");
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65 cond="mi", icond="pl";
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68 ot(" teq r10,r10,lsl #3 ;@ ge: N == V\n");
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69 cond="pl", icond="mi";
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72 ot(" teq r10,r10,lsl #3 ;@ lt: N != V\n");
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73 cond="mi", icond="pl";
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76 ot(" eor r0,r10,r10,lsl #3 ;@ gt: !Z && N == V\n");
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77 ot(" orrs r0,r10,lsl #1\n");
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78 cond="pl", icond="mi";
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81 ot(" eor r0,r10,r10,lsl #3 ;@ le: Z || N != V\n");
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82 ot(" orrs r0,r10,lsl #1\n");
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83 cond="mi", icond="pl";
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86 printf("invalid m68k_cc: %x\n", m68k_cc);
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90 return invert?icond:cond;
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93 // --------------------- Opcodes 0x0100+ ---------------------
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94 // Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa
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95 int OpBtstReg(int op)
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98 int type=0,sea=0,tea=0;
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101 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset
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102 // Get source and target EA
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105 if (tea<0x10) size=2; // For registers, 32-bits
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107 if ((tea&0x38)==0x08) return 1; // movep
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109 // See if we can do this opcode:
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110 if (EaCanRead(tea,0)==0) return 1;
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113 if (EaCanWrite(tea)==0) return 1;
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116 use=OpBase(op,size);
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117 use&=~0x0e00; // Use same handler for all registers
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118 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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122 if(type==1||type==3) {
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126 if(size>=2) Cycles+=2;
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129 EaCalcReadNoSE(-1,11,sea,0,0x0e00);
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131 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
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134 ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0
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135 else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2
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138 ot(" mov r1,#1\n");
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139 ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");
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140 ot(" bicne r10,r10,#0x40000000\n");
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141 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
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146 if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");
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147 if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");
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148 if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");
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150 EaWrite(8,1,tea,size,0x003f,0,0);
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157 // --------------------- Opcodes 0x0800+ ---------------------
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158 // Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn
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159 int OpBtstImm(int op)
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161 int type=0,sea=0,tea=0;
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166 // Get source and target EA
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169 if (tea<0x10) size=2; // For registers, 32-bits
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171 // See if we can do this opcode:
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172 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;
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175 if (EaCanWrite(tea)==0) return 1;
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178 use=OpBase(op,size);
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179 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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181 OpStart(op,sea,tea);
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184 EaCalcReadNoSE(-1,0,sea,0,0);
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185 ot(" mov r11,#1\n");
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186 ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");
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188 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0
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189 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2
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190 ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");
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193 if(type==1||type==3) {
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197 if(size>=2) Cycles+=2;
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200 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);
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201 ot(" tst r0,r11 ;@ Do arithmetic\n");
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202 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");
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207 if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");
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208 if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");
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209 if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");
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211 EaWrite(8, 1,tea,size,0x003f,0,0);
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212 #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES
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213 // this is a bit hacky (device handlers might modify cycles)
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214 if (tea==0x38||tea==0x39)
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215 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");
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224 // --------------------- Opcodes 0x4000+ ---------------------
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227 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)
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228 int type=0,size=0,ea=0,use=0;
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232 size=(op>>6)&3; if (size>=3) return 1;
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234 // See if we can do this opcode:
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235 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;
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236 if (EaCanWrite(ea )==0) return 1;
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238 use=OpBase(op,size);
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239 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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241 OpStart(op,ea); Cycles=size<2?4:6;
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242 if(ea >= 0x10) Cycles*=2;
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244 EaCalc (11,0x003f,ea,size,0,0);
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246 if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)
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247 if (type==1) ot("\n");
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253 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
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254 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");
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255 ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");
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258 ot(" movs r1,r1,asr #%i\n",size?16:24);
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259 ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");
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261 ot(" andeq r10,r10,r3 ;@ fix Z\n");
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268 ot(" mov r1,#0\n");
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269 ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");
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276 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);
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277 ot(" rsbs r1,r0,#0\n");
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279 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);
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287 ot(" mov r0,r0,asl #%i\n",size?16:24);
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288 ot(" mvn r1,r0,asr #%i\n",size?16:24);
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291 ot(" mvn r1,r0\n");
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292 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
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297 if (type==1) eawrite_check_addrerr=1;
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298 EaWrite(11, 1,ea,size,0x003f,0,0);
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305 // --------------------- Opcodes 0x4840+ ---------------------
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306 // Swap, 01001000 01000nnn swap Dn
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312 use=op&~0x0007; // Use same opcode for all An
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314 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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316 OpStart(op); Cycles=4;
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318 EaCalc (11,0x0007,ea,2,1);
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319 EaRead (11, 0,ea,2,0x0007,1);
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321 ot(" mov r1,r0,ror #16\n");
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322 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
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325 EaWrite(11, 1,8,2,0x0007,1);
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332 // --------------------- Opcodes 0x4a00+ ---------------------
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333 // Emit a Tst opcode, 01001010 xxeeeeee
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340 size=(op>>6)&3; if (size>=3) return 1;
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342 // See if we can do this opcode:
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343 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;
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345 use=OpBase(op,size);
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346 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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348 OpStart(op,sea); Cycles=4;
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350 EaCalc ( 0,0x003f,sea,size,1);
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351 EaRead ( 0, 0,sea,size,0x003f,1);
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353 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
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354 ot(" mrs r10,cpsr ;@ r10=flags\n");
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361 // --------------------- Opcodes 0x4880+ ---------------------
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362 // Emit an Ext opcode, 01001000 1x000nnn
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371 shift=32-(8<<size);
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373 use=OpBase(op,size);
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374 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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376 OpStart(op); Cycles=4;
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378 EaCalc (11,0x0007,ea,size+1,0,0);
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379 EaRead (11, 0,ea,size+1,0x0007,0,0);
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381 ot(" mov r0,r0,asl #%d\n",shift);
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382 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
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383 ot(" mrs r10,cpsr ;@ r10=flags\n");
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384 ot(" mov r1,r0,asr #%d\n",shift);
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387 EaWrite(11, 1,ea,size+1,0x0007,0,0);
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393 // --------------------- Opcodes 0x50c0+ ---------------------
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394 // Emit a Set cc opcode, 0101cccc 11eeeeee
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398 int size=0,use=0,changed_cycles=0;
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404 if ((ea&0x38)==0x08) return 1; // dbra, not scc
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406 // See if we can do this opcode:
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407 if (EaCanWrite(ea)==0) return 1;
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409 use=OpBase(op,size);
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410 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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412 changed_cycles=ea<8 && cc>=2;
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413 OpStart(op,ea,0,changed_cycles); Cycles=8;
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414 if (ea<8) Cycles=4;
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419 ot(" mvn r1,#0\n");
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420 if (ea<8) Cycles+=2;
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423 ot(" mov r1,#0\n");
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426 ot(" mov r1,#0\n");
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428 ot(" mvn%s r1,#0\n",cond);
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429 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond);
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435 eawrite_check_addrerr=1;
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436 EaCalc (0,0x003f, ea,size,0,0);
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437 EaWrite(0, 1, ea,size,0x003f,0,0);
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439 opend_op_changes_cycles=changed_cycles;
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444 // Emit a Asr/Lsr/Roxr/Ror opcode
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445 static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)
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447 char pct[8]=""; // count
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448 int shift=32-(8<<size);
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450 if (count>=1) sprintf(pct,"#%d",count); // Fixed count
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454 ot(";@ Use Dn for count:\n");
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455 ot(" and r2,r8,#0x0e00\n");
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456 ot(" ldr r2,[r7,r2,lsr #7]\n");
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457 ot(" and r2,r2,#63\n");
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463 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");
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464 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");
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467 // Take 2*n cycles:
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468 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");
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469 else Cycles+=count<<1;
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474 if (dir==0 && size<2)
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476 ot(";@ For shift right, use loworder bits for the operation:\n");
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477 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));
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481 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");
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483 ot(";@ Shift register:\n");
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484 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);
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485 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);
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488 if (usereg) { // store X only if count is not 0
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489 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);
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490 ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");
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491 ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");
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493 // count will never be 0 if we use immediate
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494 ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");
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498 if (dir==0 && size<2)
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500 ot(";@ restore after right shift:\n");
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501 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));
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503 ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");
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507 if (type==0 && dir) {
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508 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");
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509 ot(" mov r1,#0x80000000\n");
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510 ot(" ands r3,r3,r1,asr %s\n", pct);
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511 ot(" cmpne r3,r1,asr %s\n", pct);
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512 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this
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513 ot(" tsteq r1,#0x80000000\n");
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514 ot(" orrne r10,r10,#0x10000000\n");
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519 // --------------------------------------
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529 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);
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530 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));
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533 ot(" movs r0,r0,rrx\n");
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536 ot(" ldr r3,[r7,#0x4c]\n");
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537 ot(" movs r0,r0,lsl #1\n");
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539 ot(" tst r3,#0x20000000\n");
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540 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));
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541 ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");
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543 ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");
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551 ot(" subs r2,r2,#33\n");
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552 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);
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556 ot(";@ Reduce r2 until <0:\n");
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557 ot("Reduce_%.4x%s\n",op,ms?"":":");
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558 ot(" subs r2,r2,#%d\n",wide+1);
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559 ot(" bpl Reduce_%.4x\n",op);
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560 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);
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562 ot(" beq norotx_%.4x\n",op);
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566 if (usereg||count < 0)
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568 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);
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572 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);
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573 else ot(" mov r2,#%d\n",count);
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576 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);
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579 ot(";@ First get X bit (middle):\n");
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580 ot(" ldr r3,[r7,#0x4c]\n");
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581 ot(" rsb r1,r2,#%d\n",wide);
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582 ot(" and r3,r3,#0x20000000\n");
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583 ot(" mov r3,r3,lsr #29\n");
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584 ot(" mov r3,r3,lsl r1\n");
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586 ot(";@ Rotate bits:\n");
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587 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");
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588 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);
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589 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");
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592 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);
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593 OpGetFlags(0,!usereg);
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594 if (usereg) { // store X only if count is not 0
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595 ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");
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596 ot(" b nozerox%.4x\n",op);
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597 ot("norotx_%.4x%s\n",op,ms?"":":");
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598 ot(" ldr r2,[r7,#0x4c]\n");
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599 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");
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601 ot(" and r2,r2,#0x20000000\n");
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602 ot(" orr r10,r10,r2 ;@ C = old_X\n");
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603 ot("nozerox%.4x%s\n",op,ms?"":":");
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609 // --------------------------------------
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615 ot(";@ Mirror value in whole 32 bits:\n");
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616 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");
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617 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");
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621 ot(";@ Rotate register:\n");
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622 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0
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625 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);
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626 ot(" movs r0,r0,ror %s\n",pct);
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631 if (dir) ror=32-ror;
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632 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);
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638 ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");
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639 ot(";@ Get carry bit from bit 0:\n");
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642 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);
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643 ot(" tstne r0,#1 ;@ no, check bit 0\n");
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646 ot(" tst r0,#1\n");
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647 ot(" orrne r10,r10,#0x20000000\n");
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652 // --------------------------------------
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657 // Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn
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658 // (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)
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663 int size=0,usereg=0,type=0;
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668 if (size>=3) return 1; // use OpAsrEa()
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672 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8
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674 // Use the same opcode for target registers:
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677 // As long as count is not 8, use the same opcode for all shift counts:
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678 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }
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679 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn
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681 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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683 OpStart(op,ea,0,count<0); Cycles=size<2?6:8;
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685 EaCalc(11,0x0007, ea,size,1);
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686 EaRead(11, 0, ea,size,0x0007,1);
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688 EmitAsr(op,type,dir,count, size,usereg);
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690 EaWrite(11, 0, ea,size,0x0007,1);
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692 opend_op_changes_cycles = (count<0);
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698 // Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee
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699 int OpAsrEa(int op)
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701 int use=0,type=0,dir=0,ea=0,size=1;
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707 if (ea<0x10) return 1;
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708 // See if we can do this opcode:
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709 if (EaCanRead(ea,0)==0) return 1;
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710 if (EaCanWrite(ea)==0) return 1;
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712 use=OpBase(op,size);
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713 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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715 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2
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717 EaCalc (11,0x003f,ea,size,1);
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718 EaRead (11, 0,ea,size,0x003f,1);
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720 EmitAsr(op,type,dir,1,size,0);
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722 EaWrite(11, 0,ea,size,0x003f,1);
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728 int OpTas(int op, int gen_special)
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735 // See if we can do this opcode:
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736 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;
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739 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler
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741 if (!gen_special) OpStart(op,ea);
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743 ot("Op%.4x_%s\n", op, ms?"":":");
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746 if(ea>=8) Cycles+=10;
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748 EaCalc (11,0x003f,ea,0,1);
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749 EaRead (11, 1,ea,0,0x003f,1);
\r
751 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");
\r
755 #if CYCLONE_FOR_GENESIS
\r
756 // the original Sega hardware ignores write-back phase (to memory only)
\r
757 if (ea < 0x10 || gen_special) {
\r
759 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");
\r
761 EaWrite(11, 1,ea,0,0x003f,1);
\r
762 #if CYCLONE_FOR_GENESIS
\r
768 #if (CYCLONE_FOR_GENESIS == 2)
\r
769 if (!gen_special && ea >= 0x10) {
\r