\r
// Cyclone 68000 Emulator - Header File\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 GraÅžvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
+#ifndef __CYCLONE_H__\r
+#define __CYCLONE_H__\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
struct Cyclone\r
{\r
- unsigned int d[8]; // [r7,#0x00]\r
- unsigned int a[8]; // [r7,#0x20]\r
- unsigned int pc; // [r7,#0x40] Memory Base+PC\r
- unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
- unsigned char xc; // [r7,#0x45] Extend flag (____??X?)\r
- unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV)\r
- unsigned char irq; // [r7,#0x47] IRQ level\r
- unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
- unsigned int vector; // [r7,#0x50] IRQ vector (temporary)\r
- int pad1[3];\r
- int cycles; // [r7,#0x5c]\r
- int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
- unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] - Called to recalc Memory Base+pc\r
- unsigned char (*read8 )(unsigned int a); // [r7,#0x68]\r
- unsigned short (*read16 )(unsigned int a); // [r7,#0x6c]\r
- unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
+ unsigned int d[8]; // [r7,#0x00]\r
+ unsigned int a[8]; // [r7,#0x20]\r
+ unsigned int pc; // [r7,#0x40] Memory Base (.membase) + 68k PC\r
+ unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
+ unsigned char unused; // [r7,#0x45] Unused\r
+ unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
+ unsigned char irq; // [r7,#0x47] IRQ level\r
+ unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
+ unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r
+ unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)\r
+ unsigned int jumptab; // [r7,#0x54] Jump table pointer\r
+ int state_flags; // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt\r
+ int cycles; // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()\r
+ int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
+ unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc\r
+ unsigned int (*read8 )(unsigned int a); // [r7,#0x68]\r
+ unsigned int (*read16 )(unsigned int a); // [r7,#0x6c]\r
+ unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r
void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r
void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r
- unsigned char (*fetch8 )(unsigned int a); // [r7,#0x80]\r
- unsigned short (*fetch16)(unsigned int a); // [r7,#0x84]\r
- unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
+ unsigned int (*fetch8 )(unsigned int a); // [r7,#0x80]\r
+ unsigned int (*fetch16)(unsigned int a); // [r7,#0x84]\r
+ unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
+ int (*IrqCallback)(int int_level); // [r7,#0x8c] optional irq callback function, see config.h\r
+ void (*ResetCallback)(void); // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.\r
+ int (*UnrecognizedCallback)(void); // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r
+ unsigned int internal[6]; // [r7,#0x98] reserved for internal use, do not change.\r
};\r
\r
+// Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h\r
+void CycloneInit(void);\r
+\r
+// Reset\r
+void CycloneReset(struct Cyclone *pcy);\r
+\r
+// Run cyclone. Cycles should be specified in context (pcy->cycles)\r
void CycloneRun(struct Cyclone *pcy);\r
\r
+// Utility functions to get and set SR\r
+void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
+unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
+\r
+// Generates irq exception if needed (if pcy->irq > mask).\r
+// Returns cycles used for exception if it was generated, 0 otherwise.\r
+int CycloneFlushIrq(struct Cyclone *pcy);\r
+\r
+// Functions for saving and restoring state.\r
+// CycloneUnpack() uses checkpc(), so it must be initialized.\r
+// save_buffer must point to buffer of 128 (0x80) bytes of size.\r
+void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
+void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
+\r
+// genesis: if 1, switch to normal TAS handlers\r
+void CycloneSetRealTAS(int use_real);\r
+\r
+\r
+// These values are special return values for IrqCallback.\r
+\r
+// Causes an interrupt autovector (0x18 + interrupt level) to be taken.\r
+// This happens in a real 68K if VPA or AVEC is asserted during an interrupt\r
+// acknowledge cycle instead of DTACK (the most common situation).\r
+#define CYCLONE_INT_ACK_AUTOVECTOR -1\r
+\r
+// Causes the spurious interrupt vector (0x18) to be taken\r
+// This happens in a real 68K if BERR is asserted during the interrupt\r
+// acknowledge cycle (i.e. no devices responded to the acknowledge).\r
+#define CYCLONE_INT_ACK_SPURIOUS -2\r
+\r
+\r
#ifdef __cplusplus\r
} // End of extern "C"\r
#endif\r
+\r
+#endif // __CYCLONE_H__\r
+\r
notaz.gp2x.de / cyclone68000.git / blobdiff