\r
// This file is part of the Cyclone 68000 Emulator\r
\r
-// Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\r
+// Copyright (c) 2005-2011 Gražvydas "notaz" Ignotas (notasas (at) gmail.com)\r
\r
// This code is licensed under the GNU General Public License version 2.0 and the MAME License.\r
// You can choose the license that has the most advantages for you.\r
\r
// SVN repository can be found at http://code.google.com/p/cyclone68000/\r
\r
+\r
#include "app.h"\r
\r
static FILE *AsmFile=NULL;\r
\r
-static int CycloneVer=0x0069; // Version number of library\r
+static int CycloneVer=0x0099; // Version number of library\r
int *CyJump=NULL; // Jump table\r
-int ms=0; // If non-zero, output in Microsoft ARMASM format\r
-char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
-char *Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
-int Cycles=0; // Current cycles for opcode\r
-int Amatch=1; // If one, try to match A68K timing\r
-int Accu=-1; // Accuracy\r
-int Debug=0; // Debug info\r
+int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
+const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
+const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
+int Cycles; // Current cycles for opcode\r
+int pc_dirty; // something changed PC during processing\r
+int arm_op_count;\r
+\r
+// opcodes often used by games\r
+static const unsigned short hot_opcodes[] = {\r
+ 0x6701, // beq $3\r
+ 0x6601, // bne $3\r
+ 0x51c8, // dbra Dn, $2\r
+ 0x4a38, // tst.b $0.w\r
+ 0xd040, // add.w Dn, Dn\r
+ 0x4a79, // tst.w $0.l\r
+ 0x0240, // andi.w #$0, D0\r
+ 0x2038, // move.l $0.w, D0\r
+ 0xb0b8, // cmp.l $0.w, D0\r
+ 0x6001, // bra $3\r
+ 0x30c0, // move.w D0, (A0)+\r
+ 0x3028, // move.w ($0,A0), D0\r
+ 0x0c40, // cmpi.w #$0, D0\r
+ 0x0c79, // cmpi.w #$0, $0.l\r
+ 0x4e75, // rts\r
+ 0x4e71, // nop\r
+ 0x3000, // move.w D0, D0\r
+ 0x0839, // btst #$0, $0.l\r
+ 0x7000, // moveq #$0, D0\r
+ 0x3040, // movea.w D0, A0\r
+ 0x0838, // btst #$0, $0.w\r
+ 0x4a39, // tst.b $0.l\r
+ 0x33d8, // move.w (A0)+, $0.l\r
+ 0x6700, // beq $2\r
+ 0xb038, // cmp.b $0.w, D0\r
+ 0x3039, // move.w $0.l, D0\r
+ 0x4840, // swap D0\r
+ 0x6101, // bsr $3\r
+ 0x6100, // bsr $2\r
+ 0x5e40, // addq.w #7, D0\r
+ 0x1039, // move.b $0.l, D0\r
+ 0x20c0, // move.l D0, (A0)+\r
+ 0x1018, // move.b (A0)+, D0\r
+ 0x30d0, // move.w (A0), (A0)+\r
+ 0x3080, // move.w D0, (A0)\r
+ 0x3018, // move.w (A0)+, D0\r
+ 0xc040, // and.w D0, D0\r
+ 0x3180, // move.w D0, (A0,D0.w)\r
+ 0x1198, // move.b (A0)+, (A0,D0.w)\r
+ 0x6501, // bcs $3\r
+ 0x6500, // bcs $2\r
+ 0x6401, // bcc $3\r
+ 0x6a01, // bpl $3\r
+ 0x41f0, // lea (A0,D0.w), A0\r
+ 0x4a28, // tst.b ($0,A0)\r
+ 0x0828, // btst #$0, ($0,A0)\r
+ 0x0640, // addi.w #$0, D0\r
+ 0x10c0, // move.b D0, (A0)+\r
+ 0x10d8, // move.b (A0)+, (A0)+\r
+};\r
+#define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r
+\r
+static int is_op_hot(int op)\r
+{\r
+ int i;\r
+ for (i = 0; i < hot_opcode_count; i++)\r
+ if (op == hot_opcodes[i])\r
+ return 1;\r
+ return 0;\r
+}\r
\r
void ot(const char *format, ...)\r
{\r
va_list valist;\r
+ int i, len;\r
+\r
+ // notaz: stop me from leaving newlines in the middle of format string\r
+ // and generating bad code\r
+ for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
+ if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
+\r
+ if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
+ arm_op_count++;\r
+\r
va_start(valist,format);\r
if (AsmFile) vfprintf(AsmFile,format,valist);\r
va_end(valist);\r
else ot(" .ltorg\n");\r
}\r
\r
-static void PrintException()\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+// r12=ptr to tas in table, trashes r0,r1\r
+static void ChangeTAS(int norm)\r
{\r
- ot(" ;@ Cause an Exception - Vector in [r7,#0x50]\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- OpPush32();\r
- OpPushSr(1);\r
- ot(" ldr r0,[r7,#0x50] ;@ Get Vector\n");\r
- ot(";@ Read IRQ Vector:\n");\r
- MemHandler(0,2);\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
- ot(" mov lr,pc\n");\r
- ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
- ot(" mov r4,r0\n");\r
- ot("\n");\r
-\r
- // todo - make Interrupt code use this function as well\r
+ ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i0\n",norm);\r
+ ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");\r
+ ot(" mov r1,#7\n");\r
+ ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i1\n",norm);\r
+ ot(" ldr r0,=Op4adf%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");\r
+ ot(" mov r1,#7\n");\r
+ ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i2\n",norm);\r
+ ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i3\n",norm);\r
+ ot(" ldr r0,=Op4af0%s\n",norm?"_":"");\r
+ ot(" mov r1,#8\n");\r
+ ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");\r
+ ot(" subs r1,r1,#1\n");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" bne setrtas_loop%i4\n",norm);\r
+ ot(" ldr r0,=Op4af8%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
+ ot(" ldr r0,=Op4af9%s\n",norm?"_":"");\r
+ ot(" str r0,[r12],#4\n");\r
}\r
+#endif\r
\r
-// Trashes r0\r
-void CheckInterrupt()\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r
{\r
- ot(";@ CheckInterrupt:\n");\r
- ot(" ldrb r0,[r7,#0x47] ;@ Get IRQ level\n");\r
- ot(" tst r0,r0\n");\r
- ot(" blne DoInterrupt\n");\r
+ ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" mov r6,#0x%02x\n", iw);\r
+ ot(" mov r11,r0\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r6,r6,#4\n");\r
+ ot(" b ExceptionAddressError\n");\r
ot("\n");\r
}\r
+#endif\r
+\r
+void FlushPC(void)\r
+{\r
+#if MEMHANDLERS_NEED_PC\r
+ if (pc_dirty)\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+#endif\r
+ pc_dirty = 0;\r
+}\r
\r
static void PrintFramework()\r
{\r
+ int state_flags_to_check = 1; // stopped\r
+#if EMULATE_TRACE\r
+ state_flags_to_check |= 2; // tracing\r
+#endif\r
+#if EMULATE_HALT\r
+ state_flags_to_check |= 0x10; // halted\r
+#endif\r
+\r
ot(";@ --------------------------- Framework --------------------------\n");\r
if (ms) ot("CycloneRun\n");\r
else ot("CycloneRun:\n");\r
\r
- ot(" stmdb sp!,{r4-r11,lr}\n");\r
+ ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r
\r
ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
ot(" ;@ r0-3 = Temporary registers\n");\r
- ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
- ot(" ldr r6,=JumpTab ;@ r6 = Opcode Jump table\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
+ ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");\r
ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
ot(" ;@ r8 = Current Opcode\n");\r
- ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
- ot(" ;@ r10 = Source value / Memory Base\n");\r
+ ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" ;@ r11 = Source value / Memory Base\n");\r
+ ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");\r
+ ot("\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" mov r2,#0\n");\r
+ ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
+#endif\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" beq NoInts0\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterrupt\n");\r
+ ot("NoInts0%s\n", ms?"":":");\r
+ ot("\n");\r
+ ot(";@ Check if our processor is in special state\n");\r
+ ot(";@ and jump to opcode handler if not\n");\r
+ ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
+ ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
+ ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+ ot("CycloneSpecial%s\n", ms?"":":");\r
+#if EMULATE_TRACE\r
+ ot(" tst r0,#2 ;@ tracing?\n");\r
+ ot(" bne CycloneDoTrace\n");\r
+#endif\r
+ ot(";@ stopped or halted\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
+ ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r
ot("\n");\r
- CheckInterrupt();\r
- ot(";@ Check if interrupt used up all the cycles:\n");\r
- ot(" subs r5,r5,#0\n");\r
- ot(" blt CycloneEndNoBack\n");\r
-\r
- OpFirst();\r
- ltorg();\r
ot("\n");\r
\r
ot(";@ We come back here after execution\n");\r
ot("CycloneEnd%s\n", ms?"":":");\r
ot(" sub r4,r4,#2\n");\r
ot("CycloneEndNoBack%s\n", ms?"":":");\r
- ot(" mov r9,r9,lsr #28\n");\r
+#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r10,r10,lsr #28\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
+#else\r
+ ot(" mov r10,r10,lsr #28\n");\r
+#endif\r
ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
- ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
- ot(" ldmia sp!,{r4-r11,pc}\n");\r
+ ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r
+ ltorg();\r
ot("\n");\r
-\r
- ot(";@ DoInterrupt - r0=IRQ number\n");\r
- ot("DoInterrupt%s\n", ms?"":":");\r
ot("\n");\r
- ot(" ldrb r1,[r7,#0x44] ;@ Get SR high: T_S__III\n");\r
- ot(" and r1,r1,#7 ;@ Get interrupt mask\n");\r
- ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
- ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
- ot(" movle pc,lr ;@ irq<=6 and mask, not allowed\n");\r
+\r
+ ot("CycloneInit%s\n", ms?"":":");\r
+#if COMPRESS_JUMPTABLE\r
+ ot(";@ decompress jump table\n");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
+ ot(" ldr r1,[r0,#-4]\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" movne pc,lr ;@ already uncompressed\n");\r
+ ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
+ ot("unc_loop%s\n", ms?"":":");\r
+ ot(" ldrh r1,[r0],#2\n");\r
+ ot(" and r2,r1,#0xf\n");\r
+ ot(" bic r1,r1,#0xf\n");\r
+ ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
+ ot(" cmp r2,#0xf\n");\r
+ ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
+ ot(" tst r2,r2\n");\r
+ ot(" beq unc_finish ;@ done decompressing\n");\r
+ ot(" tst r1,r1\n");\r
+ ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
+ ot(" beq unc_loop\n");\r
+ ot("unc_loop_in%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r12],#4\n");\r
+ ot(" bgt unc_loop_in\n");\r
+ ot(" b unc_loop\n");\r
+ ot("unc_finish%s\n", ms?"":":");\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" ;@ set a-line and f-line handlers\n");\r
+ ot(" add r0,r12,#0xa000*4\n");\r
+ ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
+ ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill3%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bgt unc_fill3\n");\r
+ ot(" add r0,r12,#0xf000*4\n");\r
+ ot(" mov r2,#0x1000\n");\r
+ ot("unc_fill4%s\n", ms?"":":");\r
+ ot(" subs r2,r2,#1\n");\r
+ ot(" str r3,[r0],#4\n");\r
+ ot(" bgt unc_fill4\n");\r
+ ot(" bx lr\n");\r
+ ltorg();\r
+#else\r
+ ot(";@ do nothing\n");\r
+ ot(" bx lr\n");\r
+#endif\r
ot("\n");\r
- ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
- ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
- ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
- OpPush32();\r
- OpPushSr(1);\r
- ot(";@ Get IRQ Vector address:\n");\r
- ot(" ldrb r1,[r7,#0x47] ;@ IRQ\n");\r
- ot(" mov r0,r1,asl #2\n");\r
- ot(" add r0,r0,#0x60\n");\r
- ot(";@ Read IRQ Vector:\n");\r
+\r
+ // --------------\r
+ ot("CycloneReset%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r7,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,#0\n");\r
+ ot(" str r0,[r7,#0x58] ;@ state_flags\n");\r
+ ot(" str r0,[r7,#0x48] ;@ OSP\n");\r
+ ot(" mov r1,#0x27 ;@ Supervisor mode\n");\r
+ ot(" strb r1,[r7,#0x44] ;@ set SR high\n");\r
+ ot(" strb r0,[r7,#0x47] ;@ IRQ\n");\r
MemHandler(0,2);\r
- ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Stack pointer\n");\r
+ ot(" mov r0,#0\n");\r
+ ot(" str r0,[r7,#0x60] ;@ Membase\n");\r
+ ot(" mov r0,#4\n");\r
+ MemHandler(0,2);\r
+#ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+#else\r
ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+#endif\r
+ ot(" str r0,[r7,#0x40] ;@ PC + base\n");\r
+ ot(" ldmfd sp!,{r7,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ // 68k: XNZVC, ARM: NZCV\r
+ ot("CycloneSetSr%s\n", ms?"":":");\r
+ ot(" mov r2,r1,lsr #8\n");\r
+// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
+// ot(" eor r3,r3,r2\n");\r
+// ot(" tst r3,#0x20\n");\r
+#if EMULATE_TRACE\r
+ ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
+#else\r
+ ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
+#endif\r
+ ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
+ ot(" mov r2,r1,lsl #25\n");\r
+ ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
+ ot(" bic r2,r1,#0xf3\n");\r
+ ot(" tst r1,#1\n");\r
+ ot(" orrne r2,r2,#2\n");\r
+ ot(" tst r1,#2\n");\r
+ ot(" orrne r2,r2,#1\n");\r
+ ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneGetSr%s\n", ms?"":":");\r
+ ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
+ ot(" bic r2,r1,#0xf3\n");\r
+ ot(" tst r1,#1\n");\r
+ ot(" orrne r2,r2,#2\n");\r
+ ot(" tst r1,#2\n");\r
+ ot(" orrne r2,r2,#1\n");\r
+ ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
+ ot(" tst r1,#0x20000000\n");\r
+ ot(" orrne r2,r2,#0x10\n");\r
+ ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
+ ot(" orr r0,r2,r1,lsl #8\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CyclonePack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r4,r5,lr}\n");\r
ot(" mov r4,r0\n");\r
+ ot(" mov r5,r1\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_pack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r0],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r5],#4\n");\r
+ ot(" bne c_pack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
+ ot(" sub r0,r0,r1\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" mov r0,r4\n");\r
+ ot(" bl CycloneGetSr\n");\r
+ ot(" strh r0,[r5],#2\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r4,#0x47]\n");\r
+ ot(" strb r0,[r5],#2\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r4,#0x48]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r4,#0x58]\n");\r
+ ot(" str r0,[r5],#4\n");\r
+ ot(" ldmfd sp!,{r4,r5,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneUnpack%s\n", ms?"":":");\r
+ ot(" stmfd sp!,{r5,r7,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" movs r5,r1\n");\r
+ ot(" beq c_unpack_do_pc\n");\r
+ ot(" mov r3,#16\n");\r
+ ot(";@ 0x00-0x3f: DA registers\n");\r
+ ot("c_unpack_loop%s\n",ms?"":":");\r
+ ot(" ldr r1,[r5],#4\n");\r
+ ot(" subs r3,r3,#1\n");\r
+ ot(" str r1,[r0],#4\n");\r
+ ot(" bne c_unpack_loop\n");\r
+ ot(";@ 0x40: PC\n");\r
+ ot(" ldr r0,[r5],#4 ;@ PC\n");\r
+ ot(" str r0,[r7,#0x40] ;@ handle later\n");\r
+ ot(";@ 0x44: SR\n");\r
+ ot(" ldrh r1,[r5],#2\n");\r
+ ot(" mov r0,r7\n");\r
+ ot(" bl CycloneSetSr\n");\r
+ ot(";@ 0x46: IRQ level\n");\r
+ ot(" ldrb r0,[r5],#2\n");\r
+ ot(" strb r0,[r7,#0x47]\n");\r
+ ot(";@ 0x48: other SP\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r7,#0x48]\n");\r
+ ot(";@ 0x4c: CPU state flags\n");\r
+ ot(" ldr r0,[r5],#4\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot("c_unpack_do_pc%s\n",ms?"":":");\r
+ ot(" ldr r0,[r7,#0x40] ;@ unbased PC\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" mov r1,#0\n");\r
+ ot(" str r1,[r7,#0x60] ;@ Memory base\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" mov lr,pc\n");\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+#else\r
+ ot(" ldr r1,[r7,#0x60] ;@ Memory base\n");\r
+ ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
+#endif\r
+ ot(" str r0,[r7,#0x40] ;@ PC + Memory Base\n");\r
+ ot(" ldmfd sp!,{r5,r7,pc}\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneFlushIrq%s\n", ms?"":":");\r
+ ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
+ ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
+ ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" movle r0,#0\n");\r
+ ot(" bxle lr ;@ no ints\n");\r
+ ot("\n");\r
+ ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
+ ot(" mov r7,r0\n");\r
+ ot(" mov r0,r2\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
+ ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r
+ ot(" adr r2,CycloneFlushIrqEnd\n");\r
+ ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
+ ot(" b CycloneDoInterrupt\n");\r
+ ot("\n");\r
+ ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
+ ot(" rsb r0,r5,#0\n");\r
+ ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
+ ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r
+ ot(" bx lr\n");\r
+ ot("\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot("CycloneSetRealTAS%s\n", ms?"":":");\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ ot(" ldr r12,=CycloneJumpTab\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" add r12,r12,#0x4a00*4\n");\r
+ ot(" add r12,r12,#0x00d0*4\n");\r
+ ot(" beq setrtas_off\n");\r
+ ChangeTAS(1);\r
+ ot(" bx lr\n");\r
+ ot("setrtas_off%s\n",ms?"":":");\r
+ ChangeTAS(0);\r
+ ot(" bx lr\n");\r
+ ltorg();\r
+#else\r
+ ot(" bx lr\n");\r
+#endif\r
+ ot("\n");\r
+\r
+ // --------------\r
+ ot(";@ DoInterrupt - r0=IRQ level\n");\r
+ ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+ ot("CycloneDoInterrupt%s\n", ms?"":":");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
+\r
+ // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
+ // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r0,r0,#7\n");\r
+ ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#endif\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
ot("\n");\r
- ot(";@ todo - swap OSP and A7 if not in Supervisor mode\n");\r
- ot(" ldrb r0,[r7,#0x47] ;@ IRQ\n");\r
- ot(" orr r0,r0,#0x20 ;@ Supervisor mode + IRQ number\n");\r
- ot(" strb r0,[r7,#0x44] ;@ Put SR high\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r6,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r11,[r7,#0x48]\n");\r
+ ot(" moveq r11,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r
+ ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
ot("\n");\r
+\r
+ // 2. Obtain the exception vector.\r
+ ot(" mov r11,r8,lsr #29\n");\r
+ ot(" mov r0,r11\n");\r
+#if USE_INT_ACK_CALLBACK\r
+ ot(";@ call IrqCallback if it is defined\n");\r
+#if INT_ACK_NEEDS_STUFF\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+#endif\r
+ ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
+ ot(" add lr,pc,#4*3\n");\r
+ ot(" tst r3,r3\n");\r
+ ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
+ ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
+ ot(" bxne r3\n");\r
+#if INT_ACK_CHANGES_CYCLES\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#endif\r
+ ot(";@ get IRQ vector address:\n");\r
+ ot(" cmn r0,#1 ;@ returned -1?\n");\r
+ ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
+ ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
+ ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
+#else // !USE_INT_ACK_CALLBACK\r
ot(";@ Clear irq:\n");\r
- ot(" mov r0,#0\n");\r
- ot(" strb r0,[r7,#0x47]\n");\r
- ot(" subs r5,r5,#%d ;@ Subtract cycles\n",46);\r
- ot(" mov pc,r11 ;@ Return\n");\r
+ ot(" mov r2,#0\n");\r
+ ot(" strb r2,[r7,#0x47]\n");\r
+ ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
+#endif\r
+ ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
+ ot("\n");\r
+ ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(";@ Read IRQ Vector:\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
+ ot(" moveq r0,#0x3c\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bleq %sread32 ;@ Call read32(r0) handler\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" moveq lr,pc\n");\r
+ ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
+ #endif\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
ot("\n");\r
\r
- ot("Exception%s\n", ms?"":":");\r
+ // 4. Obtain a new context and resume instruction processing.\r
+ // note: the obtain part was already done in previous steps\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
ot("\n");\r
+\r
+ // --------------\r
+ // trashes all temp regs\r
+ ot("Exception%s\n", ms?"":":");\r
+ ot(" ;@ Cause an Exception - Vector number in r0\n");\r
ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
- PrintException();\r
- ot(" mov pc,r11 ;@ Return\n");\r
+ ot(" bic r8,r8,#0xff000000\n");\r
+ ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r6,#0x20\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ MemHandler(1,2);\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,r8,lsr #24\n");\r
+ ot(" mov r0,r0,lsl #2\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" mov r4,r0\n");\r
+ #else\r
+ ot(" bic r4,r0,#1\n");\r
+ #endif\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+ #if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" bic r4,r4,#1\n");\r
+ #endif\r
+#endif\r
ot("\n");\r
+\r
+ // 4. Resume execution.\r
+#if EMULATE_ADDRESS_ERRORS_JUMP\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#endif\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" bx r11 ;@ Return\n");\r
+ ot("\n");\r
+\r
+ // --------------\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ // first some wrappers: I see no point inlining this code,\r
+ // as it will be executed in really rare cases.\r
+ AddressErrorWrapper('r', "data", 0x11);\r
+ AddressErrorWrapper('r', "prg", 0x12);\r
+ AddressErrorWrapper('w', "data", 0x01);\r
+ // there are no program writes\r
+ // cpu space is only for bus errors?\r
+ ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
+ ot(" ldr r1,[r7,#0x44]\n");\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" mov r6,#0x12\n");\r
+ ot(" sub r11,r4,r3\n");\r
+ ot(" tst r1,#0x20\n");\r
+ ot(" orrne r6,r6,#4\n");\r
+ ot("\n");\r
+\r
+ ot("ExceptionAddressError%s\n", ms?"":":");\r
+ ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r
+\r
+ // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
+ ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
+ ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
+ ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
+ ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
+ ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
+ ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
+ ot(" tst r2,#4\n");\r
+ ot(" orrne r6,r6,#8 ;@ complete info word\n");\r
+ ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+#if EMULATE_HALT\r
+ ot(" tst r2,#8\n");\r
+ ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
+ ot(" orr r2,r2,#8 ;@ processing address error\n");\r
+ ot(" str r2,[r7,#0x58]\n");\r
+ ot(" movne r5,#0\n");\r
+ ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
+#else\r
+ ot(" str r2,[r7,#0x58]\n");\r
+#endif\r
+ ot(" and r10,r10,#0xf0000000\n");\r
+ ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r
+ ot("\n");\r
+\r
+ // 3. Save the current processor context + additional information.\r
+ ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
+ ot(" tst r10,#0x200\n");\r
+ ot(";@ get our SP:\n");\r
+ ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
+ ot(" streq r0,[r7,#0x48]\n");\r
+ ot(" moveq r0,r2\n");\r
+ // PC\r
+ ot(";@ Push old PC onto stack\n");\r
+ ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
+ ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,EMULATE_HALT);\r
+ // SR\r
+ ot(";@ Push old SR:\n");\r
+ ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
+ ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r
+ ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
+ ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
+ ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
+ ot(" and r0,r0,#0x20000000\n");\r
+ ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" and r10,r10,#0xf0000000\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // IR (instruction register)\r
+ ot(";@ Push IR:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r8\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ // access address\r
+ ot(";@ Push address:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r11\n");\r
+ ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,2,0,0);\r
+ // information word\r
+ ot(";@ Push info word:\n");\r
+ ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
+ ot(" mov r1,r6\n");\r
+ ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
+ ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
+ MemHandler(1,1,0,0);\r
+ ot("\n");\r
+\r
+ // 2. Obtain the exception vector\r
+ ot(";@ Read Exception Vector:\n");\r
+ ot(" mov r0,#0x0c\n");\r
+ MemHandler(0,2,0,0);\r
+ ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
+#if USE_CHECKPC_CALLBACK\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
+ #ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ ot(" bl %scheckpc ;@ Call checkpc()\n", MEMHANDLERS_DIRECT_PREFIX);\r
+ #else\r
+ ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
+ #endif\r
+ ot(" mov r4,r0\n");\r
+#else\r
+ ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
+#endif\r
+ ot("\n");\r
+\r
+#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
+ ot(" tst r4,#1\n");\r
+ ot(" bne ExceptionAddressError_r_prg_r4\n");\r
+#else\r
+ ot(" bic r4,r4,#1\n");\r
+#endif\r
+\r
+ // 4. Resume execution.\r
+ ot(" ldr r6,[r7,#0x54]\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
+\r
+ // --------------\r
+#if EMULATE_TRACE\r
+ // expects srh and irq level in r1, next opcode already fetched to r8\r
+ ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
+ ot(" ldr r0,[r7,#0x58]\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
+ ot(" str r0,[r7,#0x58]\n");\r
+ ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
+ ot(";@ CheckInterrupt:\n");\r
+ ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
+ ot(" beq CycloneDoTrace\n");\r
+ ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
+ ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
+ ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
+ ot(" bgt CycloneDoInterruptGoBack\n");\r
+ ot("\n");\r
+\r
+ // expects next opcode to be already fetched to r8\r
+ ot("CycloneDoTrace%s\n", ms?"":":");\r
+ ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
+ ot(" ldr r1,[r7,#0x98]\n");\r
+ ot(" mov r5,#0\n");\r
+ ot(" str r1,[r7,#0xa0]\n");\r
+ ot(" adr r0,TraceEnd\n");\r
+ ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
+ ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot("\n");\r
+\r
+ ot("TraceEnd%s\n", ms?"":":");\r
+ ot(" ldr r2,[r7,#0x58]\n");\r
+ ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
+ ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" add r5,r0,r5\n");\r
+ ot(" str r1,[r7,#0x98]\n");\r
+ ot(";@ still tracing?\n"); // exception might have happend\r
+ ot(" tst r2,#2\n");\r
+ ot(" beq TraceDisabled\n");\r
+ ot(";@ trace exception\n");\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" mov r0,#9\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" mov r0,#9\n");\r
+#endif\r
+ ot(" bl Exception\n");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+ ot("TraceDisabled%s\n", ms?"":":");\r
+ ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
+ ot(" cmp r5,#0\n");\r
+ ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
+ ot(" b CycloneEnd\n");\r
+ ot("\n");\r
+#endif\r
}\r
\r
// ---------------------------------------------------------------------------\r
// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
-// Trashes r0-r3\r
-int MemHandler(int type,int size)\r
+// Trashes r0-r3,r12,lr\r
+int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
{\r
- int func=0;\r
- func=0x68+type*0xc+(size<<2); // Find correct offset\r
+ int func=0x68+type*0xc+(size<<2); // Find correct offset\r
+ char what[32];\r
\r
- if (Debug&4) ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
- if (Debug&3) ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+#if MEMHANDLERS_NEED_FLAGS\r
+ ot(" mov r3,r10,lsr #28\n");\r
+ ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+#endif\r
+ FlushPC();\r
\r
- ot(" mov lr,pc\n");\r
+#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
+ addrreg=0;\r
+#endif\r
+#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
+ ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
+ addrreg=0;\r
+#endif\r
+\r
+#if EMULATE_ADDRESS_ERRORS_IO\r
+ if (size > 0 && need_addrerr_check)\r
+ {\r
+ ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
+ if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
+ ot(" tst r0,#1 ;@ address error?\n");\r
+ switch (type) {\r
+ case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
+ case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
+ case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
+ }\r
+ }\r
+ else\r
+#endif\r
+\r
+ sprintf(what, "%s%d", type==0 ? "read" : (type==1 ? "write" : "fetch"), 8<<size);\r
+#ifdef MEMHANDLERS_DIRECT_PREFIX\r
+ if (addrreg != 0)\r
+ ot(" mov r0,r%i\n", addrreg);\r
+ ot(" bl %s%s ;@ Call ", MEMHANDLERS_DIRECT_PREFIX, what);\r
+ (void)func; // avoid warning\r
+#else\r
+ if (addrreg != 0)\r
+ {\r
+ ot(" add lr,pc,#4\n");\r
+ ot(" mov r0,r%i\n", addrreg);\r
+ }\r
+ else\r
+ ot(" mov lr,pc\n");\r
ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
+#endif\r
\r
// Document what we are calling:\r
- if (type==0) ot("read");\r
- if (type==1) ot("write");\r
- if (type==2) ot("fetch");\r
-\r
- if (type==1) ot("%d(r0,r1)",8<<size);\r
- else ot("%d(r0)", 8<<size);\r
+ if (type==1) ot("%s(r0,r1)",what);\r
+ else ot("%s(r0)", what);\r
ot(" handler\n");\r
\r
- if (Debug&2) ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+#if MEMHANDLERS_CHANGE_FLAGS\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+#endif\r
+#if MEMHANDLERS_CHANGE_PC\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+#endif\r
+\r
return 0;\r
}\r
\r
static void PrintOpcodes()\r
{\r
int op=0;\r
- \r
+\r
printf("Creating Opcodes: [");\r
\r
ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
\r
// Emit null opcode:\r
ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
- OpStart(-1); Cycles=4; OpEnd(); //test\r
+#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
+ ot(" ldr r1,[r7,#0x58]\n");\r
+ ot(" sub r4,r4,#2\n");\r
+ ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
+ ot(" str r1,[r7,#0x58]\n");\r
+#else\r
+ ot(" sub r4,r4,#2\n");\r
+#endif\r
+#if USE_UNRECOGNIZED_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#4\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#4\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=34;\r
+ OpEnd();\r
+\r
+ // Unrecognised a-line and f-line opcodes throw an exception:\r
+ ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+#if USE_AFLINE_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#0x0a\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#0x0a\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=4;\r
+ OpEnd();\r
+\r
+ ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
+ ot(" sub r4,r4,#2\n");\r
+#if USE_AFLINE_CALLBACK\r
+ ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
+ ot(" mov r1,r10,lsr #28\n");\r
+ ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
+ ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
+ ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
+ ot(" tst r11,r11\n");\r
+ ot(" movne lr,pc\n");\r
+ ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
+ ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
+ ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
+ ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
+ ot(" mov r10,r10,lsl #28\n");\r
+ ot(" tst r0,r0\n");\r
+ ot(" moveq r0,#0x0b\n");\r
+ ot(" bleq Exception\n");\r
+#else\r
+ ot(" mov r0,#0x0b\n");\r
+ ot(" bl Exception\n");\r
+#endif\r
+ ot("\n");\r
+ Cycles=4;\r
+ OpEnd();\r
+\r
\r
- ot(" b CycloneEnd\n\n");\r
+ for (op=0;op<hot_opcode_count;op++)\r
+ OpAny(hot_opcodes[op]);\r
\r
for (op=0;op<0x10000;op++)\r
{\r
if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
\r
- OpAny(op);\r
+ if (!is_op_hot(op))\r
+ OpAny(op);\r
}\r
\r
ot("\n");\r
printf("]\n");\r
}\r
\r
+// helper\r
+static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
+{\r
+ switch(size) {\r
+ case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
+ case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
+ case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
+ }\r
+ ot(str, par);\r
+ if((counter&7)==7) ot(nl,nlp); else ot(",");\r
+}\r
+\r
static void PrintJumpTable()\r
{\r
int i=0,op=0,len=0;\r
\r
ot(";@ -------------------------- Jump Table --------------------------\n");\r
- ot("JumpTab%s\n", ms?"":":");\r
\r
- len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
- for (i=0;i<len;i++)\r
- {\r
- op=CyJump[i];\r
+ // space for decompressed table\r
+ ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
\r
- if ((i&7)==0) ot(ms?" dcd ":" .long ");\r
- if (op<0) ot("Op____"); else ot("Op%.4x",op);\r
- \r
- if ((i&7)==7) ot(" ;@ %.4x\n",i-7);\r
- else if (i+1<len) ot(",");\r
- }\r
+#if COMPRESS_JUMPTABLE\r
+ int handlers=0,reps=0,*indexes,ip,u,out;\r
+ // use some weird compression on the jump table\r
+ indexes=(int *)malloc(0x10000*4);\r
+ if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
+ len=0x10000;\r
\r
- ot("\n");\r
+ ot("CycloneJumpTab%s\n", ms?"":":");\r
+ if(ms) {\r
+ for(i = 0; i < 0xa000/8; i++)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else\r
+ ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
+\r
+ // hanlers live in "a-line" part of the table\r
+ // first output nop,a-line,f-line handlers\r
+ ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
+ handlers=3;\r
+\r
+ for(i=0;i<len;i++)\r
+ {\r
+ op=CyJump[i];\r
+\r
+ for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
+ if(u==-1 && op >= 0) {\r
+ ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
+ indexes[op] = handlers;\r
+ handlers++;\r
+ }\r
+ }\r
+ if(handlers&7) {\r
+ fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+ for(i = 8-(handlers&7); i > 0; i--)\r
+ ot(",000000");\r
+ ot("\n");\r
+ }\r
+ if(ms) {\r
+ for(i = (0x4000-handlers)/8; i > 0; i--)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else {\r
+ ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
+ }\r
+ printf("total distinct hanlers: %i\n",handlers);\r
+ // output data\r
+ for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
+ op=CyJump[i];\r
+ if(op == -2) {\r
+ // it must skip a-line area, because we keep our data there\r
+ ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
+ ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
+ i+=0xfff;\r
+ continue;\r
+ }\r
+ for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
+ if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
+ if(reps <= 0xe || reps==0x10) {\r
+ if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
+ ott("0x%.4x", out, "\n",0,ip,1);\r
+ } else {\r
+ ott("0x%.4x", out, "\n",0,ip++,1);\r
+ ott("0x%.4x", reps,"\n",0,ip,1);\r
+ }\r
+ }\r
+ if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
+ if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+ if(ip&7) {\r
+ for(i = 8-(ip&7); i > 0; i--)\r
+ ot(",0x0000");\r
+ }\r
+ ot("\n");\r
+ if(ms) {\r
+ for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
+ ot(" dcd 0,0,0,0,0,0,0,0\n");\r
+ } else {\r
+ ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
+ }\r
+ ot("\n");\r
+ free(indexes);\r
+#else\r
+ ot("CycloneJumpTab%s\n", ms?"":":");\r
+ len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
+ // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
+ // this is due to COFF objects using only 2 bytes for reloc count\r
+\r
+ for (i=0;i<len;i++)\r
+ {\r
+ op=CyJump[i];\r
+\r
+ if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
+ else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
+ else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
+ else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
+ }\r
+ if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
+\r
+ ot("\n");\r
+ ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
+ ot(";@ so we leave this pattern to patch it later\n");\r
+ ot("%s 0x78563412\n", ms?" dcd":" .long");\r
+ ot("%s 0x56341290\n", ms?" dcd":" .long");\r
+#endif\r
}\r
\r
static int CycloneMake()\r
{\r
- char *name="Cyclone.s";\r
- \r
+ int i;\r
+ const char *name="Cyclone.s";\r
+ const char *globl=ms?"export":".global";\r
+\r
// Open the assembly file\r
if (ms) name="Cyclone.asm";\r
AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
- \r
+\r
printf("Making %s...\n",name);\r
\r
ot("\n;@ Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
\r
- ot(";@ Copyright (c) 2011 FinalDave (emudave (at) gmail.com)\n\n");\r
+ ot(";@ Copyright (c) 2004,2011 FinalDave (emudave (at) gmail.com)\n");\r
+ ot(";@ Copyright (c) 2005-2011 Gražvydas \"notaz\" Ignotas (notasas (at) gmail.com)\n\n");\r
\r
ot(";@ This code is licensed under the GNU General Public License version 2.0 and the MAME License.\n");\r
ot(";@ You can choose the license that has the most advantages for you.\n\n");\r
\r
CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
memset(CyJump,0xff,0x40000); // Init to -1\r
+ for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
+ for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
\r
- if (ms)\r
- {\r
- ot(" area |.text|, code\n");\r
- ot(" export CycloneRun\n");\r
- ot(" export CycloneVer\n");\r
- ot("\n");\r
- ot("CycloneVer dcd 0x%.4x\n",CycloneVer);\r
- }\r
- else\r
- {\r
- ot(" .global CycloneRun\n");\r
- ot(" .global CycloneVer\n");\r
- ot("CycloneVer: .long 0x%.4x\n",CycloneVer);\r
- }\r
+ ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
+ ot(" %s CycloneInit\n",globl);\r
+ ot(" %s CycloneReset\n",globl);\r
+ ot(" %s CycloneRun\n",globl);\r
+ ot(" %s CycloneSetSr\n",globl);\r
+ ot(" %s CycloneGetSr\n",globl);\r
+ ot(" %s CycloneFlushIrq\n",globl);\r
+ ot(" %s CyclonePack\n",globl);\r
+ ot(" %s CycloneUnpack\n",globl);\r
+ ot(" %s CycloneVer\n",globl);\r
+#if (CYCLONE_FOR_GENESIS == 2)\r
+ ot(" %s CycloneSetRealTAS\n",globl);\r
+ ot(" %s CycloneDoInterrupt\n",globl);\r
+ ot(" %s CycloneDoTrace\n",globl);\r
+ ot(" %s CycloneJumpTab\n",globl);\r
+ ot(" %s Op____\n",globl);\r
+ ot(" %s Op6001\n",globl);\r
+ ot(" %s Op6601\n",globl);\r
+ ot(" %s Op6701\n",globl);\r
+#endif\r
+ ot("\n");\r
+ ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
+ ot("%.4x\n",CycloneVer);\r
ot("\n");\r
\r
PrintFramework();\r
+ arm_op_count = 0;\r
PrintOpcodes();\r
+ printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
PrintJumpTable();\r
\r
if (ms) ot(" END\n");\r
\r
+ ot("\n\n;@ vim:filetype=armasm\n");\r
+\r
fclose(AsmFile); AsmFile=NULL;\r
\r
+#if 0\r
printf("Assembling...\n");\r
// Assemble the file\r
if (ms) system("armasm Cyclone.asm");\r
else system("as -o Cyclone.o Cyclone.s");\r
printf("Done!\n\n");\r
+#endif\r
\r
free(CyJump);\r
return 0;\r
{\r
printf("\n Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
\r
- // Make GAS and ARMASM versions\r
- for (ms=0;ms<2;ms++) CycloneMake();\r
+ // Make GAS or ARMASM version\r
+ CycloneMake();\r
return 0;\r
}\r
+\r
notaz.gp2x.de / cyclone68000.git / blobdiff