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2823a4c8 1/* gameplaySP
2 *
3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef ARM_EMIT_H
21#define ARM_EMIT_H
22
23#include "arm_codegen.h"
24
25u32 arm_update_gba_arm(u32 pc);
26u32 arm_update_gba_thumb(u32 pc);
27u32 arm_update_gba_idle_arm(u32 pc);
28u32 arm_update_gba_idle_thumb(u32 pc);
29
30// Although these are defined as a function, don't call them as
31// such (jump to it instead)
32void arm_indirect_branch_arm(u32 address);
33void arm_indirect_branch_thumb(u32 address);
34void arm_indirect_branch_dual_arm(u32 address);
35void arm_indirect_branch_dual_thumb(u32 address);
36
37void execute_store_cpsr(u32 new_cpsr, u32 store_mask, u32 address);
38u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address);
39void execute_store_spsr(u32 new_cpsr, u32 store_mask);
40u32 execute_read_spsr();
41u32 execute_spsr_restore(u32 address);
42
43void execute_swi_arm(u32 pc);
44void execute_swi_thumb(u32 pc);
45
46void function_cc execute_store_u32_safe(u32 address, u32 source);
47
48void step_debug_arm(u32 pc);
49
50
51#define write32(value) \
52 *((u32 *)translation_ptr) = value; \
53 translation_ptr += 4 \
54
55#define arm_relative_offset(source, offset) \
56 (((((u32)offset - (u32)source) - 8) >> 2) & 0xFFFFFF) \
57
58
59// reg_base_offset is the amount of bytes after reg_base where the registers
60// actually begin.
61
62#define reg_base_offset 1024
63
64
65#define reg_a0 ARMREG_R0
66#define reg_a1 ARMREG_R1
67#define reg_a2 ARMREG_R2
68
69#define reg_s0 ARMREG_R9
70#define reg_base ARMREG_SP
71#define reg_flags ARMREG_R11
72
73#define reg_cycles ARMREG_R12
74
75#define reg_rv ARMREG_R0
76
77#define reg_rm ARMREG_R0
78#define reg_rn ARMREG_R1
79#define reg_rs ARMREG_R14
80#define reg_rd ARMREG_R0
81
82
83// Register allocation layout for ARM and Thumb:
84// Map from a GBA register to a host ARM register. -1 means load it
85// from memory into one of the temp registers.
86
87// The following registers are chosen based on statistical analysis
88// of a few games (see below), but might not be the best ones. Results
89// vary tremendously between ARM and Thumb (for obvious reasons), so
90// two sets are used. Take care to not call any function which can
91// overwrite any of these registers from the dynarec - only call
92// trusted functions in arm_stub.S which know how to save/restore
93// them and know how to transfer them to the C functions it calls
94// if necessary.
95
96// The following define the actual registers available for allocation.
97// As registers are freed up add them to this list.
98
99// Note that r15 is linked to the a0 temp reg - this register will
100// be preloaded with a constant upon read, and used to link to
101// indirect branch functions upon write.
102
103#define reg_x0 ARMREG_R3
104#define reg_x1 ARMREG_R4
105#define reg_x2 ARMREG_R5
106#define reg_x3 ARMREG_R6
107#define reg_x4 ARMREG_R7
108#define reg_x5 ARMREG_R8
109
110#define mem_reg -1
111
112/*
113
114ARM register usage (38.775138% ARM instructions):
115r00: 18.263814% (-- 18.263814%)
116r12: 11.531477% (-- 29.795291%)
117r09: 11.500162% (-- 41.295453%)
118r14: 9.063440% (-- 50.358893%)
119r06: 7.837682% (-- 58.196574%)
120r01: 7.401049% (-- 65.597623%)
121r07: 6.778340% (-- 72.375963%)
122r05: 5.445009% (-- 77.820973%)
123r02: 5.427288% (-- 83.248260%)
124r03: 5.293743% (-- 88.542003%)
125r04: 3.601103% (-- 92.143106%)
126r11: 3.207311% (-- 95.350417%)
127r10: 2.334864% (-- 97.685281%)
128r08: 1.708207% (-- 99.393488%)
129r15: 0.311270% (-- 99.704757%)
130r13: 0.295243% (-- 100.000000%)
131
132Thumb register usage (61.224862% Thumb instructions):
133r00: 34.788858% (-- 34.788858%)
134r01: 26.564083% (-- 61.352941%)
135r03: 10.983500% (-- 72.336441%)
136r02: 8.303127% (-- 80.639567%)
137r04: 4.900381% (-- 85.539948%)
138r05: 3.941292% (-- 89.481240%)
139r06: 3.257582% (-- 92.738822%)
140r07: 2.644851% (-- 95.383673%)
141r13: 1.408824% (-- 96.792497%)
142r08: 0.906433% (-- 97.698930%)
143r09: 0.679693% (-- 98.378623%)
144r10: 0.656446% (-- 99.035069%)
145r12: 0.453668% (-- 99.488737%)
146r14: 0.248909% (-- 99.737646%)
147r11: 0.171066% (-- 99.908713%)
148r15: 0.091287% (-- 100.000000%)
149
150*/
151
152s32 arm_register_allocation[] =
153{
154 reg_x0, // GBA r0
155 reg_x1, // GBA r1
156 mem_reg, // GBA r2
157 mem_reg, // GBA r3
158 mem_reg, // GBA r4
159 mem_reg, // GBA r5
160 reg_x2, // GBA r6
161 mem_reg, // GBA r7
162 mem_reg, // GBA r8
163 reg_x3, // GBA r9
164 mem_reg, // GBA r10
165 mem_reg, // GBA r11
166 reg_x4, // GBA r12
167 mem_reg, // GBA r13
168 reg_x5, // GBA r14
169 reg_a0 // GBA r15
170
171 mem_reg,
172 mem_reg,
173 mem_reg,
174 mem_reg,
175 mem_reg,
176 mem_reg,
177 mem_reg,
178 mem_reg,
179 mem_reg,
180 mem_reg,
181 mem_reg,
182 mem_reg,
183 mem_reg,
184 mem_reg,
185 mem_reg,
186 mem_reg,
187};
188
189s32 thumb_register_allocation[] =
190{
191 reg_x0, // GBA r0
192 reg_x1, // GBA r1
193 reg_x2, // GBA r2
194 reg_x3, // GBA r3
195 reg_x4, // GBA r4
196 reg_x5, // GBA r5
197 mem_reg, // GBA r6
198 mem_reg, // GBA r7
199 mem_reg, // GBA r8
200 mem_reg, // GBA r9
201 mem_reg, // GBA r10
202 mem_reg, // GBA r11
203 mem_reg, // GBA r12
204 mem_reg, // GBA r13
205 mem_reg, // GBA r14
206 reg_a0 // GBA r15
207
208 mem_reg,
209 mem_reg,
210 mem_reg,
211 mem_reg,
212 mem_reg,
213 mem_reg,
214 mem_reg,
215 mem_reg,
216 mem_reg,
217 mem_reg,
218 mem_reg,
219 mem_reg,
220 mem_reg,
221 mem_reg,
222 mem_reg,
223 mem_reg,
224};
225
226
227
228#define arm_imm_lsl_to_rot(value) \
229 (32 - value) \
230
231
232u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
233{
234 u32 store_count = 0;
235 u32 left_shift = 0;
236 u32 i;
237
238 // Otherwise it'll return 0 things to store because it'll never
239 // find anything.
240 if(imm == 0)
241 {
242 rotations[0] = 0;
243 stores[0] = 0;
244 return 1;
245 }
246
247 // Find chunks of non-zero data at 2 bit alignments.
248 while(1)
249 {
250 for(; left_shift < 32; left_shift += 2)
251 {
252 if((imm >> left_shift) & 0x03)
253 break;
254 }
255
256 if(left_shift == 32)
257 {
258 // We've hit the end of the useful data.
259 return store_count;
260 }
261
262 // Hit the end, it might wrap back around to the beginning.
263 if(left_shift >= 24)
264 {
265 // Make a mask for the residual bits. IE, if we have
266 // 5 bits of data at the end we can wrap around to 3
267 // bits of data in the beginning. Thus the first
268 // thing, after being shifted left, has to be less
269 // than 111b, 0x7, or (1 << 3) - 1.
270 u32 top_bits = 32 - left_shift;
271 u32 residual_bits = 8 - top_bits;
272 u32 residual_mask = (1 << residual_bits) - 1;
273
274 if((store_count > 1) && (left_shift > 24) &&
275 ((stores[0] << ((32 - rotations[0]) & 0x1F)) < residual_mask))
276 {
277 // Then we can throw out the last bit and tack it on
278 // to the first bit.
279 u32 initial_bits = rotations[0];
280 stores[0] =
281 (stores[0] << ((top_bits + (32 - rotations[0])) & 0x1F)) |
282 ((imm >> left_shift) & 0xFF);
283 rotations[0] = top_bits;
284
285 return store_count;
286 }
287 else
288 {
289 // There's nothing to wrap over to in the beginning
290 stores[store_count] = (imm >> left_shift) & 0xFF;
291 rotations[store_count] = (32 - left_shift) & 0x1F;
292 return store_count + 1;
293 }
294 break;
295 }
296
297 stores[store_count] = (imm >> left_shift) & 0xFF;
298 rotations[store_count] = (32 - left_shift) & 0x1F;
299
300 store_count++;
301 left_shift += 8;
302 }
303}
304
305#define arm_load_imm_32bit(ireg, imm) \
306{ \
307 u32 stores[4]; \
308 u32 rotations[4]; \
309 u32 store_count = arm_disect_imm_32bit(imm, stores, rotations); \
310 u32 i; \
311 \
312 ARM_MOV_REG_IMM(0, ireg, stores[0], rotations[0]); \
313 \
314 for(i = 1; i < store_count; i++) \
315 { \
316 ARM_ORR_REG_IMM(0, ireg, ireg, stores[i], rotations[i]); \
317 } \
318} \
319
320
321#define generate_load_pc(ireg, new_pc) \
322 arm_load_imm_32bit(ireg, new_pc) \
323
324#define generate_load_imm(ireg, imm, imm_ror) \
325 ARM_MOV_REG_IMM(0, ireg, imm, imm_ror) \
326
327
328
329#define generate_shift_left(ireg, imm) \
330 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSL, imm) \
331
332#define generate_shift_right(ireg, imm) \
333 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_LSR, imm) \
334
335#define generate_shift_right_arithmetic(ireg, imm) \
336 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ASR, imm) \
337
338#define generate_rotate_right(ireg, imm) \
339 ARM_MOV_REG_IMMSHIFT(0, ireg, ireg, ARMSHIFT_ROR, imm) \
340
341#define generate_add(ireg_dest, ireg_src) \
342 ARM_ADD_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
343
344#define generate_sub(ireg_dest, ireg_src) \
345 ARM_SUB_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
346
347#define generate_or(ireg_dest, ireg_src) \
348 ARM_ORR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
349
350#define generate_xor(ireg_dest, ireg_src) \
351 ARM_EOR_REG_REG(0, ireg_dest, ireg_dest, ireg_src) \
352
353#define generate_add_imm(ireg, imm, imm_ror) \
354 ARM_ADD_REG_IMM(0, ireg, ireg, imm, imm_ror) \
355
356#define generate_sub_imm(ireg, imm, imm_ror) \
357 ARM_SUB_REG_IMM(0, ireg, ireg, imm, imm_ror) \
358
359#define generate_xor_imm(ireg, imm, imm_ror) \
360 ARM_EOR_REG_IMM(0, ireg, ireg, imm, imm_ror) \
361
362#define generate_add_reg_reg_imm(ireg_dest, ireg_src, imm, imm_ror) \
363 ARM_ADD_REG_IMM(0, ireg_dest, ireg_src, imm, imm_ror) \
364
365#define generate_and_imm(ireg, imm, imm_ror) \
366 ARM_AND_REG_IMM(0, ireg, ireg, imm, imm_ror) \
367
368#define generate_mov(ireg_dest, ireg_src) \
369 if(ireg_dest != ireg_src) \
370 { \
371 ARM_MOV_REG_REG(0, ireg_dest, ireg_src); \
372 } \
373
374#define generate_function_call(function_location) \
375 ARM_BL(0, arm_relative_offset(translation_ptr, function_location)) \
376
377#define generate_exit_block() \
378 ARM_BX(0, ARMREG_LR) \
379
380// The branch target is to be filled in later (thus a 0 for now)
381
382#define generate_branch_filler(condition_code, writeback_location) \
383 (writeback_location) = translation_ptr; \
384 ARM_B_COND(0, condition_code, 0) \
385
386#define generate_update_pc(new_pc) \
387 generate_load_pc(reg_a0, new_pc) \
388
389#define generate_cycle_update() \
390 if(cycle_count) \
391 { \
392 if(cycle_count >> 8) \
393 { \
394 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \
395 arm_imm_lsl_to_rot(8)); \
396 } \
397 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \
398 cycle_count = 0; \
399 } \
400
401#define generate_cycle_update_flag_set() \
402 if(cycle_count >> 8) \
403 { \
404 ARM_ADD_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count >> 8) & 0xFF, \
405 arm_imm_lsl_to_rot(8)); \
406 } \
407 generate_save_flags(); \
408 ARM_ADDS_REG_IMM(0, reg_cycles, reg_cycles, (cycle_count & 0xFF), 0); \
409 cycle_count = 0 \
410
411#define generate_branch_patch_conditional(dest, offset) \
412 *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
413 arm_relative_offset(dest, offset) \
414
415#define generate_branch_patch_unconditional(dest, offset) \
416 *((u32 *)(dest)) = (*((u32 *)dest) & 0xFF000000) | \
417 arm_relative_offset(dest, offset) \
418
419// A different function is called for idle updates because of the relative
420// location of the embedded PC. The idle version could be optimized to put
421// the CPU into halt mode too, however.
422
423#define generate_branch_idle_eliminate(writeback_location, new_pc, mode) \
424 generate_function_call(arm_update_gba_idle_##mode); \
425 write32(new_pc); \
426 generate_branch_filler(ARMCOND_AL, writeback_location) \
427
428#define generate_branch_update(writeback_location, new_pc, mode) \
429 ARM_MOV_REG_IMMSHIFT(0, reg_a0, reg_cycles, ARMSHIFT_LSR, 31); \
430 ARM_ADD_REG_IMMSHIFT(0, ARMREG_PC, ARMREG_PC, reg_a0, ARMSHIFT_LSL, 2); \
431 write32(new_pc); \
432 generate_function_call(arm_update_gba_##mode); \
433 generate_branch_filler(ARMCOND_AL, writeback_location) \
434
435
436#define generate_branch_no_cycle_update(writeback_location, new_pc, mode) \
437 if(pc == idle_loop_target_pc) \
438 { \
439 generate_branch_idle_eliminate(writeback_location, new_pc, mode); \
440 } \
441 else \
442 { \
443 generate_branch_update(writeback_location, new_pc, mode); \
444 } \
445
446#define generate_branch_cycle_update(writeback_location, new_pc, mode) \
447 generate_cycle_update(); \
448 generate_branch_no_cycle_update(writeback_location, new_pc, mode) \
449
450// a0 holds the destination
451
452#define generate_indirect_branch_no_cycle_update(type) \
453 ARM_B(0, arm_relative_offset(translation_ptr, arm_indirect_branch_##type)) \
454
455#define generate_indirect_branch_cycle_update(type) \
456 generate_cycle_update(); \
457 generate_indirect_branch_no_cycle_update(type) \
458
459#define generate_block_prologue() \
460
461#define generate_block_extra_vars_arm() \
462 void generate_indirect_branch_arm() \
463 { \
464 if(condition == 0x0E) \
465 { \
466 generate_cycle_update(); \
467 } \
468 generate_indirect_branch_no_cycle_update(arm); \
469 } \
470 \
471 void generate_indirect_branch_dual() \
472 { \
473 if(condition == 0x0E) \
474 { \
475 generate_cycle_update(); \
476 } \
477 generate_indirect_branch_no_cycle_update(dual_arm); \
478 } \
479 \
480 u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \
481 { \
482 u32 reg_use = arm_register_allocation[reg_index]; \
483 if(reg_use == mem_reg) \
484 { \
485 ARM_LDR_IMM(0, scratch_reg, reg_base, \
486 (reg_base_offset + (reg_index * 4))); \
487 return scratch_reg; \
488 } \
489 \
490 return reg_use; \
491 } \
492 \
493 u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \
494 { \
495 if(reg_index == 15) \
496 { \
497 generate_load_pc(scratch_reg, pc + pc_offset); \
498 return scratch_reg; \
499 } \
500 return prepare_load_reg(scratch_reg, reg_index); \
501 } \
502 \
503 u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \
504 { \
505 u32 reg_use = arm_register_allocation[reg_index]; \
506 if(reg_use == mem_reg) \
507 return scratch_reg; \
508 \
509 return reg_use; \
510 } \
511 \
512 void complete_store_reg(u32 scratch_reg, u32 reg_index) \
513 { \
514 if(arm_register_allocation[reg_index] == mem_reg) \
515 { \
516 ARM_STR_IMM(0, scratch_reg, reg_base, \
517 (reg_base_offset + (reg_index * 4))); \
518 } \
519 } \
520 \
521 void complete_store_reg_pc_no_flags(u32 scratch_reg, u32 reg_index) \
522 { \
523 if(reg_index == 15) \
524 { \
525 generate_indirect_branch_arm(); \
526 } \
527 else \
528 { \
529 complete_store_reg(scratch_reg, reg_index); \
530 } \
531 } \
532 \
533 void complete_store_reg_pc_flags(u32 scratch_reg, u32 reg_index) \
534 { \
535 if(reg_index == 15) \
536 { \
537 if(condition == 0x0E) \
538 { \
539 generate_cycle_update(); \
540 } \
541 generate_function_call(execute_spsr_restore); \
542 } \
543 else \
544 { \
545 complete_store_reg(scratch_reg, reg_index); \
546 } \
547 } \
548 \
549 void generate_load_reg(u32 ireg, u32 reg_index) \
550 { \
551 s32 load_src = arm_register_allocation[reg_index]; \
552 if(load_src != mem_reg) \
553 { \
554 ARM_MOV_REG_REG(0, ireg, load_src); \
555 } \
556 else \
557 { \
558 ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
559 } \
560 } \
561 \
562 void generate_store_reg(u32 ireg, u32 reg_index) \
563 { \
564 s32 store_dest = arm_register_allocation[reg_index]; \
565 if(store_dest != mem_reg) \
566 { \
567 ARM_MOV_REG_REG(0, store_dest, ireg); \
568 } \
569 else \
570 { \
571 ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
572 } \
573 } \
574
575
576#define generate_block_extra_vars_thumb() \
577 u32 prepare_load_reg(u32 scratch_reg, u32 reg_index) \
578 { \
579 u32 reg_use = thumb_register_allocation[reg_index]; \
580 if(reg_use == mem_reg) \
581 { \
582 ARM_LDR_IMM(0, scratch_reg, reg_base, \
583 (reg_base_offset + (reg_index * 4))); \
584 return scratch_reg; \
585 } \
586 \
587 return reg_use; \
588 } \
589 \
590 u32 prepare_load_reg_pc(u32 scratch_reg, u32 reg_index, u32 pc_offset) \
591 { \
592 if(reg_index == 15) \
593 { \
594 generate_load_pc(scratch_reg, pc + pc_offset); \
595 return scratch_reg; \
596 } \
597 return prepare_load_reg(scratch_reg, reg_index); \
598 } \
599 \
600 u32 prepare_store_reg(u32 scratch_reg, u32 reg_index) \
601 { \
602 u32 reg_use = thumb_register_allocation[reg_index]; \
603 if(reg_use == mem_reg) \
604 return scratch_reg; \
605 \
606 return reg_use; \
607 } \
608 \
609 void complete_store_reg(u32 scratch_reg, u32 reg_index) \
610 { \
611 if(thumb_register_allocation[reg_index] == mem_reg) \
612 { \
613 ARM_STR_IMM(0, scratch_reg, reg_base, \
614 (reg_base_offset + (reg_index * 4))); \
615 } \
616 } \
617 \
618 void generate_load_reg(u32 ireg, u32 reg_index) \
619 { \
620 s32 load_src = thumb_register_allocation[reg_index]; \
621 if(load_src != mem_reg) \
622 { \
623 ARM_MOV_REG_REG(0, ireg, load_src); \
624 } \
625 else \
626 { \
627 ARM_LDR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
628 } \
629 } \
630 \
631 void generate_store_reg(u32 ireg, u32 reg_index) \
632 { \
633 s32 store_dest = thumb_register_allocation[reg_index]; \
634 if(store_dest != mem_reg) \
635 { \
636 ARM_MOV_REG_REG(0, store_dest, ireg); \
637 } \
638 else \
639 { \
640 ARM_STR_IMM(0, ireg, reg_base, (reg_base_offset + (reg_index * 4))); \
641 } \
642 } \
643
4c808278 644u8 *last_rom_translation_ptr = rom_translation_cache;
645u8 *last_ram_translation_ptr = ram_translation_cache;
646u8 *last_bios_translation_ptr = bios_translation_cache;
647
648#define translate_invalidate_dcache_one(which) \
4c808278 649 if (which##_translation_ptr > last_##which##_translation_ptr) \
650 { \
f50ad10a 651 warm_cache_op_range(WOP_D_CLEAN, last_##which##_translation_ptr, \
652 which##_translation_ptr - last_##which##_translation_ptr); \
4c808278 653 warm_cache_op_range(WOP_I_INVALIDATE, last_##which##_translation_ptr, 32);\
654 last_##which##_translation_ptr = which##_translation_ptr; \
655 }
656
2823a4c8 657#define translate_invalidate_dcache() \
658{ \
4c808278 659 translate_invalidate_dcache_one(rom) \
660 translate_invalidate_dcache_one(ram) \
661 translate_invalidate_dcache_one(bios) \
4c808278 662}
663
664#define invalidate_icache_region(addr, size) \
665 warm_cache_op_range(WOP_I_INVALIDATE, addr, size)
666
2823a4c8 667
668#define block_prologue_size 0
669
670
671// It should be okay to still generate result flags, spsr will overwrite them.
672// This is pretty infrequent (returning from interrupt handlers, et al) so
673// probably not worth optimizing for.
674
675#define check_for_interrupts() \
676 if((io_registers[REG_IE] & io_registers[REG_IF]) && \
677 io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \
678 { \
679 reg_mode[MODE_IRQ][6] = pc + 4; \
680 spsr[MODE_IRQ] = reg[REG_CPSR]; \
681 reg[REG_CPSR] = 0xD2; \
682 pc = 0x00000018; \
683 set_cpu_mode(MODE_IRQ); \
684 } \
685
686#define generate_load_reg_pc(ireg, reg_index, pc_offset) \
687 if(reg_index == 15) \
688 { \
689 generate_load_pc(ireg, pc + pc_offset); \
690 } \
691 else \
692 { \
693 generate_load_reg(ireg, reg_index); \
694 } \
695
696#define generate_store_reg_pc_no_flags(ireg, reg_index) \
697 generate_store_reg(ireg, reg_index); \
698 if(reg_index == 15) \
699 { \
700 generate_indirect_branch_arm(); \
701 } \
702
703
704u32 function_cc execute_spsr_restore_body(u32 pc)
705{
706 set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]);
707 check_for_interrupts();
708
709 return pc;
710}
711
712
713#define generate_store_reg_pc_flags(ireg, reg_index) \
714 generate_store_reg(ireg, reg_index); \
715 if(reg_index == 15) \
716 { \
717 if(condition == 0x0E) \
718 { \
719 generate_cycle_update(); \
720 } \
721 generate_function_call(execute_spsr_restore); \
722 } \
723
724
725#define generate_load_flags() \
726/* ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) */ \
727
728#define generate_store_flags() \
729/* ARM_MRS_CPSR(0, reg_flags) */ \
730
731#define generate_save_flags() \
732 ARM_MRS_CPSR(0, reg_flags) \
733
734#define generate_restore_flags() \
735 ARM_MSR_REG(0, ARM_PSR_F, reg_flags, ARM_CPSR) \
736
737
738#define condition_opposite_eq ARMCOND_NE
739#define condition_opposite_ne ARMCOND_EQ
740#define condition_opposite_cs ARMCOND_CC
741#define condition_opposite_cc ARMCOND_CS
742#define condition_opposite_mi ARMCOND_PL
743#define condition_opposite_pl ARMCOND_MI
744#define condition_opposite_vs ARMCOND_VC
745#define condition_opposite_vc ARMCOND_VS
746#define condition_opposite_hi ARMCOND_LS
747#define condition_opposite_ls ARMCOND_HI
748#define condition_opposite_ge ARMCOND_LT
749#define condition_opposite_lt ARMCOND_GE
750#define condition_opposite_gt ARMCOND_LE
751#define condition_opposite_le ARMCOND_GT
752#define condition_opposite_al ARMCOND_NV
753#define condition_opposite_nv ARMCOND_AL
754
755#define generate_branch(mode) \
756{ \
757 generate_branch_cycle_update( \
758 block_exits[block_exit_position].branch_source, \
759 block_exits[block_exit_position].branch_target, mode); \
760 block_exit_position++; \
761} \
762
763
764#define generate_op_and_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
765 ARM_AND_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
766
767#define generate_op_orr_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
768 ARM_ORR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
769
770#define generate_op_eor_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
771 ARM_EOR_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
772
773#define generate_op_bic_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
774 ARM_BIC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
775
776#define generate_op_sub_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
777 ARM_SUB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
778
779#define generate_op_rsb_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
780 ARM_RSB_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
781
782#define generate_op_sbc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
783 ARM_SBC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
784
785#define generate_op_rsc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
786 ARM_RSC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
787
788#define generate_op_add_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
789 ARM_ADD_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
790
791#define generate_op_adc_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
792 ARM_ADC_REG_IMMSHIFT(0, _rd, _rn, _rm, shift_type, shift) \
793
794#define generate_op_mov_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
795 ARM_MOV_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
796
797#define generate_op_mvn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
798 ARM_MVN_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
799
800
801#define generate_op_and_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
802 ARM_AND_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
803
804#define generate_op_orr_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
805 ARM_ORR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
806
807#define generate_op_eor_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
808 ARM_EOR_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
809
810#define generate_op_bic_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
811 ARM_BIC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
812
813#define generate_op_sub_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
814 ARM_SUB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
815
816#define generate_op_rsb_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
817 ARM_RSB_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
818
819#define generate_op_sbc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
820 ARM_SBC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
821
822#define generate_op_rsc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
823 ARM_RSC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
824
825#define generate_op_add_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
826 ARM_ADD_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
827
828#define generate_op_adc_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
829 ARM_ADC_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
830
831#define generate_op_mov_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
832 ARM_MOV_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
833
834#define generate_op_mvn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
835 ARM_MVN_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
836
837
838#define generate_op_and_imm(_rd, _rn) \
839 ARM_AND_REG_IMM(0, _rd, _rn, imm, imm_ror) \
840
841#define generate_op_orr_imm(_rd, _rn) \
842 ARM_ORR_REG_IMM(0, _rd, _rn, imm, imm_ror) \
843
844#define generate_op_eor_imm(_rd, _rn) \
845 ARM_EOR_REG_IMM(0, _rd, _rn, imm, imm_ror) \
846
847#define generate_op_bic_imm(_rd, _rn) \
848 ARM_BIC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
849
850#define generate_op_sub_imm(_rd, _rn) \
851 ARM_SUB_REG_IMM(0, _rd, _rn, imm, imm_ror) \
852
853#define generate_op_rsb_imm(_rd, _rn) \
854 ARM_RSB_REG_IMM(0, _rd, _rn, imm, imm_ror) \
855
856#define generate_op_sbc_imm(_rd, _rn) \
857 ARM_SBC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
858
859#define generate_op_rsc_imm(_rd, _rn) \
860 ARM_RSC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
861
862#define generate_op_add_imm(_rd, _rn) \
863 ARM_ADD_REG_IMM(0, _rd, _rn, imm, imm_ror) \
864
865#define generate_op_adc_imm(_rd, _rn) \
866 ARM_ADC_REG_IMM(0, _rd, _rn, imm, imm_ror) \
867
868#define generate_op_mov_imm(_rd, _rn) \
869 ARM_MOV_REG_IMM(0, _rd, imm, imm_ror) \
870
871#define generate_op_mvn_imm(_rd, _rn) \
872 ARM_MVN_REG_IMM(0, _rd, imm, imm_ror) \
873
874
875#define generate_op_reg_immshift_lflags(name, _rd, _rn, _rm, st, shift) \
876 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \
877
878#define generate_op_reg_immshift_aflags(name, _rd, _rn, _rm, st, shift) \
879 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, shift) \
880
881#define generate_op_reg_immshift_aflags_load_c(name, _rd, _rn, _rm, st, sh) \
882 ARM_##name##_REG_IMMSHIFT(0, _rd, _rn, _rm, st, sh) \
883
884#define generate_op_reg_immshift_uflags(name, _rd, _rm, shift_type, shift) \
885 ARM_##name##_REG_IMMSHIFT(0, _rd, _rm, shift_type, shift) \
886
887#define generate_op_reg_immshift_tflags(name, _rn, _rm, shift_type, shift) \
888 ARM_##name##_REG_IMMSHIFT(0, _rn, _rm, shift_type, shift) \
889
890
891#define generate_op_reg_regshift_lflags(name, _rd, _rn, _rm, shift_type, _rs) \
892 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, shift_type, _rs) \
893
894#define generate_op_reg_regshift_aflags(name, _rd, _rn, _rm, st, _rs) \
895 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \
896
897#define generate_op_reg_regshift_aflags_load_c(name, _rd, _rn, _rm, st, _rs) \
898 ARM_##name##_REG_REGSHIFT(0, _rd, _rn, _rm, st, _rs) \
899
900#define generate_op_reg_regshift_uflags(name, _rd, _rm, shift_type, _rs) \
901 ARM_##name##_REG_REGSHIFT(0, _rd, _rm, shift_type, _rs) \
902
903#define generate_op_reg_regshift_tflags(name, _rn, _rm, shift_type, _rs) \
904 ARM_##name##_REG_REGSHIFT(0, _rn, _rm, shift_type, _rs) \
905
906
907#define generate_op_imm_lflags(name, _rd, _rn) \
908 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
909
910#define generate_op_imm_aflags(name, _rd, _rn) \
911 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
912
913#define generate_op_imm_aflags_load_c(name, _rd, _rn) \
914 ARM_##name##_REG_IMM(0, _rd, _rn, imm, imm_ror) \
915
916#define generate_op_imm_uflags(name, _rd) \
917 ARM_##name##_REG_IMM(0, _rd, imm, imm_ror) \
918
919#define generate_op_imm_tflags(name, _rn) \
920 ARM_##name##_REG_IMM(0, _rn, imm, imm_ror) \
921
922
923#define generate_op_ands_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
924 generate_op_reg_immshift_lflags(ANDS, _rd, _rn, _rm, shift_type, shift) \
925
926#define generate_op_orrs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
927 generate_op_reg_immshift_lflags(ORRS, _rd, _rn, _rm, shift_type, shift) \
928
929#define generate_op_eors_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
930 generate_op_reg_immshift_lflags(EORS, _rd, _rn, _rm, shift_type, shift) \
931
932#define generate_op_bics_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
933 generate_op_reg_immshift_lflags(BICS, _rd, _rn, _rm, shift_type, shift) \
934
935#define generate_op_subs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
936 generate_op_reg_immshift_aflags(SUBS, _rd, _rn, _rm, shift_type, shift) \
937
938#define generate_op_rsbs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
939 generate_op_reg_immshift_aflags(RSBS, _rd, _rn, _rm, shift_type, shift) \
940
941#define generate_op_sbcs_reg_immshift(_rd, _rn, _rm, st, shift) \
942 generate_op_reg_immshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, shift) \
943
944#define generate_op_rscs_reg_immshift(_rd, _rn, _rm, st, shift) \
945 generate_op_reg_immshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, shift) \
946
947#define generate_op_adds_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
948 generate_op_reg_immshift_aflags(ADDS, _rd, _rn, _rm, shift_type, shift) \
949
950#define generate_op_adcs_reg_immshift(_rd, _rn, _rm, st, shift) \
951 generate_op_reg_immshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, shift) \
952
953#define generate_op_movs_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
954 generate_op_reg_immshift_uflags(MOVS, _rd, _rm, shift_type, shift) \
955
956#define generate_op_mvns_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
957 generate_op_reg_immshift_uflags(MVNS, _rd, _rm, shift_type, shift) \
958
959// The reg operand is in reg_rm, not reg_rn like expected, so rsbs isn't
960// being used here. When rsbs is fully inlined it can be used with the
961// apropriate operands.
962
963#define generate_op_neg_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
964{ \
965 generate_load_imm(reg_rn, 0, 0); \
966 generate_op_subs_reg_immshift(_rd, reg_rn, _rm, ARMSHIFT_LSL, 0); \
967} \
968
969#define generate_op_muls_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
970 generate_load_flags(); \
971 ARM_MULS(0, _rd, _rn, _rm); \
972 generate_store_flags() \
973
974#define generate_op_cmp_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
975 generate_op_reg_immshift_tflags(CMP, _rn, _rm, shift_type, shift) \
976
977#define generate_op_cmn_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
978 generate_op_reg_immshift_tflags(CMN, _rn, _rm, shift_type, shift) \
979
980#define generate_op_tst_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
981 generate_op_reg_immshift_tflags(TST, _rn, _rm, shift_type, shift) \
982
983#define generate_op_teq_reg_immshift(_rd, _rn, _rm, shift_type, shift) \
984 generate_op_reg_immshift_tflags(TEQ, _rn, _rm, shift_type, shift) \
985
986
987#define generate_op_ands_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
988 generate_op_reg_regshift_lflags(ANDS, _rd, _rn, _rm, shift_type, _rs) \
989
990#define generate_op_orrs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
991 generate_op_reg_regshift_lflags(ORRS, _rd, _rn, _rm, shift_type, _rs) \
992
993#define generate_op_eors_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
994 generate_op_reg_regshift_lflags(EORS, _rd, _rn, _rm, shift_type, _rs) \
995
996#define generate_op_bics_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
997 generate_op_reg_regshift_lflags(BICS, _rd, _rn, _rm, shift_type, _rs) \
998
999#define generate_op_subs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1000 generate_op_reg_regshift_aflags(SUBS, _rd, _rn, _rm, shift_type, _rs) \
1001
1002#define generate_op_rsbs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1003 generate_op_reg_regshift_aflags(RSBS, _rd, _rn, _rm, shift_type, _rs) \
1004
1005#define generate_op_sbcs_reg_regshift(_rd, _rn, _rm, st, _rs) \
1006 generate_op_reg_regshift_aflags_load_c(SBCS, _rd, _rn, _rm, st, _rs) \
1007
1008#define generate_op_rscs_reg_regshift(_rd, _rn, _rm, st, _rs) \
1009 generate_op_reg_regshift_aflags_load_c(RSCS, _rd, _rn, _rm, st, _rs) \
1010
1011#define generate_op_adds_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1012 generate_op_reg_regshift_aflags(ADDS, _rd, _rn, _rm, shift_type, _rs) \
1013
1014#define generate_op_adcs_reg_regshift(_rd, _rn, _rm, st, _rs) \
1015 generate_op_reg_regshift_aflags_load_c(ADCS, _rd, _rn, _rm, st, _rs) \
1016
1017#define generate_op_movs_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1018 generate_op_reg_regshift_uflags(MOVS, _rd, _rm, shift_type, _rs) \
1019
1020#define generate_op_mvns_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1021 generate_op_reg_regshift_uflags(MVNS, _rd, _rm, shift_type, _rs) \
1022
1023#define generate_op_cmp_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1024 generate_op_reg_regshift_tflags(CMP, _rn, _rm, shift_type, _rs) \
1025
1026#define generate_op_cmn_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1027 generate_op_reg_regshift_tflags(CMN, _rn, _rm, shift_type, _rs) \
1028
1029#define generate_op_tst_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1030 generate_op_reg_regshift_tflags(TST, _rn, _rm, shift_type, _rs) \
1031
1032#define generate_op_teq_reg_regshift(_rd, _rn, _rm, shift_type, _rs) \
1033 generate_op_reg_regshift_tflags(TEQ, _rn, _rm, shift_type, _rs) \
1034
1035
1036#define generate_op_ands_imm(_rd, _rn) \
1037 generate_op_imm_lflags(ANDS, _rd, _rn) \
1038
1039#define generate_op_orrs_imm(_rd, _rn) \
1040 generate_op_imm_lflags(ORRS, _rd, _rn) \
1041
1042#define generate_op_eors_imm(_rd, _rn) \
1043 generate_op_imm_lflags(EORS, _rd, _rn) \
1044
1045#define generate_op_bics_imm(_rd, _rn) \
1046 generate_op_imm_lflags(BICS, _rd, _rn) \
1047
1048#define generate_op_subs_imm(_rd, _rn) \
1049 generate_op_imm_aflags(SUBS, _rd, _rn) \
1050
1051#define generate_op_rsbs_imm(_rd, _rn) \
1052 generate_op_imm_aflags(RSBS, _rd, _rn) \
1053
1054#define generate_op_sbcs_imm(_rd, _rn) \
1055 generate_op_imm_aflags_load_c(SBCS, _rd, _rn) \
1056
1057#define generate_op_rscs_imm(_rd, _rn) \
1058 generate_op_imm_aflags_load_c(RSCS, _rd, _rn) \
1059
1060#define generate_op_adds_imm(_rd, _rn) \
1061 generate_op_imm_aflags(ADDS, _rd, _rn) \
1062
1063#define generate_op_adcs_imm(_rd, _rn) \
1064 generate_op_imm_aflags_load_c(ADCS, _rd, _rn) \
1065
1066#define generate_op_movs_imm(_rd, _rn) \
1067 generate_op_imm_uflags(MOVS, _rd) \
1068
1069#define generate_op_mvns_imm(_rd, _rn) \
1070 generate_op_imm_uflags(MVNS, _rd) \
1071
1072#define generate_op_cmp_imm(_rd, _rn) \
1073 generate_op_imm_tflags(CMP, _rn) \
1074
1075#define generate_op_cmn_imm(_rd, _rn) \
1076 generate_op_imm_tflags(CMN, _rn) \
1077
1078#define generate_op_tst_imm(_rd, _rn) \
1079 generate_op_imm_tflags(TST, _rn) \
1080
1081#define generate_op_teq_imm(_rd, _rn) \
1082 generate_op_imm_tflags(TEQ, _rn) \
1083
1084
1085#define prepare_load_rn_yes() \
1086 u32 _rn = prepare_load_reg_pc(reg_rn, rn, 8) \
1087
1088#define prepare_load_rn_no() \
1089
1090#define prepare_store_rd_yes() \
1091 u32 _rd = prepare_store_reg(reg_rd, rd) \
1092
1093#define prepare_store_rd_no() \
1094
1095#define complete_store_rd_yes(flags_op) \
1096 complete_store_reg_pc_##flags_op(_rd, rd) \
1097
1098#define complete_store_rd_no(flags_op) \
1099
1100#define arm_generate_op_reg(name, load_op, store_op, flags_op) \
1101 u32 shift_type = (opcode >> 5) & 0x03; \
1102 arm_decode_data_proc_reg(); \
1103 prepare_load_rn_##load_op(); \
1104 prepare_store_rd_##store_op(); \
1105 \
1106 if((opcode >> 4) & 0x01) \
1107 { \
1108 u32 rs = ((opcode >> 8) & 0x0F); \
1109 u32 _rs = prepare_load_reg(reg_rs, rs); \
1110 u32 _rm = prepare_load_reg_pc(reg_rm, rm, 12); \
1111 generate_op_##name##_reg_regshift(_rd, _rn, _rm, shift_type, _rs); \
1112 } \
1113 else \
1114 { \
1115 u32 shift_imm = ((opcode >> 7) & 0x1F); \
1116 u32 _rm = prepare_load_reg_pc(reg_rm, rm, 8); \
1117 generate_op_##name##_reg_immshift(_rd, _rn, _rm, shift_type, shift_imm); \
1118 } \
1119 complete_store_rd_##store_op(flags_op) \
1120
1121#define arm_generate_op_reg_flags(name, load_op, store_op, flags_op) \
1122 arm_generate_op_reg(name, load_op, store_op, flags_op) \
1123
1124// imm will be loaded by the called function if necessary.
1125
1126#define arm_generate_op_imm(name, load_op, store_op, flags_op) \
1127 arm_decode_data_proc_imm(); \
1128 prepare_load_rn_##load_op(); \
1129 prepare_store_rd_##store_op(); \
1130 generate_op_##name##_imm(_rd, _rn); \
1131 complete_store_rd_##store_op(flags_op) \
1132
1133#define arm_generate_op_imm_flags(name, load_op, store_op, flags_op) \
1134 arm_generate_op_imm(name, load_op, store_op, flags_op) \
1135
1136#define arm_data_proc(name, type, flags_op) \
1137{ \
1138 arm_generate_op_##type(name, yes, yes, flags_op); \
1139} \
1140
1141#define arm_data_proc_test(name, type) \
1142{ \
1143 arm_generate_op_##type(name, yes, no, no); \
1144} \
1145
1146#define arm_data_proc_unary(name, type, flags_op) \
1147{ \
1148 arm_generate_op_##type(name, no, yes, flags_op); \
1149} \
1150
1151
1152#define arm_multiply_add_no_flags_no() \
1153 ARM_MUL(0, _rd, _rm, _rs) \
1154
1155#define arm_multiply_add_yes_flags_no() \
1156 u32 _rn = prepare_load_reg(reg_a2, rn); \
1157 ARM_MLA(0, _rd, _rm, _rs, _rn) \
1158
1159#define arm_multiply_add_no_flags_yes() \
1160 generate_load_flags(); \
1161 ARM_MULS(0, reg_a0, reg_a0, reg_a1) \
1162 generate_store_flags() \
1163
1164#define arm_multiply_add_yes_flags_yes() \
1165 u32 _rn = prepare_load_reg(reg_a2, rn); \
1166 generate_load_flags(); \
1167 ARM_MLAS(0, _rd, _rm, _rs, _rn); \
1168 generate_store_flags()
1169
1170
1171#define arm_multiply(add_op, flags) \
1172{ \
1173 arm_decode_multiply(); \
1174 u32 _rm = prepare_load_reg(reg_a0, rm); \
1175 u32 _rs = prepare_load_reg(reg_a1, rs); \
1176 u32 _rd = prepare_store_reg(reg_a0, rd); \
1177 arm_multiply_add_##add_op##_flags_##flags(); \
1178 complete_store_reg(_rd, rd); \
1179} \
1180
1181
1182#define arm_multiply_long_name_s64 SMULL
1183#define arm_multiply_long_name_u64 UMULL
1184#define arm_multiply_long_name_s64_add SMLAL
1185#define arm_multiply_long_name_u64_add UMLAL
1186
1187
1188#define arm_multiply_long_flags_no(name) \
1189 ARM_##name(0, _rdlo, _rdhi, _rm, _rs) \
1190
1191#define arm_multiply_long_flags_yes(name) \
1192 generate_load_flags(); \
1193 ARM_##name##S(0, _rdlo, _rdhi, _rm, _rs); \
1194 generate_store_flags() \
1195
1196
1197#define arm_multiply_long_add_no(name) \
1198
1199#define arm_multiply_long_add_yes(name) \
1200 prepare_load_reg(reg_a0, rdlo); \
1201 prepare_load_reg(reg_a1, rdhi) \
1202
1203
1204#define arm_multiply_long_op(flags, name) \
1205 arm_multiply_long_flags_##flags(name) \
1206
1207#define arm_multiply_long(name, add_op, flags) \
1208{ \
1209 arm_decode_multiply_long(); \
1210 u32 _rm = prepare_load_reg(reg_a2, rm); \
1211 u32 _rs = prepare_load_reg(reg_rs, rs); \
1212 u32 _rdlo = prepare_store_reg(reg_a0, rdlo); \
1213 u32 _rdhi = prepare_store_reg(reg_a1, rdhi); \
1214 arm_multiply_long_add_##add_op(name); \
1215 arm_multiply_long_op(flags, arm_multiply_long_name_##name); \
1216 complete_store_reg(_rdlo, rdlo); \
1217 complete_store_reg(_rdhi, rdhi); \
1218} \
1219
1220#define arm_psr_read_cpsr() \
1221 u32 _rd = prepare_store_reg(reg_a0, rd); \
1222 generate_load_reg(_rd, REG_CPSR); \
1223 ARM_BIC_REG_IMM(0, _rd, _rd, 0xF0, arm_imm_lsl_to_rot(24)); \
1224 ARM_AND_REG_IMM(0, reg_flags, reg_flags, 0xF0, arm_imm_lsl_to_rot(24)); \
1225 ARM_ORR_REG_REG(0, _rd, _rd, reg_flags); \
1226 complete_store_reg(_rd, rd) \
1227
1228#define arm_psr_read_spsr() \
1229 generate_function_call(execute_read_spsr) \
1230 generate_store_reg(reg_a0, rd) \
1231
1232#define arm_psr_read(op_type, psr_reg) \
1233 arm_psr_read_##psr_reg() \
1234
1235// This function's okay because it's called from an ASM function that can
1236// wrap it correctly.
1237
1238u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
1239{
1240 reg[REG_CPSR] = _cpsr;
1241 if(store_mask & 0xFF)
1242 {
1243 set_cpu_mode(cpu_modes[_cpsr & 0x1F]);
1244 if((io_registers[REG_IE] & io_registers[REG_IF]) &&
1245 io_registers[REG_IME] && ((_cpsr & 0x80) == 0))
1246 {
1247 reg_mode[MODE_IRQ][6] = address + 4;
1248 spsr[MODE_IRQ] = _cpsr;
1249 reg[REG_CPSR] = 0xD2;
1250 set_cpu_mode(MODE_IRQ);
1251 return 0x00000018;
1252 }
1253 }
1254
1255 return 0;
1256}
1257
1258#define arm_psr_load_new_reg() \
1259 generate_load_reg(reg_a0, rm) \
1260
1261#define arm_psr_load_new_imm() \
1262 generate_load_imm(reg_a0, imm, imm_ror) \
1263
1264#define arm_psr_store_cpsr() \
1265 arm_load_imm_32bit(reg_a1, psr_masks[psr_field]); \
1266 generate_function_call(execute_store_cpsr); \
1267 write32(pc) \
1268
1269#define arm_psr_store_spsr() \
1270 generate_function_call(execute_store_spsr) \
1271
1272#define arm_psr_store(op_type, psr_reg) \
1273 arm_psr_load_new_##op_type(); \
1274 arm_psr_store_##psr_reg() \
1275
1276
1277#define arm_psr(op_type, transfer_type, psr_reg) \
1278{ \
1279 arm_decode_psr_##op_type(); \
1280 arm_psr_##transfer_type(op_type, psr_reg); \
1281} \
1282
1283// TODO: loads will need the PC passed as well for open address, however can
1284// eventually be rectified with a hash table on the memory accesses
1285// (same with the stores)
1286
1287#define arm_access_memory_load(mem_type) \
1288 cycle_count += 2; \
1289 generate_function_call(execute_load_##mem_type); \
1290 write32((pc + 8)); \
1291 generate_store_reg_pc_no_flags(reg_rv, rd) \
1292
1293#define arm_access_memory_store(mem_type) \
1294 cycle_count++; \
1295 generate_load_reg_pc(reg_a1, rd, 12); \
1296 generate_function_call(execute_store_##mem_type); \
1297 write32((pc + 4)) \
1298
1299// Calculate the address into a0 from _rn, _rm
1300
1301#define arm_access_memory_adjust_reg_sh_up(ireg) \
1302 ARM_ADD_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \
1303 ((opcode >> 7) & 0x1F)) \
1304
1305#define arm_access_memory_adjust_reg_sh_down(ireg) \
1306 ARM_SUB_REG_IMMSHIFT(0, ireg, _rn, _rm, ((opcode >> 5) & 0x03), \
1307 ((opcode >> 7) & 0x1F)) \
1308
1309#define arm_access_memory_adjust_reg_up(ireg) \
1310 ARM_ADD_REG_REG(0, ireg, _rn, _rm) \
1311
1312#define arm_access_memory_adjust_reg_down(ireg) \
1313 ARM_SUB_REG_REG(0, ireg, _rn, _rm) \
1314
1315#define arm_access_memory_adjust_imm(op, ireg) \
1316{ \
1317 u32 stores[4]; \
1318 u32 rotations[4]; \
1319 u32 store_count = arm_disect_imm_32bit(offset, stores, rotations); \
1320 \
1321 if(store_count > 1) \
1322 { \
1323 ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \
1324 ARM_##op##_REG_IMM(0, ireg, ireg, stores[1], rotations[1]); \
1325 } \
1326 else \
1327 { \
1328 ARM_##op##_REG_IMM(0, ireg, _rn, stores[0], rotations[0]); \
1329 } \
1330} \
1331
1332#define arm_access_memory_adjust_imm_up(ireg) \
1333 arm_access_memory_adjust_imm(ADD, ireg) \
1334
1335#define arm_access_memory_adjust_imm_down(ireg) \
1336 arm_access_memory_adjust_imm(SUB, ireg) \
1337
1338
1339#define arm_access_memory_pre(type, direction) \
1340 arm_access_memory_adjust_##type##_##direction(reg_a0) \
1341
1342#define arm_access_memory_pre_wb(type, direction) \
1343 arm_access_memory_adjust_##type##_##direction(reg_a0); \
1344 generate_store_reg(reg_a0, rn) \
1345
1346#define arm_access_memory_post(type, direction) \
1347 u32 _rn_dest = prepare_store_reg(reg_a1, rn); \
1348 if(_rn != reg_a0) \
1349 { \
1350 generate_load_reg(reg_a0, rn); \
1351 } \
1352 arm_access_memory_adjust_##type##_##direction(_rn_dest); \
1353 complete_store_reg(_rn_dest, rn) \
1354
1355
1356#define arm_data_trans_reg(adjust_op, direction) \
1357 arm_decode_data_trans_reg(); \
1358 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1359 u32 _rm = prepare_load_reg(reg_a1, rm); \
1360 arm_access_memory_##adjust_op(reg_sh, direction) \
1361
1362#define arm_data_trans_imm(adjust_op, direction) \
1363 arm_decode_data_trans_imm(); \
1364 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1365 arm_access_memory_##adjust_op(imm, direction) \
1366
1367
1368#define arm_data_trans_half_reg(adjust_op, direction) \
1369 arm_decode_half_trans_r(); \
1370 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1371 u32 _rm = prepare_load_reg(reg_a1, rm); \
1372 arm_access_memory_##adjust_op(reg, direction) \
1373
1374#define arm_data_trans_half_imm(adjust_op, direction) \
1375 arm_decode_half_trans_of(); \
1376 u32 _rn = prepare_load_reg_pc(reg_a0, rn, 8); \
1377 arm_access_memory_##adjust_op(imm, direction) \
1378
1379
1380#define arm_access_memory(access_type, direction, adjust_op, mem_type, \
1381 offset_type) \
1382{ \
1383 arm_data_trans_##offset_type(adjust_op, direction); \
1384 arm_access_memory_##access_type(mem_type); \
1385} \
1386
1387
1388#define word_bit_count(word) \
1389 (bit_count[word >> 8] + bit_count[word & 0xFF]) \
1390
1391#define sprint_no(access_type, pre_op, post_op, wb) \
1392
1393#define sprint_yes(access_type, pre_op, post_op, wb) \
1394 printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
1395
1396
1397// TODO: Make these use cached registers. Implement iwram_stack_optimize.
1398
1399#define arm_block_memory_load() \
1400 generate_function_call(execute_load_u32); \
1401 write32((pc + 8)); \
1402 generate_store_reg(reg_rv, i) \
1403
1404#define arm_block_memory_store() \
1405 generate_load_reg_pc(reg_a1, i, 8); \
1406 generate_function_call(execute_store_u32_safe) \
1407
1408#define arm_block_memory_final_load() \
1409 arm_block_memory_load() \
1410
1411#define arm_block_memory_final_store() \
1412 generate_load_reg_pc(reg_a1, i, 12); \
1413 generate_function_call(execute_store_u32); \
1414 write32((pc + 4)) \
1415
1416#define arm_block_memory_adjust_pc_store() \
1417
1418#define arm_block_memory_adjust_pc_load() \
1419 if(reg_list & 0x8000) \
1420 { \
1421 generate_mov(reg_a0, reg_rv); \
1422 generate_indirect_branch_arm(); \
1423 } \
1424
1425#define arm_block_memory_offset_down_a() \
1426 generate_sub_imm(reg_s0, ((word_bit_count(reg_list) * 4) - 4), 0) \
1427
1428#define arm_block_memory_offset_down_b() \
1429 generate_sub_imm(reg_s0, (word_bit_count(reg_list) * 4), 0) \
1430
1431#define arm_block_memory_offset_no() \
1432
1433#define arm_block_memory_offset_up() \
1434 generate_add_imm(reg_s0, 4, 0) \
1435
1436#define arm_block_memory_writeback_down() \
1437 generate_load_reg(reg_a0, rn); \
1438 generate_sub_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \
1439 generate_store_reg(reg_a0, rn) \
1440
1441#define arm_block_memory_writeback_up() \
1442 generate_load_reg(reg_a0, rn); \
1443 generate_add_imm(reg_a0, (word_bit_count(reg_list) * 4), 0); \
1444 generate_store_reg(reg_a0, rn) \
1445
1446#define arm_block_memory_writeback_no()
1447
1448// Only emit writeback if the register is not in the list
1449
1450#define arm_block_memory_writeback_load(writeback_type) \
1451 if(!((reg_list >> rn) & 0x01)) \
1452 { \
1453 arm_block_memory_writeback_##writeback_type(); \
1454 } \
1455
1456#define arm_block_memory_writeback_store(writeback_type) \
1457 arm_block_memory_writeback_##writeback_type() \
1458
1459#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \
1460{ \
1461 arm_decode_block_trans(); \
1462 u32 offset = 0; \
1463 u32 i; \
1464 \
1465 generate_load_reg(reg_s0, rn); \
1466 arm_block_memory_offset_##offset_type(); \
1467 arm_block_memory_writeback_##access_type(writeback_type); \
1468 ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
1469 \
1470 for(i = 0; i < 16; i++) \
1471 { \
1472 if((reg_list >> i) & 0x01) \
1473 { \
1474 cycle_count++; \
1475 generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
1476 if(reg_list & ~((2 << i) - 1)) \
1477 { \
1478 arm_block_memory_##access_type(); \
1479 offset += 4; \
1480 } \
1481 else \
1482 { \
1483 arm_block_memory_final_##access_type(); \
1484 break; \
1485 } \
1486 } \
1487 } \
1488 \
1489 arm_block_memory_adjust_pc_##access_type(); \
1490} \
1491
1492#define arm_swap(type) \
1493{ \
1494 arm_decode_swap(); \
1495 cycle_count += 3; \
1496 generate_load_reg(reg_a0, rn); \
1497 generate_function_call(execute_load_##type); \
1498 write32((pc + 8)); \
1499 generate_mov(reg_s0, reg_rv); \
1500 generate_load_reg(reg_a0, rn); \
1501 generate_load_reg(reg_a1, rm); \
1502 generate_function_call(execute_store_##type); \
1503 write32((pc + 4)); \
1504 generate_store_reg(reg_s0, rd); \
1505} \
1506
1507
1508#define thumb_generate_op_reg(name, _rd, _rs, _rn) \
1509 u32 __rm = prepare_load_reg(reg_rm, _rn); \
1510 generate_op_##name##_reg_immshift(__rd, __rn, __rm, ARMSHIFT_LSL, 0) \
1511
1512#define thumb_generate_op_imm(name, _rd, _rs, imm_) \
1513{ \
1514 u32 imm_ror = 0; \
1515 generate_op_##name##_imm(__rd, __rn); \
1516} \
1517
1518
1519#define thumb_data_proc(type, name, op_type, _rd, _rs, _rn) \
1520{ \
1521 thumb_decode_##type(); \
1522 u32 __rn = prepare_load_reg(reg_rn, _rs); \
1523 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1524 generate_load_reg(reg_rn, _rs); \
1525 thumb_generate_op_##op_type(name, _rd, _rs, _rn); \
1526 complete_store_reg(__rd, _rd); \
1527} \
1528
1529#define thumb_data_proc_test(type, name, op_type, _rd, _rs) \
1530{ \
1531 thumb_decode_##type(); \
1532 u32 __rn = prepare_load_reg(reg_rn, _rd); \
1533 thumb_generate_op_##op_type(name, 0, _rd, _rs); \
1534} \
1535
1536#define thumb_data_proc_unary(type, name, op_type, _rd, _rs) \
1537{ \
1538 thumb_decode_##type(); \
1539 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1540 thumb_generate_op_##op_type(name, _rd, 0, _rs); \
1541 complete_store_reg(__rd, _rd); \
1542} \
1543
1544
1545#define complete_store_reg_pc_thumb() \
1546 if(rd == 15) \
1547 { \
1548 generate_indirect_branch_cycle_update(thumb); \
1549 } \
1550 else \
1551 { \
1552 complete_store_reg(_rd, rd); \
1553 } \
1554
1555#define thumb_data_proc_hi(name) \
1556{ \
1557 thumb_decode_hireg_op(); \
1558 u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \
1559 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1560 generate_op_##name##_reg_immshift(_rd, _rd, _rs, ARMSHIFT_LSL, 0); \
1561 complete_store_reg_pc_thumb(); \
1562} \
1563
1564#define thumb_data_proc_test_hi(name) \
1565{ \
1566 thumb_decode_hireg_op(); \
1567 u32 _rd = prepare_load_reg_pc(reg_rd, rd, 4); \
1568 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1569 generate_op_##name##_reg_immshift(0, _rd, _rs, ARMSHIFT_LSL, 0); \
1570} \
1571
1572#define thumb_data_proc_mov_hi() \
1573{ \
1574 thumb_decode_hireg_op(); \
1575 u32 _rs = prepare_load_reg_pc(reg_rn, rs, 4); \
1576 u32 _rd = prepare_store_reg(reg_rd, rd); \
1577 ARM_MOV_REG_REG(0, _rd, _rs); \
1578 complete_store_reg_pc_thumb(); \
1579} \
1580
1581
1582
1583#define thumb_load_pc(_rd) \
1584{ \
1585 thumb_decode_imm(); \
1586 u32 __rd = prepare_store_reg(reg_rd, _rd); \
1587 generate_load_pc(__rd, (((pc & ~2) + 4) + (imm * 4))); \
1588 complete_store_reg(__rd, _rd); \
1589} \
1590
1591#define thumb_load_sp(_rd) \
1592{ \
1593 thumb_decode_imm(); \
1594 u32 __sp = prepare_load_reg(reg_a0, REG_SP); \
1595 u32 __rd = prepare_store_reg(reg_a0, _rd); \
1596 ARM_ADD_REG_IMM(0, __rd, __sp, imm, arm_imm_lsl_to_rot(2)); \
1597 complete_store_reg(__rd, _rd); \
1598} \
1599
1600#define thumb_adjust_sp_up() \
1601 ARM_ADD_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \
1602
1603#define thumb_adjust_sp_down() \
1604 ARM_SUB_REG_IMM(0, _sp, _sp, imm, arm_imm_lsl_to_rot(2)) \
1605
1606#define thumb_adjust_sp(direction) \
1607{ \
1608 thumb_decode_add_sp(); \
1609 u32 _sp = prepare_load_reg(reg_a0, REG_SP); \
1610 thumb_adjust_sp_##direction(); \
1611 complete_store_reg(_sp, REG_SP); \
1612} \
1613
1614#define generate_op_lsl_reg(_rd, _rm, _rs) \
1615 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSL, _rs) \
1616
1617#define generate_op_lsr_reg(_rd, _rm, _rs) \
1618 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_LSR, _rs) \
1619
1620#define generate_op_asr_reg(_rd, _rm, _rs) \
1621 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ASR, _rs) \
1622
1623#define generate_op_ror_reg(_rd, _rm, _rs) \
1624 generate_op_movs_reg_regshift(_rd, 0, _rm, ARMSHIFT_ROR, _rs) \
1625
1626
1627#define generate_op_lsl_imm(_rd, _rm) \
1628 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSL, imm) \
1629
1630#define generate_op_lsr_imm(_rd, _rm) \
1631 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_LSR, imm) \
1632
1633#define generate_op_asr_imm(_rd, _rm) \
1634 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ASR, imm) \
1635
1636#define generate_op_ror_imm(_rd, _rm) \
1637 generate_op_movs_reg_immshift(_rd, 0, _rm, ARMSHIFT_ROR, imm) \
1638
1639
1640#define generate_shift_reg(op_type) \
1641 u32 __rm = prepare_load_reg(reg_rd, rd); \
1642 u32 __rs = prepare_load_reg(reg_rs, rs); \
1643 generate_op_##op_type##_reg(__rd, __rm, __rs) \
1644
1645#define generate_shift_imm(op_type) \
1646 u32 __rs = prepare_load_reg(reg_rs, rs); \
1647 generate_op_##op_type##_imm(__rd, __rs) \
1648
1649
1650#define thumb_shift(decode_type, op_type, value_type) \
1651{ \
1652 thumb_decode_##decode_type(); \
1653 u32 __rd = prepare_store_reg(reg_rd, rd); \
1654 generate_shift_##value_type(op_type); \
1655 complete_store_reg(__rd, rd); \
1656} \
1657
1658// Operation types: imm, mem_reg, mem_imm
1659
1660#define thumb_access_memory_load(mem_type, _rd) \
1661 cycle_count += 2; \
1662 generate_function_call(execute_load_##mem_type); \
1663 write32((pc + 4)); \
1664 generate_store_reg(reg_rv, _rd) \
1665
1666#define thumb_access_memory_store(mem_type, _rd) \
1667 cycle_count++; \
1668 generate_load_reg(reg_a1, _rd); \
1669 generate_function_call(execute_store_##mem_type); \
1670 write32((pc + 2)) \
1671
1672#define thumb_access_memory_generate_address_pc_relative(offset, _rb, _ro) \
1673 generate_load_pc(reg_a0, (offset)) \
1674
1675#define thumb_access_memory_generate_address_reg_imm(offset, _rb, _ro) \
1676 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1677 ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, 0) \
1678
1679#define thumb_access_memory_generate_address_reg_imm_sp(offset, _rb, _ro) \
1680 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1681 ARM_ADD_REG_IMM(0, reg_a0, __rb, offset, arm_imm_lsl_to_rot(2)) \
1682
1683#define thumb_access_memory_generate_address_reg_reg(offset, _rb, _ro) \
1684 u32 __rb = prepare_load_reg(reg_a0, _rb); \
1685 u32 __ro = prepare_load_reg(reg_a1, _ro); \
1686 ARM_ADD_REG_REG(0, reg_a0, __rb, __ro) \
1687
1688#define thumb_access_memory(access_type, op_type, _rd, _rb, _ro, \
1689 address_type, offset, mem_type) \
1690{ \
1691 thumb_decode_##op_type(); \
1692 thumb_access_memory_generate_address_##address_type(offset, _rb, _ro); \
1693 thumb_access_memory_##access_type(mem_type, _rd); \
1694} \
1695
1696// TODO: Make these use cached registers. Implement iwram_stack_optimize.
1697
1698#define thumb_block_address_preadjust_up() \
1699 generate_add_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
1700
1701#define thumb_block_address_preadjust_down() \
1702 generate_sub_imm(reg_s0, (bit_count[reg_list] * 4), 0) \
1703
1704#define thumb_block_address_preadjust_push_lr() \
1705 generate_sub_imm(reg_s0, ((bit_count[reg_list] + 1) * 4), 0) \
1706
1707#define thumb_block_address_preadjust_no() \
1708
1709#define thumb_block_address_postadjust_no(base_reg) \
1710 generate_store_reg(reg_s0, base_reg) \
1711
1712#define thumb_block_address_postadjust_up(base_reg) \
1713 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1714 generate_store_reg(reg_a0, base_reg) \
1715
1716#define thumb_block_address_postadjust_down(base_reg) \
1717 generate_mov(reg_a0, reg_s0); \
1718 generate_sub_imm(reg_a0, (bit_count[reg_list] * 4), 0); \
1719 generate_store_reg(reg_a0, base_reg) \
1720
1721#define thumb_block_address_postadjust_pop_pc(base_reg) \
1722 generate_add_reg_reg_imm(reg_a0, reg_s0, \
1723 ((bit_count[reg_list] + 1) * 4), 0); \
1724 generate_store_reg(reg_a0, base_reg) \
1725
1726#define thumb_block_address_postadjust_push_lr(base_reg) \
1727 generate_store_reg(reg_s0, base_reg) \
1728
1729#define thumb_block_memory_extra_no() \
1730
1731#define thumb_block_memory_extra_up() \
1732
1733#define thumb_block_memory_extra_down() \
1734
1735#define thumb_block_memory_extra_pop_pc() \
1736 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1737 generate_function_call(execute_load_u32); \
1738 write32((pc + 4)); \
1739 generate_mov(reg_a0, reg_rv); \
1740 generate_indirect_branch_cycle_update(thumb) \
1741
1742#define thumb_block_memory_extra_push_lr(base_reg) \
1743 generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
1744 generate_load_reg(reg_a1, REG_LR); \
1745 generate_function_call(execute_store_u32_safe) \
1746
1747#define thumb_block_memory_load() \
1748 generate_function_call(execute_load_u32); \
1749 write32((pc + 4)); \
1750 generate_store_reg(reg_rv, i) \
1751
1752#define thumb_block_memory_store() \
1753 generate_load_reg(reg_a1, i); \
1754 generate_function_call(execute_store_u32_safe) \
1755
1756#define thumb_block_memory_final_load() \
1757 thumb_block_memory_load() \
1758
1759#define thumb_block_memory_final_store() \
1760 generate_load_reg(reg_a1, i); \
1761 generate_function_call(execute_store_u32); \
1762 write32((pc + 2)) \
1763
1764#define thumb_block_memory_final_no(access_type) \
1765 thumb_block_memory_final_##access_type() \
1766
1767#define thumb_block_memory_final_up(access_type) \
1768 thumb_block_memory_final_##access_type() \
1769
1770#define thumb_block_memory_final_down(access_type) \
1771 thumb_block_memory_final_##access_type() \
1772
1773#define thumb_block_memory_final_push_lr(access_type) \
1774 thumb_block_memory_##access_type() \
1775
1776#define thumb_block_memory_final_pop_pc(access_type) \
1777 thumb_block_memory_##access_type() \
1778
1779#define thumb_block_memory(access_type, pre_op, post_op, base_reg) \
1780{ \
1781 thumb_decode_rlist(); \
1782 u32 i; \
1783 u32 offset = 0; \
1784 \
1785 generate_load_reg(reg_s0, base_reg); \
1786 ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
1787 thumb_block_address_preadjust_##pre_op(); \
1788 thumb_block_address_postadjust_##post_op(base_reg); \
1789 \
1790 for(i = 0; i < 8; i++) \
1791 { \
1792 if((reg_list >> i) & 0x01) \
1793 { \
1794 cycle_count++; \
1795 generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
1796 if(reg_list & ~((2 << i) - 1)) \
1797 { \
1798 thumb_block_memory_##access_type(); \
1799 offset += 4; \
1800 } \
1801 else \
1802 { \
1803 thumb_block_memory_final_##post_op(access_type); \
1804 break; \
1805 } \
1806 } \
1807 } \
1808 \
1809 thumb_block_memory_extra_##post_op(); \
1810} \
1811
1812#define thumb_conditional_branch(condition) \
1813{ \
1814 generate_cycle_update(); \
1815 generate_load_flags(); \
1816 generate_branch_filler(condition_opposite_##condition, backpatch_address); \
1817 generate_branch_no_cycle_update( \
1818 block_exits[block_exit_position].branch_source, \
1819 block_exits[block_exit_position].branch_target, thumb); \
1820 generate_branch_patch_conditional(backpatch_address, translation_ptr); \
1821 block_exit_position++; \
1822} \
1823
1824
1825#define arm_conditional_block_header() \
1826 generate_cycle_update(); \
1827 generate_load_flags(); \
1828 /* This will choose the opposite condition */ \
1829 condition ^= 0x01; \
1830 generate_branch_filler(condition, backpatch_address) \
1831
1832#define arm_b() \
1833 generate_branch(arm) \
1834
1835#define arm_bl() \
1836 generate_update_pc((pc + 4)); \
1837 generate_store_reg(reg_a0, REG_LR); \
1838 generate_branch(arm) \
1839
1840#define arm_bx() \
1841 arm_decode_branchx(); \
1842 generate_load_reg(reg_a0, rn); \
1843 generate_indirect_branch_dual(); \
1844
1845#define arm_swi() \
1846 generate_swi_hle_handler((opcode >> 16) & 0xFF, arm); \
1847 generate_function_call(execute_swi_arm); \
1848 write32((pc + 4)); \
1849 generate_branch(arm) \
1850
1851#define thumb_b() \
1852 generate_branch(thumb) \
1853
1854#define thumb_bl() \
1855 generate_update_pc(((pc + 2) | 0x01)); \
1856 generate_store_reg(reg_a0, REG_LR); \
1857 generate_branch(thumb) \
1858
1859#define thumb_blh() \
1860{ \
1861 thumb_decode_branch(); \
1862 generate_update_pc(((pc + 2) | 0x01)); \
1863 generate_load_reg(reg_a1, REG_LR); \
1864 generate_store_reg(reg_a0, REG_LR); \
1865 generate_mov(reg_a0, reg_a1); \
1866 generate_add_imm(reg_a0, (offset * 2), 0); \
1867 generate_indirect_branch_cycle_update(thumb); \
1868} \
1869
1870#define thumb_bx() \
1871{ \
1872 thumb_decode_hireg_op(); \
1873 generate_load_reg_pc(reg_a0, rs, 4); \
1874 generate_indirect_branch_cycle_update(dual_thumb); \
1875} \
1876
1877#define thumb_swi() \
1878 generate_swi_hle_handler(opcode & 0xFF, thumb); \
1879 generate_function_call(execute_swi_thumb); \
1880 write32((pc + 2)); \
1881 /* We're in ARM mode now */ \
1882 generate_branch(arm) \
1883
1884u8 swi_hle_handle[256] =
1885{
1886 0x0, // SWI 0: SoftReset
1887 0x0, // SWI 1: RegisterRAMReset
1888 0x0, // SWI 2: Halt
1889 0x0, // SWI 3: Stop/Sleep
1890 0x0, // SWI 4: IntrWait
1891 0x0, // SWI 5: VBlankIntrWait
1892 0x1, // SWI 6: Div
1893 0x0, // SWI 7: DivArm
1894 0x0, // SWI 8: Sqrt
1895 0x0, // SWI 9: ArcTan
1896 0x0, // SWI A: ArcTan2
1897 0x0, // SWI B: CpuSet
1898 0x0, // SWI C: CpuFastSet
1899 0x0, // SWI D: GetBIOSCheckSum
1900 0x0, // SWI E: BgAffineSet
1901 0x0, // SWI F: ObjAffineSet
1902 0x0, // SWI 10: BitUnpack
1903 0x0, // SWI 11: LZ77UnCompWram
1904 0x0, // SWI 12: LZ77UnCompVram
1905 0x0, // SWI 13: HuffUnComp
1906 0x0, // SWI 14: RLUnCompWram
1907 0x0, // SWI 15: RLUnCompVram
1908 0x0, // SWI 16: Diff8bitUnFilterWram
1909 0x0, // SWI 17: Diff8bitUnFilterVram
1910 0x0, // SWI 18: Diff16bitUnFilter
1911 0x0, // SWI 19: SoundBias
1912 0x0, // SWI 1A: SoundDriverInit
1913 0x0, // SWI 1B: SoundDriverMode
1914 0x0, // SWI 1C: SoundDriverMain
1915 0x0, // SWI 1D: SoundDriverVSync
1916 0x0, // SWI 1E: SoundChannelClear
1917 0x0, // SWI 1F: MidiKey2Freq
1918 0x0, // SWI 20: SoundWhatever0
1919 0x0, // SWI 21: SoundWhatever1
1920 0x0, // SWI 22: SoundWhatever2
1921 0x0, // SWI 23: SoundWhatever3
1922 0x0, // SWI 24: SoundWhatever4
1923 0x0, // SWI 25: MultiBoot
1924 0x0, // SWI 26: HardReset
1925 0x0, // SWI 27: CustomHalt
1926 0x0, // SWI 28: SoundDriverVSyncOff
1927 0x0, // SWI 29: SoundDriverVSyncOn
1928 0x0 // SWI 2A: SoundGetJumpList
1929};
1930
1931void execute_swi_hle_div_arm();
1932void execute_swi_hle_div_thumb();
1933
1934void execute_swi_hle_div_c()
1935{
1936 s32 result = (s32)reg[0] / (s32)reg[1];
1937 reg[1] = (s32)reg[0] % (s32)reg[1];
1938 reg[0] = result;
1939
1940 reg[3] = (result ^ (result >> 31)) - (result >> 31);
1941}
1942
1943#define generate_swi_hle_handler(_swi_number, mode) \
1944{ \
1945 u32 swi_number = _swi_number; \
1946 if(swi_hle_handle[swi_number]) \
1947 { \
1948 /* Div */ \
1949 if(swi_number == 0x06) \
1950 { \
1951 generate_function_call(execute_swi_hle_div_##mode); \
1952 } \
1953 break; \
1954 } \
1955} \
1956
1957#define generate_translation_gate(type) \
1958 generate_update_pc(pc); \
1959 generate_indirect_branch_no_cycle_update(type) \
1960
1961#define generate_step_debug() \
1962 generate_function_call(step_debug_arm); \
1963 write32(pc) \
1964
1965#endif
1966
gpSP fork tuned for ARM Linux