initial pandora port, with hardware scaling and stuff

[gpsp.git] / cpu_threaded.c

diff --git a/cpu_threaded.c b/cpu_threaded.c
index a753c17..547b3c0 100644 (file)
--- a/cpu_threaded.c
+++ b/cpu_threaded.c
@@ -21,7 +21,6 @@
 // - stm reglist writeback when base is in the list needs adjustment
 // - block memory needs psr swapping and user mode reg swapping
 
-#include <stdio.h>
 #include "common.h"
 
 u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
@@ -190,13 +189,9 @@ extern u8 bit_count[256];
 
 #include "psp/mips_emit.h"
 
-#elif defined(GP2X_BUILD)
+#elif defined(ARM_ARCH)
 
-#include "gp2x/arm_emit.h"
-
-#elif defined(GIZ_BUILD)
-
-#include "giz/arm_emit.h"
+#include "arm/arm_emit.h"
 
 #else
 
@@ -2841,7 +2836,7 @@ u8 function_cc *block_lookup_address_##type(u32 pc)                           \
         char buffer[256];                                                     \
         sprintf(buffer, "bad jump %x (%x) (%x)\n", pc, reg[REG_PC],           \
          last_instruction);                                                   \
-        printf(buffer);                                                       \
+        printf("%s", buffer);                                                 \
         quit();                                                               \
       }                                                                       \
       block_address = (u8 *)(-1);                                             \
@@ -3410,6 +3405,9 @@ void flush_translation_cache_ram()
 #ifndef PC_BUILD
   invalidate_icache_region(ram_translation_cache,
    (ram_translation_ptr - ram_translation_cache) + 0x100);
+#endif
+#ifdef ARM_ARCH
+  last_ram_translation_ptr = ram_translation_cache;
 #endif
   ram_translation_ptr = ram_translation_cache;
   ram_block_tag_top = 0x0101;
@@ -3465,6 +3463,9 @@ void flush_translation_cache_rom()
   invalidate_icache_region(rom_translation_cache,
    rom_translation_ptr - rom_translation_cache + 0x100);
 #endif
+#ifdef ARM_ARCH
+  last_rom_translation_ptr = rom_translation_cache;
+#endif
 
   rom_translation_ptr = rom_translation_cache;
   memset(rom_branch_hash, 0, sizeof(rom_branch_hash));
@@ -3476,17 +3477,16 @@ void flush_translation_cache_bios()
   invalidate_icache_region(bios_translation_cache,
    bios_translation_ptr - bios_translation_cache + 0x100);
 #endif
+#ifdef ARM_ARCH
+  last_bios_translation_ptr = bios_translation_cache;
+#endif
 
   bios_block_tag_top = 0x0101;
   bios_translation_ptr = bios_translation_cache;
   memset(bios_rom + 0x4000, 0, 0x4000);
 }
 
-#ifdef GP2X_BUILD
-  #define cache_dump_prefix "/mnt/nand/"
-#else
-  #define cache_dump_prefix ""
-#endif
+#define cache_dump_prefix ""
 
 void dump_translation_cache()
 {