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testpico: adjust for irixxxx's PD, 32x disable
[megadrive.git] / testpico / main.c
CommitLineData
ffd4b35c 1/*
2 * This software is released into the public domain.
3 * See UNLICENSE file in top level directory.
4 */
5#include <stdlib.h>
6#include <stdarg.h>
9d39a80e 7#include "common.h"
ffd4b35c 8#include "asmtools.h"
9
10#define VDP_DATA_PORT 0xC00000
11#define VDP_CTRL_PORT 0xC00004
a385208c 12#define VDP_HV_COUNTER 0xC00008
ffd4b35c 13
14#define TILE_MEM_END 0xB000
15
16#define FONT_LEN 128
a385208c 17#define TILE_FONT_BASE (TILE_MEM_END - FONT_LEN * 32)
ffd4b35c 18
19/* note: using ED menu's layout here.. */
20#define WPLANE (TILE_MEM_END + 0x0000)
21#define HSCRL (TILE_MEM_END + 0x0800)
22#define SLIST (TILE_MEM_END + 0x0C00)
23#define APLANE (TILE_MEM_END + 0x1000)
24#define BPLANE (TILE_MEM_END + 0x3000)
25
ffd4b35c 26#define write16_z80le(a, d) \
27 ((volatile u8 *)(a))[0] = (u8)(d), \
28 ((volatile u8 *)(a))[1] = ((d) >> 8)
29
30static inline u16 read16_z80le(const void *a_)
31{
32 volatile const u8 *a = (volatile const u8 *)a_;
33 return a[0] | ((u16)a[1] << 8);
34}
35
36#define CTL_WRITE_VRAM(adr) \
37 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
38#define CTL_WRITE_VSRAM(adr) \
39 (((0x4000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
40#define CTL_WRITE_CRAM(adr) \
41 (((0xC000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
42#define CTL_READ_VRAM(adr) \
43 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x00)
44#define CTL_READ_VSRAM(adr) \
45 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x10)
46#define CTL_READ_CRAM(adr) \
47 (((0x0000 | ((adr) & 0x3FFF)) << 16) | ((adr) >> 14) | 0x20)
48
49#define CTL_WRITE_DMA 0x80
50
51#define VDP_setReg(r, v) \
52 write16(VDP_CTRL_PORT, 0x8000 | ((r) << 8) | ((v) & 0xff))
53
54enum {
55 VDP_MODE1 = 0x00,
56 VDP_MODE2 = 0x01,
57 VDP_NT_SCROLLA = 0x02,
58 VDP_NT_WIN = 0x03,
59 VDP_NT_SCROLLB = 0x04,
60 VDP_SAT_BASE = 0x05,
61 VDP_BACKDROP = 0x07,
62 VDP_MODE3 = 0x0b,
63 VDP_MODE4 = 0x0c,
64 VDP_HSCROLL = 0x0d,
65 VDP_AUTOINC = 0x0f,
66 VDP_SCROLLSZ = 0x10,
67 VDP_DMA_LEN0 = 0x13,
68 VDP_DMA_LEN1 = 0x14,
69 VDP_DMA_SRC0 = 0x15,
70 VDP_DMA_SRC1 = 0x16,
71 VDP_DMA_SRC2 = 0x17,
72};
73
74#define VDP_MODE1_PS 0x04
75#define VDP_MODE1_IE1 0x10 // h int
76#define VDP_MODE2_MD 0x04
77#define VDP_MODE2_PAL 0x08 // 30 col
78#define VDP_MODE2_DMA 0x10
79#define VDP_MODE2_IE0 0x20 // v int
80#define VDP_MODE2_DISP 0x40
a385208c 81#define VDP_MODE2_128K 0x80
82
83#define SR_PAL (1 << 0)
84#define SR_DMA (1 << 1)
85#define SR_HB (1 << 2)
86#define SR_VB (1 << 3)
87#define SR_ODD (1 << 4)
88#define SR_C (1 << 5)
89#define SR_SOVR (1 << 6)
90#define SR_F (1 << 7)
91#define SR_FULL (1 << 8)
92#define SR_EMPT (1 << 9)
ffd4b35c 93
94/* cell counts */
95#define LEFT_BORDER 1 /* lame TV */
96#define PLANE_W 64
97#define PLANE_H 32
98#define CSCREEN_H 28
99
100/* data.s */
101extern const u32 font_base[];
102extern const u8 z80_test[];
103extern const u8 z80_test_end[];
104
105static int text_pal;
106
107static noinline void VDP_drawTextML(const char *str, u16 plane_base,
108 u16 x, u16 y)
109{
110 const u8 *src = (const u8 *)str;
111 u16 basetile = text_pal << 13;
112 int max_len = 40 - LEFT_BORDER;
113 int len;
114 u32 addr;
115
116 x += LEFT_BORDER;
117
118 for (len = 0; str[len] && len < max_len; len++)
119 ;
120 if (len > (PLANE_W - x))
121 len = PLANE_W - x;
122
123 addr = plane_base + ((x + (PLANE_W * y)) << 1);
124 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
125
126 while (len-- > 0) {
127 write16(VDP_DATA_PORT,
128 basetile | ((*src++) - 32 + TILE_FONT_BASE / 32));
129 }
130}
131
132static int printf_ypos;
133
134static void printf_line(int x, const char *buf)
135{
136 u32 addr;
137 int i;
138
139 VDP_drawTextML(buf, APLANE, x, printf_ypos++ & (PLANE_H - 1));
140
141 if (printf_ypos >= CSCREEN_H) {
142 /* clear next line */
143 addr = APLANE;
144 addr += (PLANE_W * (printf_ypos & (PLANE_H - 1))) << 1;
145 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr));
146 for (i = 0; i < 40 / 2; i++)
147 write32(VDP_DATA_PORT, 0);
148
149 /* scroll plane */
150 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
151 write16(VDP_DATA_PORT, (printf_ypos - CSCREEN_H + 1) * 8);
152 }
153}
154
155#define PRINTF_LEN 40
156
157static int printf_xpos;
158
159static noinline int printf(const char *fmt, ...)
160{
161 static const char hexchars[] = "0123456789abcdef";
162 char c, buf[PRINTF_LEN + 11 + 1];
163 const char *s;
164 va_list ap;
165 int ival;
166 u32 uval;
167 int d = 0;
168 int i, j;
169
170 va_start(ap, fmt);
171 for (d = 0; *fmt; ) {
172 int prefix0 = 0;
173 int fwidth = 0;
174
175 c = *fmt++;
176 if (d < PRINTF_LEN)
177 buf[d] = c;
178
179 if (c != '%') {
180 if (c == '\n') {
181 buf[d] = 0;
182 printf_line(printf_xpos, buf);
183 d = 0;
184 printf_xpos = 0;
185 continue;
186 }
187 d++;
188 continue;
189 }
190 if (d >= PRINTF_LEN)
191 continue;
192
193 if (*fmt == '0') {
194 prefix0 = 1;
195 fmt++;
196 }
197
198 while ('1' <= *fmt && *fmt <= '9') {
199 fwidth = fwidth * 10 + *fmt - '0';
200 fmt++;
201 }
202
203 switch (*fmt++) {
204 case '%':
205 d++;
206 break;
207 case 'd':
208 case 'i':
209 ival = va_arg(ap, int);
210 if (ival < 0) {
211 buf[d++] = '-';
212 ival = -ival;
213 }
214 for (i = 1000000000; i >= 10; i /= 10)
215 if (ival >= i)
216 break;
217 for (; i >= 10; i /= 10) {
218 buf[d++] = '0' + ival / i;
219 ival %= i;
220 }
221 buf[d++] = '0' + ival;
222 break;
223 case 'x':
224 uval = va_arg(ap, int);
225 while (fwidth > 1 && uval < (1 << (fwidth - 1) * 4)) {
226 buf[d++] = prefix0 ? '0' : ' ';
227 fwidth--;
228 }
229 for (j = 1; j < 8 && uval >= (1 << j * 4); j++)
230 ;
231 for (j--; j >= 0; j--)
232 buf[d++] = hexchars[(uval >> j * 4) & 0x0f];
233 break;
234 case 's':
235 s = va_arg(ap, char *);
236 while (*s && d < PRINTF_LEN)
237 buf[d++] = *s++;
238 break;
239 default:
240 // don't handle, for now
241 d++;
242 va_arg(ap, void *);
243 break;
244 }
245 }
246 buf[d] = 0;
247 va_end(ap);
248
249 if (d != 0) {
250 // line without \n
251 VDP_drawTextML(buf, APLANE, printf_xpos,
252 printf_ypos & (PLANE_H - 1));
253 printf_xpos += d;
254 }
255
256 return d; // wrong..
257}
258
259static const char *exc_names[] = {
260 NULL,
261 NULL,
262 "Bus Error",
263 "Address Error",
264 "Illegal Instruction",
265 "Zero Divide",
266 "CHK Instruction",
267 "TRAPV Instruction",
268 "Privilege Violation", /* 8 8 */
269 "Trace",
270 "Line 1010 Emulator",
271 "Line 1111 Emulator",
272 NULL,
273 NULL,
274 NULL,
275 "Uninitialized Interrupt",
276 NULL, /* 10 16 */
277 NULL,
278 NULL,
279 NULL,
280 NULL,
281 NULL,
282 NULL,
283 NULL,
284 "Spurious Interrupt", /* 18 24 */
285 "l1 irq",
286 "l2 irq",
287 "l3 irq",
288 "l4 irq",
289 "l5 irq",
290 "l6 irq",
291 "l7 irq",
292};
293
294struct exc_frame {
295 u32 dr[8];
296 u32 ar[8];
297 u16 ecxnum; // from handler
298 union {
299 struct {
300 u16 sr;
301 u32 pc;
302 } g _packed;
303 struct {
304 u16 fc;
305 u32 addr;
306 u16 ir;
307 u16 sr;
308 u32 pc;
309 } bae _packed; // bus/address error frame
310 };
311} _packed;
312
ffd4b35c 313void exception(const struct exc_frame *f)
314{
234c4556 315 u32 *sp, sp_add;
ffd4b35c 316 int i;
317
318 while (read16(VDP_CTRL_PORT) & 2)
319 ;
320 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
321 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DISP);
322 /* adjust scroll */
323 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
324 write16(VDP_DATA_PORT,
325 printf_ypos >= CSCREEN_H ?
326 (printf_ypos - CSCREEN_H + 1) * 8 : 0);
327
328 printf("exception %i ", f->ecxnum);
329 if (f->ecxnum < ARRAY_SIZE(exc_names) && exc_names[f->ecxnum] != NULL)
330 printf("(%s)", exc_names[f->ecxnum]);
331 if (f->ecxnum < 4)
332 printf(" (%s)", (f->bae.fc & 0x10) ? "r" : "w");
333 printf(" \n");
334
335 if (f->ecxnum < 4) {
234c4556 336 printf(" PC: %08x SR: %04x \n", f->bae.pc, f->bae.sr);
ffd4b35c 337 printf("addr: %08x IR: %04x FC: %02x \n",
338 f->bae.addr, f->bae.ir, f->bae.fc);
234c4556 339 sp_add = 14;
ffd4b35c 340 }
341 else {
234c4556 342 printf(" PC: %08x SR: %04x \n", f->g.pc, f->g.sr);
343 sp_add = 6;
ffd4b35c 344 }
345 for (i = 0; i < 8; i++)
346 printf(" D%d: %08x A%d: %08x \n", i, f->dr[i], i, f->ar[i]);
234c4556 347 printf(" \n");
348 sp = (u32 *)(f->ar[7] + sp_add);
349 printf(" %08x %08x %08x %08x\n", sp[0], sp[1], sp[2], sp[3]);
350 printf(" %08x %08x %08x %08x\n", sp[4], sp[5], sp[6], sp[7]);
ffd4b35c 351}
352
353// ---
354
355static void setup_default_palette(void)
356{
357 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
358 write32(VDP_DATA_PORT, 0);
359 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(15 * 2)); // font normal
360 write16(VDP_DATA_PORT, 0xeee);
361 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(31 * 2)); // green
362 write16(VDP_DATA_PORT, 0x0e0);
363 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(47 * 2)); // red
364 write16(VDP_DATA_PORT, 0x00e);
365}
366
367static void do_setup_dma(const void *src_, u16 words)
368{
369 u32 src = (u32)src_;
370 // VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
371 VDP_setReg(VDP_DMA_LEN0, words);
372 VDP_setReg(VDP_DMA_LEN1, words >> 8);
373 VDP_setReg(VDP_DMA_SRC0, src >> 1);
374 VDP_setReg(VDP_DMA_SRC1, src >> 9);
375 VDP_setReg(VDP_DMA_SRC2, src >> 17);
376 // write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(addr) | CTL_WRITE_DMA);
377}
378
a385208c 379static void vdp_wait_for_fifo_empty(void)
380{
381 while (!(read16(VDP_CTRL_PORT) & 0x200))
382 /* fifo not empty */;
383}
384
385static void vdp_wait_for_dma_idle(void)
386{
387 while (read16(VDP_CTRL_PORT) & 2)
388 /* dma busy */;
389}
390
391static void vdp_wait_for_line_0(void)
392{
393 // in PAL vcounter reports 0 twice in a frame,
394 // so wait for vblank to clear first
395 while (!(read16(VDP_CTRL_PORT) & 8))
396 /* not blanking */;
397 while (read16(VDP_CTRL_PORT) & 8)
398 /* blanking */;
399 while (read8(VDP_HV_COUNTER) != 0)
400 ;
401}
402
ffd4b35c 403static void t_dma_zero_wrap_early(void)
404{
405 const u32 *src = (const u32 *)0x3c0000;
406 u32 *ram = (u32 *)0xff0000;
407
408 do_setup_dma(src + 4, 2);
409 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
410 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) | CTL_WRITE_DMA);
411
412 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
413 ram[0] = read32(VDP_DATA_PORT);
414 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfffc));
415 ram[1] = read32(VDP_DATA_PORT);
416}
417
418static void t_dma_zero_fill_early(void)
419{
420 u32 *ram = (u32 *)0xff0000;
421
422 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
423 write32(VDP_DATA_PORT, 0);
424 write32(VDP_DATA_PORT, 0);
425 write32(VDP_DATA_PORT, 0);
426 write32(VDP_DATA_PORT, 0);
427
428 VDP_setReg(VDP_AUTOINC, 1);
429 VDP_setReg(VDP_DMA_SRC2, 0x80);
430 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(1) | CTL_WRITE_DMA);
431 write16(VDP_DATA_PORT, 0x1122);
432 ram[2] = read16(VDP_CTRL_PORT);
a385208c 433 vdp_wait_for_dma_idle();
ffd4b35c 434
435 VDP_setReg(VDP_AUTOINC, 2);
436 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
437 ram[3] = read32(VDP_DATA_PORT);
438}
439
440#define expect(ok_, v0_, v1_) \
441if ((v0_) != (v1_)) { \
442 printf("%s: %08x %08x\n", #v0_, v0_, v1_); \
443 ok_ = 0; \
444}
445
a385208c 446#define expect_range(ok_, v0_, vmin_, vmax_) \
447if ((v0_) < (vmin_) || (v0_) > (vmax_)) { \
448 printf("%s: %02x /%02x-%02x\n", #v0_, v0_, vmin_, vmax_); \
449 ok_ = 0; \
450}
451
452#define expect_bits(ok_, v0_, val_, mask_) \
453if (((v0_) & (mask_)) != (val_)) { \
454 printf("%s: %04x & %04x != %04x\n", #v0_, v0_, mask_, val_); \
455 ok_ = 0; \
456}
457
ffd4b35c 458static int t_dma_zero_wrap(void)
459{
460 const u32 *src = (const u32 *)0x3c0000;
461 const u32 *ram = (const u32 *)0xff0000;
462 int ok = 1;
463
464 expect(ok, ram[0], src[5 + 0x10000/4]);
465 expect(ok, ram[1], src[4]);
466 return ok;
467}
468
469static int t_dma_zero_fill(void)
470{
471 const u32 *ram = (const u32 *)0xff0000;
472 u32 v0 = ram[2] & 2;
473 int ok = 1;
474
475 expect(ok, v0, 2);
476 expect(ok, ram[3], 0x11111111);
477 return ok;
478}
479
480static int t_dma_ram_wrap(void)
481{
482 u32 *ram = (u32 *)0xff0000;
483 u32 saved, v0, v1;
484 int ok = 1;
485
486 saved = read32(&ram[0x10000/4 - 1]);
487 ram[0x10000/4 - 1] = 0x01020304;
488 ram[0] = 0x05060708;
489 do_setup_dma(&ram[0x10000/4 - 1], 4);
490 mem_barrier();
491 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
492
493 mem_barrier();
494 write32(&ram[0x10000/4 - 1], saved);
495
496 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
497 v0 = read32(VDP_DATA_PORT);
498 v1 = read32(VDP_DATA_PORT);
499
500 expect(ok, v0, 0x01020304);
501 expect(ok, v1, 0x05060708);
502 return ok;
503}
504
505// test no src reprogram, only len0
506static int t_dma_multi(void)
507{
508 const u32 *src = (const u32 *)0x3c0000;
509 u32 v0, v1;
510 int ok = 1;
511
512 do_setup_dma(src, 2);
513 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
514 VDP_setReg(VDP_DMA_LEN0, 2);
515 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
516
517 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
518 v0 = read32(VDP_DATA_PORT);
519 v1 = read32(VDP_DATA_PORT);
520
521 expect(ok, v0, src[0]);
522 expect(ok, v1, src[1]);
523 return ok;
524}
525
526static int t_dma_cram_wrap(void)
527{
528 u32 *ram = (u32 *)0xff0000;
529 u32 v0, v1;
530 int ok = 1;
531
532 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
533 write32(VDP_DATA_PORT, 0);
534
535 ram[0] = 0x0ec20ec4;
536 ram[1] = 0x0ec60ec8;
537 mem_barrier();
538 do_setup_dma(ram, 4);
539 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0x7c | 0xff81) | CTL_WRITE_DMA);
540
541 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0x7c));
542 v0 = read32(VDP_DATA_PORT) & 0x0eee0eee;
543 write32(VDP_CTRL_PORT, CTL_READ_CRAM(0));
544 v1 = read32(VDP_DATA_PORT) & 0x0eee0eee;
545
546 setup_default_palette();
547
548 expect(ok, v0, ram[0]);
549 expect(ok, v1, ram[1]);
550 return ok;
551}
552
553static int t_dma_vsram_wrap(void)
554{
555 u32 *ram32 = (u32 *)0xff0000;
556 u16 *ram16 = (u16 *)0xff0000;
557 u32 v0, v1;
558 int ok = 1;
559 int i;
560
561 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
562 write32(VDP_DATA_PORT, 0);
563
564 for (i = 0; i < 0x48/2; i++)
565 ram16[i] = i + 1;
566 mem_barrier();
567 do_setup_dma(ram16, 0x48/2);
568 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0x3c | 0xff81) | CTL_WRITE_DMA);
569
570 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0x3c));
571 v0 = read32(VDP_DATA_PORT) & 0x03ff03ff;
572 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
573 v1 = read32(VDP_DATA_PORT) & 0x03ff03ff;
574
575 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
576 write32(VDP_DATA_PORT, 0);
577
578 expect(ok, v0, ram32[0]);
579 expect(ok, v1, ram32[0x48/4 - 1]);
580 return ok;
581}
582
583static int t_dma_and_data(void)
584{
585 const u32 *src = (const u32 *)0x3c0000;
a385208c 586 u32 v0, v1;
ffd4b35c 587 int ok = 1;
588
589 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
590 write32(VDP_DATA_PORT, 0);
591
592 do_setup_dma(src, 2);
593 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfc) | CTL_WRITE_DMA);
594 write32(VDP_DATA_PORT, 0x5ec8a248);
595
a385208c 596 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfc));
ffd4b35c 597 v0 = read32(VDP_DATA_PORT);
a385208c 598 v1 = read32(VDP_DATA_PORT);
ffd4b35c 599
a385208c 600 expect(ok, v0, src[0]);
601 expect(ok, v1, 0x5ec8a248);
602 return ok;
603}
604
605static int t_dma_short_cmd(void)
606{
607 const u32 *src = (const u32 *)0x3c0000;
608 u32 v0, v1, v2;
609 int ok = 1;
610
611 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4));
612 write32(VDP_DATA_PORT, 0x10111213);
613 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0));
614 write32(VDP_DATA_PORT, 0x20212223);
615 write32(VDP_DATA_PORT, 0x30313233);
cc7e5122 616 vdp_wait_for_fifo_empty();
a385208c 617
618 do_setup_dma(src, 2);
619 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfff0) | CTL_WRITE_DMA);
620 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x3ff4) >> 16);
621 write32(VDP_DATA_PORT, 0x40414243);
622
623 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x3ff4));
624 v0 = read32(VDP_DATA_PORT);
625 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0xfff0));
626 v1 = read32(VDP_DATA_PORT);
627 v2 = read32(VDP_DATA_PORT);
628
629 expect(ok, v0, 0x10111213);
630 expect(ok, v1, src[0]);
631 expect(ok, v2, 0x40414243);
ffd4b35c 632 return ok;
633}
634
635static int t_dma_fill3_odd(void)
636{
637 u32 v0, v1, v2;
638 int ok = 1;
639
640 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
641 write32(VDP_DATA_PORT, 0);
642 write32(VDP_DATA_PORT, 0);
643 write32(VDP_DATA_PORT, 0);
cc7e5122 644 vdp_wait_for_fifo_empty();
ffd4b35c 645
646 VDP_setReg(VDP_AUTOINC, 3);
647 VDP_setReg(VDP_DMA_LEN0, 3);
648 VDP_setReg(VDP_DMA_SRC2, 0x80);
649 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x101) | CTL_WRITE_DMA);
650 write16(VDP_DATA_PORT, 0x1122);
a385208c 651 vdp_wait_for_dma_idle();
ffd4b35c 652
653 VDP_setReg(VDP_AUTOINC, 2);
654 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
655 v0 = read32(VDP_DATA_PORT);
656 v1 = read32(VDP_DATA_PORT);
657 v2 = read32(VDP_DATA_PORT);
658
659 expect(ok, v0, 0x22110000);
660 expect(ok, v1, 0x00111100);
661 expect(ok, v2, 0x00000011);
662 return ok;
663}
664
665static int t_dma_fill3_even(void)
666{
667 u32 v0, v1, v2;
668 int ok = 1;
669
670 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
671 write32(VDP_DATA_PORT, 0);
672 write32(VDP_DATA_PORT, 0);
673 write32(VDP_DATA_PORT, 0);
cc7e5122 674 vdp_wait_for_fifo_empty();
ffd4b35c 675
676 VDP_setReg(VDP_AUTOINC, 3);
677 VDP_setReg(VDP_DMA_LEN0, 3);
678 VDP_setReg(VDP_DMA_SRC2, 0x80);
679 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
680 write16(VDP_DATA_PORT, 0x1122);
a385208c 681 vdp_wait_for_dma_idle();
ffd4b35c 682
683 VDP_setReg(VDP_AUTOINC, 2);
684 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
685 v0 = read32(VDP_DATA_PORT);
686 v1 = read32(VDP_DATA_PORT);
687 v2 = read32(VDP_DATA_PORT);
688
689 expect(ok, v0, 0x11221100);
690 expect(ok, v1, 0x00000011);
691 expect(ok, v2, 0x11000000);
692 return ok;
693}
694
695static unused int t_dma_fill3_vsram(void)
696{
697 u32 v0, v1, v2;
698 int ok = 1;
699
700 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
701 write32(VDP_DATA_PORT, 0);
702 write32(VDP_DATA_PORT, 0);
703 write32(VDP_DATA_PORT, 0);
704
705 write16(VDP_DATA_PORT, 0x0111);
706 write16(VDP_DATA_PORT, 0x0222);
707 write16(VDP_DATA_PORT, 0x0333);
a385208c 708 vdp_wait_for_fifo_empty();
ffd4b35c 709
710 VDP_setReg(VDP_AUTOINC, 3);
711 VDP_setReg(VDP_DMA_LEN0, 3);
712 VDP_setReg(VDP_DMA_SRC2, 0x80);
713 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(1) | CTL_WRITE_DMA);
714 write16(VDP_DATA_PORT, 0x0102);
a385208c 715 vdp_wait_for_dma_idle();
ffd4b35c 716
717 VDP_setReg(VDP_AUTOINC, 2);
718 write32(VDP_CTRL_PORT, CTL_READ_VSRAM(0));
719 v0 = read32(VDP_DATA_PORT);
720 v1 = read32(VDP_DATA_PORT);
721 v2 = read32(VDP_DATA_PORT);
722
723 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
724 write32(VDP_DATA_PORT, 0);
725
726 expect(ok, v0, 0x01020000);
727 expect(ok, v1, 0x01110111);
728 expect(ok, v2, 0x00000111);
729 return ok;
730}
731
732static int t_dma_fill_dis(void)
733{
734 u32 v0, v1;
735 int ok = 1;
736
737 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
738 write32(VDP_DATA_PORT, 0);
739 write32(VDP_DATA_PORT, 0);
740
741 VDP_setReg(VDP_DMA_LEN0, 1);
742 VDP_setReg(VDP_DMA_SRC2, 0x80);
743 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
744 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
745 write16(VDP_DATA_PORT, 0x1122);
a385208c 746 vdp_wait_for_dma_idle();
ffd4b35c 747
748 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
749 write16(VDP_DATA_PORT, 0x3344);
a385208c 750 vdp_wait_for_dma_idle();
ffd4b35c 751
752 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
753 v0 = read32(VDP_DATA_PORT);
754 v1 = read32(VDP_DATA_PORT);
755
756 expect(ok, v0, 0);
757 expect(ok, v1, 0);
758 return ok;
759}
760
761static int t_dma_fill_src(void)
762{
763 const u32 *src = (const u32 *)0x3c0000;
764 u32 v0, v1;
765 int ok = 1;
766
767 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
768 write32(VDP_DATA_PORT, 0);
769
770 // do_setup_dma(src, 2); // hang, can't write src2 twice
771 VDP_setReg(VDP_DMA_LEN0, 2);
772 VDP_setReg(VDP_DMA_SRC0, (u32)src >> 1);
773 VDP_setReg(VDP_DMA_SRC1, (u32)src >> 9);
774 VDP_setReg(VDP_DMA_SRC2, 0x80);
775 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
776 write16(VDP_DATA_PORT, 0x1122);
a385208c 777 vdp_wait_for_dma_idle();
ffd4b35c 778
779 VDP_setReg(VDP_DMA_LEN0, 2);
780 VDP_setReg(VDP_DMA_SRC2, (u32)src >> 17);
781 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x104) | CTL_WRITE_DMA);
782
783 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
784 v0 = read32(VDP_DATA_PORT);
785 v1 = read32(VDP_DATA_PORT);
786
787 expect(ok, v0, 0x11220011);
788 expect(ok, v1, src[1]);
789 return ok;
790}
791
a385208c 792// (((a & 2) >> 1) ^ 1) | ((a & $400) >> 9) | (a & $3FC) | ((a & $1F800) >> 1)
793static int t_dma_128k(void)
794{
795 u16 *ram = (u16 *)0xff0000;
796 u32 v0, v1;
797 int ok = 1;
798
799 ram[0] = 0x5a11;
800 ram[1] = 0x5a22;
801 ram[2] = 0x5a33;
802
803 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
804 write32(VDP_DATA_PORT, 0x01020304);
805 write32(VDP_DATA_PORT, 0x05060708);
806 vdp_wait_for_fifo_empty();
807
808 mem_barrier();
809 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
810 do_setup_dma(ram, 3);
811 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) | CTL_WRITE_DMA);
812 vdp_wait_for_fifo_empty();
813
814 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
815 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
816 v0 = read32(VDP_DATA_PORT);
817 v1 = read32(VDP_DATA_PORT);
818
819 expect(ok, v0, 0x22110304);
820 expect(ok, v1, 0x05330708);
821 return ok;
822}
823
824static int t_vdp_128k_b16(void)
825{
826 u32 v0, v1;
827 int ok = 1;
828
829 VDP_setReg(VDP_AUTOINC, 0);
830 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8100));
831 write32(VDP_DATA_PORT, 0x01020304);
832 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10100));
833 write32(VDP_DATA_PORT, 0x05060708);
834 vdp_wait_for_fifo_empty();
835
836 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
837 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100) >> 16); // note: upper cmd
838 write32(VDP_DATA_PORT, 0x11223344);
839 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x10102));
840 write32(VDP_DATA_PORT, 0x55667788);
841 vdp_wait_for_fifo_empty();
842
843 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
844 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8100));
845 v0 = read16(VDP_DATA_PORT);
846 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
847 v1 = read16(VDP_DATA_PORT);
848
849 VDP_setReg(VDP_AUTOINC, 2);
850
851 expect(ok, v0, 0x8844);
852 expect(ok, v1, 0x0708);
853 return ok;
854}
855
856static unused int t_vdp_128k_b16_inc(void)
857{
858 u32 v0, v1;
859 int ok = 1;
860
861 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
862 write32(VDP_DATA_PORT, 0x01020304);
863 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
864 write32(VDP_DATA_PORT, 0x05060708);
865 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0xfffe));
866 write32(VDP_DATA_PORT, 0x090a0b0c);
867 vdp_wait_for_fifo_empty();
868
869 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_128K);
870 write16(VDP_CTRL_PORT, CTL_WRITE_VRAM(0) >> 16); // note: upper cmd
871 write16(VDP_DATA_PORT, 0x1122);
872 vdp_wait_for_fifo_empty();
873
874 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
875 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0));
876 v0 = read32(VDP_DATA_PORT);
877 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x8000));
878 v1 = read32(VDP_DATA_PORT);
879 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
880 write32(VDP_DATA_PORT, 0);
881 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x8000));
882 write32(VDP_DATA_PORT, 0);
883
884 expect(ok, v0, 0x0b0c0304); // XXX: no 22 anywhere?
885 expect(ok, v1, 0x05060708);
886 return ok;
887}
888
889static int t_vdp_reg_cmd(void)
890{
891 u32 v0;
892 int ok = 1;
893
894 VDP_setReg(VDP_AUTOINC, 0);
895 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
896 write32(VDP_DATA_PORT, 0x01020304);
897 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
898 write32(VDP_DATA_PORT, 0x05060708);
899
900 VDP_setReg(VDP_AUTOINC, 2);
901 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x0100));
902 v0 = read16(VDP_DATA_PORT);
903
904 expect(ok, v0, 0x0304);
905 return ok;
906}
907
cc7e5122 908static int t_vdp_sr_vb(void)
909{
910 u16 sr[4];
911 int ok = 1;
912
913 while (read8(VDP_HV_COUNTER) != 242)
914 ;
915 sr[0] = read16(VDP_CTRL_PORT);
916 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
917 sr[1] = read16(VDP_CTRL_PORT);
918 while (read8(VDP_HV_COUNTER) != 4)
919 ;
920 sr[2] = read16(VDP_CTRL_PORT);
921 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
922 sr[3] = read16(VDP_CTRL_PORT);
923
924 expect_bits(ok, sr[0], SR_VB, SR_VB);
925 expect_bits(ok, sr[1], SR_VB, SR_VB);
926 expect_bits(ok, sr[2], SR_VB, SR_VB);
927 expect_bits(ok, sr[3], 0, SR_VB);
928 return ok;
929}
930
ffd4b35c 931/* z80 tests assume busreq state */
932static int t_z80mem_long_mirror(void)
933{
934 u8 *zram = (u8 *)0xa00000;
935 int ok = 1;
936
937 write8(&zram[0x1100], 0x11);
938 write8(&zram[0x1101], 0x22);
939 write8(&zram[0x1102], 0x33);
940 write8(&zram[0x1103], 0x44);
941 mem_barrier();
942 write32(&zram[0x3100], 0x55667788);
943 mem_barrier();
944
945 expect(ok, zram[0x1100], 0x55);
946 expect(ok, zram[0x1101], 0x22);
947 expect(ok, zram[0x1102], 0x77);
948 expect(ok, zram[0x1103], 0x44);
949 return ok;
950}
951
a385208c 952static int t_z80mem_noreq_w(void)
953{
954 u8 *zram = (u8 *)0xa00000;
955 int ok = 1;
956
957 write8(&zram[0x1100], 0x11);
958 mem_barrier();
959 write16(0xa11100, 0x000);
960 write8(&zram[0x1100], 0x22);
961 mem_barrier();
962
963 write16(0xa11100, 0x100);
964 while (read16(0xa11100) & 0x100)
965 ;
966
967 expect(ok, zram[0x1100], 0x11);
968 return ok;
969}
970
971#define Z80_CP_CYCLES(b) (118 + ((b) - 1) * 21 + 26 + 17)
972
ffd4b35c 973static int t_z80mem_vdp_r(void)
974{
975 u8 *zram = (u8 *)0xa00000;
976 int ok = 1;
977
978 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
979 write32(VDP_DATA_PORT, 0x11223344);
980 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
981
982 zram[0x1000] = 1; // cp
ffd4b35c 983 write16_z80le(&zram[0x1002], 0x7f00); // src
a385208c 984 write16_z80le(&zram[0x1004], 0x1100); // dst
985 write16_z80le(&zram[0x1006], 2); // len
986 zram[0x1100] = zram[0x1101] = zram[0x1102] = 0x5a;
ffd4b35c 987 mem_barrier();
988 write16(0xa11100, 0x000);
a385208c 989 burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10);
ffd4b35c 990
991 write16(0xa11100, 0x100);
992 while (read16(0xa11100) & 0x100)
993 ;
994
995 expect(ok, zram[0x1000], 0);
a385208c 996 expect(ok, zram[0x1100], 0x11);
997 expect(ok, zram[0x1101], 0x44);
998 expect(ok, zram[0x1102], 0x5a);
ffd4b35c 999 return ok;
1000}
1001
1002static unused int t_z80mem_vdp_w(void)
1003{
1004 u8 *zram = (u8 *)0xa00000;
1005 u32 v0;
1006 int ok = 1;
1007
1008 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1009 write32(VDP_DATA_PORT, 0x11223344);
1010 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
a385208c 1011 vdp_wait_for_fifo_empty();
ffd4b35c 1012
1013 zram[0x1000] = 1; // cp
a385208c 1014 write16_z80le(&zram[0x1002], 0x1100); // src
ffd4b35c 1015 write16_z80le(&zram[0x1004], 0x7f00); // dst
a385208c 1016 write16_z80le(&zram[0x1006], 2); // len
1017 zram[0x1100] = 0x55;
1018 zram[0x1101] = 0x66;
ffd4b35c 1019 mem_barrier();
1020 write16(0xa11100, 0x000);
a385208c 1021 burn10(Z80_CP_CYCLES(2) * 15 / 7 * 2 / 10);
ffd4b35c 1022
1023 write16(0xa11100, 0x100);
1024 while (read16(0xa11100) & 0x100)
1025 ;
1026
1027 write32(VDP_CTRL_PORT, CTL_READ_VRAM(0x100));
1028 v0 = read32(VDP_DATA_PORT);
1029
1030 expect(ok, zram[0x1000], 0);
1031 expect(ok, v0, 0x55556666);
1032 return ok;
1033}
1034
a385208c 1035static int t_tim_loop(void)
1036{
1037 u8 vcnt;
1038 int ok = 1;
1039
1040 vdp_wait_for_line_0();
1041 burn10(488*220/10);
1042 vcnt = read8(VDP_HV_COUNTER);
1043 mem_barrier();
1044
1045 //expect_range(ok, vcnt, 0x80, 0x80);
1046 expect(ok, vcnt, 223);
1047 return ok;
1048}
1049
1050#define Z80_RD_V_CYCLES(b) (132 + (b) * 38 + 50 + 17)
1051
1052// 80 80 91 95-96
1053static void z80_read_loop(u8 *zram, u16 src)
1054{
1055 const int pairs = 512 + 256;
1056
1057 zram[0x1000] = 2; // read loop, save vcnt
1058 write16_z80le(&zram[0x1002], src); // src
1059 write16_z80le(&zram[0x1004], 0x1100); // vcnt dst
1060 write16_z80le(&zram[0x1006], pairs); // reads/2
1061 zram[0x1100] = 0;
1062 mem_barrier();
1063
1064 vdp_wait_for_line_0();
1065 write16(0xa11100, 0x000);
1066 burn10(Z80_RD_V_CYCLES(pairs) * 15 / 7 * 4 / 10);
1067
1068 write16(0xa11100, 0x100);
1069 while (read16(0xa11100) & 0x100)
1070 ;
1071}
1072
1073static int t_tim_z80_ram(void)
1074{
1075 u8 *zram = (u8 *)0xa00000;
1076 int ok = 1;
1077
1078 z80_read_loop(zram, 0);
1079
1080 expect(ok, zram[0x1000], 0);
1081 expect_range(ok, zram[0x1100], 0x80, 0x80);
1082 return ok;
1083}
1084
1085static int t_tim_z80_ym(void)
1086{
1087 u8 *zram = (u8 *)0xa00000;
1088 int ok = 1;
1089
1090 z80_read_loop(zram, 0x4000);
1091
1092 expect(ok, zram[0x1000], 0);
1093 expect_range(ok, zram[0x1100], 0x80, 0x80);
1094 return ok;
1095}
1096
1097static int t_tim_z80_vdp(void)
1098{
1099 u8 *zram = (u8 *)0xa00000;
1100 int ok = 1;
1101
1102 z80_read_loop(zram, 0x7f08);
1103
1104 expect(ok, zram[0x1000], 0);
a385208c 1105 expect_range(ok, zram[0x1100], 0x91, 0x91);
a385208c 1106 return ok;
1107}
1108
1109static int t_tim_z80_bank_rom(void)
1110{
1111 u8 *zram = (u8 *)0xa00000;
1112 int i, ok = 1;
1113
1114 for (i = 0; i < 17; i++)
1115 write8(0xa06000, 0); // bank 0
1116
1117 z80_read_loop(zram, 0x8000);
1118
1119 expect(ok, zram[0x1000], 0);
a385208c 1120 expect_range(ok, zram[0x1100], 0x95, 0x96);
a385208c 1121 return ok;
1122}
1123
1124/* borderline too slow */
1125#if 0
cc7e5122 1126static void test_vcnt_vb(void)
a385208c 1127{
1128 const u32 *srhv = (u32 *)0xc00006; // to read SR and HV counter
1129 u32 *ram = (u32 *)0xff0000;
1130 u16 vcnt, vcnt_expect = 0;
1131 u16 sr, count = 0;
1132 u32 val, old;
1133
1134 vdp_wait_for_line_0();
1135 old = read32(srhv);
1136 *ram++ = old;
1137 for (;;) {
1138 val = read32(srhv);
1139 vcnt = val & 0xff00;
1140 if (vcnt == vcnt_expect)
1141 continue;
1142 sr = val >> 16;
1143 if (vcnt == 0 && !(sr & SR_VB)) // not VB
1144 break; // wrapped to start of frame
1145// count++;
1146 vcnt_expect += 0x100;
1147 if (vcnt == vcnt_expect && !((sr ^ (old >> 16)) & SR_VB)) {
1148 old = val;
1149 continue;
1150 }
1151 // should have a vcnt jump here
1152 *ram++ = old;
1153 *ram++ = val;
1154 vcnt_expect = vcnt;
1155 old = val;
1156 }
1157 *ram++ = val;
1158 *ram = count;
1159 mem_barrier();
1160}
1161#endif
1162
1163static int t_tim_vcnt(void)
1164{
1165 const u32 *ram32 = (u32 *)0xff0000;
1166 const u8 *ram = (u8 *)0xff0000;
1167 u8 pal = read8(0xa10001) & 0x40;
1168 u8 vc_jmp_b = pal ? 0x02 : 0xea;
1169 u8 vc_jmp_a = pal ? 0xca : 0xe5;
1170 u16 lines = pal ? 313 : 262;
1171 int ok = 1;
1172
cc7e5122 1173 test_vcnt_vb();
a385208c 1174 expect(ok, ram[0*4+2], 0); // line 0
1175 expect_bits(ok, ram[0*4+1], 0, SR_VB);
1176 expect(ok, ram[1*4+2], 223); // last no blank
1177 expect_bits(ok, ram[1*4+1], 0, SR_VB);
1178 expect(ok, ram[2*4+2], 224); // 1st blank
1179 expect_bits(ok, ram[2*4+1], SR_VB, SR_VB);
1180 expect(ok, ram[3*4+2], vc_jmp_b); // before jump
1181 expect_bits(ok, ram[3*4+1], SR_VB, SR_VB);
1182 expect(ok, ram[4*4+2], vc_jmp_a); // after jump
1183 expect_bits(ok, ram[4*4+1], SR_VB, SR_VB);
1184 expect(ok, ram[5*4+2], 0xfe); // before vb clear
1185 expect_bits(ok, ram[5*4+1], SR_VB, SR_VB);
1186 expect(ok, ram[6*4+2], 0xff); // after vb clear
1187 expect_bits(ok, ram[6*4+1], 0, SR_VB);
1188 expect(ok, ram[7*4+2], 0); // next line 0
1189 expect_bits(ok, ram[7*4+1], 0, SR_VB);
1190 expect(ok, ram32[8], lines - 1);
1191 return ok;
1192}
1193
cc7e5122 1194static int t_tim_hblank_h40(void)
1195{
1196 const u8 *r = (u8 *)0xff0000;
1197 int ok = 1;
1198
1199 test_hb();
1200
1201 // set: 0-2
1202 expect_bits(ok, r[2], SR_HB, SR_HB);
1203 expect_bits(ok, r[5], SR_HB, SR_HB);
1204 // <wait>
1205 expect_bits(ok, r[7], SR_HB, SR_HB);
1206 // clear: 8-11
1207 expect_bits(ok, r[12], 0, SR_HB);
1208 return ok;
1209}
1210
1211static int t_tim_hblank_h32(void)
1212{
1213 const u8 *r = (u8 *)0xff0000;
1214 int ok = 1;
1215
1216 VDP_setReg(VDP_MODE4, 0x00);
1217 test_hb();
1218 VDP_setReg(VDP_MODE4, 0x81);
1219
cc7e5122 1220 expect_bits(ok, r[0], 0, SR_HB);
cc7e5122 1221 // set: 1-4
1222 expect_bits(ok, r[4], SR_HB, SR_HB);
1223 expect_bits(ok, r[5], SR_HB, SR_HB);
1224 // <wait>
1225 expect_bits(ok, r[8], SR_HB, SR_HB);
1226 // clear: 9-11
1227 expect_bits(ok, r[12], 0, SR_HB);
1228 return ok;
1229}
1230
a385208c 1231static int t_tim_vdp_as_vram_w(void)
1232{
1233 int ok = 1;
1234 u8 vcnt;
1235
1236 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0x100));
1237 vdp_wait_for_line_0();
1238 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1239 vcnt = read8(VDP_HV_COUNTER);
1240 mem_barrier();
1241
1242 expect(ok, vcnt, 112*2-1);
1243 return ok;
1244}
1245
1246static int t_tim_vdp_as_cram_w(void)
1247{
1248 int ok = 1;
1249 u8 vcnt;
1250
1251 write32(VDP_CTRL_PORT, CTL_WRITE_CRAM(0));
1252 vdp_wait_for_line_0();
1253 write16_x16(VDP_DATA_PORT, 112*18 / 16, 0);
1254 vcnt = read8(VDP_HV_COUNTER);
1255 mem_barrier();
1256
1257 setup_default_palette();
1258
a385208c 1259 expect(ok, vcnt, 112);
a385208c 1260 return ok;
1261}
1262
4f936a9c 1263struct irq_test {
1264 u16 cnt;
1265 union {
1266 u16 hv;
1267 u8 v;
1268 } first, last;
8517a6df 1269 u16 pad;
4f936a9c 1270};
1271
6c839579 1272static int t_irq_hint(void)
1273{
4f936a9c 1274 struct irq_test *it = (void *)0xfff000;
6c839579 1275 int ok = 1;
1276
1277 // for more fun, disable the display
1278 VDP_setReg(VDP_MODE2, VDP_MODE2_MD);
1279
4f936a9c 1280 it->cnt = it->first.hv = it->last.hv = 0;
6c839579 1281 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1282 VDP_setReg(10, 0);
1283 while (read8(VDP_HV_COUNTER) != 100)
1284 ;
1285 while (read8(VDP_HV_COUNTER) != 229)
1286 ;
1287 // take the pending irq
1288 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1289 move_sr(0x2000);
1290 burn10(488 * 2 / 10);
1291 move_sr(0x2700);
4f936a9c 1292 expect(ok, it->first.v, 229); // pending irq trigger
1293 expect(ok, it->cnt, 1);
1294
6c839579 1295 // count irqs
4f936a9c 1296 it->cnt = it->first.hv = it->last.hv = 0;
6c839579 1297 move_sr(0x2000);
cc7e5122 1298 while (read8(VDP_HV_COUNTER) != 4)
6c839579 1299 ;
1300 while (read8(VDP_HV_COUNTER) != 228)
1301 ;
1302 move_sr(0x2700);
4f936a9c 1303 expect(ok, it->cnt, 225);
1304 expect(ok, it->first.v, 0);
1305 expect(ok, it->last.v, 224);
1306
6c839579 1307 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1308
4f936a9c 1309 // detect reload line
1310 it->cnt = it->first.hv = it->last.hv = 0;
1311 VDP_setReg(10, 17);
1312 move_sr(0x2000);
1313 while (read16(VDP_CTRL_PORT) & 8)
1314 /* blanking */;
1315 VDP_setReg(10, 255);
1316 while (read8(VDP_HV_COUNTER) != 228)
1317 ;
1318 move_sr(0x2700);
1319 expect(ok, it->cnt, 1);
1320 expect(ok, it->first.v, 17);
1321 expect(ok, it->last.v, 17);
1322
1323 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1324
6c839579 1325 return ok;
1326}
1327
8517a6df 1328static int t_irq_both_cpu_unmask(void)
1329{
1330 struct irq_test *ith = (void *)0xfff000;
1331 struct irq_test *itv = ith + 1;
1332 u16 s0, s1;
1333 int ok = 1;
1334
1335 memset_(ith, 0, sizeof(*ith) * 2);
1336 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1337 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1338 VDP_setReg(10, 0);
1339 while (read8(VDP_HV_COUNTER) != 100)
1340 ;
1341 while (read8(VDP_HV_COUNTER) != 226)
1342 ;
1343 VDP_setReg(10, 99);
1344 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1345 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1346 /* go to active display line 100 */
1347 while (read8(VDP_HV_COUNTER) != 100)
1348 ;
1349 s0 = read16(VDP_CTRL_PORT);
1350 s1 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1351 move_sr(0x2700);
1352 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1353 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1354
1355 expect(ok, itv->cnt, 1); // vint count
1356 expect(ok, itv->first.v, 100); // vint line
1357 expect(ok, ith->cnt, 1); // hint count
1358 expect(ok, ith->first.v, 100); // hint line
1359 expect_bits(ok, s0, SR_F, SR_F);
1360 expect_bits(ok, s1, 0, SR_F);
1361 return ok;
1362}
1363
6c839579 1364static int t_irq_ack_v_h(void)
1365{
8517a6df 1366 struct irq_test *ith = (void *)0xfff000;
1367 struct irq_test *itv = ith + 1;
6c839579 1368 u16 s0, s1, s2;
1369 int ok = 1;
1370
8517a6df 1371 memset_(ith, 0, sizeof(*ith) * 2);
6c839579 1372 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1373 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1374 VDP_setReg(10, 0);
4f936a9c 1375 /* ensure hcnt reload */
1376 while (!(read16(VDP_CTRL_PORT) & 8))
1377 /* not blanking */;
1378 while (read16(VDP_CTRL_PORT) & 8)
1379 /* blanking */;
6c839579 1380 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1381 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0);
1382 while (read8(VDP_HV_COUNTER) != 100)
1383 ;
1384 while (read8(VDP_HV_COUNTER) != 226)
1385 ;
1386 s0 = read16(VDP_CTRL_PORT);
1387 s1 = move_sr_and_read(0x2500, VDP_CTRL_PORT);
1388 burn10(666 / 10);
1389 s2 = move_sr_and_read(0x2000, VDP_CTRL_PORT);
1390 burn10(488 / 10);
1391 move_sr(0x2700);
1392 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1393 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1394
8517a6df 1395 expect(ok, itv->cnt, 1); // vint count
1396 expect(ok, itv->first.v, 226); // vint line
1397 expect(ok, ith->cnt, 1); // hint count
1398 expect(ok, ith->first.v, 228); // hint line
6c839579 1399 expect_bits(ok, s0, SR_F, SR_F);
1400 expect_bits(ok, s1, 0, SR_F);
1401 expect_bits(ok, s2, 0, SR_F);
1402 return ok;
1403}
1404
cc7e5122 1405static int t_irq_ack_v_h_2(void)
1406{
8517a6df 1407 struct irq_test *ith = (void *)0xfff000;
1408 struct irq_test *itv = ith + 1;
cc7e5122 1409 u16 s0, s1;
1410 int ok = 1;
1411
8517a6df 1412 memset_(ith, 0, sizeof(*ith) * 2);
cc7e5122 1413 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1414 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1415 VDP_setReg(10, 0);
1416 while (read8(VDP_HV_COUNTER) != 100)
1417 ;
1418 while (read8(VDP_HV_COUNTER) != 226)
1419 ;
1420 s0 = read16(VDP_CTRL_PORT);
1421 test_v_h_2();
1422 s1 = read16(VDP_CTRL_PORT);
1423 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1424 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1425
8517a6df 1426 expect(ok, itv->cnt, 2); // vint count
1427 expect(ok, itv->first.v, 226); // vint line
1428 expect(ok, ith->cnt, 1); // hint count
1429 expect(ok, ith->first.v, 227); // hint line
cc7e5122 1430 expect_bits(ok, s0, SR_F, SR_F);
1431 expect_bits(ok, s1, 0, SR_F);
1432 return ok;
1433}
1434
6c839579 1435static int t_irq_ack_h_v(void)
1436{
1437 u16 *ram = (u16 *)0xfff000;
1438 u8 *ram8 = (u8 *)0xfff000;
1439 u16 s0, s1, s[4];
1440 int ok = 1;
1441
1442 ram[0] = ram[1] = ram[2] =
1443 ram[4] = ram[5] = ram[6] = 0;
1444 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1445 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1446 VDP_setReg(10, 0);
1447 while (read8(VDP_HV_COUNTER) != 100)
1448 ;
1449 while (read8(VDP_HV_COUNTER) != 226)
1450 ;
1451 s0 = read16(VDP_CTRL_PORT);
1452 VDP_setReg(VDP_MODE1, VDP_MODE1_PS | VDP_MODE1_IE1);
1453 move_sr(0x2000);
1454 burn10(666 / 10);
1455 s1 = read16(VDP_CTRL_PORT);
1456 write_and_read1(VDP_CTRL_PORT, 0x8000 | (VDP_MODE2 << 8)
1457 | VDP_MODE2_MD | VDP_MODE2_IE0, s);
6c839579 1458 move_sr(0x2700);
1459 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1460 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1461
1462 expect(ok, ram[0], 1); // hint count
1463 expect(ok, ram8[2], 226); // hint line
1464 expect(ok, ram[4], 1); // vint count
1465 expect(ok, ram8[10], 228); // vint line
1466 expect_bits(ok, s0, SR_F, SR_F);
1467 expect_bits(ok, s1, SR_F, SR_F);
1468 expect_bits(ok, s[0], SR_F, SR_F);
1469 expect_bits(ok, s[1], SR_F, SR_F);
1470 expect_bits(ok, s[2], 0, SR_F);
1471 expect_bits(ok, s[3], 0, SR_F);
1472 return ok;
1473}
1474
cc7e5122 1475static int t_irq_ack_h_v_2(void)
1476{
1477 u16 *ram = (u16 *)0xfff000;
1478 u8 *ram8 = (u8 *)0xfff000;
1479 u16 s0, s1;
1480 int ok = 1;
1481
1482 ram[0] = ram[1] = ram[2] =
1483 ram[4] = ram[5] = ram[6] = 0;
1484 memcpy_((void *)0xff0100, test_hint, test_hint_end - test_hint);
1485 memcpy_((void *)0xff0140, test_vint, test_vint_end - test_vint);
1486 VDP_setReg(10, 0);
1487 while (read8(VDP_HV_COUNTER) != 100)
1488 ;
1489 while (read8(VDP_HV_COUNTER) != 226)
1490 ;
1491 s0 = read16(VDP_CTRL_PORT);
1492 test_h_v_2();
1493 s1 = read16(VDP_CTRL_PORT);
1494 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1495 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1496
1497 expect(ok, ram[0], 2); // hint count
1498 expect(ok, ram8[2], 226); // hint first line
1499 expect(ok, ram8[4], 226); // hint last line
1500 expect(ok, ram[4], 0); // vint count
1501 expect(ok, ram8[10], 0); // vint line
1502 expect_bits(ok, s0, SR_F, SR_F);
1503 expect_bits(ok, s1, 0, SR_F);
1504 return ok;
1505}
1506
1507static void t_irq_f_flag(void)
1508{
1509 memcpy_((void *)0xff0140, test_f_vint, test_f_vint_end - test_f_vint);
1510 memset_((void *)0xff0000, 0, 10);
1511 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_IE0 | VDP_MODE2_DISP);
1512 test_f();
1513 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1514}
1515
1516static int t_irq_f_flag_h40(void)
1517{
1518 u8 f, *r = (u8 *)0xff0000;
1519 int ok = 1;
1520
1521 t_irq_f_flag();
1522
1523 expect_bits(ok, r[0], 0, SR_F);
1524 expect_bits(ok, r[1], 0, SR_F);
1525 expect_bits(ok, r[2], 0, SR_F);
1526 // hits 1-3 times in range 3-9, usually ~5
1527 f = r[3] | r[4] | r[5] | r[6] | r[7];
1528
1529 expect_bits(ok, r[10], 0, SR_F);
1530 expect_bits(ok, r[11], 0, SR_F);
1531 expect_bits(ok, f, SR_F, SR_F);
1532 return ok;
1533}
1534
1535static int t_irq_f_flag_h32(void)
1536{
1537 u8 f, *r = (u8 *)0xff0000;
1538 int ok = 1;
1539
1540 VDP_setReg(VDP_MODE4, 0x00);
1541 t_irq_f_flag();
1542 VDP_setReg(VDP_MODE4, 0x81);
1543
1544 expect_bits(ok, r[0], 0, SR_F);
1545 expect_bits(ok, r[1], 0, SR_F);
1546 // hits 1-3 times in range 2-7, usually 3
1547 f = r[2] | r[3] | r[4] | r[5] | r[6] | r[7];
1548
1549 expect_bits(ok, r[8], 0, SR_F);
1550 expect_bits(ok, r[9], 0, SR_F);
1551 expect_bits(ok, r[10], 0, SR_F);
1552 expect_bits(ok, r[11], 0, SR_F);
1553 expect_bits(ok, f, SR_F, SR_F);
1554 return ok;
1555}
1556
9d39a80e 1557// 32X
1558
1559static int t_32x_init(void)
1560{
1561 void (*do_32x_enable)(void) = (void *)0xff0040;
1562 u32 M_OK = MKLONG('M','_','O','K');
1563 u32 S_OK = MKLONG('S','_','O','K');
1564 u32 *r = (u32 *)0xa15100;
1565 u16 *r16 = (u16 *)r;
71b41fdd 1566 int i, ok = 1;
9d39a80e 1567
71b41fdd 1568 //v1070 = read32(0x1070);
1569
1570 /* what does REN mean exactly?
1571 * Seems to be sometimes clear after reset */
1572 for (i = 0; i < 1000000; i++)
1573 if (read16(r16) & 0x80)
1574 break;
9d39a80e 1575 expect(ok, r16[0x00/2], 0x82);
1576 expect(ok, r16[0x02/2], 0);
1577 expect(ok, r16[0x04/2], 0);
1578 expect(ok, r16[0x06/2], 0);
1579 expect(ok, r[0x14/4], 0);
1580 expect(ok, r[0x18/4], 0);
1581 expect(ok, r[0x1c/4], 0);
1582 write32(&r[0x20/4], 0); // master resp
1583 write32(&r[0x24/4], 0); // slave resp
71b41fdd 1584 write32(&r[0x28/4], 0);
1585 write32(&r[0x2c/4], 0);
9d39a80e 1586
1587 // could just set RV, but BIOS reads ROM, so can't
1588 memcpy_(do_32x_enable, x32x_enable,
1589 x32x_enable_end - x32x_enable);
1590 do_32x_enable();
1591
1592 expect(ok, r16[0x00/2], 0x83);
1593 expect(ok, r16[0x02/2], 0);
1594 expect(ok, r16[0x04/2], 0);
1595 expect(ok, r16[0x06/2], 1); // RV
1596 expect(ok, r[0x14/4], 0);
1597 expect(ok, r[0x18/4], 0);
1598 expect(ok, r[0x1c/4], 0);
1599 expect(ok, r[0x20/4], M_OK);
1600 while (!read16(&r16[0x24/2]))
1601 ;
1602 expect(ok, r[0x24/4], S_OK);
06d7984c 1603 write32(&r[0x20/4], 0);
9d39a80e 1604 return ok;
1605}
1606
06d7984c 1607static void x32_cmd(enum x32x_cmd cmd, u32 a0, u32 a1, u16 is_slave)
9d39a80e 1608{
1609 u16 v, *r = (u16 *)0xa15120;
1610 u16 cmd_s = cmd | (is_slave << 15);
71b41fdd 1611 int i;
06d7984c 1612
1613 write32(&r[4/2], a0);
1614 write32(&r[8/2], a1);
1615 mem_barrier();
9d39a80e 1616 write16(r, cmd_s);
1617 mem_barrier();
71b41fdd 1618 for (i = 0; i < 10000 && (v = read16(r)) == cmd_s; i++)
9d39a80e 1619 burn10(1);
71b41fdd 1620 if (v != 0) {
9d39a80e 1621 printf("cmd clr: %x\n", v);
06d7984c 1622 mem_barrier();
1623 printf("c, e: %02x %02x\n", r[0x0c/2], r[0x0e/2]);
71b41fdd 1624 write16(r, 0);
1625 }
06d7984c 1626 v = read16(&r[1]);
1627 if (v != 0) {
1628 printf("cmd err: %x\n", v);
1629 write16(&r[1], 0);
1630 }
9d39a80e 1631}
1632
1633static int t_32x_echo(void)
1634{
1635 u16 *r = (u16 *)0xa15120;
1636 int ok = 1;
1637
06d7984c 1638 x32_cmd(CMD_ECHO, 0x12340000, 0, 0);
1639 expect(ok, r[0x06/2], 0x1234);
1640 x32_cmd(CMD_ECHO, 0x23450000, 0, 1);
1641 expect(ok, r[0x06/2], 0xa345);
1642 return ok;
1643}
1644
1645static int t_32x_md_bios(void)
1646{
1647 void (*do_call_c0)(int a, int d) = (void *)0xff0040;
1648 u8 *rmb = (u8 *)0xff0000;
1649 u32 *rl = (u32 *)0;
1650 int ok = 1;
1651
1652 memcpy_(do_call_c0, test_32x_b_c0,
1653 test_32x_b_c0_end - test_32x_b_c0);
1654 write8(rmb, 0);
1655 do_call_c0(0xff0000, 0x5a);
1656
1657 expect(ok, rmb[0], 0x5a);
1658 expect(ok, rl[0x04/4], 0x880200);
234c4556 1659 expect(ok, rl[0x10/4], 0x880212);
1660 expect(ok, rl[0x94/4], 0x8802d8);
9d39a80e 1661 return ok;
1662}
1663
1664static int t_32x_md_rom(void)
1665{
1666 u32 *rl = (u32 *)0;
1667 int ok = 1;
1668
1669 expect(ok, rl[0x004/4], 0x880200);
1670 expect(ok, rl[0x100/4], 0x53454741);
1671 expect(ok, rl[0x70/4], 0);
71b41fdd 1672 write32(&rl[0x70/4], 0xa5123456);
9d39a80e 1673 write32(&rl[0x78/4], ~0);
1674 mem_barrier();
9d39a80e 1675 expect(ok, rl[0x78/4], 0x8802ae);
71b41fdd 1676 expect(ok, rl[0x70/4], 0xa5123456);
1677 //expect(ok, rl[0x1070/4], v1070);
1678 write32(&rl[0x70/4], 0);
1679 // with RV 0x880000/0x900000 hangs, can't test
9d39a80e 1680 return ok;
1681}
1682
06d7984c 1683static int t_32x_md_fb(void)
1684{
1685 u8 *fbb = (u8 *)0x840000;
1686 u16 *fbw = (u16 *)fbb;
1687 u32 *fbl = (u32 *)fbb;
1688 u8 *fob = (u8 *)0x860000;
1689 u16 *fow = (u16 *)fob;
1690 u32 *fol = (u32 *)fob;
1691 int ok = 1;
1692
1693 fbl[0] = 0x12345678;
1694 fol[1] = 0x89abcdef;
1695 mem_barrier();
1696 expect(ok, fbw[1], 0x5678);
1697 expect(ok, fow[2], 0x89ab);
1698 fbb[0] = 0;
1699 fob[1] = 0;
1700 fbw[1] = 0;
1701 fow[2] = 0;
1702 fow[3] = 1;
1703 mem_barrier();
1704 fow[3] = 0x200;
1705 mem_barrier();
1706 expect(ok, fol[0], 0x12340000);
1707 expect(ok, fbl[1], 0x89ab0201);
1708 return ok;
1709}
1710
1711static int t_32x_sh_fb(void)
1712{
1713 u32 *fbl = (u32 *)0x840000;
1714 int ok = 1;
1715
1716 fbl[0] = 0x12345678;
1717 fbl[1] = 0x89abcdef;
1718 mem_barrier();
1719 write8(0xa15100, 0x80); // FM=1
1720 x32_cmd(CMD_WRITE8, 0x24000000, 0, 0);
1721 x32_cmd(CMD_WRITE8, 0x24020001, 0, 0);
1722 x32_cmd(CMD_WRITE16, 0x24000002, 0, 0);
1723 x32_cmd(CMD_WRITE16, 0x24020000, 0, 0);
1724 x32_cmd(CMD_WRITE32, 0x24020004, 0x5a0000a5, 1);
1725 write8(0xa15100, 0x00); // FM=0
1726 mem_barrier();
1727 expect(ok, fbl[0], 0x12340000);
1728 expect(ok, fbl[1], 0x5aabcda5);
1729 return ok;
1730}
1731
234c4556 1732static int t_32x_disable(void)
1733{
1734 void (*do_32x_disable)(void) = (void *)0xff0040;
1735 u32 *r = (u32 *)0xa15100;
1736 u16 *r16 = (u16 *)r;
1737 u32 *rl = (u32 *)0;
1738 int ok = 1;
1739
1740 expect(ok, r16[0x00/2], 0x83);
1741
1742 memcpy_(do_32x_disable, x32x_disable,
1743 x32x_disable_end - x32x_disable);
1744 do_32x_disable();
1745
1746 expect(ok, r16[0x00/2], 0x82);
1747 expect(ok, r16[0x02/2], 0);
1748 expect(ok, r16[0x04/2], 0);
1749 expect(ok, r16[0x06/2], 1); // RV
1750 expect(ok, r[0x14/4], 0);
1751 expect(ok, r[0x18/4], 0);
1752 expect(ok, r[0x1c/4], 0);
1753 expect(ok, rl[0x04/4], 0x000800);
1754
1755 write16(&r16[0x06/2], 0); // can just set without ADEN
1756 mem_barrier();
1757 expect(ok, r16[0x06/2], 0); // RV
1758 return ok;
1759}
1760
9d39a80e 1761enum {
1762 T_MD = 0,
1763 T_32 = 1, // 32X
1764};
1765
ffd4b35c 1766static const struct {
9d39a80e 1767 u8 type;
ffd4b35c 1768 int (*test)(void);
1769 const char *name;
1770} g_tests[] = {
9d39a80e 1771 { T_MD, t_dma_zero_wrap, "dma zero len + wrap" },
1772 { T_MD, t_dma_zero_fill, "dma zero len + fill" },
1773 { T_MD, t_dma_ram_wrap, "dma ram wrap" },
1774 { T_MD, t_dma_multi, "dma multi" },
1775 { T_MD, t_dma_cram_wrap, "dma cram wrap" },
1776 { T_MD, t_dma_vsram_wrap, "dma vsram wrap" },
1777 { T_MD, t_dma_and_data, "dma and data" },
1778 { T_MD, t_dma_short_cmd, "dma short cmd" },
1779 { T_MD, t_dma_fill3_odd, "dma fill3 odd" },
1780 { T_MD, t_dma_fill3_even, "dma fill3 even" },
9d39a80e 1781 { T_MD, t_dma_fill3_vsram, "dma fill3 vsram" },
9d39a80e 1782 { T_MD, t_dma_fill_dis, "dma fill disabled" },
1783 { T_MD, t_dma_fill_src, "dma fill src incr" },
1784 { T_MD, t_dma_128k, "dma 128k mode" },
1785 { T_MD, t_vdp_128k_b16, "vdp 128k addr bit16" },
a385208c 1786 // { t_vdp_128k_b16_inc, "vdp 128k bit16 inc" }, // mystery
9d39a80e 1787 { T_MD, t_vdp_reg_cmd, "vdp reg w cmd reset" },
1788 { T_MD, t_vdp_sr_vb, "vdp status reg vb" },
1789 { T_MD, t_z80mem_long_mirror, "z80 ram long mirror" },
1790 { T_MD, t_z80mem_noreq_w, "z80 ram noreq write" },
1791 { T_MD, t_z80mem_vdp_r, "z80 vdp read" },
ffd4b35c 1792 // { t_z80mem_vdp_w, "z80 vdp write" }, // hang
9d39a80e 1793 { T_MD, t_tim_loop, "time loop" },
1794 { T_MD, t_tim_z80_ram, "time z80 ram" },
1795 { T_MD, t_tim_z80_ym, "time z80 ym2612" },
1796 { T_MD, t_tim_z80_vdp, "time z80 vdp" },
1797 { T_MD, t_tim_z80_bank_rom, "time z80 bank rom" },
1798 { T_MD, t_tim_vcnt, "time V counter" },
1799 { T_MD, t_tim_hblank_h40, "time hblank h40" },
1800 { T_MD, t_tim_hblank_h32, "time hblank h32" },
1801 { T_MD, t_tim_vdp_as_vram_w, "time vdp vram w" },
1802 { T_MD, t_tim_vdp_as_cram_w, "time vdp cram w" },
1803 { T_MD, t_irq_hint, "irq4 / line" },
8517a6df 1804 { T_MD, t_irq_both_cpu_unmask, "irq both umask" },
9d39a80e 1805 { T_MD, t_irq_ack_v_h, "irq ack v-h" },
1806 { T_MD, t_irq_ack_v_h_2, "irq ack v-h 2" },
1807 { T_MD, t_irq_ack_h_v, "irq ack h-v" },
1808 { T_MD, t_irq_ack_h_v_2, "irq ack h-v 2" },
1809 { T_MD, t_irq_f_flag_h40, "irq f flag h40" },
9d39a80e 1810 { T_MD, t_irq_f_flag_h32, "irq f flag h32" },
1811
06d7984c 1812 // the first one enables 32X, so must be kept
1813 // all tests assume RV=1 FM=0
9d39a80e 1814 { T_32, t_32x_init, "32x init" },
1815 { T_32, t_32x_echo, "32x echo" },
06d7984c 1816 { T_32, t_32x_md_bios, "32x md bios" },
1817 { T_32, t_32x_md_rom, "32x md rom" },
1818 { T_32, t_32x_md_fb, "32x md fb" },
1819 { T_32, t_32x_sh_fb, "32x sh fb" },
234c4556 1820 { T_32, t_32x_disable, "32x disable" }, // must be last 32x
ffd4b35c 1821};
1822
1823static void setup_z80(void)
1824{
1825 u8 *zram = (u8 *)0xa00000;
1826 int i, len;
1827
1828 /* z80 */
1829 write16(0xa11100, 0x100);
1830 write16(0xa11200, 0x100);
1831
1832 while (read16(0xa11100) & 0x100)
1833 ;
1834
1835 // load the default test program, clear it's data
1836 len = z80_test_end - z80_test;
1837 for (i = 0; i < len; i++)
1838 write8(&zram[i], z80_test[i]);
1839 for (i = 0x1000; i < 0x1007; i++)
1840 write8(&zram[i], 0);
a385208c 1841
1842 // reset
1843 write16(0xa11200, 0x000);
1844 write16(0xa11100, 0x000);
1845 burn10(1);
1846 write16(0xa11200, 0x100);
1847 burn10(1);
1848
1849 // take back the bus
1850 write16(0xa11100, 0x100);
1851 while (read16(0xa11100) & 0x100)
1852 ;
1853}
1854
1855static void wait_next_vsync(void)
1856{
1857 while (read16(VDP_CTRL_PORT) & 8)
1858 /* blanking */;
1859 while (!(read16(VDP_CTRL_PORT) & 8))
1860 /* not blanking */;
1861}
1862
cc7e5122 1863static unused int hexinc(char *c)
a385208c 1864{
1865 (*c)++;
1866 if (*c > 'f') {
1867 *c = '0';
1868 return 1;
1869 }
1870 if (*c == '9' + 1)
1871 *c = 'a';
1872 return 0;
ffd4b35c 1873}
1874
1875int main()
1876{
1877 int passed = 0;
9d39a80e 1878 int skipped = 0;
1879 int have_32x;
234c4556 1880 int en_32x;
ffd4b35c 1881 int ret;
a385208c 1882 u8 v8;
ffd4b35c 1883 int i;
1884
1885 setup_z80();
1886
a385208c 1887 /* io */
1888 write8(0xa10009, 0x40);
1889
ffd4b35c 1890 /* setup VDP */
1891 while (read16(VDP_CTRL_PORT) & 2)
1892 ;
1893
1894 VDP_setReg(VDP_MODE1, VDP_MODE1_PS);
1895 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA);
1896 VDP_setReg(VDP_MODE3, 0x00);
1897 VDP_setReg(VDP_MODE4, 0x81);
1898 VDP_setReg(VDP_NT_SCROLLA, APLANE >> 10);
1899 VDP_setReg(VDP_NT_SCROLLB, BPLANE >> 13);
1900 VDP_setReg(VDP_SAT_BASE, SLIST >> 9);
1901 VDP_setReg(VDP_HSCROLL, HSCRL >> 10);
1902 VDP_setReg(VDP_AUTOINC, 2);
1903 VDP_setReg(VDP_SCROLLSZ, 0x01);
1904 VDP_setReg(VDP_BACKDROP, 0);
1905
1906 // early tests
1907 t_dma_zero_wrap_early();
1908 t_dma_zero_fill_early();
1909
1910 /* pattern 0 */
1911 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(0));
1912 for (i = 0; i < 32 / 4; i++)
1913 write32(VDP_DATA_PORT, 0);
1914
1915 /* clear name tables */
1916 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
1917 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
1918 write32(VDP_DATA_PORT, 0);
1919
1920 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(BPLANE));
1921 for (i = 0; i < PLANE_W * PLANE_H / 2; i++)
1922 write32(VDP_DATA_PORT, 0);
1923
1924 /* SAT, h. scroll */
1925 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(SLIST));
1926 write32(VDP_DATA_PORT, 0);
1927
1928 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
1929 write32(VDP_DATA_PORT, 0);
1930
1931 /* scroll plane vscroll */
1932 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
1933 write32(VDP_DATA_PORT, 0);
1934 printf_ypos = 1;
1935
1936 /* load font */
1937 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(TILE_FONT_BASE));
1938 for (i = 0; i < FONT_LEN * 32 / 4; i++)
1939 write32(VDP_DATA_PORT, font_base[i]);
1940
1941 /* set colors */
1942 setup_default_palette();
1943
1944 VDP_setReg(VDP_MODE2, VDP_MODE2_MD | VDP_MODE2_DMA | VDP_MODE2_DISP);
1945
9d39a80e 1946 have_32x = read32(0xa130ec) == MKLONG('M','A','R','S');
234c4556 1947 en_32x = have_32x && (read32(0xa15100) & 1);
a385208c 1948 v8 = read8(0xa10001);
234c4556 1949 printf("MD version: %02x %s %s %s%s\n", v8,
a385208c 1950 (v8 & 0x80) ? "world" : "jap",
9d39a80e 1951 (v8 & 0x40) ? "pal" : "ntsc",
234c4556 1952 have_32x ? "32X" : "",
1953 en_32x ? "+" : "");
ffd4b35c 1954
1955 for (i = 0; i < ARRAY_SIZE(g_tests); i++) {
1956 // print test number if we haven't scrolled away
1957 if (printf_ypos < CSCREEN_H) {
1958 int old_ypos = printf_ypos;
1959 printf_ypos = 0;
ffd4b35c 1960 printf("%02d/%02d", i, ARRAY_SIZE(g_tests));
1961 printf_ypos = old_ypos;
1962 printf_xpos = 0;
1963 }
9d39a80e 1964 if ((g_tests[i].type & T_32) && !have_32x) {
1965 skipped++;
1966 continue;
1967 }
ffd4b35c 1968 ret = g_tests[i].test();
a385208c 1969 if (ret != 1) {
1970 text_pal = 2;
ffd4b35c 1971 printf("failed %d: %s\n", i, g_tests[i].name);
a385208c 1972 text_pal = 0;
1973 }
ffd4b35c 1974 else
1975 passed++;
1976 }
1977
1978 text_pal = 0;
9d39a80e 1979 printf("%d/%d passed, %d skipped.\n",
1980 passed, ARRAY_SIZE(g_tests), skipped);
ffd4b35c 1981
1982 printf_ypos = 0;
1983 printf(" ");
1984
a385208c 1985 while (!(get_input() & BTNM_A))
1986 wait_next_vsync();
1987
1988
1989 {
1990 char c[3] = { '0', '0', '0' };
1991 short hscroll = 0, vscroll = 0;
1992 short hsz = 1, vsz = 0;
1993 short cellmode = 0;
1994
1995 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(APLANE));
1996
cc7e5122 1997#if 0
1998 for (i = 0, c[0] = 'a'; i < 8 * 1024 / 2; i++) {
1999 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2000 c[0]++;
2001 if (c[0] == 'z' + 1)
2002 c[0] = 'a';
2003 }
2004#else
a385208c 2005 for (i = 0; i < 8 * 1024 / 2 / 4; i++) {
2006 write16(VDP_DATA_PORT, (u16)'.' - 32 + TILE_FONT_BASE / 32);
2007 write16(VDP_DATA_PORT, (u16)c[2] - 32 + TILE_FONT_BASE / 32);
2008 write16(VDP_DATA_PORT, (u16)c[1] - 32 + TILE_FONT_BASE / 32);
2009 write16(VDP_DATA_PORT, (u16)c[0] - 32 + TILE_FONT_BASE / 32);
2010 if (hexinc(&c[0]))
2011 if (hexinc(&c[1]))
2012 hexinc(&c[2]);
2013 }
cc7e5122 2014#endif
a385208c 2015 while (get_input() & BTNM_A)
2016 wait_next_vsync();
2017
2018 wait_next_vsync();
2019 for (;;) {
2020 int b = get_input();
2021
2022 if (b & BTNM_C) {
2023 hscroll = 1, vscroll = -1;
2024 do {
2025 wait_next_vsync();
2026 } while (get_input() & BTNM_C);
2027 cellmode ^= 1;
2028 }
2029 if (b & (BTNM_L | BTNM_R | BTNM_C)) {
2030 hscroll += (b & BTNM_L) ? 1 : -1;
2031 write32(VDP_CTRL_PORT, CTL_WRITE_VRAM(HSCRL));
2032 write16(VDP_DATA_PORT, hscroll);
2033 }
2034 if (b & (BTNM_U | BTNM_D | BTNM_C)) {
2035 vscroll += (b & BTNM_U) ? -1 : 1;
2036 write32(VDP_CTRL_PORT, CTL_WRITE_VSRAM(0));
2037 if (cellmode) {
2038 int end = (int)vscroll + 21;
2039 for (i = vscroll; i < end; i++)
2040 write32(VDP_DATA_PORT, i << 17);
2041 VDP_setReg(VDP_MODE3, 0x04);
2042 }
2043 else {
2044 write16(VDP_DATA_PORT, vscroll);
2045 VDP_setReg(VDP_MODE3, 0x00);
2046 }
2047 }
2048 if (b & BTNM_A) {
2049 hsz = (hsz + 1) & 3;
2050 do {
2051 wait_next_vsync();
2052 } while (get_input() & BTNM_A);
2053 }
2054 if (b & BTNM_B) {
2055 vsz = (vsz + 1) & 3;
2056 do {
2057 wait_next_vsync();
2058 } while (get_input() & BTNM_B);
2059 }
2060 VDP_setReg(VDP_SCROLLSZ, (vsz << 4) | hsz);
2061
2062 printf_xpos = 1;
2063 printf_ypos = 0;
2064 text_pal = 1;
2065 printf(" %d %d ", hsz, vsz);
2066
2067 wait_next_vsync();
2068 }
2069 }
2070
ffd4b35c 2071 for (;;)
2072 ;
2073
2074 return 0;
2075}
2076
2077// vim:ts=4:sw=4:expandtab
Genesis/MegaDrive related projects