source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <stdarg.h>
  24 #include <stdlib.h>
  25 #include <stdint.h> //include for uint64_t
  26 //#include <assert.h>
  27 #define assert(a)       {}
  28
  29 #include "../recomp.h"
  30 #include "../recomph.h" //include for function prototypes
  31 #include "../macros.h"
  32 #include "../r4300.h"
  33 #include "../ops.h"
  34 #include "../interupt.h"
  35 #include "new_dynarec.h"
  36
  37 #include "../../memory/memory.h"
  38 #include "../../main/rom.h"
  39
  40 #include <sys/mman.h>
  41
  42 #if NEW_DYNAREC == NEW_DYNAREC_X86
  43 #include "assem_x86.h"
  44 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
  45 #include "assem_arm.h"
  46 #else
  47 #error Unsupported dynarec architecture
  48 #endif
  49
  50 #define MAXBLOCK 4096
  51 #define MAX_OUTPUT_BLOCK_SIZE 262144
  52 #define CLOCK_DIVIDER count_per_op
  53
  54 void *base_addr;
  55
  56 struct regstat
  57 {
  58   signed char regmap_entry[HOST_REGS];
  59   signed char regmap[HOST_REGS];
  60   uint64_t was32;
  61   uint64_t is32;
  62   uint64_t wasdirty;
  63   uint64_t dirty;
  64   uint64_t u;
  65   uint64_t uu;
  66   u_int wasconst;
  67   u_int isconst;
  68   uint64_t constmap[HOST_REGS];
  69 };
  70
  71 struct ll_entry
  72 {
  73   u_int vaddr;
  74   u_int reg32;
  75   void *addr;
  76   struct ll_entry *next;
  77 };
  78
  79 static u_int start;
  80 static u_int *source;
  81 static u_int pagelimit;
  82 static char insn[MAXBLOCK][10];
  83 static u_char itype[MAXBLOCK];
  84 static u_char opcode[MAXBLOCK];
  85 static u_char opcode2[MAXBLOCK];
  86 static u_char bt[MAXBLOCK];
  87 static u_char rs1[MAXBLOCK];
  88 static u_char rs2[MAXBLOCK];
  89 static u_char rt1[MAXBLOCK];
  90 static u_char rt2[MAXBLOCK];
  91 static u_char us1[MAXBLOCK];
  92 static u_char us2[MAXBLOCK];
  93 static u_char dep1[MAXBLOCK];
  94 static u_char dep2[MAXBLOCK];
  95 static u_char lt1[MAXBLOCK];
  96 static int imm[MAXBLOCK];
  97 static u_int ba[MAXBLOCK];
  98 static char likely[MAXBLOCK];
  99 static char is_ds[MAXBLOCK];
 100 static char ooo[MAXBLOCK];
 101 static uint64_t unneeded_reg[MAXBLOCK];
 102 static uint64_t unneeded_reg_upper[MAXBLOCK];
 103 static uint64_t branch_unneeded_reg[MAXBLOCK];
 104 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 105 static uint64_t p32[MAXBLOCK];
 106 static uint64_t pr32[MAXBLOCK];
 107 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
 108 #ifdef ASSEM_DEBUG
 109 static signed char regmap[MAXBLOCK][HOST_REGS];
 110 static signed char regmap_entry[MAXBLOCK][HOST_REGS];
 111 #endif
 112 static uint64_t constmap[MAXBLOCK][HOST_REGS];
 113 static struct regstat regs[MAXBLOCK];
 114 static struct regstat branch_regs[MAXBLOCK];
 115 static signed char minimum_free_regs[MAXBLOCK];
 116 static u_int needed_reg[MAXBLOCK];
 117 static uint64_t requires_32bit[MAXBLOCK];
 118 static u_int wont_dirty[MAXBLOCK];
 119 static u_int will_dirty[MAXBLOCK];
 120 static int ccadj[MAXBLOCK];
 121 static int slen;
 122 static u_int instr_addr[MAXBLOCK];
 123 static u_int link_addr[MAXBLOCK][3];
 124 static int linkcount;
 125 static u_int stubs[MAXBLOCK*3][8];
 126 static int stubcount;
 127 static int literalcount;
 128 static int is_delayslot;
 129 static int cop1_usable;
 130 u_char *out;
 131 struct ll_entry *jump_in[4096];
 132 static struct ll_entry *jump_out[4096];
 133 struct ll_entry *jump_dirty[4096];
 134 u_int hash_table[65536][4]  __attribute__((aligned(16)));
 135 static char shadow[2097152]  __attribute__((aligned(16)));
 136 static void *copy;
 137 static int expirep;
 138 u_int using_tlb;
 139 static u_int stop_after_jal;
 140 extern u_char restore_candidate[512];
 141 extern int cycle_count;
 142
 143   /* registers that may be allocated */
 144   /* 1-31 gpr */
 145 #define HIREG 32 // hi
 146 #define LOREG 33 // lo
 147 #define FSREG 34 // FPU status (FCSR)
 148 #define CSREG 35 // Coprocessor status
 149 #define CCREG 36 // Cycle count
 150 #define INVCP 37 // Pointer to invalid_code
 151 #define MMREG 38 // Pointer to memory_map
 152 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 153 #define TEMPREG 40
 154 #define FTEMP 40 // FPU temporary register
 155 #define PTEMP 41 // Prefetch temporary register
 156 #define TLREG 42 // TLB mapping offset
 157 #define RHASH 43 // Return address hash
 158 #define RHTBL 44 // Return address hash table address
 159 #define RTEMP 45 // JR/JALR address register
 160 #define MAXREG 45
 161 #define AGEN1 46 // Address generation temporary register
 162 #define AGEN2 47 // Address generation temporary register
 163 #define MGEN1 48 // Maptable address generation temporary register
 164 #define MGEN2 49 // Maptable address generation temporary register
 165 #define BTREG 50 // Branch target temporary register
 166
 167   /* instruction types */
 168 #define NOP 0     // No operation
 169 #define LOAD 1    // Load
 170 #define STORE 2   // Store
 171 #define LOADLR 3  // Unaligned load
 172 #define STORELR 4 // Unaligned store
 173 #define MOV 5     // Move
 174 #define ALU 6     // Arithmetic/logic
 175 #define MULTDIV 7 // Multiply/divide
 176 #define SHIFT 8   // Shift by register
 177 #define SHIFTIMM 9// Shift by immediate
 178 #define IMM16 10  // 16-bit immediate
 179 #define RJUMP 11  // Unconditional jump to register
 180 #define UJUMP 12  // Unconditional jump
 181 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 182 #define SJUMP 14  // Conditional branch (regimm format)
 183 #define COP0 15   // Coprocessor 0
 184 #define COP1 16   // Coprocessor 1
 185 #define C1LS 17   // Coprocessor 1 load/store
 186 #define FJUMP 18  // Conditional branch (floating point)
 187 #define FLOAT 19  // Floating point unit
 188 #define FCONV 20  // Convert integer to float
 189 #define FCOMP 21  // Floating point compare (sets FSREG)
 190 #define SYSCALL 22// SYSCALL
 191 #define OTHER 23  // Other
 192 #define SPAN 24   // Branch/delay slot spans 2 pages
 193 #define NI 25     // Not implemented
 194
 195   /* stubs */
 196 #define CC_STUB 1
 197 #define FP_STUB 2
 198 #define LOADB_STUB 3
 199 #define LOADH_STUB 4
 200 #define LOADW_STUB 5
 201 #define LOADD_STUB 6
 202 #define LOADBU_STUB 7
 203 #define LOADHU_STUB 8
 204 #define STOREB_STUB 9
 205 #define STOREH_STUB 10
 206 #define STOREW_STUB 11
 207 #define STORED_STUB 12
 208 #define STORELR_STUB 13
 209 #define INVCODE_STUB 14
 210
 211   /* branch codes */
 212 #define TAKEN 1
 213 #define NOTTAKEN 2
 214 #define NULLDS 3
 215
 216 /* bug-fix to implement __clear_cache (missing in Android; http://code.google.com/p/android/issues/detail?id=1803) */
 217 void __clear_cache_bugfix(char* begin, char *end);
 218 #ifdef ANDROID
 219         #define __clear_cache __clear_cache_bugfix
 220 #endif
 221
 222 // asm linkage
 223 int new_recompile_block(int addr);
 224 void *get_addr_ht(u_int vaddr);
 225 static void remove_hash(int vaddr);
 226 void dyna_linker();
 227 void dyna_linker_ds();
 228 void verify_code();
 229 void verify_code_vm();
 230 void verify_code_ds();
 231 void cc_interrupt();
 232 void fp_exception();
 233 void fp_exception_ds();
 234 void jump_syscall();
 235 void jump_eret();
 236 #if NEW_DYNAREC == NEW_DYNAREC_ARM
 237 static void invalidate_addr(u_int addr);
 238 #endif
 239
 240 // TLB
 241 void TLBWI_new();
 242 void TLBWR_new();
 243 void read_nomem_new();
 244 void read_nomemb_new();
 245 void read_nomemh_new();
 246 void read_nomemd_new();
 247 void write_nomem_new();
 248 void write_nomemb_new();
 249 void write_nomemh_new();
 250 void write_nomemd_new();
 251 void write_rdram_new();
 252 void write_rdramb_new();
 253 void write_rdramh_new();
 254 void write_rdramd_new();
 255 extern u_int memory_map[1048576];
 256
 257 // Needed by assembler
 258 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 259 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 260 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 261 static void load_all_regs(signed char i_regmap[]);
 262 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 263 static void load_regs_entry(int t);
 264 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 265
 266 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e);
 267 static void add_to_linker(int addr,int target,int ext);
 268 static int verify_dirty(void *addr);
 269
 270 //static int tracedebug=0;
 271
 272 //#define DEBUG_CYCLE_COUNT 1
 273
 274 // Uncomment these two lines to generate debug output:
 275 #//define ASSEM_DEBUG 1
 276 //#define INV_DEBUG 1
 277
 278 // Uncomment this line to output the number of NOTCOMPILED blocks as they occur:
 279 //#define COUNT_NOTCOMPILEDS 1
 280
 281 #if defined (COUNT_NOTCOMPILEDS )
 282         int notcompiledCount = 0;
 283 #endif
 284 static void nullf() {}
 285
 286 #if defined( ASSEM_DEBUG )
 287     #define assem_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 288 #else
 289     #define assem_debug nullf
 290 #endif
 291 #if defined( INV_DEBUG )
 292     #define inv_debug(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 293 #else
 294     #define inv_debug nullf
 295 #endif
 296
 297 #define log_message(...) DebugMessage(M64MSG_VERBOSE, __VA_ARGS__)
 298
 299 static void tlb_hacks()
 300 {
 301   // Goldeneye hack
 302   if (strncmp((char *) ROM_HEADER.Name, "GOLDENEYE",9) == 0)
 303   {
 304     u_int addr;
 305     int n;
 306     switch (ROM_HEADER.Country_code&0xFF)
 307     {
 308       case 0x45: // U
 309         addr=0x34b30;
 310         break;
 311       case 0x4A: // J
 312         addr=0x34b70;
 313         break;
 314       case 0x50: // E
 315         addr=0x329f0;
 316         break;
 317       default:
 318         // Unknown country code
 319         addr=0;
 320         break;
 321     }
 322     u_int rom_addr=(u_int)rom;
 323     #ifdef ROM_COPY
 324     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 325     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 326     if((void *)rom>(void *)0xffffffff) {
 327       munmap(ROM_COPY, 67108864);
 328       if(mmap(ROM_COPY, 12582912,
 329               PROT_READ | PROT_WRITE,
 330               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 331               -1, 0) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
 332       memcpy(ROM_COPY,rom,12582912);
 333       rom_addr=(u_int)ROM_COPY;
 334     }
 335     #endif
 336     if(addr) {
 337       for(n=0x7F000;n<0x80000;n++) {
 338         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 339       }
 340     }
 341   }
 342 }
 343
 344 // Get address from virtual address
 345 // This is called from the recompiled JR/JALR instructions
 346 void *get_addr(u_int vaddr)
 347 {
 348   u_int page=(vaddr^0x80000000)>>12;
 349   u_int vpage=page;
 350   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 351   if(page>2048) page=2048+(page&2047);
 352   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 353   if(vpage>2048) vpage=2048+(vpage&2047);
 354   struct ll_entry *head;
 355   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr %x,page %d)",Count,next_interupt,vaddr,page);
 356   head=jump_in[page];
 357   while(head!=NULL) {
 358     if(head->vaddr==vaddr&&head->reg32==0) {
 359   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 360       u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 361       ht_bin[3]=ht_bin[1];
 362       ht_bin[2]=ht_bin[0];
 363       ht_bin[1]=(int)head->addr;
 364       ht_bin[0]=vaddr;
 365       return head->addr;
 366     }
 367     head=head->next;
 368   }
 369   head=jump_dirty[vpage];
 370   while(head!=NULL) {
 371     if(head->vaddr==vaddr&&head->reg32==0) {
 372       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 373       // Don't restore blocks which are about to expire from the cache
 374       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 375       if(verify_dirty(head->addr)) {
 376         //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
 377         invalid_code[vaddr>>12]=0;
 378         memory_map[vaddr>>12]|=0x40000000;
 379         if(vpage<2048) {
 380           if(tlb_LUT_r[vaddr>>12]) {
 381             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 382             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 383           }
 384           restore_candidate[vpage>>3]|=1<<(vpage&7);
 385         }
 386         else restore_candidate[page>>3]|=1<<(page&7);
 387         u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 388         if(ht_bin[0]==vaddr) {
 389           ht_bin[1]=(int)head->addr; // Replace existing entry
 390         }
 391         else
 392         {
 393           ht_bin[3]=ht_bin[1];
 394           ht_bin[2]=ht_bin[0];
 395           ht_bin[1]=(int)head->addr;
 396           ht_bin[0]=vaddr;
 397         }
 398         return head->addr;
 399       }
 400     }
 401     head=head->next;
 402   }
 403   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr no-match %x)",Count,next_interupt,vaddr);
 404   int r=new_recompile_block(vaddr);
 405   if(r==0) return get_addr(vaddr);
 406   // Execute in unmapped page, generate pagefault execption
 407   Status|=2;
 408   Cause=(vaddr<<31)|0x8;
 409   EPC=(vaddr&1)?vaddr-5:vaddr;
 410   BadVAddr=(vaddr&~1);
 411   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 412   EntryHi=BadVAddr&0xFFFFE000;
 413   return get_addr_ht(0x80000000);
 414 }
 415 // Look up address in hash table first
 416 void *get_addr_ht(u_int vaddr)
 417 {
 418   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_ht %x)",Count,next_interupt,vaddr);
 419   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 420   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 421   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 422   return get_addr(vaddr);
 423 }
 424
 425 void *get_addr_32(u_int vaddr,u_int flags)
 426 {
 427   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 %x,flags %x)",Count,next_interupt,vaddr,flags);
 428   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 429   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 430   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 431   u_int page=(vaddr^0x80000000)>>12;
 432   u_int vpage=page;
 433   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 434   if(page>2048) page=2048+(page&2047);
 435   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 436   if(vpage>2048) vpage=2048+(vpage&2047);
 437   struct ll_entry *head;
 438   head=jump_in[page];
 439   while(head!=NULL) {
 440     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 441       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 442       if(head->reg32==0) {
 443         u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 444         if(ht_bin[0]==-1) {
 445           ht_bin[1]=(int)head->addr;
 446           ht_bin[0]=vaddr;
 447         }else if(ht_bin[2]==-1) {
 448           ht_bin[3]=(int)head->addr;
 449           ht_bin[2]=vaddr;
 450         }
 451         //ht_bin[3]=ht_bin[1];
 452         //ht_bin[2]=ht_bin[0];
 453         //ht_bin[1]=(int)head->addr;
 454         //ht_bin[0]=vaddr;
 455       }
 456       return head->addr;
 457     }
 458     head=head->next;
 459   }
 460   head=jump_dirty[vpage];
 461   while(head!=NULL) {
 462     if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
 463       //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)",Count,next_interupt,vaddr,(int)head->addr);
 464       // Don't restore blocks which are about to expire from the cache
 465       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 466       if(verify_dirty(head->addr)) {
 467         //DebugMessage(M64MSG_VERBOSE, "restore candidate: %x (%d) d=%d",vaddr,page,invalid_code[vaddr>>12]);
 468         invalid_code[vaddr>>12]=0;
 469         memory_map[vaddr>>12]|=0x40000000;
 470         if(vpage<2048) {
 471           if(tlb_LUT_r[vaddr>>12]) {
 472             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 473             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 474           }
 475           restore_candidate[vpage>>3]|=1<<(vpage&7);
 476         }
 477         else restore_candidate[page>>3]|=1<<(page&7);
 478         if(head->reg32==0) {
 479           u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 480           if(ht_bin[0]==-1) {
 481             ht_bin[1]=(int)head->addr;
 482             ht_bin[0]=vaddr;
 483           }else if(ht_bin[2]==-1) {
 484             ht_bin[3]=(int)head->addr;
 485             ht_bin[2]=vaddr;
 486           }
 487           //ht_bin[3]=ht_bin[1];
 488           //ht_bin[2]=ht_bin[0];
 489           //ht_bin[1]=(int)head->addr;
 490           //ht_bin[0]=vaddr;
 491         }
 492         return head->addr;
 493       }
 494     }
 495     head=head->next;
 496   }
 497   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)",Count,next_interupt,vaddr,flags);
 498   int r=new_recompile_block(vaddr);
 499   if(r==0) return get_addr(vaddr);
 500   // Execute in unmapped page, generate pagefault execption
 501   Status|=2;
 502   Cause=(vaddr<<31)|0x8;
 503   EPC=(vaddr&1)?vaddr-5:vaddr;
 504   BadVAddr=(vaddr&~1);
 505   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 506   EntryHi=BadVAddr&0xFFFFE000;
 507   return get_addr_ht(0x80000000);
 508 }
 509
 510 static void clear_all_regs(signed char regmap[])
 511 {
 512   int hr;
 513   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 514 }
 515
 516 static signed char get_reg(signed char regmap[],int r)
 517 {
 518   int hr;
 519   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 520   return -1;
 521 }
 522
 523 // Find a register that is available for two consecutive cycles
 524 static signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 525 {
 526   int hr;
 527   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 528   return -1;
 529 }
 530
 531 static int count_free_regs(signed char regmap[])
 532 {
 533   int count=0;
 534   int hr;
 535   for(hr=0;hr<HOST_REGS;hr++)
 536   {
 537     if(hr!=EXCLUDE_REG) {
 538       if(regmap[hr]<0) count++;
 539     }
 540   }
 541   return count;
 542 }
 543
 544 static void dirty_reg(struct regstat *cur,signed char reg)
 545 {
 546   int hr;
 547   if(!reg) return;
 548   for (hr=0;hr<HOST_REGS;hr++) {
 549     if((cur->regmap[hr]&63)==reg) {
 550       cur->dirty|=1<<hr;
 551     }
 552   }
 553 }
 554
 555 // If we dirty the lower half of a 64 bit register which is now being
 556 // sign-extended, we need to dump the upper half.
 557 // Note: Do this only after completion of the instruction, because
 558 // some instructions may need to read the full 64-bit value even if
 559 // overwriting it (eg SLTI, DSRA32).
 560 static void flush_dirty_uppers(struct regstat *cur)
 561 {
 562   int hr,reg;
 563   for (hr=0;hr<HOST_REGS;hr++) {
 564     if((cur->dirty>>hr)&1) {
 565       reg=cur->regmap[hr];
 566       if(reg>=64)
 567         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 568     }
 569   }
 570 }
 571
 572 static void set_const(struct regstat *cur,signed char reg,uint64_t value)
 573 {
 574   int hr;
 575   if(!reg) return;
 576   for (hr=0;hr<HOST_REGS;hr++) {
 577     if(cur->regmap[hr]==reg) {
 578       cur->isconst|=1<<hr;
 579       cur->constmap[hr]=value;
 580     }
 581     else if((cur->regmap[hr]^64)==reg) {
 582       cur->isconst|=1<<hr;
 583       cur->constmap[hr]=value>>32;
 584     }
 585   }
 586 }
 587
 588 static void clear_const(struct regstat *cur,signed char reg)
 589 {
 590   int hr;
 591   if(!reg) return;
 592   for (hr=0;hr<HOST_REGS;hr++) {
 593     if((cur->regmap[hr]&63)==reg) {
 594       cur->isconst&=~(1<<hr);
 595     }
 596   }
 597 }
 598
 599 static int is_const(struct regstat *cur,signed char reg)
 600 {
 601   int hr;
 602   if(reg<0) return 0;
 603   if(!reg) return 1;
 604   for (hr=0;hr<HOST_REGS;hr++) {
 605     if((cur->regmap[hr]&63)==reg) {
 606       return (cur->isconst>>hr)&1;
 607     }
 608   }
 609   return 0;
 610 }
 611 static uint64_t get_const(struct regstat *cur,signed char reg)
 612 {
 613   int hr;
 614   if(!reg) return 0;
 615   for (hr=0;hr<HOST_REGS;hr++) {
 616     if(cur->regmap[hr]==reg) {
 617       return cur->constmap[hr];
 618     }
 619   }
 620   DebugMessage(M64MSG_ERROR, "Unknown constant in r%d",reg);
 621   exit(1);
 622 }
 623
 624 // Least soon needed registers
 625 // Look at the next ten instructions and see which registers
 626 // will be used.  Try not to reallocate these.
 627 static void lsn(u_char hsn[], int i, int *preferred_reg)
 628 {
 629   int j;
 630   int b=-1;
 631   for(j=0;j<9;j++)
 632   {
 633     if(i+j>=slen) {
 634       j=slen-i-1;
 635       break;
 636     }
 637     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 638     {
 639       // Don't go past an unconditonal jump
 640       j++;
 641       break;
 642     }
 643   }
 644   for(;j>=0;j--)
 645   {
 646     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 647     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 648     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 649     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 650     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 651       // Stores can allocate zero
 652       hsn[rs1[i+j]]=j;
 653       hsn[rs2[i+j]]=j;
 654     }
 655     // On some architectures stores need invc_ptr
 656     #if defined(HOST_IMM8)
 657     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39) {
 658       hsn[INVCP]=j;
 659     }
 660     #endif
 661     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 662     {
 663       hsn[CCREG]=j;
 664       b=j;
 665     }
 666   }
 667   if(b>=0)
 668   {
 669     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 670     {
 671       // Follow first branch
 672       int t=(ba[i+b]-start)>>2;
 673       j=7-b;if(t+j>=slen) j=slen-t-1;
 674       for(;j>=0;j--)
 675       {
 676         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 677         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 678         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 679         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 680       }
 681     }
 682     // TODO: preferred register based on backward branch
 683   }
 684   // Delay slot should preferably not overwrite branch conditions or cycle count
 685   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 686     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 687     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 688     hsn[CCREG]=1;
 689     // ...or hash tables
 690     hsn[RHASH]=1;
 691     hsn[RHTBL]=1;
 692   }
 693   // Coprocessor load/store needs FTEMP, even if not declared
 694   if(itype[i]==C1LS) {
 695     hsn[FTEMP]=0;
 696   }
 697   // Load L/R also uses FTEMP as a temporary register
 698   if(itype[i]==LOADLR) {
 699     hsn[FTEMP]=0;
 700   }
 701   // Also 64-bit SDL/SDR
 702   if(opcode[i]==0x2c||opcode[i]==0x2d) {
 703     hsn[FTEMP]=0;
 704   }
 705   // Don't remove the TLB registers either
 706   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS ) {
 707     hsn[TLREG]=0;
 708   }
 709   // Don't remove the miniht registers
 710   if(itype[i]==UJUMP||itype[i]==RJUMP)
 711   {
 712     hsn[RHASH]=0;
 713     hsn[RHTBL]=0;
 714   }
 715 }
 716
 717 // We only want to allocate registers if we're going to use them again soon
 718 static int needed_again(int r, int i)
 719 {
 720   int j;
 721   /*int b=-1;*/
 722   int rn=10;
 723
 724   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 725   {
 726     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 727       return 0; // Don't need any registers if exiting the block
 728   }
 729   for(j=0;j<9;j++)
 730   {
 731     if(i+j>=slen) {
 732       j=slen-i-1;
 733       break;
 734     }
 735     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 736     {
 737       // Don't go past an unconditonal jump
 738       j++;
 739       break;
 740     }
 741     if(itype[i+j]==SYSCALL||((source[i+j]&0xfc00003f)==0x0d))
 742     {
 743       break;
 744     }
 745   }
 746   for(;j>=1;j--)
 747   {
 748     if(rs1[i+j]==r) rn=j;
 749     if(rs2[i+j]==r) rn=j;
 750     if((unneeded_reg[i+j]>>r)&1) rn=10;
 751     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 752     {
 753       /*b=j;*/
 754     }
 755   }
 756   /*
 757   if(b>=0)
 758   {
 759     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 760     {
 761       // Follow first branch
 762       int o=rn;
 763       int t=(ba[i+b]-start)>>2;
 764       j=7-b;if(t+j>=slen) j=slen-t-1;
 765       for(;j>=0;j--)
 766       {
 767         if(!((unneeded_reg[t+j]>>r)&1)) {
 768           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 769           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 770         }
 771         else rn=o;
 772       }
 773     }
 774   }*/
 775   if(rn<10) return 1;
 776   return 0;
 777 }
 778
 779 // Try to match register allocations at the end of a loop with those
 780 // at the beginning
 781 static int loop_reg(int i, int r, int hr)
 782 {
 783   int j,k;
 784   for(j=0;j<9;j++)
 785   {
 786     if(i+j>=slen) {
 787       j=slen-i-1;
 788       break;
 789     }
 790     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 791     {
 792       // Don't go past an unconditonal jump
 793       j++;
 794       break;
 795     }
 796   }
 797   k=0;
 798   if(i>0){
 799     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 800       k--;
 801   }
 802   for(;k<j;k++)
 803   {
 804     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 805     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 806     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 807     {
 808       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 809       {
 810         int t=(ba[i+k]-start)>>2;
 811         int reg=get_reg(regs[t].regmap_entry,r);
 812         if(reg>=0) return reg;
 813         //reg=get_reg(regs[t+1].regmap_entry,r);
 814         //if(reg>=0) return reg;
 815       }
 816     }
 817   }
 818   return hr;
 819 }
 820
 821
 822 // Allocate every register, preserving source/target regs
 823 static void alloc_all(struct regstat *cur,int i)
 824 {
 825   int hr;
 826
 827   for(hr=0;hr<HOST_REGS;hr++) {
 828     if(hr!=EXCLUDE_REG) {
 829       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 830          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 831       {
 832         cur->regmap[hr]=-1;
 833         cur->dirty&=~(1<<hr);
 834       }
 835       // Don't need zeros
 836       if((cur->regmap[hr]&63)==0)
 837       {
 838         cur->regmap[hr]=-1;
 839         cur->dirty&=~(1<<hr);
 840       }
 841     }
 842   }
 843 }
 844
 845
 846 static void div64(int64_t dividend,int64_t divisor)
 847 {
 848   if ((dividend) && (divisor)) {
 849   lo=dividend/divisor;
 850   hi=dividend%divisor;
 851   } else {
 852   lo=0;
 853   hi=0;
 854   }
 855   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 856   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 857 }
 858 static void divu64(uint64_t dividend,uint64_t divisor)
 859 {
 860   if ((dividend) && (divisor)) {
 861   lo=dividend/divisor;
 862   hi=dividend%divisor;
 863   } else {
 864   lo=0;
 865   hi=0;
 866   }
 867   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 868   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 869 }
 870 static void div32(int32_t dividend,int32_t divisor)
 871 {
 872   if ((dividend) && (divisor)) {
 873   lo=dividend/divisor;
 874   hi=dividend%divisor;
 875   } else {
 876   lo=0;
 877   hi=0;
 878   }
 879   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddiv %8x%8x %8x%8x" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 880   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 881 }
 882 static void divu32(uint32_t dividend,uint32_t divisor)
 883 {
 884   if ((dividend) && (divisor)) {
 885   lo=dividend/divisor;
 886   hi=dividend%divisor;
 887   } else {
 888   lo=0;
 889   hi=0;
 890   }
 891   //DebugMessage(M64MSG_VERBOSE, "TRACE: ddivu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 892   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 893 }
 894
 895 static void mult64(int64_t m1,int64_t m2)
 896 {
 897    uint64_t op1, op2, op3, op4;
 898    uint64_t result1, result2, result3, result4;
 899    uint64_t temp1, temp2, temp3, temp4;
 900    int sign = 0;
 901
 902    if (m1 < 0)
 903      {
 904     op2 = -m1;
 905     sign = 1 - sign;
 906      }
 907    else op2 = m1;
 908    if (m2 < 0)
 909      {
 910     op4 = -m2;
 911     sign = 1 - sign;
 912      }
 913    else op4 = m2;
 914
 915    op1 = op2 & 0xFFFFFFFF;
 916    op2 = (op2 >> 32) & 0xFFFFFFFF;
 917    op3 = op4 & 0xFFFFFFFF;
 918    op4 = (op4 >> 32) & 0xFFFFFFFF;
 919
 920    temp1 = op1 * op3;
 921    temp2 = (temp1 >> 32) + op1 * op4;
 922    temp3 = op2 * op3;
 923    temp4 = (temp3 >> 32) + op2 * op4;
 924
 925    result1 = temp1 & 0xFFFFFFFF;
 926    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 927    result3 = (result2 >> 32) + temp4;
 928    result4 = (result3 >> 32);
 929
 930    lo = result1 | (result2 << 32);
 931    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 932    if (sign)
 933      {
 934     hi = ~hi;
 935     if (!lo) hi++;
 936     else lo = ~lo + 1;
 937      }
 938 }
 939
 940 #if NEW_DYNAREC == NEW_DYNAREC_ARM
 941 static void multu64(uint64_t m1,uint64_t m2)
 942 {
 943    uint64_t op1, op2, op3, op4;
 944    uint64_t result1, result2, result3, result4;
 945    uint64_t temp1, temp2, temp3, temp4;
 946
 947    op1 = m1 & 0xFFFFFFFF;
 948    op2 = (m1 >> 32) & 0xFFFFFFFF;
 949    op3 = m2 & 0xFFFFFFFF;
 950    op4 = (m2 >> 32) & 0xFFFFFFFF;
 951
 952    temp1 = op1 * op3;
 953    temp2 = (temp1 >> 32) + op1 * op4;
 954    temp3 = op2 * op3;
 955    temp4 = (temp3 >> 32) + op2 * op4;
 956
 957    result1 = temp1 & 0xFFFFFFFF;
 958    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 959    result3 = (result2 >> 32) + temp4;
 960    result4 = (result3 >> 32);
 961
 962    lo = result1 | (result2 << 32);
 963    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 964
 965   //DebugMessage(M64MSG_VERBOSE, "TRACE: dmultu %8x%8x %8x%8x",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 966   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 967 }
 968 #endif
 969
 970 static uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 971 {
 972   if(bits) {
 973     original<<=64-bits;
 974     original>>=64-bits;
 975     loaded<<=bits;
 976     original|=loaded;
 977   }
 978   else original=loaded;
 979   return original;
 980 }
 981 static uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 982 {
 983   if(bits^56) {
 984     original>>=64-(bits^56);
 985     original<<=64-(bits^56);
 986     loaded>>=bits^56;
 987     original|=loaded;
 988   }
 989   else original=loaded;
 990   return original;
 991 }
 992
 993 #if NEW_DYNAREC == NEW_DYNAREC_X86
 994 #include "assem_x86.c"
 995 #elif NEW_DYNAREC == NEW_DYNAREC_ARM
 996 #include "assem_arm.c"
 997 #else
 998 #error Unsupported dynarec architecture
 999 #endif
1000
1001 // Add virtual address mapping to linked list
1002 static void ll_add(struct ll_entry **head,int vaddr,void *addr)
1003 {
1004   struct ll_entry *new_entry;
1005   new_entry=malloc(sizeof(struct ll_entry));
1006   assert(new_entry!=NULL);
1007   new_entry->vaddr=vaddr;
1008   new_entry->reg32=0;
1009   new_entry->addr=addr;
1010   new_entry->next=*head;
1011   *head=new_entry;
1012 }
1013
1014 // Add virtual address mapping for 32-bit compiled block
1015 static void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1016 {
1017   struct ll_entry *new_entry;
1018   new_entry=malloc(sizeof(struct ll_entry));
1019   assert(new_entry!=NULL);
1020   new_entry->vaddr=vaddr;
1021   new_entry->reg32=reg32;
1022   new_entry->addr=addr;
1023   new_entry->next=*head;
1024   *head=new_entry;
1025 }
1026
1027 // Check if an address is already compiled
1028 // but don't return addresses which are about to expire from the cache
1029 static void *check_addr(u_int vaddr)
1030 {
1031   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1032   if(ht_bin[0]==vaddr) {
1033     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1034       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1035   }
1036   if(ht_bin[2]==vaddr) {
1037     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1038       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1039   }
1040   u_int page=(vaddr^0x80000000)>>12;
1041   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1042   if(page>2048) page=2048+(page&2047);
1043   struct ll_entry *head;
1044   head=jump_in[page];
1045   while(head!=NULL) {
1046     if(head->vaddr==vaddr&&head->reg32==0) {
1047       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1048         // Update existing entry with current address
1049         if(ht_bin[0]==vaddr) {
1050           ht_bin[1]=(int)head->addr;
1051           return head->addr;
1052         }
1053         if(ht_bin[2]==vaddr) {
1054           ht_bin[3]=(int)head->addr;
1055           return head->addr;
1056         }
1057         // Insert into hash table with low priority.
1058         // Don't evict existing entries, as they are probably
1059         // addresses that are being accessed frequently.
1060         if(ht_bin[0]==-1) {
1061           ht_bin[1]=(int)head->addr;
1062           ht_bin[0]=vaddr;
1063         }else if(ht_bin[2]==-1) {
1064           ht_bin[3]=(int)head->addr;
1065           ht_bin[2]=vaddr;
1066         }
1067         return head->addr;
1068       }
1069     }
1070     head=head->next;
1071   }
1072   return 0;
1073 }
1074
1075 static void remove_hash(int vaddr)
1076 {
1077   //DebugMessage(M64MSG_VERBOSE, "remove hash: %x",vaddr);
1078   u_int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1079   if(ht_bin[2]==vaddr) {
1080     ht_bin[2]=ht_bin[3]=-1;
1081   }
1082   if(ht_bin[0]==vaddr) {
1083     ht_bin[0]=ht_bin[2];
1084     ht_bin[1]=ht_bin[3];
1085     ht_bin[2]=ht_bin[3]=-1;
1086   }
1087 }
1088
1089 static void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1090 {
1091   struct ll_entry *next;
1092   while(*head) {
1093     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1094        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1095     {
1096       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1097       remove_hash((*head)->vaddr);
1098       next=(*head)->next;
1099       free(*head);
1100       *head=next;
1101     }
1102     else
1103     {
1104       head=&((*head)->next);
1105     }
1106   }
1107 }
1108
1109 // Remove all entries from linked list
1110 static void ll_clear(struct ll_entry **head)
1111 {
1112   struct ll_entry *cur;
1113   struct ll_entry *next;
1114   if((cur=*head)) {
1115     *head=0;
1116     while(cur) {
1117       next=cur->next;
1118       free(cur);
1119       cur=next;
1120     }
1121   }
1122 }
1123
1124 // Dereference the pointers and remove if it matches
1125 static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1126 {
1127   while(head) {
1128     int ptr=get_pointer(head->addr);
1129     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1130     if(((ptr>>shift)==(addr>>shift)) ||
1131        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1132     {
1133       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1134       u_int host_addr=(int)kill_pointer(head->addr);
1135       #if NEW_DYNAREC == NEW_DYNAREC_ARM
1136         needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1137       #endif
1138     }
1139     head=head->next;
1140   }
1141 }
1142
1143 // This is called when we write to a compiled block (see do_invstub)
1144 static void invalidate_page(u_int page)
1145 {
1146   struct ll_entry *head;
1147   struct ll_entry *next;
1148   head=jump_in[page];
1149   jump_in[page]=0;
1150   while(head!=NULL) {
1151     inv_debug("INVALIDATE: %x\n",head->vaddr);
1152     remove_hash(head->vaddr);
1153     next=head->next;
1154     free(head);
1155     head=next;
1156   }
1157   head=jump_out[page];
1158   jump_out[page]=0;
1159   while(head!=NULL) {
1160     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1161     u_int host_addr=(int)kill_pointer(head->addr);
1162     #if NEW_DYNAREC == NEW_DYNAREC_ARM
1163       needs_clear_cache[(host_addr-(u_int)base_addr)>>17]|=1<<(((host_addr-(u_int)base_addr)>>12)&31);
1164     #endif
1165     next=head->next;
1166     free(head);
1167     head=next;
1168   }
1169 }
1170 void invalidate_block(u_int block)
1171 {
1172   u_int page,vpage;
1173   page=vpage=block^0x80000;
1174   if(page>262143&&tlb_LUT_r[block]) page=(tlb_LUT_r[block]^0x80000000)>>12;
1175   if(page>2048) page=2048+(page&2047);
1176   if(vpage>262143&&tlb_LUT_r[block]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
1177   if(vpage>2048) vpage=2048+(vpage&2047);
1178   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1179   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1180   u_int first,last;
1181   first=last=page;
1182   struct ll_entry *head;
1183   head=jump_dirty[vpage];
1184   //DebugMessage(M64MSG_VERBOSE, "page=%d vpage=%d",page,vpage);
1185   while(head!=NULL) {
1186     u_int start,end;
1187     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1188       get_bounds((int)head->addr,&start,&end);
1189       //DebugMessage(M64MSG_VERBOSE, "start: %x end: %x",start,end);
1190       if(page<2048&&start>=0x80000000&&end<0x80800000) {
1191         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1192           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1193           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1194         }
1195       }
1196       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1197         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1198           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1199           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1200         }
1201       }
1202     }
1203     head=head->next;
1204   }
1205   //DebugMessage(M64MSG_VERBOSE, "first=%d last=%d",first,last);
1206   invalidate_page(page);
1207   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1208   assert(last<page+5);
1209   // Invalidate the adjacent pages if a block crosses a 4K boundary
1210   while(first<page) {
1211     invalidate_page(first);
1212     first++;
1213   }
1214   for(first=page+1;first<last;first++) {
1215     invalidate_page(first);
1216   }
1217   #if NEW_DYNAREC == NEW_DYNAREC_ARM
1218     do_clear_cache();
1219   #endif
1220
1221   // Don't trap writes
1222   invalid_code[block]=1;
1223   // If there is a valid TLB entry for this page, remove write protect
1224   if(tlb_LUT_w[block]) {
1225     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1226     // CHECK: Is this right?
1227     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1228     u_int real_block=tlb_LUT_w[block]>>12;
1229     invalid_code[real_block]=1;
1230     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1231   }
1232   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1233   #ifdef USE_MINI_HT
1234   memset(mini_ht,-1,sizeof(mini_ht));
1235   #endif
1236 }
1237
1238 #if NEW_DYNAREC == NEW_DYNAREC_ARM
1239 static void invalidate_addr(u_int addr)
1240 {
1241   invalidate_block(addr>>12);
1242 }
1243 #endif
1244
1245 // This is called when loading a save state.
1246 // Anything could have changed, so invalidate everything.
1247 void invalidate_all_pages()
1248 {
1249   u_int page;
1250   for(page=0;page<4096;page++)
1251     invalidate_page(page);
1252   for(page=0;page<1048576;page++)
1253     if(!invalid_code[page]) {
1254       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1255       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1256     }
1257   #if NEW_DYNAREC == NEW_DYNAREC_ARM
1258   __clear_cache((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2));
1259   //cacheflush((void *)base_addr,(void *)base_addr+(1<<TARGET_SIZE_2),0);
1260   #endif
1261   #ifdef USE_MINI_HT
1262   memset(mini_ht,-1,sizeof(mini_ht));
1263   #endif
1264   // TLB
1265   for(page=0;page<0x100000;page++) {
1266     if(tlb_LUT_r[page]) {
1267       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1268       if(!tlb_LUT_w[page]||!invalid_code[page])
1269         memory_map[page]|=0x40000000; // Write protect
1270     }
1271     else memory_map[page]=-1;
1272     if(page==0x80000) page=0xC0000;
1273   }
1274   tlb_hacks();
1275 }
1276
1277 // Add an entry to jump_out after making a link
1278 void add_link(u_int vaddr,void *src)
1279 {
1280   u_int page=(vaddr^0x80000000)>>12;
1281   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
1282   if(page>4095) page=2048+(page&2047);
1283   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1284   ll_add(jump_out+page,vaddr,src);
1285   //int ptr=get_pointer(src);
1286   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1287 }
1288
1289 // If a code block was found to be unmodified (bit was set in
1290 // restore_candidate) and it remains unmodified (bit is clear
1291 // in invalid_code) then move the entries for that 4K page from
1292 // the dirty list to the clean list.
1293 void clean_blocks(u_int page)
1294 {
1295   struct ll_entry *head;
1296   inv_debug("INV: clean_blocks page=%d\n",page);
1297   head=jump_dirty[page];
1298   while(head!=NULL) {
1299     if(!invalid_code[head->vaddr>>12]) {
1300       // Don't restore blocks which are about to expire from the cache
1301       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1302         u_int start,end;
1303         if(verify_dirty(head->addr)) {
1304           //DebugMessage(M64MSG_VERBOSE, "Possibly Restore %x (%x)",head->vaddr, (int)head->addr);
1305           u_int i;
1306           u_int inv=0;
1307           get_bounds((int)head->addr,&start,&end);
1308           if(start-(u_int)rdram<0x800000) {
1309             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1310               inv|=invalid_code[i];
1311             }
1312           }
1313           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1314             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1315             //DebugMessage(M64MSG_VERBOSE, "addr=%x start=%x end=%x",addr,start,end);
1316             if(addr<start||addr>=end) inv=1;
1317           }
1318           else if((signed int)head->vaddr>=(signed int)0x80800000) {
1319             inv=1;
1320           }
1321           if(!inv) {
1322             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1323             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1324               u_int ppage=page;
1325               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1326               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1327               //DebugMessage(M64MSG_VERBOSE, "page=%x, addr=%x",page,head->vaddr);
1328               //assert(head->vaddr>>12==(page|0x80000));
1329               ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1330               u_int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1331               if(!head->reg32) {
1332                 if(ht_bin[0]==head->vaddr) {
1333                   ht_bin[1]=(int)clean_addr; // Replace existing entry
1334                 }
1335                 if(ht_bin[2]==head->vaddr) {
1336                   ht_bin[3]=(int)clean_addr; // Replace existing entry
1337                 }
1338               }
1339             }
1340           }
1341         }
1342       }
1343     }
1344     head=head->next;
1345   }
1346 }
1347
1348
1349 static void mov_alloc(struct regstat *current,int i)
1350 {
1351   // Note: Don't need to actually alloc the source registers
1352   if((~current->is32>>rs1[i])&1) {
1353     //alloc_reg64(current,i,rs1[i]);
1354     alloc_reg64(current,i,rt1[i]);
1355     current->is32&=~(1LL<<rt1[i]);
1356   } else {
1357     //alloc_reg(current,i,rs1[i]);
1358     alloc_reg(current,i,rt1[i]);
1359     current->is32|=(1LL<<rt1[i]);
1360   }
1361   clear_const(current,rs1[i]);
1362   clear_const(current,rt1[i]);
1363   dirty_reg(current,rt1[i]);
1364 }
1365
1366 static void shiftimm_alloc(struct regstat *current,int i)
1367 {
1368   clear_const(current,rs1[i]);
1369   clear_const(current,rt1[i]);
1370   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1371   {
1372     if(rt1[i]) {
1373       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1374       else lt1[i]=rs1[i];
1375       alloc_reg(current,i,rt1[i]);
1376       current->is32|=1LL<<rt1[i];
1377       dirty_reg(current,rt1[i]);
1378     }
1379   }
1380   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1381   {
1382     if(rt1[i]) {
1383       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1384       alloc_reg64(current,i,rt1[i]);
1385       current->is32&=~(1LL<<rt1[i]);
1386       dirty_reg(current,rt1[i]);
1387     }
1388   }
1389   if(opcode2[i]==0x3c) // DSLL32
1390   {
1391     if(rt1[i]) {
1392       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1393       alloc_reg64(current,i,rt1[i]);
1394       current->is32&=~(1LL<<rt1[i]);
1395       dirty_reg(current,rt1[i]);
1396     }
1397   }
1398   if(opcode2[i]==0x3e) // DSRL32
1399   {
1400     if(rt1[i]) {
1401       alloc_reg64(current,i,rs1[i]);
1402       if(imm[i]==32) {
1403         alloc_reg64(current,i,rt1[i]);
1404         current->is32&=~(1LL<<rt1[i]);
1405       } else {
1406         alloc_reg(current,i,rt1[i]);
1407         current->is32|=1LL<<rt1[i];
1408       }
1409       dirty_reg(current,rt1[i]);
1410     }
1411   }
1412   if(opcode2[i]==0x3f) // DSRA32
1413   {
1414     if(rt1[i]) {
1415       alloc_reg64(current,i,rs1[i]);
1416       alloc_reg(current,i,rt1[i]);
1417       current->is32|=1LL<<rt1[i];
1418       dirty_reg(current,rt1[i]);
1419     }
1420   }
1421 }
1422
1423 static void shift_alloc(struct regstat *current,int i)
1424 {
1425   if(rt1[i]) {
1426     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1427     {
1428       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1429       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1430       alloc_reg(current,i,rt1[i]);
1431       if(rt1[i]==rs2[i]) {
1432         alloc_reg_temp(current,i,-1);
1433         minimum_free_regs[i]=1;
1434       }
1435       current->is32|=1LL<<rt1[i];
1436     } else { // DSLLV/DSRLV/DSRAV
1437       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1438       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1439       alloc_reg64(current,i,rt1[i]);
1440       current->is32&=~(1LL<<rt1[i]);
1441       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1442       {
1443         alloc_reg_temp(current,i,-1);
1444         minimum_free_regs[i]=1;
1445       }
1446     }
1447     clear_const(current,rs1[i]);
1448     clear_const(current,rs2[i]);
1449     clear_const(current,rt1[i]);
1450     dirty_reg(current,rt1[i]);
1451   }
1452 }
1453
1454 static void alu_alloc(struct regstat *current,int i)
1455 {
1456   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1457     if(rt1[i]) {
1458       if(rs1[i]&&rs2[i]) {
1459         alloc_reg(current,i,rs1[i]);
1460         alloc_reg(current,i,rs2[i]);
1461       }
1462       else {
1463         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1464         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1465       }
1466       alloc_reg(current,i,rt1[i]);
1467     }
1468     current->is32|=1LL<<rt1[i];
1469   }
1470   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1471     if(rt1[i]) {
1472       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1473       {
1474         alloc_reg64(current,i,rs1[i]);
1475         alloc_reg64(current,i,rs2[i]);
1476         alloc_reg(current,i,rt1[i]);
1477       } else {
1478         alloc_reg(current,i,rs1[i]);
1479         alloc_reg(current,i,rs2[i]);
1480         alloc_reg(current,i,rt1[i]);
1481       }
1482     }
1483     current->is32|=1LL<<rt1[i];
1484   }
1485   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1486     if(rt1[i]) {
1487       if(rs1[i]&&rs2[i]) {
1488         alloc_reg(current,i,rs1[i]);
1489         alloc_reg(current,i,rs2[i]);
1490       }
1491       else
1492       {
1493         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1494         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1495       }
1496       alloc_reg(current,i,rt1[i]);
1497       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1498       {
1499         if(!((current->uu>>rt1[i])&1)) {
1500           alloc_reg64(current,i,rt1[i]);
1501         }
1502         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1503           if(rs1[i]&&rs2[i]) {
1504             alloc_reg64(current,i,rs1[i]);
1505             alloc_reg64(current,i,rs2[i]);
1506           }
1507           else
1508           {
1509             // Is is really worth it to keep 64-bit values in registers?
1510             #ifdef NATIVE_64BIT
1511             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1512             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1513             #endif
1514           }
1515         }
1516         current->is32&=~(1LL<<rt1[i]);
1517       } else {
1518         current->is32|=1LL<<rt1[i];
1519       }
1520     }
1521   }
1522   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1523     if(rt1[i]) {
1524       if(rs1[i]&&rs2[i]) {
1525         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1526           alloc_reg64(current,i,rs1[i]);
1527           alloc_reg64(current,i,rs2[i]);
1528           alloc_reg64(current,i,rt1[i]);
1529         } else {
1530           alloc_reg(current,i,rs1[i]);
1531           alloc_reg(current,i,rs2[i]);
1532           alloc_reg(current,i,rt1[i]);
1533         }
1534       }
1535       else {
1536         alloc_reg(current,i,rt1[i]);
1537         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1538           // DADD used as move, or zeroing
1539           // If we have a 64-bit source, then make the target 64 bits too
1540           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1541             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1542             alloc_reg64(current,i,rt1[i]);
1543           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1544             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1545             alloc_reg64(current,i,rt1[i]);
1546           }
1547           if(opcode2[i]>=0x2e&&rs2[i]) {
1548             // DSUB used as negation - 64-bit result
1549             // If we have a 32-bit register, extend it to 64 bits
1550             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1551             alloc_reg64(current,i,rt1[i]);
1552           }
1553         }
1554       }
1555       if(rs1[i]&&rs2[i]) {
1556         current->is32&=~(1LL<<rt1[i]);
1557       } else if(rs1[i]) {
1558         current->is32&=~(1LL<<rt1[i]);
1559         if((current->is32>>rs1[i])&1)
1560           current->is32|=1LL<<rt1[i];
1561       } else if(rs2[i]) {
1562         current->is32&=~(1LL<<rt1[i]);
1563         if((current->is32>>rs2[i])&1)
1564           current->is32|=1LL<<rt1[i];
1565       } else {
1566         current->is32|=1LL<<rt1[i];
1567       }
1568     }
1569   }
1570   clear_const(current,rs1[i]);
1571   clear_const(current,rs2[i]);
1572   clear_const(current,rt1[i]);
1573   dirty_reg(current,rt1[i]);
1574 }
1575
1576 static void imm16_alloc(struct regstat *current,int i)
1577 {
1578   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1579   else lt1[i]=rs1[i];
1580   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1581   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1582     current->is32&=~(1LL<<rt1[i]);
1583     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584       // TODO: Could preserve the 32-bit flag if the immediate is zero
1585       alloc_reg64(current,i,rt1[i]);
1586       alloc_reg64(current,i,rs1[i]);
1587     }
1588     clear_const(current,rs1[i]);
1589     clear_const(current,rt1[i]);
1590   }
1591   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1592     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1593     current->is32|=1LL<<rt1[i];
1594     clear_const(current,rs1[i]);
1595     clear_const(current,rt1[i]);
1596   }
1597   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1598     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1599       if(rs1[i]!=rt1[i]) {
1600         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1601         alloc_reg64(current,i,rt1[i]);
1602         current->is32&=~(1LL<<rt1[i]);
1603       }
1604     }
1605     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1606     if(is_const(current,rs1[i])) {
1607       int v=get_const(current,rs1[i]);
1608       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1609       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1610       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1611     }
1612     else clear_const(current,rt1[i]);
1613   }
1614   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1615     if(is_const(current,rs1[i])) {
1616       int v=get_const(current,rs1[i]);
1617       set_const(current,rt1[i],v+imm[i]);
1618     }
1619     else clear_const(current,rt1[i]);
1620     current->is32|=1LL<<rt1[i];
1621   }
1622   else {
1623     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1624     current->is32|=1LL<<rt1[i];
1625   }
1626   dirty_reg(current,rt1[i]);
1627 }
1628
1629 static void load_alloc(struct regstat *current,int i)
1630 {
1631   clear_const(current,rt1[i]);
1632   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1633   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1634   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1635   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1636     alloc_reg(current,i,rt1[i]);
1637     assert(get_reg(current->regmap,rt1[i])>=0);
1638     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1639     {
1640       current->is32&=~(1LL<<rt1[i]);
1641       alloc_reg64(current,i,rt1[i]);
1642     }
1643     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1644     {
1645       current->is32&=~(1LL<<rt1[i]);
1646       alloc_reg64(current,i,rt1[i]);
1647       alloc_all(current,i);
1648       alloc_reg64(current,i,FTEMP);
1649       minimum_free_regs[i]=HOST_REGS;
1650     }
1651     else current->is32|=1LL<<rt1[i];
1652     dirty_reg(current,rt1[i]);
1653     // If using TLB, need a register for pointer to the mapping table
1654     if(using_tlb) alloc_reg(current,i,TLREG);
1655     // LWL/LWR need a temporary register for the old value
1656     if(opcode[i]==0x22||opcode[i]==0x26)
1657     {
1658       alloc_reg(current,i,FTEMP);
1659       alloc_reg_temp(current,i,-1);
1660       minimum_free_regs[i]=1;
1661     }
1662   }
1663   else
1664   {
1665     // Load to r0 or unneeded register (dummy load)
1666     // but we still need a register to calculate the address
1667     if(opcode[i]==0x22||opcode[i]==0x26)
1668     {
1669       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1670     }
1671     // If using TLB, need a register for pointer to the mapping table
1672     if(using_tlb) alloc_reg(current,i,TLREG);
1673     alloc_reg_temp(current,i,-1);
1674     minimum_free_regs[i]=1;
1675     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1676     {
1677       alloc_all(current,i);
1678       alloc_reg64(current,i,FTEMP);
1679       minimum_free_regs[i]=HOST_REGS;
1680     }
1681   }
1682 }
1683
1684 static void store_alloc(struct regstat *current,int i)
1685 {
1686   clear_const(current,rs2[i]);
1687   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1688   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1689   alloc_reg(current,i,rs2[i]);
1690   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1691     alloc_reg64(current,i,rs2[i]);
1692     if(rs2[i]) alloc_reg(current,i,FTEMP);
1693   }
1694   // If using TLB, need a register for pointer to the mapping table
1695   if(using_tlb) alloc_reg(current,i,TLREG);
1696   #if defined(HOST_IMM8)
1697   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1698   else alloc_reg(current,i,INVCP);
1699   #endif
1700   if(opcode[i]==0x2c||opcode[i]==0x2d) { // 64-bit SDL/SDR
1701     alloc_reg(current,i,FTEMP);
1702   }
1703   // We need a temporary register for address generation
1704   alloc_reg_temp(current,i,-1);
1705   minimum_free_regs[i]=1;
1706 }
1707
1708 static void c1ls_alloc(struct regstat *current,int i)
1709 {
1710   //clear_const(current,rs1[i]); // FIXME
1711   clear_const(current,rt1[i]);
1712   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1713   alloc_reg(current,i,CSREG); // Status
1714   alloc_reg(current,i,FTEMP);
1715   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1716     alloc_reg64(current,i,FTEMP);
1717   }
1718   // If using TLB, need a register for pointer to the mapping table
1719   if(using_tlb) alloc_reg(current,i,TLREG);
1720   #if defined(HOST_IMM8)
1721   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1722   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1723     alloc_reg(current,i,INVCP);
1724   #endif
1725   // We need a temporary register for address generation
1726   alloc_reg_temp(current,i,-1);
1727   minimum_free_regs[i]=1;
1728 }
1729
1730 #ifndef multdiv_alloc
1731 void multdiv_alloc(struct regstat *current,int i)
1732 {
1733   //  case 0x18: MULT
1734   //  case 0x19: MULTU
1735   //  case 0x1A: DIV
1736   //  case 0x1B: DIVU
1737   //  case 0x1C: DMULT
1738   //  case 0x1D: DMULTU
1739   //  case 0x1E: DDIV
1740   //  case 0x1F: DDIVU
1741   clear_const(current,rs1[i]);
1742   clear_const(current,rs2[i]);
1743   if(rs1[i]&&rs2[i])
1744   {
1745     if((opcode2[i]&4)==0) // 32-bit
1746     {
1747       current->u&=~(1LL<<HIREG);
1748       current->u&=~(1LL<<LOREG);
1749       alloc_reg(current,i,HIREG);
1750       alloc_reg(current,i,LOREG);
1751       alloc_reg(current,i,rs1[i]);
1752       alloc_reg(current,i,rs2[i]);
1753       current->is32|=1LL<<HIREG;
1754       current->is32|=1LL<<LOREG;
1755       dirty_reg(current,HIREG);
1756       dirty_reg(current,LOREG);
1757     }
1758     else // 64-bit
1759     {
1760       current->u&=~(1LL<<HIREG);
1761       current->u&=~(1LL<<LOREG);
1762       current->uu&=~(1LL<<HIREG);
1763       current->uu&=~(1LL<<LOREG);
1764       alloc_reg64(current,i,HIREG);
1765           alloc_reg64(current,i,LOREG);
1766       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);  //*SEB* Why commenting this line? uncommenting make SM64 freeze after title (before mario head and spinning stars)
1767       alloc_reg64(current,i,rs1[i]);
1768       alloc_reg64(current,i,rs2[i]);
1769       alloc_all(current,i);
1770       current->is32&=~(1LL<<HIREG);
1771       current->is32&=~(1LL<<LOREG);
1772       dirty_reg(current,HIREG);
1773       dirty_reg(current,LOREG);
1774       minimum_free_regs[i]=HOST_REGS;
1775     }
1776   }
1777   else
1778   {
1779     // Multiply by zero is zero.
1780     // MIPS does not have a divide by zero exception.
1781     // The result is undefined, we return zero.
1782         if((opcode2[i]&4)==0) // 32-bit
1783         {
1784                 alloc_reg(current,i,HIREG);
1785                 alloc_reg(current,i,LOREG);
1786                 current->is32|=1LL<<HIREG;
1787                 current->is32|=1LL<<LOREG;
1788         } else {
1789                 alloc_reg64(current,i,HIREG);
1790                 alloc_reg64(current,i,LOREG);
1791                 current->is32&=~(1LL<<HIREG);
1792                 current->is32&=~(1LL<<LOREG);
1793         }
1794         dirty_reg(current,HIREG);
1795         dirty_reg(current,LOREG);
1796   }
1797 }
1798 #endif
1799
1800 static void cop0_alloc(struct regstat *current,int i)
1801 {
1802   if(opcode2[i]==0) // MFC0
1803   {
1804     if(rt1[i]) {
1805       clear_const(current,rt1[i]);
1806       alloc_all(current,i);
1807       alloc_reg(current,i,rt1[i]);
1808       current->is32|=1LL<<rt1[i];
1809       dirty_reg(current,rt1[i]);
1810     }
1811   }
1812   else if(opcode2[i]==4) // MTC0
1813   {
1814     if(rs1[i]){
1815       clear_const(current,rs1[i]);
1816       alloc_reg(current,i,rs1[i]);
1817       alloc_all(current,i);
1818     }
1819     else {
1820       alloc_all(current,i); // FIXME: Keep r0
1821       current->u&=~1LL;
1822       alloc_reg(current,i,0);
1823     }
1824   }
1825   else
1826   {
1827     // TLBR/TLBWI/TLBWR/TLBP/ERET
1828     assert(opcode2[i]==0x10);
1829     alloc_all(current,i);
1830   }
1831   minimum_free_regs[i]=HOST_REGS;
1832 }
1833
1834 static void cop1_alloc(struct regstat *current,int i)
1835 {
1836   alloc_reg(current,i,CSREG); // Load status
1837   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1838   {
1839     assert(rt1[i]);
1840     clear_const(current,rt1[i]);
1841     if(opcode2[i]==1) {
1842       alloc_reg64(current,i,rt1[i]); // DMFC1
1843       current->is32&=~(1LL<<rt1[i]);
1844     }else{
1845       alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1846       current->is32|=1LL<<rt1[i];
1847     }
1848     dirty_reg(current,rt1[i]);
1849     alloc_reg_temp(current,i,-1);
1850   }
1851   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1852   {
1853     if(rs1[i]){
1854       clear_const(current,rs1[i]);
1855       if(opcode2[i]==5)
1856         alloc_reg64(current,i,rs1[i]); // DMTC1
1857       else
1858         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1859       alloc_reg_temp(current,i,-1);
1860     }
1861     else {
1862       current->u&=~1LL;
1863       alloc_reg(current,i,0);
1864       alloc_reg_temp(current,i,-1);
1865     }
1866   }
1867   minimum_free_regs[i]=1;
1868 }
1869 static void fconv_alloc(struct regstat *current,int i)
1870 {
1871   alloc_reg(current,i,CSREG); // Load status
1872   alloc_reg_temp(current,i,-1);
1873   minimum_free_regs[i]=1;
1874 }
1875 static void float_alloc(struct regstat *current,int i)
1876 {
1877   alloc_reg(current,i,CSREG); // Load status
1878   alloc_reg_temp(current,i,-1);
1879   minimum_free_regs[i]=1;
1880 }
1881 static void fcomp_alloc(struct regstat *current,int i)
1882 {
1883   alloc_reg(current,i,CSREG); // Load status
1884   alloc_reg(current,i,FSREG); // Load flags
1885   dirty_reg(current,FSREG); // Flag will be modified
1886   alloc_reg_temp(current,i,-1);
1887   minimum_free_regs[i]=1;
1888 }
1889
1890 static void syscall_alloc(struct regstat *current,int i)
1891 {
1892   alloc_cc(current,i);
1893   dirty_reg(current,CCREG);
1894   alloc_all(current,i);
1895   minimum_free_regs[i]=HOST_REGS;
1896   current->isconst=0;
1897 }
1898
1899 static void delayslot_alloc(struct regstat *current,int i)
1900 {
1901   switch(itype[i]) {
1902     case UJUMP:
1903     case CJUMP:
1904     case SJUMP:
1905     case RJUMP:
1906     case FJUMP:
1907     case SYSCALL:
1908     case SPAN:
1909       assem_debug("jump in the delay slot.  this shouldn't happen.");//exit(1);
1910       DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
1911       stop_after_jal=1;
1912       break;
1913     case IMM16:
1914       imm16_alloc(current,i);
1915       break;
1916     case LOAD:
1917     case LOADLR:
1918       load_alloc(current,i);
1919       break;
1920     case STORE:
1921     case STORELR:
1922       store_alloc(current,i);
1923       break;
1924     case ALU:
1925       alu_alloc(current,i);
1926       break;
1927     case SHIFT:
1928       shift_alloc(current,i);
1929       break;
1930     case MULTDIV:
1931       multdiv_alloc(current,i);
1932       break;
1933     case SHIFTIMM:
1934       shiftimm_alloc(current,i);
1935       break;
1936     case MOV:
1937       mov_alloc(current,i);
1938       break;
1939     case COP0:
1940       cop0_alloc(current,i);
1941       break;
1942     case COP1:
1943       cop1_alloc(current,i);
1944       break;
1945     case C1LS:
1946       c1ls_alloc(current,i);
1947       break;
1948     case FCONV:
1949       fconv_alloc(current,i);
1950       break;
1951     case FLOAT:
1952       float_alloc(current,i);
1953       break;
1954     case FCOMP:
1955       fcomp_alloc(current,i);
1956       break;
1957   }
1958 }
1959
1960 // Special case where a branch and delay slot span two pages in virtual memory
1961 static void pagespan_alloc(struct regstat *current,int i)
1962 {
1963   current->isconst=0;
1964   current->wasconst=0;
1965   regs[i].wasconst=0;
1966   minimum_free_regs[i]=HOST_REGS;
1967   alloc_all(current,i);
1968   alloc_cc(current,i);
1969   dirty_reg(current,CCREG);
1970   if(opcode[i]==3) // JAL
1971   {
1972     alloc_reg(current,i,31);
1973     dirty_reg(current,31);
1974   }
1975   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1976   {
1977     alloc_reg(current,i,rs1[i]);
1978     if (rt1[i]!=0) {
1979       alloc_reg(current,i,rt1[i]);
1980       dirty_reg(current,rt1[i]);
1981     }
1982   }
1983   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1984   {
1985     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1986     if(rs2[i]) alloc_reg(current,i,rs2[i]);
1987     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1988     {
1989       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1990       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1991     }
1992   }
1993   else
1994   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1995   {
1996     if(rs1[i]) alloc_reg(current,i,rs1[i]);
1997     if(!((current->is32>>rs1[i])&1))
1998     {
1999       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2000     }
2001   }
2002   else
2003   if(opcode[i]==0x11) // BC1
2004   {
2005     alloc_reg(current,i,FSREG);
2006     alloc_reg(current,i,CSREG);
2007   }
2008   //else ...
2009 }
2010
2011 static void add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2012 {
2013   stubs[stubcount][0]=type;
2014   stubs[stubcount][1]=addr;
2015   stubs[stubcount][2]=retaddr;
2016   stubs[stubcount][3]=a;
2017   stubs[stubcount][4]=b;
2018   stubs[stubcount][5]=c;
2019   stubs[stubcount][6]=d;
2020   stubs[stubcount][7]=e;
2021   stubcount++;
2022 }
2023
2024 // Write out a single register
2025 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2026 {
2027   int hr;
2028   for(hr=0;hr<HOST_REGS;hr++) {
2029     if(hr!=EXCLUDE_REG) {
2030       if((regmap[hr]&63)==r) {
2031         if((dirty>>hr)&1) {
2032           if(regmap[hr]<64) {
2033             emit_storereg(r,hr);
2034             if((is32>>regmap[hr])&1) {
2035               emit_sarimm(hr,31,hr);
2036               emit_storereg(r|64,hr);
2037             }
2038           }else{
2039             emit_storereg(r|64,hr);
2040           }
2041         }
2042       }
2043     }
2044   }
2045 }
2046 #if 0
2047 static int mchecksum()
2048 {
2049   //if(!tracedebug) return 0;
2050   int i;
2051   int sum=0;
2052   for(i=0;i<2097152;i++) {
2053     unsigned int temp=sum;
2054     sum<<=1;
2055     sum|=(~temp)>>31;
2056     sum^=((u_int *)rdram)[i];
2057   }
2058   return sum;
2059 }
2060
2061 static int rchecksum()
2062 {
2063   int i;
2064   int sum=0;
2065   for(i=0;i<64;i++)
2066     sum^=((u_int *)reg)[i];
2067   return sum;
2068 }
2069
2070 static void rlist()
2071 {
2072   int i;
2073   DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2074   for(i=0;i<32;i++)
2075     DebugMessage(M64MSG_VERBOSE, "r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2076   DebugMessage(M64MSG_VERBOSE, "TRACE: ");
2077   for(i=0;i<32;i++)
2078     DebugMessage(M64MSG_VERBOSE, "f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2079 }
2080
2081 static void enabletrace()
2082 {
2083   tracedebug=1;
2084 }
2085
2086
2087 static void memdebug(int i)
2088 {
2089   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) lo=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2090   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (rchecksum %x)",Count,next_interupt,rchecksum());
2091   //rlist();
2092   //if(tracedebug) {
2093   //if(Count>=-2084597794) {
2094   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2095   //if(0) {
2096     DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
2097     //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) Status=%x",Count,next_interupt,mchecksum(),Status);
2098     //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x) hi=%8x%8x",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2099     rlist();
2100     #if NEW_DYNAREC == NEW_DYNAREC_X86
2101     DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2102     #endif
2103     #if NEW_DYNAREC == NEW_DYNAREC_ARM
2104     int j;
2105     DebugMessage(M64MSG_VERBOSE, "TRACE: %x ",(&j)[10]);
2106     DebugMessage(M64MSG_VERBOSE, "TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2107     #endif
2108     //fflush(stdout);
2109   }
2110   //DebugMessage(M64MSG_VERBOSE, "TRACE: %x",(&i)[-1]);
2111 }
2112 #endif
2113
2114 /* Debug:
2115 static void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2116 {
2117   DebugMessage(M64MSG_VERBOSE, "TLB Exception: instruction=%x addr=%x cause=%x",iaddr, addr, cause);
2118 }
2119 end debug */
2120
2121 static void alu_assemble(int i,struct regstat *i_regs)
2122 {
2123   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2124     if(rt1[i]) {
2125       signed char s1,s2,t;
2126       t=get_reg(i_regs->regmap,rt1[i]);
2127       if(t>=0) {
2128         s1=get_reg(i_regs->regmap,rs1[i]);
2129         s2=get_reg(i_regs->regmap,rs2[i]);
2130         if(rs1[i]&&rs2[i]) {
2131           assert(s1>=0);
2132           assert(s2>=0);
2133           if(opcode2[i]&2) emit_sub(s1,s2,t);
2134           else emit_add(s1,s2,t);
2135         }
2136         else if(rs1[i]) {
2137           if(s1>=0) emit_mov(s1,t);
2138           else emit_loadreg(rs1[i],t);
2139         }
2140         else if(rs2[i]) {
2141           if(s2>=0) {
2142             if(opcode2[i]&2) emit_neg(s2,t);
2143             else emit_mov(s2,t);
2144           }
2145           else {
2146             emit_loadreg(rs2[i],t);
2147             if(opcode2[i]&2) emit_neg(t,t);
2148           }
2149         }
2150         else emit_zeroreg(t);
2151       }
2152     }
2153   }
2154   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2155     if(rt1[i]) {
2156       signed char s1l,s2l,s1h,s2h,tl,th;
2157       tl=get_reg(i_regs->regmap,rt1[i]);
2158       th=get_reg(i_regs->regmap,rt1[i]|64);
2159       if(tl>=0) {
2160         s1l=get_reg(i_regs->regmap,rs1[i]);
2161         s2l=get_reg(i_regs->regmap,rs2[i]);
2162         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2163         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2164         if(rs1[i]&&rs2[i]) {
2165           assert(s1l>=0);
2166           assert(s2l>=0);
2167           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2168           else emit_adds(s1l,s2l,tl);
2169           if(th>=0) {
2170             #ifdef INVERTED_CARRY
2171             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2172             #else
2173             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2174             #endif
2175             else emit_add(s1h,s2h,th);
2176           }
2177         }
2178         else if(rs1[i]) {
2179           if(s1l>=0) emit_mov(s1l,tl);
2180           else emit_loadreg(rs1[i],tl);
2181           if(th>=0) {
2182             if(s1h>=0) emit_mov(s1h,th);
2183             else emit_loadreg(rs1[i]|64,th);
2184           }
2185         }
2186         else if(rs2[i]) {
2187           if(s2l>=0) {
2188             if(opcode2[i]&2) emit_negs(s2l,tl);
2189             else emit_mov(s2l,tl);
2190           }
2191           else {
2192             emit_loadreg(rs2[i],tl);
2193             if(opcode2[i]&2) emit_negs(tl,tl);
2194           }
2195           if(th>=0) {
2196             #ifdef INVERTED_CARRY
2197             if(s2h>=0) emit_mov(s2h,th);
2198             else emit_loadreg(rs2[i]|64,th);
2199             if(opcode2[i]&2) {
2200               emit_adcimm(-1,th); // x86 has inverted carry flag
2201               emit_not(th,th);
2202             }
2203             #else
2204             if(opcode2[i]&2) {
2205               if(s2h>=0) emit_rscimm(s2h,0,th);
2206               else {
2207                 emit_loadreg(rs2[i]|64,th);
2208                 emit_rscimm(th,0,th);
2209               }
2210             }else{
2211               if(s2h>=0) emit_mov(s2h,th);
2212               else emit_loadreg(rs2[i]|64,th);
2213             }
2214             #endif
2215           }
2216         }
2217         else {
2218           emit_zeroreg(tl);
2219           if(th>=0) emit_zeroreg(th);
2220         }
2221       }
2222     }
2223   }
2224   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2225     if(rt1[i]) {
2226       signed char s1l,s1h,s2l,s2h,t;
2227       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2228       {
2229         t=get_reg(i_regs->regmap,rt1[i]);
2230         //assert(t>=0);
2231         if(t>=0) {
2232           s1l=get_reg(i_regs->regmap,rs1[i]);
2233           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2234           s2l=get_reg(i_regs->regmap,rs2[i]);
2235           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2236           if(rs2[i]==0) // rx<r0
2237           {
2238             assert(s1h>=0);
2239             if(opcode2[i]==0x2a) // SLT
2240               emit_shrimm(s1h,31,t);
2241             else // SLTU (unsigned can not be less than zero)
2242               emit_zeroreg(t);
2243           }
2244           else if(rs1[i]==0) // r0<rx
2245           {
2246             assert(s2h>=0);
2247             if(opcode2[i]==0x2a) // SLT
2248               emit_set_gz64_32(s2h,s2l,t);
2249             else // SLTU (set if not zero)
2250               emit_set_nz64_32(s2h,s2l,t);
2251           }
2252           else {
2253             assert(s1l>=0);assert(s1h>=0);
2254             assert(s2l>=0);assert(s2h>=0);
2255             if(opcode2[i]==0x2a) // SLT
2256               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2257             else // SLTU
2258               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2259           }
2260         }
2261       } else {
2262         t=get_reg(i_regs->regmap,rt1[i]);
2263         //assert(t>=0);
2264         if(t>=0) {
2265           s1l=get_reg(i_regs->regmap,rs1[i]);
2266           s2l=get_reg(i_regs->regmap,rs2[i]);
2267           if(rs2[i]==0) // rx<r0
2268           {
2269             assert(s1l>=0);
2270             if(opcode2[i]==0x2a) // SLT
2271               emit_shrimm(s1l,31,t);
2272             else // SLTU (unsigned can not be less than zero)
2273               emit_zeroreg(t);
2274           }
2275           else if(rs1[i]==0) // r0<rx
2276           {
2277             assert(s2l>=0);
2278             if(opcode2[i]==0x2a) // SLT
2279               emit_set_gz32(s2l,t);
2280             else // SLTU (set if not zero)
2281               emit_set_nz32(s2l,t);
2282           }
2283           else{
2284             assert(s1l>=0);assert(s2l>=0);
2285             if(opcode2[i]==0x2a) // SLT
2286               emit_set_if_less32(s1l,s2l,t);
2287             else // SLTU
2288               emit_set_if_carry32(s1l,s2l,t);
2289           }
2290         }
2291       }
2292     }
2293   }
2294   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2295     if(rt1[i]) {
2296       signed char s1l,s1h,s2l,s2h,th,tl;
2297       tl=get_reg(i_regs->regmap,rt1[i]);
2298       th=get_reg(i_regs->regmap,rt1[i]|64);
2299       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2300       {
2301         assert(tl>=0);
2302         if(tl>=0) {
2303           s1l=get_reg(i_regs->regmap,rs1[i]);
2304           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2305           s2l=get_reg(i_regs->regmap,rs2[i]);
2306           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2307           if(rs1[i]&&rs2[i]) {
2308             assert(s1l>=0);assert(s1h>=0);
2309             assert(s2l>=0);assert(s2h>=0);
2310             if(opcode2[i]==0x24) { // AND
2311               emit_and(s1l,s2l,tl);
2312               emit_and(s1h,s2h,th);
2313             } else
2314             if(opcode2[i]==0x25) { // OR
2315               emit_or(s1l,s2l,tl);
2316               emit_or(s1h,s2h,th);
2317             } else
2318             if(opcode2[i]==0x26) { // XOR
2319               emit_xor(s1l,s2l,tl);
2320               emit_xor(s1h,s2h,th);
2321             } else
2322             if(opcode2[i]==0x27) { // NOR
2323               emit_or(s1l,s2l,tl);
2324               emit_or(s1h,s2h,th);
2325               emit_not(tl,tl);
2326               emit_not(th,th);
2327             }
2328           }
2329           else
2330           {
2331             if(opcode2[i]==0x24) { // AND
2332               emit_zeroreg(tl);
2333               emit_zeroreg(th);
2334             } else
2335             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2336               if(rs1[i]){
2337                 if(s1l>=0) emit_mov(s1l,tl);
2338                 else emit_loadreg(rs1[i],tl);
2339                 if(s1h>=0) emit_mov(s1h,th);
2340                 else emit_loadreg(rs1[i]|64,th);
2341               }
2342               else
2343               if(rs2[i]){
2344                 if(s2l>=0) emit_mov(s2l,tl);
2345                 else emit_loadreg(rs2[i],tl);
2346                 if(s2h>=0) emit_mov(s2h,th);
2347                 else emit_loadreg(rs2[i]|64,th);
2348               }
2349               else{
2350                 emit_zeroreg(tl);
2351                 emit_zeroreg(th);
2352               }
2353             } else
2354             if(opcode2[i]==0x27) { // NOR
2355               if(rs1[i]){
2356                 if(s1l>=0) emit_not(s1l,tl);
2357                 else{
2358                   emit_loadreg(rs1[i],tl);
2359                   emit_not(tl,tl);
2360                 }
2361                 if(s1h>=0) emit_not(s1h,th);
2362                 else{
2363                   emit_loadreg(rs1[i]|64,th);
2364                   emit_not(th,th);
2365                 }
2366               }
2367               else
2368               if(rs2[i]){
2369                 if(s2l>=0) emit_not(s2l,tl);
2370                 else{
2371                   emit_loadreg(rs2[i],tl);
2372                   emit_not(tl,tl);
2373                 }
2374                 if(s2h>=0) emit_not(s2h,th);
2375                 else{
2376                   emit_loadreg(rs2[i]|64,th);
2377                   emit_not(th,th);
2378                 }
2379               }
2380               else {
2381                 emit_movimm(-1,tl);
2382                 emit_movimm(-1,th);
2383               }
2384             }
2385           }
2386         }
2387       }
2388       else
2389       {
2390         // 32 bit
2391         if(tl>=0) {
2392           s1l=get_reg(i_regs->regmap,rs1[i]);
2393           s2l=get_reg(i_regs->regmap,rs2[i]);
2394           if(rs1[i]&&rs2[i]) {
2395             assert(s1l>=0);
2396             assert(s2l>=0);
2397             if(opcode2[i]==0x24) { // AND
2398               emit_and(s1l,s2l,tl);
2399             } else
2400             if(opcode2[i]==0x25) { // OR
2401               emit_or(s1l,s2l,tl);
2402             } else
2403             if(opcode2[i]==0x26) { // XOR
2404               emit_xor(s1l,s2l,tl);
2405             } else
2406             if(opcode2[i]==0x27) { // NOR
2407               emit_or(s1l,s2l,tl);
2408               emit_not(tl,tl);
2409             }
2410           }
2411           else
2412           {
2413             if(opcode2[i]==0x24) { // AND
2414               emit_zeroreg(tl);
2415             } else
2416             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2417               if(rs1[i]){
2418                 if(s1l>=0) emit_mov(s1l,tl);
2419                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2420               }
2421               else
2422               if(rs2[i]){
2423                 if(s2l>=0) emit_mov(s2l,tl);
2424                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2425               }
2426               else emit_zeroreg(tl);
2427             } else
2428             if(opcode2[i]==0x27) { // NOR
2429               if(rs1[i]){
2430                 if(s1l>=0) emit_not(s1l,tl);
2431                 else {
2432                   emit_loadreg(rs1[i],tl);
2433                   emit_not(tl,tl);
2434                 }
2435               }
2436               else
2437               if(rs2[i]){
2438                 if(s2l>=0) emit_not(s2l,tl);
2439                 else {
2440                   emit_loadreg(rs2[i],tl);
2441                   emit_not(tl,tl);
2442                 }
2443               }
2444               else emit_movimm(-1,tl);
2445             }
2446           }
2447         }
2448       }
2449     }
2450   }
2451 }
2452
2453 static void imm16_assemble(int i,struct regstat *i_regs)
2454 {
2455   if (opcode[i]==0x0f) { // LUI
2456     if(rt1[i]) {
2457       signed char t;
2458       t=get_reg(i_regs->regmap,rt1[i]);
2459       //assert(t>=0);
2460       if(t>=0) {
2461         if(!((i_regs->isconst>>t)&1))
2462           emit_movimm(imm[i]<<16,t);
2463       }
2464     }
2465   }
2466   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2467     if(rt1[i]) {
2468       signed char s,t;
2469       t=get_reg(i_regs->regmap,rt1[i]);
2470       s=get_reg(i_regs->regmap,rs1[i]);
2471       if(rs1[i]) {
2472         //assert(t>=0);
2473         //assert(s>=0);
2474         if(t>=0) {
2475           if(!((i_regs->isconst>>t)&1)) {
2476             if(s<0) {
2477               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2478               emit_addimm(t,imm[i],t);
2479             }else{
2480               if(!((i_regs->wasconst>>s)&1))
2481                 emit_addimm(s,imm[i],t);
2482               else
2483                 emit_movimm(constmap[i][s]+imm[i],t);
2484             }
2485           }
2486         }
2487       } else {
2488         if(t>=0) {
2489           if(!((i_regs->isconst>>t)&1))
2490             emit_movimm(imm[i],t);
2491         }
2492       }
2493     }
2494   }
2495   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2496     if(rt1[i]) {
2497       signed char sh,sl,th,tl;
2498       th=get_reg(i_regs->regmap,rt1[i]|64);
2499       tl=get_reg(i_regs->regmap,rt1[i]);
2500       sh=get_reg(i_regs->regmap,rs1[i]|64);
2501       sl=get_reg(i_regs->regmap,rs1[i]);
2502       if(tl>=0) {
2503         if(rs1[i]) {
2504           assert(sh>=0);
2505           assert(sl>=0);
2506           if(th>=0) {
2507             emit_addimm64_32(sh,sl,imm[i],th,tl);
2508           }
2509           else {
2510             emit_addimm(sl,imm[i],tl);
2511           }
2512         } else {
2513           emit_movimm(imm[i],tl);
2514           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2515         }
2516       }
2517     }
2518   }
2519   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2520     if(rt1[i]) {
2521       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2522       signed char sh,sl,t;
2523       t=get_reg(i_regs->regmap,rt1[i]);
2524       sh=get_reg(i_regs->regmap,rs1[i]|64);
2525       sl=get_reg(i_regs->regmap,rs1[i]);
2526       //assert(t>=0);
2527       if(t>=0) {
2528         if(rs1[i]>0) {
2529           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2530           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2531             if(opcode[i]==0x0a) { // SLTI
2532               if(sl<0) {
2533                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2534                 emit_slti32(t,imm[i],t);
2535               }else{
2536                 emit_slti32(sl,imm[i],t);
2537               }
2538             }
2539             else { // SLTIU
2540               if(sl<0) {
2541                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2542                 emit_sltiu32(t,imm[i],t);
2543               }else{
2544                 emit_sltiu32(sl,imm[i],t);
2545               }
2546             }
2547           }else{ // 64-bit
2548             assert(sl>=0);
2549             if(opcode[i]==0x0a) // SLTI
2550               emit_slti64_32(sh,sl,imm[i],t);
2551             else // SLTIU
2552               emit_sltiu64_32(sh,sl,imm[i],t);
2553           }
2554         }else{
2555           // SLTI(U) with r0 is just stupid,
2556           // nonetheless examples can be found
2557           if(opcode[i]==0x0a) // SLTI
2558             if(0<imm[i]) emit_movimm(1,t);
2559             else emit_zeroreg(t);
2560           else // SLTIU
2561           {
2562             if(imm[i]) emit_movimm(1,t);
2563             else emit_zeroreg(t);
2564           }
2565         }
2566       }
2567     }
2568   }
2569   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2570     if(rt1[i]) {
2571       signed char sh,sl,th,tl;
2572       th=get_reg(i_regs->regmap,rt1[i]|64);
2573       tl=get_reg(i_regs->regmap,rt1[i]);
2574       sh=get_reg(i_regs->regmap,rs1[i]|64);
2575       sl=get_reg(i_regs->regmap,rs1[i]);
2576       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2577         if(opcode[i]==0x0c) //ANDI
2578         {
2579           if(rs1[i]) {
2580             if(sl<0) {
2581               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2582               emit_andimm(tl,imm[i],tl);
2583             }else{
2584               if(!((i_regs->wasconst>>sl)&1))
2585                 emit_andimm(sl,imm[i],tl);
2586               else
2587                 emit_movimm(constmap[i][sl]&imm[i],tl);
2588             }
2589           }
2590           else
2591             emit_zeroreg(tl);
2592           if(th>=0) emit_zeroreg(th);
2593         }
2594         else
2595         {
2596           if(rs1[i]) {
2597             if(sl<0) {
2598               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2599             }
2600             if(th>=0) {
2601               if(sh<0) {
2602                 emit_loadreg(rs1[i]|64,th);
2603               }else{
2604                 emit_mov(sh,th);
2605               }
2606             }
2607             if(opcode[i]==0x0d) { //ORI
2608             if(sl<0) {
2609               emit_orimm(tl,imm[i],tl);
2610             }else{
2611               if(!((i_regs->wasconst>>sl)&1))
2612                 emit_orimm(sl,imm[i],tl);
2613               else
2614                 emit_movimm(constmap[i][sl]|imm[i],tl);
2615             }
2616             }
2617             if(opcode[i]==0x0e) { //XORI
2618             if(sl<0) {
2619               emit_xorimm(tl,imm[i],tl);
2620             }else{
2621               if(!((i_regs->wasconst>>sl)&1))
2622                 emit_xorimm(sl,imm[i],tl);
2623               else
2624                 emit_movimm(constmap[i][sl]^imm[i],tl);
2625             }
2626             }
2627           }
2628           else {
2629             emit_movimm(imm[i],tl);
2630             if(th>=0) emit_zeroreg(th);
2631           }
2632         }
2633       }
2634     }
2635   }
2636 }
2637
2638 static void shiftimm_assemble(int i,struct regstat *i_regs)
2639 {
2640   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2641   {
2642     if(rt1[i]) {
2643       signed char s,t;
2644       t=get_reg(i_regs->regmap,rt1[i]);
2645       s=get_reg(i_regs->regmap,rs1[i]);
2646       //assert(t>=0);
2647       if(t>=0){
2648         if(rs1[i]==0)
2649         {
2650           emit_zeroreg(t);
2651         }
2652         else
2653         {
2654           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2655           if(imm[i]) {
2656             if(opcode2[i]==0) // SLL
2657             {
2658               emit_shlimm(s<0?t:s,imm[i],t);
2659             }
2660             if(opcode2[i]==2) // SRL
2661             {
2662               emit_shrimm(s<0?t:s,imm[i],t);
2663             }
2664             if(opcode2[i]==3) // SRA
2665             {
2666               emit_sarimm(s<0?t:s,imm[i],t);
2667             }
2668           }else{
2669             // Shift by zero
2670             if(s>=0 && s!=t) emit_mov(s,t);
2671           }
2672         }
2673       }
2674       //emit_storereg(rt1[i],t); //DEBUG
2675     }
2676   }
2677   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2678   {
2679     if(rt1[i]) {
2680       signed char sh,sl,th,tl;
2681       th=get_reg(i_regs->regmap,rt1[i]|64);
2682       tl=get_reg(i_regs->regmap,rt1[i]);
2683       sh=get_reg(i_regs->regmap,rs1[i]|64);
2684       sl=get_reg(i_regs->regmap,rs1[i]);
2685       if(tl>=0) {
2686         if(rs1[i]==0)
2687         {
2688           emit_zeroreg(tl);
2689           if(th>=0) emit_zeroreg(th);
2690         }
2691         else
2692         {
2693           assert(sl>=0);
2694           assert(sh>=0);
2695           if(imm[i]) {
2696             if(opcode2[i]==0x38) // DSLL
2697             {
2698               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2699               emit_shlimm(sl,imm[i],tl);
2700             }
2701             if(opcode2[i]==0x3a) // DSRL
2702             {
2703               emit_shrdimm(sl,sh,imm[i],tl);
2704               if(th>=0) emit_shrimm(sh,imm[i],th);
2705             }
2706             if(opcode2[i]==0x3b) // DSRA
2707             {
2708               emit_shrdimm(sl,sh,imm[i],tl);
2709               if(th>=0) emit_sarimm(sh,imm[i],th);
2710             }
2711           }else{
2712             // Shift by zero
2713             if(sl!=tl) emit_mov(sl,tl);
2714             if(th>=0&&sh!=th) emit_mov(sh,th);
2715           }
2716         }
2717       }
2718     }
2719   }
2720   if(opcode2[i]==0x3c) // DSLL32
2721   {
2722     if(rt1[i]) {
2723       signed char sl,tl,th;
2724       tl=get_reg(i_regs->regmap,rt1[i]);
2725       th=get_reg(i_regs->regmap,rt1[i]|64);
2726       sl=get_reg(i_regs->regmap,rs1[i]);
2727       if(th>=0||tl>=0){
2728         assert(tl>=0);
2729         assert(th>=0);
2730         assert(sl>=0);
2731         emit_mov(sl,th);
2732         emit_zeroreg(tl);
2733         if(imm[i]>32)
2734         {
2735           emit_shlimm(th,imm[i]&31,th);
2736         }
2737       }
2738     }
2739   }
2740   if(opcode2[i]==0x3e) // DSRL32
2741   {
2742     if(rt1[i]) {
2743       signed char sh,tl,th;
2744       tl=get_reg(i_regs->regmap,rt1[i]);
2745       th=get_reg(i_regs->regmap,rt1[i]|64);
2746       sh=get_reg(i_regs->regmap,rs1[i]|64);
2747       if(tl>=0){
2748         assert(sh>=0);
2749         emit_mov(sh,tl);
2750         if(th>=0) emit_zeroreg(th);
2751         if(imm[i]>32)
2752         {
2753           emit_shrimm(tl,imm[i]&31,tl);
2754         }
2755       }
2756     }
2757   }
2758   if(opcode2[i]==0x3f) // DSRA32
2759   {
2760     if(rt1[i]) {
2761       signed char sh,tl;
2762       tl=get_reg(i_regs->regmap,rt1[i]);
2763       sh=get_reg(i_regs->regmap,rs1[i]|64);
2764       if(tl>=0){
2765         assert(sh>=0);
2766         emit_mov(sh,tl);
2767         if(imm[i]>32)
2768         {
2769           emit_sarimm(tl,imm[i]&31,tl);
2770         }
2771       }
2772     }
2773   }
2774 }
2775
2776 #ifndef shift_assemble
2777 void shift_assemble(int i,struct regstat *i_regs)
2778 {
2779   DebugMessage(M64MSG_ERROR, "Need shift_assemble for this architecture.");
2780   exit(1);
2781 }
2782 #endif
2783
2784 static void load_assemble(int i,struct regstat *i_regs)
2785 {
2786   int s,th,tl,addr,map=-1,cache=-1;
2787   int offset;
2788   int jaddr=0;
2789   int memtarget,c=0;
2790   u_int hr,reglist=0;
2791   th=get_reg(i_regs->regmap,rt1[i]|64);
2792   tl=get_reg(i_regs->regmap,rt1[i]);
2793   s=get_reg(i_regs->regmap,rs1[i]);
2794   offset=imm[i];
2795   for(hr=0;hr<HOST_REGS;hr++) {
2796     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2797   }
2798   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2799   if(s>=0) {
2800     c=(i_regs->wasconst>>s)&1;
2801     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
2802     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2803   }
2804   if(tl<0) tl=get_reg(i_regs->regmap,-1);
2805   if(offset||s<0||c) addr=tl;
2806   else addr=s;
2807   //DebugMessage(M64MSG_VERBOSE, "load_assemble: c=%d",c);
2808   //if(c) DebugMessage(M64MSG_VERBOSE, "load_assemble: const=%x",(int)constmap[i][s]+offset);
2809   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2810   reglist&=~(1<<tl);
2811   if(th>=0) reglist&=~(1<<th);
2812   if(!using_tlb) {
2813     if(!c) {
2814       #ifdef RAM_OFFSET
2815       map=get_reg(i_regs->regmap,ROREG);
2816       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2817       #endif
2818 //#define R29_HACK 1
2819       #ifdef R29_HACK
2820       // Strmnnrmn's speed hack
2821       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
2822       #endif
2823       {
2824         emit_cmpimm(addr,0x800000);
2825         jaddr=(int)out;
2826         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2827         // Hint to branch predictor that the branch is unlikely to be taken
2828         if(rs1[i]>=28)
2829           emit_jno_unlikely(0);
2830         else
2831         #endif
2832         emit_jno(0);
2833       }
2834     }
2835   }else{ // using tlb
2836     int x=0;
2837     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2838     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2839     map=get_reg(i_regs->regmap,TLREG);
2840     cache=get_reg(i_regs->regmap,MMREG);
2841     assert(map>=0);
2842     reglist&=~(1<<map);
2843     map=do_tlb_r(addr,tl,map,cache,x,-1,-1,c,constmap[i][s]+offset);
2844     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2845   }
2846   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2847   if (opcode[i]==0x20) { // LB
2848     if(!c||memtarget) {
2849       if(!dummy) {
2850         #ifdef HOST_IMM_ADDR32
2851         if(c)
2852           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2853         else
2854         #endif
2855         {
2856           //emit_xorimm(addr,3,tl);
2857           //gen_tlb_addr_r(tl,map);
2858           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2859           int x=0;
2860           if(!c) emit_xorimm(addr,3,tl);
2861           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2862           emit_movsbl_indexed_tlb(x,tl,map,tl);
2863         }
2864       }
2865       if(jaddr)
2866         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2867     }
2868     else
2869       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2870   }
2871   if (opcode[i]==0x21) { // LH
2872     if(!c||memtarget) {
2873       if(!dummy) {
2874         #ifdef HOST_IMM_ADDR32
2875         if(c)
2876           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2877         else
2878         #endif
2879         {
2880           int x=0;
2881           if(!c) emit_xorimm(addr,2,tl);
2882           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2883           //#ifdef
2884           //emit_movswl_indexed_tlb(x,tl,map,tl);
2885           //else
2886           if(map>=0) {
2887             gen_tlb_addr_r(tl,map);
2888             emit_movswl_indexed(x,tl,tl);
2889           }else{
2890             #ifdef RAM_OFFSET
2891             emit_movswl_indexed(x,tl,tl);
2892             #else
2893             emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2894             #endif
2895           }
2896         }
2897       }
2898       if(jaddr)
2899         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2900     }
2901     else
2902       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903   }
2904   if (opcode[i]==0x23) { // LW
2905     if(!c||memtarget) {
2906       if(!dummy) {
2907         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2908         #ifdef HOST_IMM_ADDR32
2909         if(c)
2910           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2911         else
2912         #endif
2913         emit_readword_indexed_tlb(0,addr,map,tl);
2914       }
2915       if(jaddr)
2916         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2917     }
2918     else
2919       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2920   }
2921   if (opcode[i]==0x24) { // LBU
2922     if(!c||memtarget) {
2923       if(!dummy) {
2924         #ifdef HOST_IMM_ADDR32
2925         if(c)
2926           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2927         else
2928         #endif
2929         {
2930           //emit_xorimm(addr,3,tl);
2931           //gen_tlb_addr_r(tl,map);
2932           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2933           int x=0;
2934           if(!c) emit_xorimm(addr,3,tl);
2935           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2936           emit_movzbl_indexed_tlb(x,tl,map,tl);
2937         }
2938       }
2939       if(jaddr)
2940         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2941     }
2942     else
2943       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2944   }
2945   if (opcode[i]==0x25) { // LHU
2946     if(!c||memtarget) {
2947       if(!dummy) {
2948         #ifdef HOST_IMM_ADDR32
2949         if(c)
2950           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2951         else
2952         #endif
2953         {
2954           int x=0;
2955           if(!c) emit_xorimm(addr,2,tl);
2956           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2957           //#ifdef
2958           //emit_movzwl_indexed_tlb(x,tl,map,tl);
2959           //#else
2960           if(map>=0) {
2961             gen_tlb_addr_r(tl,map);
2962             emit_movzwl_indexed(x,tl,tl);
2963           }else{
2964             #ifdef RAM_OFFSET
2965             emit_movzwl_indexed(x,tl,tl);
2966             #else
2967             emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2968             #endif
2969           }
2970         }
2971       }
2972       if(jaddr)
2973         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2974     }
2975     else
2976       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2977   }
2978   if (opcode[i]==0x27) { // LWU
2979     assert(th>=0);
2980     if(!c||memtarget) {
2981       if(!dummy) {
2982         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2983         #ifdef HOST_IMM_ADDR32
2984         if(c)
2985           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2986         else
2987         #endif
2988         emit_readword_indexed_tlb(0,addr,map,tl);
2989       }
2990       if(jaddr)
2991         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2992     }
2993     else {
2994       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2995     }
2996     emit_zeroreg(th);
2997   }
2998   if (opcode[i]==0x37) { // LD
2999     if(!c||memtarget) {
3000       if(!dummy) {
3001         //gen_tlb_addr_r(tl,map);
3002         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3003         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3004         #ifdef HOST_IMM_ADDR32
3005         if(c)
3006           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3007         else
3008         #endif
3009         emit_readdword_indexed_tlb(0,addr,map,th,tl);
3010       }
3011       if(jaddr)
3012         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3013     }
3014     else
3015       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3016   }
3017   //emit_storereg(rt1[i],tl); // DEBUG
3018   //if(opcode[i]==0x23)
3019   //if(opcode[i]==0x24)
3020   //if(opcode[i]==0x23||opcode[i]==0x24)
3021   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3022   {
3023     //emit_pusha();
3024     save_regs(0x100f);
3025         emit_readword((int)&last_count,ECX);
3026         #if NEW_DYNAREC == NEW_DYNAREC_X86
3027         if(get_reg(i_regs->regmap,CCREG)<0)
3028           emit_loadreg(CCREG,HOST_CCREG);
3029         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3030         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3031         emit_writeword(HOST_CCREG,(int)&Count);
3032         #endif
3033         #if NEW_DYNAREC == NEW_DYNAREC_ARM
3034         if(get_reg(i_regs->regmap,CCREG)<0)
3035           emit_loadreg(CCREG,0);
3036         else
3037           emit_mov(HOST_CCREG,0);
3038         emit_add(0,ECX,0);
3039         emit_addimm(0,2*ccadj[i],0);
3040         emit_writeword(0,(int)&Count);
3041         #endif
3042     emit_call((int)memdebug);
3043     //emit_popa();
3044     restore_regs(0x100f);
3045   }*/
3046 }
3047
3048 #ifndef loadlr_assemble
3049 static void loadlr_assemble(int i,struct regstat *i_regs)
3050 {
3051   DebugMessage(M64MSG_ERROR, "Need loadlr_assemble for this architecture.");
3052   exit(1);
3053 }
3054 #endif
3055
3056 static void store_assemble(int i,struct regstat *i_regs)
3057 {
3058   int s,th,tl,map=-1,cache=-1;
3059   int addr,temp;
3060   int offset;
3061   int jaddr=0,jaddr2,type;
3062   int memtarget,c=0;
3063   int agr=AGEN1+(i&1);
3064   u_int hr,reglist=0;
3065   th=get_reg(i_regs->regmap,rs2[i]|64);
3066   tl=get_reg(i_regs->regmap,rs2[i]);
3067   s=get_reg(i_regs->regmap,rs1[i]);
3068   temp=get_reg(i_regs->regmap,agr);
3069   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3070   offset=imm[i];
3071   if(s>=0) {
3072     c=(i_regs->wasconst>>s)&1;
3073     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3074     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3075   }
3076   assert(tl>=0);
3077   assert(temp>=0);
3078   for(hr=0;hr<HOST_REGS;hr++) {
3079     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3080   }
3081   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3082   if(offset||s<0||c) addr=temp;
3083   else addr=s;
3084   if(!using_tlb) {
3085     #ifdef RAM_OFFSET
3086     map=get_reg(i_regs->regmap,ROREG);
3087     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3088     #endif
3089     if(!c) {
3090       #ifdef R29_HACK
3091       // Strmnnrmn's speed hack
3092       memtarget=1;
3093       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3094       #endif
3095       emit_cmpimm(addr,0x800000);
3096       #ifdef DESTRUCTIVE_SHIFT
3097       if(s==addr) emit_mov(s,temp);
3098       #endif
3099       #ifdef R29_HACK
3100       if(rs1[i]!=29||start<0x80001000||start>=0x80800000)
3101       #endif
3102       {
3103         jaddr=(int)out;
3104         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3105         // Hint to branch predictor that the branch is unlikely to be taken
3106         if(rs1[i]>=28)
3107           emit_jno_unlikely(0);
3108         else
3109         #endif
3110         emit_jno(0);
3111       }
3112     }
3113   }else{ // using tlb
3114     int x=0;
3115     if (opcode[i]==0x28) x=3; // SB
3116     if (opcode[i]==0x29) x=2; // SH
3117     map=get_reg(i_regs->regmap,TLREG);
3118     cache=get_reg(i_regs->regmap,MMREG);
3119     assert(map>=0);
3120     reglist&=~(1<<map);
3121     map=do_tlb_w(addr,temp,map,cache,x,c,constmap[i][s]+offset);
3122     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3123   }
3124
3125   if (opcode[i]==0x28) { // SB
3126     if(!c||memtarget) {
3127       int x=0;
3128       if(!c) emit_xorimm(addr,3,temp);
3129       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3130       //gen_tlb_addr_w(temp,map);
3131       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3132       emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3133     }
3134     type=STOREB_STUB;
3135   }
3136   if (opcode[i]==0x29) { // SH
3137     if(!c||memtarget) {
3138       int x=0;
3139       if(!c) emit_xorimm(addr,2,temp);
3140       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3141       //#ifdef
3142       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3143       //#else
3144       if(map>=0) {
3145         gen_tlb_addr_w(temp,map);
3146         emit_writehword_indexed(tl,x,temp);
3147       }else
3148         emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3149     }
3150     type=STOREH_STUB;
3151   }
3152   if (opcode[i]==0x2B) { // SW
3153     if(!c||memtarget)
3154       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3155       emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3156     type=STOREW_STUB;
3157   }
3158   if (opcode[i]==0x3F) { // SD
3159     if(!c||memtarget) {
3160       if(rs2[i]) {
3161         assert(th>=0);
3162         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3163         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3164         emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3165       }else{
3166         // Store zero
3167         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3168         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3169         emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3170       }
3171     }
3172     type=STORED_STUB;
3173   }
3174   if(!using_tlb) {
3175     if(!c||memtarget) {
3176       #ifdef DESTRUCTIVE_SHIFT
3177       // The x86 shift operation is 'destructive'; it overwrites the
3178       // source register, so we need to make a copy first and use that.
3179       addr=temp;
3180       #endif
3181       #if defined(HOST_IMM8)
3182       int ir=get_reg(i_regs->regmap,INVCP);
3183       assert(ir>=0);
3184       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3185       #else
3186       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3187       #endif
3188       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3189       emit_callne(invalidate_addr_reg[addr]);
3190       #else
3191       jaddr2=(int)out;
3192       emit_jne(0);
3193       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3194       #endif
3195     }
3196   }
3197   if(jaddr) {
3198     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3199   } else if(c&&!memtarget) {
3200     inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3201   }
3202   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3203   //if(opcode[i]==0x2B || opcode[i]==0x28)
3204   //if(opcode[i]==0x2B || opcode[i]==0x29)
3205   //if(opcode[i]==0x2B)
3206
3207 // Uncomment for extra debug output:
3208 /*
3209   if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3210   {
3211     #if NEW_DYNAREC == NEW_DYNAREC_X86
3212     emit_pusha();
3213     #endif
3214     #if NEW_DYNAREC == NEW_DYNAREC_ARM
3215     save_regs(0x100f);
3216     #endif
3217         emit_readword((int)&last_count,ECX);
3218         #if NEW_DYNAREC == NEW_DYNAREC_X86
3219         if(get_reg(i_regs->regmap,CCREG)<0)
3220           emit_loadreg(CCREG,HOST_CCREG);
3221         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3222         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3223         emit_writeword(HOST_CCREG,(int)&Count);
3224         #endif
3225         #if NEW_DYNAREC == NEW_DYNAREC_ARM
3226         if(get_reg(i_regs->regmap,CCREG)<0)
3227           emit_loadreg(CCREG,0);
3228         else
3229           emit_mov(HOST_CCREG,0);
3230         emit_add(0,ECX,0);
3231         emit_addimm(0,2*ccadj[i],0);
3232         emit_writeword(0,(int)&Count);
3233         #endif
3234     emit_call((int)memdebug);
3235     #if NEW_DYNAREC == NEW_DYNAREC_X86
3236     emit_popa();
3237     #endif
3238     #if NEW_DYNAREC == NEW_DYNAREC_ARM
3239     restore_regs(0x100f);
3240     #endif
3241   }
3242 */
3243 }
3244
3245 static void storelr_assemble(int i,struct regstat *i_regs)
3246 {
3247   int s,th,tl;
3248   int temp;
3249   int temp2;
3250   int offset;
3251   int jaddr=0,jaddr2;
3252   int case1,case2,case3;
3253   int done0,done1,done2;
3254   int memtarget,c=0;
3255   int agr=AGEN1+(i&1);
3256   u_int hr,reglist=0;
3257   th=get_reg(i_regs->regmap,rs2[i]|64);
3258   tl=get_reg(i_regs->regmap,rs2[i]);
3259   s=get_reg(i_regs->regmap,rs1[i]);
3260   temp=get_reg(i_regs->regmap,agr);
3261   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3262   offset=imm[i];
3263   if(s>=0) {
3264     c=(i_regs->isconst>>s)&1;
3265     memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80800000;
3266     if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3267   }
3268   assert(tl>=0);
3269   for(hr=0;hr<HOST_REGS;hr++) {
3270     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3271   }
3272   assert(temp>=0);
3273   if(!using_tlb) {
3274     if(!c) {
3275       emit_cmpimm(s<0||offset?temp:s,0x800000);
3276       if(!offset&&s!=temp) emit_mov(s,temp);
3277       jaddr=(int)out;
3278       emit_jno(0);
3279     }
3280     else
3281     {
3282       if(!memtarget||!rs1[i]) {
3283         jaddr=(int)out;
3284         emit_jmp(0);
3285       }
3286     }
3287     #ifdef RAM_OFFSET
3288     int map=get_reg(i_regs->regmap,ROREG);
3289     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3290     gen_tlb_addr_w(temp,map);
3291     #else
3292     if((u_int)rdram!=0x80000000)
3293       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3294     #endif
3295   }else{ // using tlb
3296     int map=get_reg(i_regs->regmap,TLREG);
3297     int cache=get_reg(i_regs->regmap,MMREG);
3298     assert(map>=0);
3299     reglist&=~(1<<map);
3300     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,cache,0,c,constmap[i][s]+offset);
3301     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3302     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3303     if(!jaddr&&!memtarget) {
3304       jaddr=(int)out;
3305       emit_jmp(0);
3306     }
3307     gen_tlb_addr_w(temp,map);
3308   }
3309
3310   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3311     temp2=get_reg(i_regs->regmap,FTEMP);
3312     if(!rs2[i]) temp2=th=tl;
3313   }
3314
3315   emit_testimm(temp,2);
3316   case2=(int)out;
3317   emit_jne(0);
3318   emit_testimm(temp,1);
3319   case1=(int)out;
3320   emit_jne(0);
3321   // 0
3322   if (opcode[i]==0x2A) { // SWL
3323     emit_writeword_indexed(tl,0,temp);
3324   }
3325   if (opcode[i]==0x2E) { // SWR
3326     emit_writebyte_indexed(tl,3,temp);
3327   }
3328   if (opcode[i]==0x2C) { // SDL
3329     emit_writeword_indexed(th,0,temp);
3330     if(rs2[i]) emit_mov(tl,temp2);
3331   }
3332   if (opcode[i]==0x2D) { // SDR
3333     emit_writebyte_indexed(tl,3,temp);
3334     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3335   }
3336   done0=(int)out;
3337   emit_jmp(0);
3338   // 1
3339   set_jump_target(case1,(int)out);
3340   if (opcode[i]==0x2A) { // SWL
3341     // Write 3 msb into three least significant bytes
3342     if(rs2[i]) emit_rorimm(tl,8,tl);
3343     emit_writehword_indexed(tl,-1,temp);
3344     if(rs2[i]) emit_rorimm(tl,16,tl);
3345     emit_writebyte_indexed(tl,1,temp);
3346     if(rs2[i]) emit_rorimm(tl,8,tl);
3347   }
3348   if (opcode[i]==0x2E) { // SWR
3349     // Write two lsb into two most significant bytes
3350     emit_writehword_indexed(tl,1,temp);
3351   }
3352   if (opcode[i]==0x2C) { // SDL
3353     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3354     // Write 3 msb into three least significant bytes
3355     if(rs2[i]) emit_rorimm(th,8,th);
3356     emit_writehword_indexed(th,-1,temp);
3357     if(rs2[i]) emit_rorimm(th,16,th);
3358     emit_writebyte_indexed(th,1,temp);
3359     if(rs2[i]) emit_rorimm(th,8,th);
3360   }
3361   if (opcode[i]==0x2D) { // SDR
3362     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3363     // Write two lsb into two most significant bytes
3364     emit_writehword_indexed(tl,1,temp);
3365   }
3366   done1=(int)out;
3367   emit_jmp(0);
3368   // 2
3369   set_jump_target(case2,(int)out);
3370   emit_testimm(temp,1);
3371   case3=(int)out;
3372   emit_jne(0);
3373   if (opcode[i]==0x2A) { // SWL
3374     // Write two msb into two least significant bytes
3375     if(rs2[i]) emit_rorimm(tl,16,tl);
3376     emit_writehword_indexed(tl,-2,temp);
3377     if(rs2[i]) emit_rorimm(tl,16,tl);
3378   }
3379   if (opcode[i]==0x2E) { // SWR
3380     // Write 3 lsb into three most significant bytes
3381     emit_writebyte_indexed(tl,-1,temp);
3382     if(rs2[i]) emit_rorimm(tl,8,tl);
3383     emit_writehword_indexed(tl,0,temp);
3384     if(rs2[i]) emit_rorimm(tl,24,tl);
3385   }
3386   if (opcode[i]==0x2C) { // SDL
3387     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3388     // Write two msb into two least significant bytes
3389     if(rs2[i]) emit_rorimm(th,16,th);
3390     emit_writehword_indexed(th,-2,temp);
3391     if(rs2[i]) emit_rorimm(th,16,th);
3392   }
3393   if (opcode[i]==0x2D) { // SDR
3394     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3395     // Write 3 lsb into three most significant bytes
3396     emit_writebyte_indexed(tl,-1,temp);
3397     if(rs2[i]) emit_rorimm(tl,8,tl);
3398     emit_writehword_indexed(tl,0,temp);
3399     if(rs2[i]) emit_rorimm(tl,24,tl);
3400   }
3401   done2=(int)out;
3402   emit_jmp(0);
3403   // 3
3404   set_jump_target(case3,(int)out);
3405   if (opcode[i]==0x2A) { // SWL
3406     // Write msb into least significant byte
3407     if(rs2[i]) emit_rorimm(tl,24,tl);
3408     emit_writebyte_indexed(tl,-3,temp);
3409     if(rs2[i]) emit_rorimm(tl,8,tl);
3410   }
3411   if (opcode[i]==0x2E) { // SWR
3412     // Write entire word
3413     emit_writeword_indexed(tl,-3,temp);
3414   }
3415   if (opcode[i]==0x2C) { // SDL
3416     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3417     // Write msb into least significant byte
3418     if(rs2[i]) emit_rorimm(th,24,th);
3419     emit_writebyte_indexed(th,-3,temp);
3420     if(rs2[i]) emit_rorimm(th,8,th);
3421   }
3422   if (opcode[i]==0x2D) { // SDR
3423     if(rs2[i]) emit_mov(th,temp2);
3424     // Write entire word
3425     emit_writeword_indexed(tl,-3,temp);
3426   }
3427   set_jump_target(done0,(int)out);
3428   set_jump_target(done1,(int)out);
3429   set_jump_target(done2,(int)out);
3430   if (opcode[i]==0x2C) { // SDL
3431     emit_testimm(temp,4);
3432     done0=(int)out;
3433     emit_jne(0);
3434     emit_andimm(temp,~3,temp);
3435     emit_writeword_indexed(temp2,4,temp);
3436     set_jump_target(done0,(int)out);
3437   }
3438   if (opcode[i]==0x2D) { // SDR
3439     emit_testimm(temp,4);
3440     done0=(int)out;
3441     emit_jeq(0);
3442     emit_andimm(temp,~3,temp);
3443     emit_writeword_indexed(temp2,-4,temp);
3444     set_jump_target(done0,(int)out);
3445   }
3446   if(!c||!memtarget)
3447     add_stub(STORELR_STUB,jaddr,(int)out,0,(int)i_regs,rs2[i],ccadj[i],reglist);
3448   if(!using_tlb) {
3449     #ifdef RAM_OFFSET
3450     int map=get_reg(i_regs->regmap,ROREG);
3451     if(map<0) map=HOST_TEMPREG;
3452     gen_orig_addr_w(temp,map);
3453     #else
3454     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3455     #endif
3456     #if defined(HOST_IMM8)
3457     int ir=get_reg(i_regs->regmap,INVCP);
3458     assert(ir>=0);
3459     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3460     #else
3461     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3462     #endif
3463     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3464     emit_callne(invalidate_addr_reg[temp]);
3465     #else
3466     jaddr2=(int)out;
3467     emit_jne(0);
3468     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3469     #endif
3470   }
3471   /*
3472     emit_pusha();
3473     //save_regs(0x100f);
3474         emit_readword((int)&last_count,ECX);
3475         if(get_reg(i_regs->regmap,CCREG)<0)
3476           emit_loadreg(CCREG,HOST_CCREG);
3477         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3478         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3479         emit_writeword(HOST_CCREG,(int)&Count);
3480     emit_call((int)memdebug);
3481     emit_popa();
3482     //restore_regs(0x100f);
3483   */
3484 }
3485
3486 static void c1ls_assemble(int i,struct regstat *i_regs)
3487 {
3488   int s,th,tl;
3489   int temp,ar;
3490   int map=-1;
3491   int offset;
3492   int c=0;
3493   int jaddr,jaddr2=0,jaddr3,type;
3494   int agr=AGEN1+(i&1);
3495   u_int hr,reglist=0;
3496   th=get_reg(i_regs->regmap,FTEMP|64);
3497   tl=get_reg(i_regs->regmap,FTEMP);
3498   s=get_reg(i_regs->regmap,rs1[i]);
3499   temp=get_reg(i_regs->regmap,agr);
3500   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3501   offset=imm[i];
3502   assert(tl>=0);
3503   assert(rs1[i]>0);
3504   assert(temp>=0);
3505   for(hr=0;hr<HOST_REGS;hr++) {
3506     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3507   }
3508   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3509   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3510   {
3511     // Loads use a temporary register which we need to save
3512     reglist|=1<<temp;
3513   }
3514   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3515     ar=temp;
3516   else // LWC1/LDC1
3517     ar=tl;
3518   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3519   //else c=(i_regs->wasconst>>s)&1;
3520   if(s>=0) c=(i_regs->wasconst>>s)&1;
3521   // Check cop1 unusable
3522   if(!cop1_usable) {
3523     signed char rs=get_reg(i_regs->regmap,CSREG);
3524     assert(rs>=0);
3525     emit_testimm(rs,0x20000000);
3526     jaddr=(int)out;
3527     emit_jeq(0);
3528     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3529     cop1_usable=1;
3530   }
3531   if (opcode[i]==0x39) { // SWC1 (get float address)
3532     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3533   }
3534   if (opcode[i]==0x3D) { // SDC1 (get double address)
3535     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3536   }
3537   // Generate address + offset
3538   if(!using_tlb) {
3539     #ifdef RAM_OFFSET
3540     if (!c||opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3541     {
3542       map=get_reg(i_regs->regmap,ROREG);
3543       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3544     }
3545     #endif
3546     if(!c)
3547       emit_cmpimm(offset||c||s<0?ar:s,0x800000);
3548   }
3549   else
3550   {
3551     map=get_reg(i_regs->regmap,TLREG);
3552     int cache=get_reg(i_regs->regmap,MMREG);
3553     assert(map>=0);
3554     reglist&=~(1<<map);
3555     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3556       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,cache,0,-1,-1,c,constmap[i][s]+offset);
3557     }
3558     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3559       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,cache,0,c,constmap[i][s]+offset);
3560     }
3561   }
3562   if (opcode[i]==0x39) { // SWC1 (read float)
3563     emit_readword_indexed(0,tl,tl);
3564   }
3565   if (opcode[i]==0x3D) { // SDC1 (read double)
3566     emit_readword_indexed(4,tl,th);
3567     emit_readword_indexed(0,tl,tl);
3568   }
3569   if (opcode[i]==0x31) { // LWC1 (get target address)
3570     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3571   }
3572   if (opcode[i]==0x35) { // LDC1 (get target address)
3573     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3574   }
3575   if(!using_tlb) {
3576     if(!c) {
3577       jaddr2=(int)out;
3578       emit_jno(0);
3579     }
3580     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80800000) {
3581       jaddr2=(int)out;
3582       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3583     }
3584     #ifdef DESTRUCTIVE_SHIFT
3585     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3586       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3587     }
3588     #endif
3589   }else{
3590     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3591       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3592     }
3593     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3594       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3595     }
3596   }
3597   if (opcode[i]==0x31) { // LWC1
3598     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3599     //gen_tlb_addr_r(ar,map);
3600     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3601     #ifdef HOST_IMM_ADDR32
3602     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3603     else
3604     #endif
3605     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3606     type=LOADW_STUB;
3607   }
3608   if (opcode[i]==0x35) { // LDC1
3609     assert(th>=0);
3610     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3611     //gen_tlb_addr_r(ar,map);
3612     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3613     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3614     #ifdef HOST_IMM_ADDR32
3615     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3616     else
3617     #endif
3618     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3619     type=LOADD_STUB;
3620   }
3621   if (opcode[i]==0x39) { // SWC1
3622     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3623     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3624     type=STOREW_STUB;
3625   }
3626   if (opcode[i]==0x3D) { // SDC1
3627     assert(th>=0);
3628     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3629     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3630     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3631     type=STORED_STUB;
3632   }
3633   if(!using_tlb) {
3634     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3635       #ifndef DESTRUCTIVE_SHIFT
3636       temp=offset||c||s<0?ar:s;
3637       #endif
3638       #if defined(HOST_IMM8)
3639       int ir=get_reg(i_regs->regmap,INVCP);
3640       assert(ir>=0);
3641       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3642       #else
3643       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3644       #endif
3645       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3646       emit_callne(invalidate_addr_reg[temp]);
3647       #else
3648       jaddr3=(int)out;
3649       emit_jne(0);
3650       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3651       #endif
3652     }
3653   }
3654   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3655   if (opcode[i]==0x31) { // LWC1 (write float)
3656     emit_writeword_indexed(tl,0,temp);
3657   }
3658   if (opcode[i]==0x35) { // LDC1 (write double)
3659     emit_writeword_indexed(th,4,temp);
3660     emit_writeword_indexed(tl,0,temp);
3661   }
3662   //if(opcode[i]==0x39)
3663   /*if(opcode[i]==0x39||opcode[i]==0x31)
3664   {
3665     emit_pusha();
3666         emit_readword((int)&last_count,ECX);
3667         if(get_reg(i_regs->regmap,CCREG)<0)
3668           emit_loadreg(CCREG,HOST_CCREG);
3669         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3670         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3671         emit_writeword(HOST_CCREG,(int)&Count);
3672     emit_call((int)memdebug);
3673     emit_popa();
3674   }*/
3675 }
3676
3677 #ifndef multdiv_assemble
3678 void multdiv_assemble(int i,struct regstat *i_regs)
3679 {
3680   DebugMessage(M64MSG_ERROR, "Need multdiv_assemble for this architecture.");
3681   exit(1);
3682 }
3683 #endif
3684
3685 static void mov_assemble(int i,struct regstat *i_regs)
3686 {
3687   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3688   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3689   if(rt1[i]) {
3690     signed char sh,sl,th,tl;
3691     th=get_reg(i_regs->regmap,rt1[i]|64);
3692     tl=get_reg(i_regs->regmap,rt1[i]);
3693     //assert(tl>=0);
3694     if(tl>=0) {
3695       sh=get_reg(i_regs->regmap,rs1[i]|64);
3696       sl=get_reg(i_regs->regmap,rs1[i]);
3697       if(sl>=0) emit_mov(sl,tl);
3698       else emit_loadreg(rs1[i],tl);
3699       if(th>=0) {
3700         if(sh>=0) emit_mov(sh,th);
3701         else emit_loadreg(rs1[i]|64,th);
3702       }
3703     }
3704   }
3705 }
3706
3707 #ifndef fconv_assemble
3708 void fconv_assemble(int i,struct regstat *i_regs)
3709 {
3710   DebugMessage(M64MSG_ERROR, "Need fconv_assemble for this architecture.");
3711   exit(1);
3712 }
3713 #endif
3714
3715 #if 0
3716 static void float_assemble(int i,struct regstat *i_regs)
3717 {
3718   DebugMessage(M64MSG_ERROR, "Need float_assemble for this architecture.");
3719   exit(1);
3720 }
3721 #endif
3722
3723 static void syscall_assemble(int i,struct regstat *i_regs)
3724 {
3725   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3726   assert(ccreg==HOST_CCREG);
3727   assert(!is_delayslot);
3728   emit_movimm(start+i*4,EAX); // Get PC
3729   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3730   emit_jmp((int)jump_syscall);
3731 }
3732
3733 static void ds_assemble(int i,struct regstat *i_regs)
3734 {
3735   is_delayslot=1;
3736   switch(itype[i]) {
3737     case ALU:
3738       alu_assemble(i,i_regs);break;
3739     case IMM16:
3740       imm16_assemble(i,i_regs);break;
3741     case SHIFT:
3742       shift_assemble(i,i_regs);break;
3743     case SHIFTIMM:
3744       shiftimm_assemble(i,i_regs);break;
3745     case LOAD:
3746       load_assemble(i,i_regs);break;
3747     case LOADLR:
3748       loadlr_assemble(i,i_regs);break;
3749     case STORE:
3750       store_assemble(i,i_regs);break;
3751     case STORELR:
3752       storelr_assemble(i,i_regs);break;
3753     case COP0:
3754       cop0_assemble(i,i_regs);break;
3755     case COP1:
3756       cop1_assemble(i,i_regs);break;
3757     case C1LS:
3758       c1ls_assemble(i,i_regs);break;
3759     case FCONV:
3760       fconv_assemble(i,i_regs);break;
3761     case FLOAT:
3762       float_assemble(i,i_regs);break;
3763     case FCOMP:
3764       fcomp_assemble(i,i_regs);break;
3765     case MULTDIV:
3766       multdiv_assemble(i,i_regs);break;
3767     case MOV:
3768       mov_assemble(i,i_regs);break;
3769     case SYSCALL:
3770     case SPAN:
3771     case UJUMP:
3772     case RJUMP:
3773     case CJUMP:
3774     case SJUMP:
3775     case FJUMP:
3776       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
3777   }
3778   is_delayslot=0;
3779 }
3780
3781 // Is the branch target a valid internal jump?
3782 static int internal_branch(uint64_t i_is32,int addr)
3783 {
3784   if(addr&1) return 0; // Indirect (register) jump
3785   if(addr>=start && addr<start+slen*4-4)
3786   {
3787     int t=(addr-start)>>2;
3788     // Delay slots are not valid branch targets
3789     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3790     // 64 -> 32 bit transition requires a recompile
3791     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3792     {
3793       if(requires_32bit[t]&~i_is32) DebugMessage(M64MSG_VERBOSE, "optimizable: no");
3794       else DebugMessage(M64MSG_VERBOSE, "optimizable: yes");
3795     }*/
3796     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3797     if(requires_32bit[t]&~i_is32) return 0;
3798     else return 1;
3799   }
3800   return 0;
3801 }
3802
3803 #ifndef wb_invalidate
3804 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3805   uint64_t u,uint64_t uu)
3806 {
3807   int hr;
3808   for(hr=0;hr<HOST_REGS;hr++) {
3809     if(hr!=EXCLUDE_REG) {
3810       if(pre[hr]!=entry[hr]) {
3811         if(pre[hr]>=0) {
3812           if((dirty>>hr)&1) {
3813             if(get_reg(entry,pre[hr])<0) {
3814               if(pre[hr]<64) {
3815                 if(!((u>>pre[hr])&1)) {
3816                   emit_storereg(pre[hr],hr);
3817                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3818                     emit_sarimm(hr,31,hr);
3819                     emit_storereg(pre[hr]|64,hr);
3820                   }
3821                 }
3822               }else{
3823                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3824                   emit_storereg(pre[hr],hr);
3825                 }
3826               }
3827             }
3828           }
3829         }
3830       }
3831     }
3832   }
3833   // Move from one register to another (no writeback)
3834   for(hr=0;hr<HOST_REGS;hr++) {
3835     if(hr!=EXCLUDE_REG) {
3836       if(pre[hr]!=entry[hr]) {
3837         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3838           int nr;
3839           if((nr=get_reg(entry,pre[hr]))>=0) {
3840             emit_mov(hr,nr);
3841           }
3842         }
3843       }
3844     }
3845   }
3846 }
3847 #endif
3848
3849 // Load the specified registers
3850 // This only loads the registers given as arguments because
3851 // we don't want to load things that will be overwritten
3852 static void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3853 {
3854   int hr;
3855   // Load 32-bit regs
3856   for(hr=0;hr<HOST_REGS;hr++) {
3857     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3858       if(entry[hr]!=regmap[hr]) {
3859         if(regmap[hr]==rs1||regmap[hr]==rs2)
3860         {
3861           if(regmap[hr]==0) {
3862             emit_zeroreg(hr);
3863           }
3864           else
3865           {
3866             emit_loadreg(regmap[hr],hr);
3867           }
3868         }
3869       }
3870     }
3871   }
3872   //Load 64-bit regs
3873   for(hr=0;hr<HOST_REGS;hr++) {
3874     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
3875       if(entry[hr]!=regmap[hr]) {
3876         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3877         {
3878           assert(regmap[hr]!=64);
3879           if((is32>>(regmap[hr]&63))&1) {
3880             int lr=get_reg(regmap,regmap[hr]-64);
3881             if(lr>=0)
3882               emit_sarimm(lr,31,hr);
3883             else
3884               emit_loadreg(regmap[hr],hr);
3885           }
3886           else
3887           {
3888             emit_loadreg(regmap[hr],hr);
3889           }
3890         }
3891       }
3892     }
3893   }
3894 }
3895
3896 // Load registers prior to the start of a loop
3897 // so that they are not loaded within the loop
3898 static void loop_preload(signed char pre[],signed char entry[])
3899 {
3900   int hr;
3901   for(hr=0;hr<HOST_REGS;hr++) {
3902     if(hr!=EXCLUDE_REG) {
3903       if(pre[hr]!=entry[hr]) {
3904         if(entry[hr]>=0) {
3905           if(get_reg(pre,entry[hr])<0) {
3906             assem_debug("loop preload:");
3907             //DebugMessage(M64MSG_VERBOSE, "loop preload: %d",hr);
3908             if(entry[hr]==0) {
3909               emit_zeroreg(hr);
3910             }
3911             else if(entry[hr]<TEMPREG)
3912             {
3913               emit_loadreg(entry[hr],hr);
3914             }
3915             else if(entry[hr]-64<TEMPREG)
3916             {
3917               emit_loadreg(entry[hr],hr);
3918             }
3919           }
3920         }
3921       }
3922     }
3923   }
3924 }
3925
3926 // Generate address for load/store instruction
3927 static void address_generation(int i,struct regstat *i_regs,signed char entry[])
3928 {
3929   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
3930     int ra;
3931     int agr=AGEN1+(i&1);
3932     int mgr=MGEN1+(i&1);
3933     if(itype[i]==LOAD) {
3934       ra=get_reg(i_regs->regmap,rt1[i]);
3935       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3936       assert(ra>=0);
3937     }
3938     if(itype[i]==LOADLR) {
3939       ra=get_reg(i_regs->regmap,FTEMP);
3940     }
3941     if(itype[i]==STORE||itype[i]==STORELR) {
3942       ra=get_reg(i_regs->regmap,agr);
3943       if(ra<0) ra=get_reg(i_regs->regmap,-1);
3944     }
3945     if(itype[i]==C1LS) {
3946       if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3947         ra=get_reg(i_regs->regmap,FTEMP);
3948       else { // SWC1/SDC1
3949         ra=get_reg(i_regs->regmap,agr);
3950         if(ra<0) ra=get_reg(i_regs->regmap,-1);
3951       }
3952     }
3953     int rs=get_reg(i_regs->regmap,rs1[i]);
3954     int rm=get_reg(i_regs->regmap,TLREG);
3955     if(ra>=0) {
3956       int offset=imm[i];
3957       int c=(i_regs->wasconst>>rs)&1;
3958       if(rs1[i]==0) {
3959         // Using r0 as a base address
3960         /*if(rm>=0) {
3961           if(!entry||entry[rm]!=mgr) {
3962             generate_map_const(offset,rm);
3963           } // else did it in the previous cycle
3964         }*/
3965         if(!entry||entry[ra]!=agr) {
3966           if (opcode[i]==0x22||opcode[i]==0x26) {
3967             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3968           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3969             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3970           }else{
3971             emit_movimm(offset,ra);
3972           }
3973         } // else did it in the previous cycle
3974       }
3975       else if(rs<0) {
3976         if(!entry||entry[ra]!=rs1[i])
3977           emit_loadreg(rs1[i],ra);
3978         //if(!entry||entry[ra]!=rs1[i])
3979         //  DebugMessage(M64MSG_VERBOSE, "poor load scheduling!");
3980       }
3981       else if(c) {
3982         if(rm>=0) {
3983           if(!entry||entry[rm]!=mgr) {
3984             if(itype[i]==STORE||itype[i]==STORELR||opcode[i]==0x39||opcode[i]==0x3D) {
3985               // Stores to memory go thru the mapper to detect self-modifying
3986               // code, loads don't.
3987               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
3988                  (unsigned int)(constmap[i][rs]+offset)<0x80800000 )
3989                 generate_map_const(constmap[i][rs]+offset,rm);
3990             }else{
3991               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
3992                 generate_map_const(constmap[i][rs]+offset,rm);
3993             }
3994           }
3995         }
3996         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3997           if(!entry||entry[ra]!=agr) {
3998             if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3999               #ifdef RAM_OFFSET
4000               if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
4001                 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
4002               else
4003               #endif
4004               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra);
4005             }else if (opcode[i]==0x1a||opcode[i]==0x1b) { // LDL/LDR
4006               #ifdef RAM_OFFSET
4007               if((signed int)constmap[i][rs]+offset<(signed int)0x80800000)
4008                 emit_movimm(((constmap[i][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
4009               else
4010               #endif
4011               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra);
4012             }else{
4013               #ifdef HOST_IMM_ADDR32
4014               if((itype[i]!=LOAD&&opcode[i]!=0x31&&opcode[i]!=0x35) ||
4015                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4016               #endif
4017               #ifdef RAM_OFFSET
4018               if((itype[i]==LOAD||opcode[i]==0x31||opcode[i]==0x35)&&(signed int)constmap[i][rs]+offset<(signed int)0x80800000)
4019                 emit_movimm(constmap[i][rs]+offset+(int)rdram-0x80000000,ra);
4020               else
4021               #endif
4022               emit_movimm(constmap[i][rs]+offset,ra);
4023             }
4024           } // else did it in the previous cycle
4025         } // else load_consts already did it
4026       }
4027       if(offset&&!c&&rs1[i]) {
4028         if(rs>=0) {
4029           emit_addimm(rs,offset,ra);
4030         }else{
4031           emit_addimm(ra,offset,ra);
4032         }
4033       }
4034     }
4035   }
4036   // Preload constants for next instruction
4037   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
4038     int agr,ra;
4039     #ifndef HOST_IMM_ADDR32
4040     // Mapper entry
4041     agr=MGEN1+((i+1)&1);
4042     ra=get_reg(i_regs->regmap,agr);
4043     if(ra>=0) {
4044       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4045       int offset=imm[i+1];
4046       int c=(regs[i+1].wasconst>>rs)&1;
4047       if(c) {
4048         if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) {
4049           // Stores to memory go thru the mapper to detect self-modifying
4050           // code, loads don't.
4051           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4052              (unsigned int)(constmap[i+1][rs]+offset)<0x80800000 )
4053             generate_map_const(constmap[i+1][rs]+offset,ra);
4054         }else{
4055           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4056             generate_map_const(constmap[i+1][rs]+offset,ra);
4057         }
4058       }
4059       /*else if(rs1[i]==0) {
4060         generate_map_const(offset,ra);
4061       }*/
4062     }
4063     #endif
4064     // Actual address
4065     agr=AGEN1+((i+1)&1);
4066     ra=get_reg(i_regs->regmap,agr);
4067     if(ra>=0) {
4068       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4069       int offset=imm[i+1];
4070       int c=(regs[i+1].wasconst>>rs)&1;
4071       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4072         if (opcode[i+1]==0x22||opcode[i+1]==0x26) { // LWL/LWR
4073           #ifdef RAM_OFFSET
4074           if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4075             emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFFC)+(int)rdram-0x80000000,ra);
4076           else
4077           #endif
4078           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra);
4079         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) { // LDL/LDR
4080           #ifdef RAM_OFFSET
4081           if((signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4082             emit_movimm(((constmap[i+1][rs]+offset)&0xFFFFFFF8)+(int)rdram-0x80000000,ra);
4083           else
4084           #endif
4085           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra);
4086         }else{
4087           #ifdef HOST_IMM_ADDR32
4088           if((itype[i+1]!=LOAD&&opcode[i+1]!=0x31&&opcode[i+1]!=0x35) ||
4089              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4090           #endif
4091           #ifdef RAM_OFFSET
4092           if((itype[i+1]==LOAD||opcode[i+1]==0x31||opcode[i+1]==0x35)&&(signed int)constmap[i+1][rs]+offset<(signed int)0x80800000)
4093             emit_movimm(constmap[i+1][rs]+offset+(int)rdram-0x80000000,ra);
4094           else
4095           #endif
4096           emit_movimm(constmap[i+1][rs]+offset,ra);
4097         }
4098       }
4099       else if(rs1[i+1]==0) {
4100         // Using r0 as a base address
4101         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4102           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4103         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4104           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4105         }else{
4106           emit_movimm(offset,ra);
4107         }
4108       }
4109     }
4110   }
4111 }
4112
4113 static int get_final_value(int hr, int i, int *value)
4114 {
4115   int reg=regs[i].regmap[hr];
4116   while(i<slen-1) {
4117     if(regs[i+1].regmap[hr]!=reg) break;
4118     if(!((regs[i+1].isconst>>hr)&1)) break;
4119     if(bt[i+1]) break;
4120     i++;
4121   }
4122   if(i<slen-1) {
4123     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4124       *value=constmap[i][hr];
4125       return 1;
4126     }
4127     if(!bt[i+1]) {
4128       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4129         // Load in delay slot, out-of-order execution
4130         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4131         {
4132           #ifdef HOST_IMM_ADDR32
4133           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4134           #endif
4135           #ifdef RAM_OFFSET
4136           if((signed int)constmap[i][hr]+imm[i+2]<(signed int)0x80800000)
4137             *value=constmap[i][hr]+imm[i+2]+(int)rdram-0x80000000;
4138           else
4139           #endif
4140           // Precompute load address
4141           *value=constmap[i][hr]+imm[i+2];
4142           return 1;
4143         }
4144       }
4145       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4146       {
4147         #ifdef HOST_IMM_ADDR32
4148         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4149         #endif
4150         #ifdef RAM_OFFSET
4151         if((signed int)constmap[i][hr]+imm[i+1]<(signed int)0x80800000)
4152           *value=constmap[i][hr]+imm[i+1]+(int)rdram-0x80000000;
4153         else
4154         #endif
4155         // Precompute load address
4156         *value=constmap[i][hr]+imm[i+1];
4157         //DebugMessage(M64MSG_VERBOSE, "c=%x imm=%x",(int)constmap[i][hr],imm[i+1]);
4158         return 1;
4159       }
4160     }
4161   }
4162   *value=constmap[i][hr];
4163   //DebugMessage(M64MSG_VERBOSE, "c=%x",(int)constmap[i][hr]);
4164   if(i==slen-1) return 1;
4165   if(reg<64) {
4166     return !((unneeded_reg[i+1]>>reg)&1);
4167   }else{
4168     return !((unneeded_reg_upper[i+1]>>reg)&1);
4169   }
4170 }
4171
4172 // Load registers with known constants
4173 static void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4174 {
4175   int hr;
4176   // Load 32-bit regs
4177   for(hr=0;hr<HOST_REGS;hr++) {
4178     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4179       //if(entry[hr]!=regmap[hr]) {
4180       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4181         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4182           int value;
4183           if(get_final_value(hr,i,&value)) {
4184             if(value==0) {
4185               emit_zeroreg(hr);
4186             }
4187             else {
4188               emit_movimm(value,hr);
4189             }
4190           }
4191         }
4192       }
4193     }
4194   }
4195   // Load 64-bit regs
4196   for(hr=0;hr<HOST_REGS;hr++) {
4197     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4198       //if(entry[hr]!=regmap[hr]) {
4199       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4200         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4201           if((is32>>(regmap[hr]&63))&1) {
4202             int lr=get_reg(regmap,regmap[hr]-64);
4203             assert(lr>=0);
4204             emit_sarimm(lr,31,hr);
4205           }
4206           else
4207           {
4208             int value;
4209             if(get_final_value(hr,i,&value)) {
4210               if(value==0) {
4211                 emit_zeroreg(hr);
4212               }
4213               else {
4214                 emit_movimm(value,hr);
4215               }
4216             }
4217           }
4218         }
4219       }
4220     }
4221   }
4222 }
4223 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4224 {
4225   int hr;
4226   // Load 32-bit regs
4227   for(hr=0;hr<HOST_REGS;hr++) {
4228     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4229       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4230         int value=constmap[i][hr];
4231         if(value==0) {
4232           emit_zeroreg(hr);
4233         }
4234         else {
4235           emit_movimm(value,hr);
4236         }
4237       }
4238     }
4239   }
4240   // Load 64-bit regs
4241   for(hr=0;hr<HOST_REGS;hr++) {
4242     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4243       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4244         if((is32>>(regmap[hr]&63))&1) {
4245           int lr=get_reg(regmap,regmap[hr]-64);
4246           assert(lr>=0);
4247           emit_sarimm(lr,31,hr);
4248         }
4249         else
4250         {
4251           int value=constmap[i][hr];
4252           if(value==0) {
4253             emit_zeroreg(hr);
4254           }
4255           else {
4256             emit_movimm(value,hr);
4257           }
4258         }
4259       }
4260     }
4261   }
4262 }
4263
4264 // Write out all dirty registers (except cycle count)
4265 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4266 {
4267   int hr;
4268   for(hr=0;hr<HOST_REGS;hr++) {
4269     if(hr!=EXCLUDE_REG) {
4270       if(i_regmap[hr]>0) {
4271         if(i_regmap[hr]!=CCREG) {
4272           if((i_dirty>>hr)&1) {
4273             if(i_regmap[hr]<64) {
4274               emit_storereg(i_regmap[hr],hr);
4275               if( ((i_is32>>i_regmap[hr])&1) ) {
4276                 #ifdef DESTRUCTIVE_WRITEBACK
4277                 emit_sarimm(hr,31,hr);
4278                 emit_storereg(i_regmap[hr]|64,hr);
4279                 #else
4280                 emit_sarimm(hr,31,HOST_TEMPREG);
4281                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4282                 #endif
4283               }
4284             }else{
4285               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4286                 emit_storereg(i_regmap[hr],hr);
4287               }
4288             }
4289           }
4290         }
4291       }
4292     }
4293   }
4294 }
4295 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4296 // This writes the registers not written by store_regs_bt
4297 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4298 {
4299   int hr;
4300   int t=(addr-start)>>2;
4301   for(hr=0;hr<HOST_REGS;hr++) {
4302     if(hr!=EXCLUDE_REG) {
4303       if(i_regmap[hr]>0) {
4304         if(i_regmap[hr]!=CCREG) {
4305           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4306             if((i_dirty>>hr)&1) {
4307               if(i_regmap[hr]<64) {
4308                 emit_storereg(i_regmap[hr],hr);
4309                 if( ((i_is32>>i_regmap[hr])&1) ) {
4310                   #ifdef DESTRUCTIVE_WRITEBACK
4311                   emit_sarimm(hr,31,hr);
4312                   emit_storereg(i_regmap[hr]|64,hr);
4313                   #else
4314                   emit_sarimm(hr,31,HOST_TEMPREG);
4315                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4316                   #endif
4317                 }
4318               }else{
4319                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4320                   emit_storereg(i_regmap[hr],hr);
4321                 }
4322               }
4323             }
4324           }
4325         }
4326       }
4327     }
4328   }
4329 }
4330
4331 // Load all registers (except cycle count)
4332 static void load_all_regs(signed char i_regmap[])
4333 {
4334   int hr;
4335   for(hr=0;hr<HOST_REGS;hr++) {
4336     if(hr!=EXCLUDE_REG) {
4337       if(i_regmap[hr]==0) {
4338         emit_zeroreg(hr);
4339       }
4340       else
4341       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4342       {
4343         emit_loadreg(i_regmap[hr],hr);
4344       }
4345     }
4346   }
4347 }
4348
4349 // Load all current registers also needed by next instruction
4350 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4351 {
4352   int hr;
4353   for(hr=0;hr<HOST_REGS;hr++) {
4354     if(hr!=EXCLUDE_REG) {
4355       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4356         if(i_regmap[hr]==0) {
4357           emit_zeroreg(hr);
4358         }
4359         else
4360         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4361         {
4362           emit_loadreg(i_regmap[hr],hr);
4363         }
4364       }
4365     }
4366   }
4367 }
4368
4369 // Load all regs, storing cycle count if necessary
4370 static void load_regs_entry(int t)
4371 {
4372   int hr;
4373   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4374   else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4375   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4376     emit_storereg(CCREG,HOST_CCREG);
4377   }
4378   // Load 32-bit regs
4379   for(hr=0;hr<HOST_REGS;hr++) {
4380     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4381       if(regs[t].regmap_entry[hr]==0) {
4382         emit_zeroreg(hr);
4383       }
4384       else if(regs[t].regmap_entry[hr]!=CCREG)
4385       {
4386         emit_loadreg(regs[t].regmap_entry[hr],hr);
4387       }
4388     }
4389   }
4390   // Load 64-bit regs
4391   for(hr=0;hr<HOST_REGS;hr++) {
4392     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4393       assert(regs[t].regmap_entry[hr]!=64);
4394       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4395         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4396         if(lr<0) {
4397           emit_loadreg(regs[t].regmap_entry[hr],hr);
4398         }
4399         else
4400         {
4401           emit_sarimm(lr,31,hr);
4402         }
4403       }
4404       else
4405       {
4406         emit_loadreg(regs[t].regmap_entry[hr],hr);
4407       }
4408     }
4409   }
4410 }
4411
4412 // Store dirty registers prior to branch
4413 static void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4414 {
4415   if(internal_branch(i_is32,addr))
4416   {
4417     int t=(addr-start)>>2;
4418     int hr;
4419     for(hr=0;hr<HOST_REGS;hr++) {
4420       if(hr!=EXCLUDE_REG) {
4421         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4422           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4423             if((i_dirty>>hr)&1) {
4424               if(i_regmap[hr]<64) {
4425                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4426                   emit_storereg(i_regmap[hr],hr);
4427                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4428                     #ifdef DESTRUCTIVE_WRITEBACK
4429                     emit_sarimm(hr,31,hr);
4430                     emit_storereg(i_regmap[hr]|64,hr);
4431                     #else
4432                     emit_sarimm(hr,31,HOST_TEMPREG);
4433                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4434                     #endif
4435                   }
4436                 }
4437               }else{
4438                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4439                   emit_storereg(i_regmap[hr],hr);
4440                 }
4441               }
4442             }
4443           }
4444         }
4445       }
4446     }
4447   }
4448   else
4449   {
4450     // Branch out of this block, write out all dirty regs
4451     wb_dirtys(i_regmap,i_is32,i_dirty);
4452   }
4453 }
4454
4455 // Load all needed registers for branch target
4456 static void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4457 {
4458   //if(addr>=start && addr<(start+slen*4))
4459   if(internal_branch(i_is32,addr))
4460   {
4461     int t=(addr-start)>>2;
4462     int hr;
4463     // Store the cycle count before loading something else
4464     if(i_regmap[HOST_CCREG]!=CCREG) {
4465       assert(i_regmap[HOST_CCREG]==-1);
4466     }
4467     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4468       emit_storereg(CCREG,HOST_CCREG);
4469     }
4470     // Load 32-bit regs
4471     for(hr=0;hr<HOST_REGS;hr++) {
4472       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4473         #ifdef DESTRUCTIVE_WRITEBACK
4474         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4475         #else
4476         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4477         #endif
4478           if(regs[t].regmap_entry[hr]==0) {
4479             emit_zeroreg(hr);
4480           }
4481           else if(regs[t].regmap_entry[hr]!=CCREG)
4482           {
4483             emit_loadreg(regs[t].regmap_entry[hr],hr);
4484           }
4485         }
4486       }
4487     }
4488     //Load 64-bit regs
4489     for(hr=0;hr<HOST_REGS;hr++) {
4490       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4491         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4492           assert(regs[t].regmap_entry[hr]!=64);
4493           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4494             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4495             if(lr<0) {
4496               emit_loadreg(regs[t].regmap_entry[hr],hr);
4497             }
4498             else
4499             {
4500               emit_sarimm(lr,31,hr);
4501             }
4502           }
4503           else
4504           {
4505             emit_loadreg(regs[t].regmap_entry[hr],hr);
4506           }
4507         }
4508         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4509           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4510           assert(lr>=0);
4511           emit_sarimm(lr,31,hr);
4512         }
4513       }
4514     }
4515   }
4516 }
4517
4518 static int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4519 {
4520   if(addr>=start && addr<start+slen*4-4)
4521   {
4522     int t=(addr-start)>>2;
4523     int hr;
4524     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4525     for(hr=0;hr<HOST_REGS;hr++)
4526     {
4527       if(hr!=EXCLUDE_REG)
4528       {
4529         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4530         {
4531           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4532           {
4533             return 0;
4534           }
4535           else
4536           if((i_dirty>>hr)&1)
4537           {
4538             if(i_regmap[hr]<TEMPREG)
4539             {
4540               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4541                 return 0;
4542             }
4543             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4544             {
4545               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4546                 return 0;
4547             }
4548           }
4549         }
4550         else // Same register but is it 32-bit or dirty?
4551         if(i_regmap[hr]>=0)
4552         {
4553           if(!((regs[t].dirty>>hr)&1))
4554           {
4555             if((i_dirty>>hr)&1)
4556             {
4557               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4558               {
4559                 //DebugMessage(M64MSG_VERBOSE, "%x: dirty no match",addr);
4560                 return 0;
4561               }
4562             }
4563           }
4564           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4565           {
4566             //DebugMessage(M64MSG_VERBOSE, "%x: is32 no match",addr);
4567             return 0;
4568           }
4569         }
4570       }
4571     }
4572     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4573     if(requires_32bit[t]&~i_is32) return 0;
4574     // Delay slots are not valid branch targets
4575     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4576     // Delay slots require additional processing, so do not match
4577     if(is_ds[t]) return 0;
4578   }
4579   else
4580   {
4581     int hr;
4582     for(hr=0;hr<HOST_REGS;hr++)
4583     {
4584       if(hr!=EXCLUDE_REG)
4585       {
4586         if(i_regmap[hr]>=0)
4587         {
4588           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4589           {
4590             if((i_dirty>>hr)&1)
4591             {
4592               return 0;
4593             }
4594           }
4595         }
4596       }
4597     }
4598   }
4599   return 1;
4600 }
4601
4602 // Used when a branch jumps into the delay slot of another branch
4603 static void ds_assemble_entry(int i)
4604 {
4605   int t=(ba[i]-start)>>2;
4606   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4607   assem_debug("Assemble delay slot at %x",ba[i]);
4608   assem_debug("<->");
4609   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4610     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4611   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4612   address_generation(t,&regs[t],regs[t].regmap_entry);
4613   if(itype[t]==LOAD||itype[t]==LOADLR||itype[t]==STORE||itype[t]==STORELR||itype[t]==C1LS)
4614     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,MMREG,ROREG);
4615   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39)
4616     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4617   cop1_usable=0;
4618   is_delayslot=0;
4619   switch(itype[t]) {
4620     case ALU:
4621       alu_assemble(t,&regs[t]);break;
4622     case IMM16:
4623       imm16_assemble(t,&regs[t]);break;
4624     case SHIFT:
4625       shift_assemble(t,&regs[t]);break;
4626     case SHIFTIMM:
4627       shiftimm_assemble(t,&regs[t]);break;
4628     case LOAD:
4629       load_assemble(t,&regs[t]);break;
4630     case LOADLR:
4631       loadlr_assemble(t,&regs[t]);break;
4632     case STORE:
4633       store_assemble(t,&regs[t]);break;
4634     case STORELR:
4635       storelr_assemble(t,&regs[t]);break;
4636     case COP0:
4637       cop0_assemble(t,&regs[t]);break;
4638     case COP1:
4639       cop1_assemble(t,&regs[t]);break;
4640     case C1LS:
4641       c1ls_assemble(t,&regs[t]);break;
4642     case FCONV:
4643       fconv_assemble(t,&regs[t]);break;
4644     case FLOAT:
4645       float_assemble(t,&regs[t]);break;
4646     case FCOMP:
4647       fcomp_assemble(t,&regs[t]);break;
4648     case MULTDIV:
4649       multdiv_assemble(t,&regs[t]);break;
4650     case MOV:
4651       mov_assemble(t,&regs[t]);break;
4652     case SYSCALL:
4653     case SPAN:
4654     case UJUMP:
4655     case RJUMP:
4656     case CJUMP:
4657     case SJUMP:
4658     case FJUMP:
4659       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
4660   }
4661   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4662   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4663   if(internal_branch(regs[t].is32,ba[i]+4))
4664     assem_debug("branch: internal");
4665   else
4666     assem_debug("branch: external");
4667   assert(internal_branch(regs[t].is32,ba[i]+4));
4668   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4669   emit_jmp(0);
4670 }
4671
4672 static void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4673 {
4674   int count;
4675   int jaddr;
4676   int idle=0;
4677   if(itype[i]==RJUMP)
4678   {
4679     *adj=0;
4680   }
4681   //if(ba[i]>=start && ba[i]<(start+slen*4))
4682   if(internal_branch(branch_regs[i].is32,ba[i]))
4683   {
4684     int t=(ba[i]-start)>>2;
4685     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4686     else *adj=ccadj[t];
4687   }
4688   else
4689   {
4690     *adj=0;
4691   }
4692   count=ccadj[i];
4693   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4694     // Idle loop
4695     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4696     idle=(int)out;
4697     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4698     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4699     jaddr=(int)out;
4700     emit_jmp(0);
4701   }
4702   else if(*adj==0||invert) {
4703     emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4704     jaddr=(int)out;
4705     emit_jns(0);
4706   }
4707   else
4708   {
4709     emit_cmpimm(HOST_CCREG,-CLOCK_DIVIDER*(count+2));
4710     jaddr=(int)out;
4711     emit_jns(0);
4712   }
4713   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4714 }
4715
4716 static void do_ccstub(int n)
4717 {
4718   literal_pool(256);
4719   assem_debug("do_ccstub %x",start+stubs[n][4]*4);
4720   set_jump_target(stubs[n][1],(int)out);
4721   int i=stubs[n][4];
4722   if(stubs[n][6]==NULLDS) {
4723     // Delay slot instruction is nullified ("likely" branch)
4724     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4725   }
4726   else if(stubs[n][6]!=TAKEN) {
4727     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4728   }
4729   else {
4730     if(internal_branch(branch_regs[i].is32,ba[i]))
4731       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4732   }
4733   if(stubs[n][5]!=-1)
4734   {
4735     // Save PC as return address
4736     emit_movimm(stubs[n][5],EAX);
4737     emit_writeword(EAX,(int)&pcaddr);
4738   }
4739   else
4740   {
4741     // Return address depends on which way the branch goes
4742     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4743     {
4744       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4745       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4746       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4747       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4748       if(rs1[i]==0)
4749       {
4750         s1l=s2l;s1h=s2h;
4751         s2l=s2h=-1;
4752       }
4753       else if(rs2[i]==0)
4754       {
4755         s2l=s2h=-1;
4756       }
4757       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4758         s1h=s2h=-1;
4759       }
4760       assert(s1l>=0);
4761       #ifdef DESTRUCTIVE_WRITEBACK
4762       if(rs1[i]) {
4763         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4764           emit_loadreg(rs1[i],s1l);
4765       }
4766       else {
4767         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4768           emit_loadreg(rs2[i],s1l);
4769       }
4770       if(s2l>=0)
4771         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4772           emit_loadreg(rs2[i],s2l);
4773       #endif
4774       int hr=0;
4775       int addr,alt,ntaddr;
4776       while(hr<HOST_REGS)
4777       {
4778         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4779            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4780            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4781         {
4782           addr=hr++;break;
4783         }
4784         hr++;
4785       }
4786       while(hr<HOST_REGS)
4787       {
4788         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4789            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4790            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4791         {
4792           alt=hr++;break;
4793         }
4794         hr++;
4795       }
4796       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4797       {
4798         while(hr<HOST_REGS)
4799         {
4800           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4801              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4802              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4803           {
4804             ntaddr=hr;break;
4805           }
4806           hr++;
4807         }
4808         assert(hr<HOST_REGS);
4809       }
4810       if((opcode[i]&0x2f)==4) // BEQ
4811       {
4812         #ifdef HAVE_CMOV_IMM
4813         if(s1h<0) {
4814           if(s2l>=0) emit_cmp(s1l,s2l);
4815           else emit_test(s1l,s1l);
4816           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4817         }
4818         else
4819         #endif
4820         {
4821           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4822           if(s1h>=0) {
4823             if(s2h>=0) emit_cmp(s1h,s2h);
4824             else emit_test(s1h,s1h);
4825             emit_cmovne_reg(alt,addr);
4826           }
4827           if(s2l>=0) emit_cmp(s1l,s2l);
4828           else emit_test(s1l,s1l);
4829           emit_cmovne_reg(alt,addr);
4830         }
4831       }
4832       if((opcode[i]&0x2f)==5) // BNE
4833       {
4834         #ifdef HAVE_CMOV_IMM
4835         if(s1h<0) {
4836           if(s2l>=0) emit_cmp(s1l,s2l);
4837           else emit_test(s1l,s1l);
4838           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4839         }
4840         else
4841         #endif
4842         {
4843           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4844           if(s1h>=0) {
4845             if(s2h>=0) emit_cmp(s1h,s2h);
4846             else emit_test(s1h,s1h);
4847             emit_cmovne_reg(alt,addr);
4848           }
4849           if(s2l>=0) emit_cmp(s1l,s2l);
4850           else emit_test(s1l,s1l);
4851           emit_cmovne_reg(alt,addr);
4852         }
4853       }
4854       if((opcode[i]&0x2f)==6) // BLEZ
4855       {
4856         //emit_movimm(ba[i],alt);
4857         //emit_movimm(start+i*4+8,addr);
4858         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4859         emit_cmpimm(s1l,1);
4860         if(s1h>=0) emit_mov(addr,ntaddr);
4861         emit_cmovl_reg(alt,addr);
4862         if(s1h>=0) {
4863           emit_test(s1h,s1h);
4864           emit_cmovne_reg(ntaddr,addr);
4865           emit_cmovs_reg(alt,addr);
4866         }
4867       }
4868       if((opcode[i]&0x2f)==7) // BGTZ
4869       {
4870         //emit_movimm(ba[i],addr);
4871         //emit_movimm(start+i*4+8,ntaddr);
4872         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4873         emit_cmpimm(s1l,1);
4874         if(s1h>=0) emit_mov(addr,alt);
4875         emit_cmovl_reg(ntaddr,addr);
4876         if(s1h>=0) {
4877           emit_test(s1h,s1h);
4878           emit_cmovne_reg(alt,addr);
4879           emit_cmovs_reg(ntaddr,addr);
4880         }
4881       }
4882       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4883       {
4884         //emit_movimm(ba[i],alt);
4885         //emit_movimm(start+i*4+8,addr);
4886         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4887         if(s1h>=0) emit_test(s1h,s1h);
4888         else emit_test(s1l,s1l);
4889         emit_cmovs_reg(alt,addr);
4890       }
4891       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4892       {
4893         //emit_movimm(ba[i],addr);
4894         //emit_movimm(start+i*4+8,alt);
4895         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4896         if(s1h>=0) emit_test(s1h,s1h);
4897         else emit_test(s1l,s1l);
4898         emit_cmovs_reg(alt,addr);
4899       }
4900       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4901         if(source[i]&0x10000) // BC1T
4902         {
4903           //emit_movimm(ba[i],alt);
4904           //emit_movimm(start+i*4+8,addr);
4905           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4906           emit_testimm(s1l,0x800000);
4907           emit_cmovne_reg(alt,addr);
4908         }
4909         else // BC1F
4910         {
4911           //emit_movimm(ba[i],addr);
4912           //emit_movimm(start+i*4+8,alt);
4913           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4914           emit_testimm(s1l,0x800000);
4915           emit_cmovne_reg(alt,addr);
4916         }
4917       }
4918       emit_writeword(addr,(int)&pcaddr);
4919     }
4920     else
4921     if(itype[i]==RJUMP)
4922     {
4923       int r=get_reg(branch_regs[i].regmap,rs1[i]);
4924       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4925         r=get_reg(branch_regs[i].regmap,RTEMP);
4926       }
4927       emit_writeword(r,(int)&pcaddr);
4928     }
4929     else {DebugMessage(M64MSG_ERROR, "Unknown branch type in do_ccstub");exit(1);}
4930   }
4931   // Update cycle count
4932   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4933   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4934   emit_call((int)cc_interrupt);
4935   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4936   if(stubs[n][6]==TAKEN) {
4937     if(internal_branch(branch_regs[i].is32,ba[i]))
4938       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4939     else if(itype[i]==RJUMP) {
4940       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4941         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4942       else
4943         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4944     }
4945   }else if(stubs[n][6]==NOTTAKEN) {
4946     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4947     else load_all_regs(branch_regs[i].regmap);
4948   }else if(stubs[n][6]==NULLDS) {
4949     // Delay slot instruction is nullified ("likely" branch)
4950     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4951     else load_all_regs(regs[i].regmap);
4952   }else{
4953     load_all_regs(branch_regs[i].regmap);
4954   }
4955   emit_jmp(stubs[n][2]); // return address
4956
4957   /* This works but uses a lot of memory...
4958   emit_readword((int)&last_count,ECX);
4959   emit_add(HOST_CCREG,ECX,EAX);
4960   emit_writeword(EAX,(int)&Count);
4961   emit_call((int)gen_interupt);
4962   emit_readword((int)&Count,HOST_CCREG);
4963   emit_readword((int)&next_interupt,EAX);
4964   emit_readword((int)&pending_exception,EBX);
4965   emit_writeword(EAX,(int)&last_count);
4966   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4967   emit_test(EBX,EBX);
4968   int jne_instr=(int)out;
4969   emit_jne(0);
4970   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4971   load_all_regs(branch_regs[i].regmap);
4972   emit_jmp(stubs[n][2]); // return address
4973   set_jump_target(jne_instr,(int)out);
4974   emit_readword((int)&pcaddr,EAX);
4975   // Call get_addr_ht instead of doing the hash table here.
4976   // This code is executed infrequently and takes up a lot of space
4977   // so smaller is better.
4978   emit_storereg(CCREG,HOST_CCREG);
4979   emit_pushreg(EAX);
4980   emit_call((int)get_addr_ht);
4981   emit_loadreg(CCREG,HOST_CCREG);
4982   emit_addimm(ESP,4,ESP);
4983   emit_jmpreg(EAX);*/
4984 }
4985
4986 static void add_to_linker(int addr,int target,int ext)
4987 {
4988   link_addr[linkcount][0]=addr;
4989   link_addr[linkcount][1]=target;
4990   link_addr[linkcount][2]=ext;
4991   linkcount++;
4992 }
4993
4994 static void ujump_assemble(int i,struct regstat *i_regs)
4995 {
4996   #ifdef REG_PREFETCH
4997   signed char *i_regmap=i_regs->regmap;
4998   #endif
4999   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5000   address_generation(i+1,i_regs,regs[i].regmap_entry);
5001   #ifdef REG_PREFETCH
5002   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5003   if(rt1[i]==31&&temp>=0)
5004   {
5005     int return_address=start+i*4+8;
5006     if(get_reg(branch_regs[i].regmap,31)>0)
5007     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5008   }
5009   #endif
5010   ds_assemble(i+1,i_regs);
5011   uint64_t bc_unneeded=branch_regs[i].u;
5012   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5013   bc_unneeded|=1|(1LL<<rt1[i]);
5014   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5015   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5016                 bc_unneeded,bc_unneeded_upper);
5017   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5018   if(rt1[i]==31) {
5019     int rt;
5020     unsigned int return_address;
5021     assert(rt1[i+1]!=31);
5022     assert(rt2[i+1]!=31);
5023     rt=get_reg(branch_regs[i].regmap,31);
5024     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5025     //assert(rt>=0);
5026     return_address=start+i*4+8;
5027     if(rt>=0) {
5028       #ifdef USE_MINI_HT
5029       if(internal_branch(branch_regs[i].is32,return_address)) {
5030         int temp=rt+1;
5031         if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5032            branch_regs[i].regmap[temp]>=0)
5033         {
5034           temp=get_reg(branch_regs[i].regmap,-1);
5035         }
5036         #ifdef HOST_TEMPREG
5037         if(temp<0) temp=HOST_TEMPREG;
5038         #endif
5039         if(temp>=0) do_miniht_insert(return_address,rt,temp);
5040         else emit_movimm(return_address,rt);
5041       }
5042       else
5043       #endif
5044       {
5045         #ifdef REG_PREFETCH
5046         if(temp>=0)
5047         {
5048           if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5049         }
5050         #endif
5051         emit_movimm(return_address,rt); // PC into link register
5052         #ifdef IMM_PREFETCH
5053         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5054         #endif
5055       }
5056     }
5057   }
5058   int cc,adj;
5059   cc=get_reg(branch_regs[i].regmap,CCREG);
5060   assert(cc==HOST_CCREG);
5061   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5062   #ifdef REG_PREFETCH
5063   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5064   #endif
5065   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5066   if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5067   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5068   if(internal_branch(branch_regs[i].is32,ba[i]))
5069     assem_debug("branch: internal");
5070   else
5071     assem_debug("branch: external");
5072   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5073     ds_assemble_entry(i);
5074   }
5075   else {
5076     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5077     emit_jmp(0);
5078   }
5079 }
5080
5081 static void rjump_assemble(int i,struct regstat *i_regs)
5082 {
5083   #ifdef REG_PREFETCH
5084   signed char *i_regmap=i_regs->regmap;
5085   #endif
5086   int temp;
5087   int rs,cc;
5088   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5089   assert(rs>=0);
5090   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5091     // Delay slot abuse, make a copy of the branch address register
5092     temp=get_reg(branch_regs[i].regmap,RTEMP);
5093     assert(temp>=0);
5094     assert(regs[i].regmap[temp]==RTEMP);
5095     emit_mov(rs,temp);
5096     rs=temp;
5097   }
5098   address_generation(i+1,i_regs,regs[i].regmap_entry);
5099   #ifdef REG_PREFETCH
5100   if(rt1[i]==31)
5101   {
5102     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5103       int return_address=start+i*4+8;
5104       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5105     }
5106   }
5107   #endif
5108   #ifdef USE_MINI_HT
5109   if(rs1[i]==31) {
5110     int rh=get_reg(regs[i].regmap,RHASH);
5111     if(rh>=0) do_preload_rhash(rh);
5112   }
5113   #endif
5114   ds_assemble(i+1,i_regs);
5115   uint64_t bc_unneeded=branch_regs[i].u;
5116   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5117   bc_unneeded|=1|(1LL<<rt1[i]);
5118   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5119   bc_unneeded&=~(1LL<<rs1[i]);
5120   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5121                 bc_unneeded,bc_unneeded_upper);
5122   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5123   if(rt1[i]!=0) {
5124     int rt,return_address;
5125     assert(rt1[i+1]!=rt1[i]);
5126     assert(rt2[i+1]!=rt1[i]);
5127     rt=get_reg(branch_regs[i].regmap,rt1[i]);
5128     assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5129     assert(rt>=0);
5130     return_address=start+i*4+8;
5131     #ifdef REG_PREFETCH
5132     if(temp>=0)
5133     {
5134       if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5135     }
5136     #endif
5137     emit_movimm(return_address,rt); // PC into link register
5138     #ifdef IMM_PREFETCH
5139     emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5140     #endif
5141   }
5142   cc=get_reg(branch_regs[i].regmap,CCREG);
5143   assert(cc==HOST_CCREG);
5144   #ifdef USE_MINI_HT
5145   int rh=get_reg(branch_regs[i].regmap,RHASH);
5146   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5147   if(rs1[i]==31) {
5148     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5149     do_preload_rhtbl(ht);
5150     do_rhash(rs,rh);
5151   }
5152   #endif
5153   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5154   #ifdef DESTRUCTIVE_WRITEBACK
5155   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5156     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5157       emit_loadreg(rs1[i],rs);
5158     }
5159   }
5160   #endif
5161   #ifdef REG_PREFETCH
5162   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5163   #endif
5164   #ifdef USE_MINI_HT
5165   if(rs1[i]==31) {
5166     do_miniht_load(ht,rh);
5167   }
5168   #endif
5169   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5170   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5171   //assert(adj==0);
5172   emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5173   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5174   emit_jns(0);
5175   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5176   #ifdef USE_MINI_HT
5177   if(rs1[i]==31) {
5178     do_miniht_jump(rs,rh,ht);
5179   }
5180   else
5181   #endif
5182   {
5183     //if(rs!=EAX) emit_mov(rs,EAX);
5184     //emit_jmp((int)jump_vaddr_eax);
5185     emit_jmp(jump_vaddr_reg[rs]);
5186   }
5187   /* Check hash table
5188   temp=!rs;
5189   emit_mov(rs,temp);
5190   emit_shrimm(rs,16,rs);
5191   emit_xor(temp,rs,rs);
5192   emit_movzwl_reg(rs,rs);
5193   emit_shlimm(rs,4,rs);
5194   emit_cmpmem_indexed((int)hash_table,rs,temp);
5195   emit_jne((int)out+14);
5196   emit_readword_indexed((int)hash_table+4,rs,rs);
5197   emit_jmpreg(rs);
5198   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5199   emit_addimm_no_flags(8,rs);
5200   emit_jeq((int)out-17);
5201   // No hit on hash table, call compiler
5202   emit_pushreg(temp);
5203 //DEBUG >
5204 #ifdef DEBUG_CYCLE_COUNT
5205   emit_readword((int)&last_count,ECX);
5206   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5207   emit_readword((int)&next_interupt,ECX);
5208   emit_writeword(HOST_CCREG,(int)&Count);
5209   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5210   emit_writeword(ECX,(int)&last_count);
5211 #endif
5212 //DEBUG <
5213   emit_storereg(CCREG,HOST_CCREG);
5214   emit_call((int)get_addr);
5215   emit_loadreg(CCREG,HOST_CCREG);
5216   emit_addimm(ESP,4,ESP);
5217   emit_jmpreg(EAX);*/
5218   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5219   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5220   #endif
5221 }
5222
5223 static void cjump_assemble(int i,struct regstat *i_regs)
5224 {
5225   signed char *i_regmap=i_regs->regmap;
5226   int cc;
5227   int match;
5228   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5229   assem_debug("match=%d",match);
5230   int s1h,s1l,s2h,s2l;
5231   int prev_cop1_usable=cop1_usable;
5232   int unconditional=0,nop=0;
5233   int only32=0;
5234   int invert=0;
5235   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5236   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5237   if(!match) invert=1;
5238   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5239   if(i>(ba[i]-start)>>2) invert=1;
5240   #endif
5241
5242   if(ooo[i]) {
5243     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5244     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5245     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5246     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5247   }
5248   else {
5249     s1l=get_reg(i_regmap,rs1[i]);
5250     s1h=get_reg(i_regmap,rs1[i]|64);
5251     s2l=get_reg(i_regmap,rs2[i]);
5252     s2h=get_reg(i_regmap,rs2[i]|64);
5253   }
5254   if(rs1[i]==0&&rs2[i]==0)
5255   {
5256     if(opcode[i]&1) nop=1;
5257     else unconditional=1;
5258     //assert(opcode[i]!=5);
5259     //assert(opcode[i]!=7);
5260     //assert(opcode[i]!=0x15);
5261     //assert(opcode[i]!=0x17);
5262   }
5263   else if(rs1[i]==0)
5264   {
5265     s1l=s2l;s1h=s2h;
5266     s2l=s2h=-1;
5267     only32=(regs[i].was32>>rs2[i])&1;
5268   }
5269   else if(rs2[i]==0)
5270   {
5271     s2l=s2h=-1;
5272     only32=(regs[i].was32>>rs1[i])&1;
5273   }
5274   else {
5275     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5276   }
5277
5278   if(ooo[i]) {
5279     // Out of order execution (delay slot first)
5280     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5281     address_generation(i+1,i_regs,regs[i].regmap_entry);
5282     ds_assemble(i+1,i_regs);
5283     int adj;
5284     uint64_t bc_unneeded=branch_regs[i].u;
5285     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5286     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5287     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5288     bc_unneeded|=1;
5289     bc_unneeded_upper|=1;
5290     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5291                   bc_unneeded,bc_unneeded_upper);
5292     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5293     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5294     cc=get_reg(branch_regs[i].regmap,CCREG);
5295     assert(cc==HOST_CCREG);
5296     if(unconditional)
5297       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5298     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5299     //assem_debug("cycle count (adj)");
5300     if(unconditional) {
5301       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5302       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5303         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5304         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5305         if(internal)
5306           assem_debug("branch: internal");
5307         else
5308           assem_debug("branch: external");
5309         if(internal&&is_ds[(ba[i]-start)>>2]) {
5310           ds_assemble_entry(i);
5311         }
5312         else {
5313           add_to_linker((int)out,ba[i],internal);
5314           emit_jmp(0);
5315         }
5316         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5317         if(((u_int)out)&7) emit_addnop(0);
5318         #endif
5319       }
5320     }
5321     else if(nop) {
5322       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5323       int jaddr=(int)out;
5324       emit_jns(0);
5325       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5326     }
5327     else {
5328       int taken=0,nottaken=0,nottaken1=0;
5329       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5330       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5331       if(!only32)
5332       {
5333         assert(s1h>=0);
5334         if(opcode[i]==4) // BEQ
5335         {
5336           if(s2h>=0) emit_cmp(s1h,s2h);
5337           else emit_test(s1h,s1h);
5338           nottaken1=(int)out;
5339           emit_jne(1);
5340         }
5341         if(opcode[i]==5) // BNE
5342         {
5343           if(s2h>=0) emit_cmp(s1h,s2h);
5344           else emit_test(s1h,s1h);
5345           if(invert) taken=(int)out;
5346           else add_to_linker((int)out,ba[i],internal);
5347           emit_jne(0);
5348         }
5349         if(opcode[i]==6) // BLEZ
5350         {
5351           emit_test(s1h,s1h);
5352 //          emit_testimm(s1h,0);
5353           if(invert) taken=(int)out;
5354           else add_to_linker((int)out,ba[i],internal);
5355           emit_js(0);
5356           nottaken1=(int)out;
5357           emit_jne(1);
5358         }
5359         if(opcode[i]==7) // BGTZ
5360         {
5361           emit_test(s1h,s1h);
5362 //          emit_testimm(s1h,0);
5363           nottaken1=(int)out;
5364           emit_js(1);
5365           if(invert) taken=(int)out;
5366           else add_to_linker((int)out,ba[i],internal);
5367           emit_jne(0);
5368         }
5369       } // if(!only32)
5370
5371       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5372       assert(s1l>=0);
5373       if(opcode[i]==4) // BEQ
5374       {
5375         if(s2l>=0) emit_cmp(s1l,s2l);
5376         else emit_test(s1l,s1l);
5377         if(invert){
5378           nottaken=(int)out;
5379           emit_jne(1);
5380         }else{
5381           add_to_linker((int)out,ba[i],internal);
5382           emit_jeq(0);
5383         }
5384       }
5385       if(opcode[i]==5) // BNE
5386       {
5387         if(s2l>=0) emit_cmp(s1l,s2l);
5388         else emit_test(s1l,s1l);
5389         if(invert){
5390           nottaken=(int)out;
5391           emit_jeq(1);
5392         }else{
5393           add_to_linker((int)out,ba[i],internal);
5394           emit_jne(0);
5395         }
5396       }
5397       if(opcode[i]==6) // BLEZ
5398       {
5399         emit_cmpimm(s1l,1);
5400         if(invert){
5401           nottaken=(int)out;
5402           emit_jge(1);
5403         }else{
5404           add_to_linker((int)out,ba[i],internal);
5405           emit_jl(0);
5406         }
5407       }
5408       if(opcode[i]==7) // BGTZ
5409       {
5410         emit_cmpimm(s1l,1);
5411         if(invert){
5412           nottaken=(int)out;
5413           emit_jl(1);
5414         }else{
5415           add_to_linker((int)out,ba[i],internal);
5416           emit_jge(0);
5417         }
5418       }
5419       if(invert) {
5420         if(taken) set_jump_target(taken,(int)out);
5421         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5422         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5423           if(adj) {
5424             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5425             add_to_linker((int)out,ba[i],internal);
5426           }else{
5427             emit_addnop(13);
5428             add_to_linker((int)out,ba[i],internal*2);
5429           }
5430           emit_jmp(0);
5431         }else
5432         #endif
5433         {
5434           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5435           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5436           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5437           if(internal)
5438             assem_debug("branch: internal");
5439           else
5440             assem_debug("branch: external");
5441           if(internal&&is_ds[(ba[i]-start)>>2]) {
5442             ds_assemble_entry(i);
5443           }
5444           else {
5445             add_to_linker((int)out,ba[i],internal);
5446             emit_jmp(0);
5447           }
5448         }
5449         set_jump_target(nottaken,(int)out);
5450       }
5451
5452       if(nottaken1) set_jump_target(nottaken1,(int)out);
5453       if(adj) {
5454         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5455       }
5456     } // (!unconditional)
5457   } // if(ooo)
5458   else
5459   {
5460     // In-order execution (branch first)
5461     //if(likely[i]) DebugMessage(M64MSG_VERBOSE, "IOL");
5462     //else
5463     //DebugMessage(M64MSG_VERBOSE, "IOE");
5464     int taken=0,nottaken=0,nottaken1=0;
5465     if(!unconditional&&!nop) {
5466       if(!only32)
5467       {
5468         assert(s1h>=0);
5469         if((opcode[i]&0x2f)==4) // BEQ
5470         {
5471           if(s2h>=0) emit_cmp(s1h,s2h);
5472           else emit_test(s1h,s1h);
5473           nottaken1=(int)out;
5474           emit_jne(2);
5475         }
5476         if((opcode[i]&0x2f)==5) // BNE
5477         {
5478           if(s2h>=0) emit_cmp(s1h,s2h);
5479           else emit_test(s1h,s1h);
5480           taken=(int)out;
5481           emit_jne(1);
5482         }
5483         if((opcode[i]&0x2f)==6) // BLEZ
5484         {
5485           emit_test(s1h,s1h);
5486           taken=(int)out;
5487           emit_js(1);
5488           nottaken1=(int)out;
5489           emit_jne(2);
5490         }
5491         if((opcode[i]&0x2f)==7) // BGTZ
5492         {
5493           emit_test(s1h,s1h);
5494           nottaken1=(int)out;
5495           emit_js(2);
5496           taken=(int)out;
5497           emit_jne(1);
5498         }
5499       } // if(!only32)
5500
5501       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5502       assert(s1l>=0);
5503       if((opcode[i]&0x2f)==4) // BEQ
5504       {
5505         if(s2l>=0) emit_cmp(s1l,s2l);
5506         else emit_test(s1l,s1l);
5507         nottaken=(int)out;
5508         emit_jne(2);
5509       }
5510       if((opcode[i]&0x2f)==5) // BNE
5511       {
5512         if(s2l>=0) emit_cmp(s1l,s2l);
5513         else emit_test(s1l,s1l);
5514         nottaken=(int)out;
5515         emit_jeq(2);
5516       }
5517       if((opcode[i]&0x2f)==6) // BLEZ
5518       {
5519         emit_cmpimm(s1l,1);
5520         nottaken=(int)out;
5521         emit_jge(2);
5522       }
5523       if((opcode[i]&0x2f)==7) // BGTZ
5524       {
5525         emit_cmpimm(s1l,1);
5526         nottaken=(int)out;
5527         emit_jl(2);
5528       }
5529     } // if(!unconditional)
5530     int adj;
5531     uint64_t ds_unneeded=branch_regs[i].u;
5532     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5533     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5534     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5535     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5536     ds_unneeded|=1;
5537     ds_unneeded_upper|=1;
5538     // branch taken
5539     if(!nop) {
5540       if(taken) set_jump_target(taken,(int)out);
5541       assem_debug("1:");
5542       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5543                     ds_unneeded,ds_unneeded_upper);
5544       // load regs
5545       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5546       address_generation(i+1,&branch_regs[i],0);
5547       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5548       ds_assemble(i+1,&branch_regs[i]);
5549       cc=get_reg(branch_regs[i].regmap,CCREG);
5550       if(cc==-1) {
5551         emit_loadreg(CCREG,cc=HOST_CCREG);
5552         // CHECK: Is the following instruction (fall thru) allocated ok?
5553       }
5554       assert(cc==HOST_CCREG);
5555       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5556       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5557       assem_debug("cycle count (adj)");
5558       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5559       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5560       if(internal)
5561         assem_debug("branch: internal");
5562       else
5563         assem_debug("branch: external");
5564       if(internal&&is_ds[(ba[i]-start)>>2]) {
5565         ds_assemble_entry(i);
5566       }
5567       else {
5568         add_to_linker((int)out,ba[i],internal);
5569         emit_jmp(0);
5570       }
5571     }
5572     // branch not taken
5573     cop1_usable=prev_cop1_usable;
5574     if(!unconditional) {
5575       if(nottaken1) set_jump_target(nottaken1,(int)out);
5576       set_jump_target(nottaken,(int)out);
5577       assem_debug("2:");
5578       if(!likely[i]) {
5579         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5580                       ds_unneeded,ds_unneeded_upper);
5581         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5582         address_generation(i+1,&branch_regs[i],0);
5583         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5584         ds_assemble(i+1,&branch_regs[i]);
5585       }
5586       cc=get_reg(branch_regs[i].regmap,CCREG);
5587       if(cc==-1&&!likely[i]) {
5588         // Cycle count isn't in a register, temporarily load it then write it out
5589         emit_loadreg(CCREG,HOST_CCREG);
5590         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5591         int jaddr=(int)out;
5592         emit_jns(0);
5593         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5594         emit_storereg(CCREG,HOST_CCREG);
5595       }
5596       else{
5597         cc=get_reg(i_regmap,CCREG);
5598         assert(cc==HOST_CCREG);
5599         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5600         int jaddr=(int)out;
5601         emit_jns(0);
5602         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5603       }
5604     }
5605   }
5606 }
5607
5608 static void sjump_assemble(int i,struct regstat *i_regs)
5609 {
5610   signed char *i_regmap=i_regs->regmap;
5611   int cc;
5612   int match;
5613   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5614   assem_debug("smatch=%d",match);
5615   int s1h,s1l;
5616   int prev_cop1_usable=cop1_usable;
5617   int unconditional=0,nevertaken=0;
5618   int only32=0;
5619   int invert=0;
5620   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5621   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5622   if(!match) invert=1;
5623   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5624   if(i>(ba[i]-start)>>2) invert=1;
5625   #endif
5626
5627   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5628   assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5629
5630   if(ooo[i]) {
5631     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5632     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5633   }
5634   else {
5635     s1l=get_reg(i_regmap,rs1[i]);
5636     s1h=get_reg(i_regmap,rs1[i]|64);
5637   }
5638   if(rs1[i]==0)
5639   {
5640     if(opcode2[i]&1) unconditional=1;
5641     else nevertaken=1;
5642     // These are never taken (r0 is never less than zero)
5643     //assert(opcode2[i]!=0);
5644     //assert(opcode2[i]!=2);
5645     //assert(opcode2[i]!=0x10);
5646     //assert(opcode2[i]!=0x12);
5647   }
5648   else {
5649     only32=(regs[i].was32>>rs1[i])&1;
5650   }
5651
5652   if(ooo[i]) {
5653     // Out of order execution (delay slot first)
5654     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5655     address_generation(i+1,i_regs,regs[i].regmap_entry);
5656     ds_assemble(i+1,i_regs);
5657     int adj;
5658     uint64_t bc_unneeded=branch_regs[i].u;
5659     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5660     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5661     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5662     bc_unneeded|=1;
5663     bc_unneeded_upper|=1;
5664     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5665                   bc_unneeded,bc_unneeded_upper);
5666     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5667     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5668     if(rt1[i]==31) {
5669       int rt,return_address;
5670       assert(rt1[i+1]!=31);
5671       assert(rt2[i+1]!=31);
5672       rt=get_reg(branch_regs[i].regmap,31);
5673       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5674       if(rt>=0) {
5675         // Save the PC even if the branch is not taken
5676         return_address=start+i*4+8;
5677         emit_movimm(return_address,rt); // PC into link register
5678         #ifdef IMM_PREFETCH
5679         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5680         #endif
5681       }
5682     }
5683     cc=get_reg(branch_regs[i].regmap,CCREG);
5684     assert(cc==HOST_CCREG);
5685     if(unconditional)
5686       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5687     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5688     assem_debug("cycle count (adj)");
5689     if(unconditional) {
5690       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5691       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5692         if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5693         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5694         if(internal)
5695           assem_debug("branch: internal");
5696         else
5697           assem_debug("branch: external");
5698         if(internal&&is_ds[(ba[i]-start)>>2]) {
5699           ds_assemble_entry(i);
5700         }
5701         else {
5702           add_to_linker((int)out,ba[i],internal);
5703           emit_jmp(0);
5704         }
5705         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5706         if(((u_int)out)&7) emit_addnop(0);
5707         #endif
5708       }
5709     }
5710     else if(nevertaken) {
5711       emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5712       int jaddr=(int)out;
5713       emit_jns(0);
5714       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5715     }
5716     else {
5717       int nottaken=0;
5718       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5719       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5720       if(!only32)
5721       {
5722         assert(s1h>=0);
5723         if(opcode2[i]==0) // BLTZ
5724         {
5725           emit_test(s1h,s1h);
5726           if(invert){
5727             nottaken=(int)out;
5728             emit_jns(1);
5729           }else{
5730             add_to_linker((int)out,ba[i],internal);
5731             emit_js(0);
5732           }
5733         }
5734         if(opcode2[i]==1) // BGEZ
5735         {
5736           emit_test(s1h,s1h);
5737           if(invert){
5738             nottaken=(int)out;
5739             emit_js(1);
5740           }else{
5741             add_to_linker((int)out,ba[i],internal);
5742             emit_jns(0);
5743           }
5744         }
5745       } // if(!only32)
5746       else
5747       {
5748         assert(s1l>=0);
5749         if(opcode2[i]==0) // BLTZ
5750         {
5751           emit_test(s1l,s1l);
5752           if(invert){
5753             nottaken=(int)out;
5754             emit_jns(1);
5755           }else{
5756             add_to_linker((int)out,ba[i],internal);
5757             emit_js(0);
5758           }
5759         }
5760         if(opcode2[i]==1) // BGEZ
5761         {
5762           emit_test(s1l,s1l);
5763           if(invert){
5764             nottaken=(int)out;
5765             emit_js(1);
5766           }else{
5767             add_to_linker((int)out,ba[i],internal);
5768             emit_jns(0);
5769           }
5770         }
5771       } // if(!only32)
5772
5773       if(invert) {
5774         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5775         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5776           if(adj) {
5777             emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5778             add_to_linker((int)out,ba[i],internal);
5779           }else{
5780             emit_addnop(13);
5781             add_to_linker((int)out,ba[i],internal*2);
5782           }
5783           emit_jmp(0);
5784         }else
5785         #endif
5786         {
5787           if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5788           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5789           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5790           if(internal)
5791             assem_debug("branch: internal");
5792           else
5793             assem_debug("branch: external");
5794           if(internal&&is_ds[(ba[i]-start)>>2]) {
5795             ds_assemble_entry(i);
5796           }
5797           else {
5798             add_to_linker((int)out,ba[i],internal);
5799             emit_jmp(0);
5800           }
5801         }
5802         set_jump_target(nottaken,(int)out);
5803       }
5804
5805       if(adj) {
5806         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5807       }
5808     } // (!unconditional)
5809   } // if(ooo)
5810   else
5811   {
5812     // In-order execution (branch first)
5813     //DebugMessage(M64MSG_VERBOSE, "IOE");
5814     int nottaken=0;
5815     if(!unconditional) {
5816       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5817       if(!only32)
5818       {
5819         assert(s1h>=0);
5820         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5821         {
5822           emit_test(s1h,s1h);
5823           nottaken=(int)out;
5824           emit_jns(1);
5825         }
5826         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5827         {
5828           emit_test(s1h,s1h);
5829           nottaken=(int)out;
5830           emit_js(1);
5831         }
5832       } // if(!only32)
5833       else
5834       {
5835         assert(s1l>=0);
5836         if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5837         {
5838           emit_test(s1l,s1l);
5839           nottaken=(int)out;
5840           emit_jns(1);
5841         }
5842         if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5843         {
5844           emit_test(s1l,s1l);
5845           nottaken=(int)out;
5846           emit_js(1);
5847         }
5848       }
5849     } // if(!unconditional)
5850     int adj;
5851     uint64_t ds_unneeded=branch_regs[i].u;
5852     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5853     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5854     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5855     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5856     ds_unneeded|=1;
5857     ds_unneeded_upper|=1;
5858     // branch taken
5859     if(!nevertaken) {
5860       //assem_debug("1:");
5861       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5862                     ds_unneeded,ds_unneeded_upper);
5863       // load regs
5864       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5865       address_generation(i+1,&branch_regs[i],0);
5866       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5867       ds_assemble(i+1,&branch_regs[i]);
5868       cc=get_reg(branch_regs[i].regmap,CCREG);
5869       if(cc==-1) {
5870         emit_loadreg(CCREG,cc=HOST_CCREG);
5871         // CHECK: Is the following instruction (fall thru) allocated ok?
5872       }
5873       assert(cc==HOST_CCREG);
5874       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5875       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5876       assem_debug("cycle count (adj)");
5877       if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5878       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5879       if(internal)
5880         assem_debug("branch: internal");
5881       else
5882         assem_debug("branch: external");
5883       if(internal&&is_ds[(ba[i]-start)>>2]) {
5884         ds_assemble_entry(i);
5885       }
5886       else {
5887         add_to_linker((int)out,ba[i],internal);
5888         emit_jmp(0);
5889       }
5890     }
5891     // branch not taken
5892     cop1_usable=prev_cop1_usable;
5893     if(!unconditional) {
5894       set_jump_target(nottaken,(int)out);
5895       assem_debug("1:");
5896       if(!likely[i]) {
5897         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5898                       ds_unneeded,ds_unneeded_upper);
5899         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5900         address_generation(i+1,&branch_regs[i],0);
5901         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5902         ds_assemble(i+1,&branch_regs[i]);
5903       }
5904       cc=get_reg(branch_regs[i].regmap,CCREG);
5905       if(cc==-1&&!likely[i]) {
5906         // Cycle count isn't in a register, temporarily load it then write it out
5907         emit_loadreg(CCREG,HOST_CCREG);
5908         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5909         int jaddr=(int)out;
5910         emit_jns(0);
5911         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5912         emit_storereg(CCREG,HOST_CCREG);
5913       }
5914       else{
5915         cc=get_reg(i_regmap,CCREG);
5916         assert(cc==HOST_CCREG);
5917         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5918         int jaddr=(int)out;
5919         emit_jns(0);
5920         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5921       }
5922     }
5923   }
5924 }
5925
5926 static void fjump_assemble(int i,struct regstat *i_regs)
5927 {
5928   signed char *i_regmap=i_regs->regmap;
5929   int cc;
5930   int match;
5931   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5932   assem_debug("fmatch=%d",match);
5933   int fs,cs;
5934   int eaddr;
5935   int invert=0;
5936   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5937   if(i==(ba[i]-start)>>2) assem_debug("idle loop");
5938   if(!match) invert=1;
5939   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5940   if(i>(ba[i]-start)>>2) invert=1;
5941   #endif
5942
5943   if(ooo[i]) {
5944     fs=get_reg(branch_regs[i].regmap,FSREG);
5945     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5946   }
5947   else {
5948     fs=get_reg(i_regmap,FSREG);
5949   }
5950
5951   // Check cop1 unusable
5952   if(!cop1_usable) {
5953     cs=get_reg(i_regmap,CSREG);
5954     assert(cs>=0);
5955     emit_testimm(cs,0x20000000);
5956     eaddr=(int)out;
5957     emit_jeq(0);
5958     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5959     cop1_usable=1;
5960   }
5961
5962   if(ooo[i]) {
5963     // Out of order execution (delay slot first)
5964     //DebugMessage(M64MSG_VERBOSE, "OOOE");
5965     ds_assemble(i+1,i_regs);
5966     int adj;
5967     uint64_t bc_unneeded=branch_regs[i].u;
5968     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5969     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5970     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5971     bc_unneeded|=1;
5972     bc_unneeded_upper|=1;
5973     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5974                   bc_unneeded,bc_unneeded_upper);
5975     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5976     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5977     cc=get_reg(branch_regs[i].regmap,CCREG);
5978     assert(cc==HOST_CCREG);
5979     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5980     assem_debug("cycle count (adj)");
5981     if(1) {
5982       int nottaken=0;
5983       if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5984       if(1) {
5985         assert(fs>=0);
5986         emit_testimm(fs,0x800000);
5987         if(source[i]&0x10000) // BC1T
5988         {
5989           if(invert){
5990             nottaken=(int)out;
5991             emit_jeq(1);
5992           }else{
5993             add_to_linker((int)out,ba[i],internal);
5994             emit_jne(0);
5995           }
5996         }
5997         else // BC1F
5998           if(invert){
5999             nottaken=(int)out;
6000             emit_jne(1);
6001           }else{
6002             add_to_linker((int)out,ba[i],internal);
6003             emit_jeq(0);
6004           }
6005         {
6006         }
6007       } // if(!only32)
6008
6009       if(invert) {
6010         if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6011         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6012         else if(match) emit_addnop(13);
6013         #endif
6014         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6015         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6016         if(internal)
6017           assem_debug("branch: internal");
6018         else
6019           assem_debug("branch: external");
6020         if(internal&&is_ds[(ba[i]-start)>>2]) {
6021           ds_assemble_entry(i);
6022         }
6023         else {
6024           add_to_linker((int)out,ba[i],internal);
6025           emit_jmp(0);
6026         }
6027         set_jump_target(nottaken,(int)out);
6028       }
6029
6030       if(adj) {
6031         if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6032       }
6033     } // (!unconditional)
6034   } // if(ooo)
6035   else
6036   {
6037     // In-order execution (branch first)
6038     //DebugMessage(M64MSG_VERBOSE, "IOE");
6039     int nottaken=0;
6040     if(1) {
6041       //DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6042       if(1) {
6043         assert(fs>=0);
6044         emit_testimm(fs,0x800000);
6045         if(source[i]&0x10000) // BC1T
6046         {
6047           nottaken=(int)out;
6048           emit_jeq(1);
6049         }
6050         else // BC1F
6051         {
6052           nottaken=(int)out;
6053           emit_jne(1);
6054         }
6055       }
6056     } // if(!unconditional)
6057     int adj;
6058     uint64_t ds_unneeded=branch_regs[i].u;
6059     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6060     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6061     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6062     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6063     ds_unneeded|=1;
6064     ds_unneeded_upper|=1;
6065     // branch taken
6066     //assem_debug("1:");
6067     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6068                   ds_unneeded,ds_unneeded_upper);
6069     // load regs
6070     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6071     address_generation(i+1,&branch_regs[i],0);
6072     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6073     ds_assemble(i+1,&branch_regs[i]);
6074     cc=get_reg(branch_regs[i].regmap,CCREG);
6075     if(cc==-1) {
6076       emit_loadreg(CCREG,cc=HOST_CCREG);
6077       // CHECK: Is the following instruction (fall thru) allocated ok?
6078     }
6079     assert(cc==HOST_CCREG);
6080     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6081     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6082     assem_debug("cycle count (adj)");
6083     if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6084     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6085     if(internal)
6086       assem_debug("branch: internal");
6087     else
6088       assem_debug("branch: external");
6089     if(internal&&is_ds[(ba[i]-start)>>2]) {
6090       ds_assemble_entry(i);
6091     }
6092     else {
6093       add_to_linker((int)out,ba[i],internal);
6094       emit_jmp(0);
6095     }
6096
6097     // branch not taken
6098     if(1) { // <- FIXME (don't need this)
6099       set_jump_target(nottaken,(int)out);
6100       assem_debug("1:");
6101       if(!likely[i]) {
6102         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6103                       ds_unneeded,ds_unneeded_upper);
6104         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6105         address_generation(i+1,&branch_regs[i],0);
6106         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6107         ds_assemble(i+1,&branch_regs[i]);
6108       }
6109       cc=get_reg(branch_regs[i].regmap,CCREG);
6110       if(cc==-1&&!likely[i]) {
6111         // Cycle count isn't in a register, temporarily load it then write it out
6112         emit_loadreg(CCREG,HOST_CCREG);
6113         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6114         int jaddr=(int)out;
6115         emit_jns(0);
6116         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6117         emit_storereg(CCREG,HOST_CCREG);
6118       }
6119       else{
6120         cc=get_reg(i_regmap,CCREG);
6121         assert(cc==HOST_CCREG);
6122         emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6123         int jaddr=(int)out;
6124         emit_jns(0);
6125         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6126       }
6127     }
6128   }
6129 }
6130
6131 static void pagespan_assemble(int i,struct regstat *i_regs)
6132 {
6133   int s1l=get_reg(i_regs->regmap,rs1[i]);
6134   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6135   int s2l=get_reg(i_regs->regmap,rs2[i]);
6136   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6137   int taken=0;
6138   int nottaken=0;
6139   int unconditional=0;
6140   if(rs1[i]==0)
6141   {
6142     s1l=s2l;s1h=s2h;
6143     s2l=s2h=-1;
6144   }
6145   else if(rs2[i]==0)
6146   {
6147     s2l=s2h=-1;
6148   }
6149   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6150     s1h=s2h=-1;
6151   }
6152   int hr=0;
6153   int addr,alt,ntaddr;
6154   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6155   else {
6156     while(hr<HOST_REGS)
6157     {
6158       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6159          (i_regs->regmap[hr]&63)!=rs1[i] &&
6160          (i_regs->regmap[hr]&63)!=rs2[i] )
6161       {
6162         addr=hr++;break;
6163       }
6164       hr++;
6165     }
6166   }
6167   while(hr<HOST_REGS)
6168   {
6169     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6170        (i_regs->regmap[hr]&63)!=rs1[i] &&
6171        (i_regs->regmap[hr]&63)!=rs2[i] )
6172     {
6173       alt=hr++;break;
6174     }
6175     hr++;
6176   }
6177   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6178   {
6179     while(hr<HOST_REGS)
6180     {
6181       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6182          (i_regs->regmap[hr]&63)!=rs1[i] &&
6183          (i_regs->regmap[hr]&63)!=rs2[i] )
6184       {
6185         ntaddr=hr;break;
6186       }
6187       hr++;
6188     }
6189   }
6190   assert(hr<HOST_REGS);
6191   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6192     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6193   }
6194   emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6195   if(opcode[i]==2) // J
6196   {
6197     unconditional=1;
6198   }
6199   if(opcode[i]==3) // JAL
6200   {
6201     // TODO: mini_ht
6202     int rt=get_reg(i_regs->regmap,31);
6203     emit_movimm(start+i*4+8,rt);
6204     unconditional=1;
6205   }
6206   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6207   {
6208     emit_mov(s1l,addr);
6209     if(opcode2[i]==9) // JALR
6210     {
6211       int rt=get_reg(i_regs->regmap,rt1[i]);
6212       emit_movimm(start+i*4+8,rt);
6213     }
6214   }
6215   if((opcode[i]&0x3f)==4) // BEQ
6216   {
6217     if(rs1[i]==rs2[i])
6218     {
6219       unconditional=1;
6220     }
6221     else
6222     #ifdef HAVE_CMOV_IMM
6223     if(s1h<0) {
6224       if(s2l>=0) emit_cmp(s1l,s2l);
6225       else emit_test(s1l,s1l);
6226       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6227     }
6228     else
6229     #endif
6230     {
6231       assert(s1l>=0);
6232       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6233       if(s1h>=0) {
6234         if(s2h>=0) emit_cmp(s1h,s2h);
6235         else emit_test(s1h,s1h);
6236         emit_cmovne_reg(alt,addr);
6237       }
6238       if(s2l>=0) emit_cmp(s1l,s2l);
6239       else emit_test(s1l,s1l);
6240       emit_cmovne_reg(alt,addr);
6241     }
6242   }
6243   if((opcode[i]&0x3f)==5) // BNE
6244   {
6245     #ifdef HAVE_CMOV_IMM
6246     if(s1h<0) {
6247       if(s2l>=0) emit_cmp(s1l,s2l);
6248       else emit_test(s1l,s1l);
6249       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6250     }
6251     else
6252     #endif
6253     {
6254       assert(s1l>=0);
6255       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6256       if(s1h>=0) {
6257         if(s2h>=0) emit_cmp(s1h,s2h);
6258         else emit_test(s1h,s1h);
6259         emit_cmovne_reg(alt,addr);
6260       }
6261       if(s2l>=0) emit_cmp(s1l,s2l);
6262       else emit_test(s1l,s1l);
6263       emit_cmovne_reg(alt,addr);
6264     }
6265   }
6266   if((opcode[i]&0x3f)==0x14) // BEQL
6267   {
6268     if(s1h>=0) {
6269       if(s2h>=0) emit_cmp(s1h,s2h);
6270       else emit_test(s1h,s1h);
6271       nottaken=(int)out;
6272       emit_jne(0);
6273     }
6274     if(s2l>=0) emit_cmp(s1l,s2l);
6275     else emit_test(s1l,s1l);
6276     if(nottaken) set_jump_target(nottaken,(int)out);
6277     nottaken=(int)out;
6278     emit_jne(0);
6279   }
6280   if((opcode[i]&0x3f)==0x15) // BNEL
6281   {
6282     if(s1h>=0) {
6283       if(s2h>=0) emit_cmp(s1h,s2h);
6284       else emit_test(s1h,s1h);
6285       taken=(int)out;
6286       emit_jne(0);
6287     }
6288     if(s2l>=0) emit_cmp(s1l,s2l);
6289     else emit_test(s1l,s1l);
6290     nottaken=(int)out;
6291     emit_jeq(0);
6292     if(taken) set_jump_target(taken,(int)out);
6293   }
6294   if((opcode[i]&0x3f)==6) // BLEZ
6295   {
6296     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6297     emit_cmpimm(s1l,1);
6298     if(s1h>=0) emit_mov(addr,ntaddr);
6299     emit_cmovl_reg(alt,addr);
6300     if(s1h>=0) {
6301       emit_test(s1h,s1h);
6302       emit_cmovne_reg(ntaddr,addr);
6303       emit_cmovs_reg(alt,addr);
6304     }
6305   }
6306   if((opcode[i]&0x3f)==7) // BGTZ
6307   {
6308     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6309     emit_cmpimm(s1l,1);
6310     if(s1h>=0) emit_mov(addr,alt);
6311     emit_cmovl_reg(ntaddr,addr);
6312     if(s1h>=0) {
6313       emit_test(s1h,s1h);
6314       emit_cmovne_reg(alt,addr);
6315       emit_cmovs_reg(ntaddr,addr);
6316     }
6317   }
6318   if((opcode[i]&0x3f)==0x16) // BLEZL
6319   {
6320     assert((opcode[i]&0x3f)!=0x16);
6321   }
6322   if((opcode[i]&0x3f)==0x17) // BGTZL
6323   {
6324     assert((opcode[i]&0x3f)!=0x17);
6325   }
6326   assert(opcode[i]!=1); // BLTZ/BGEZ
6327
6328   //FIXME: Check CSREG
6329   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6330     if((source[i]&0x30000)==0) // BC1F
6331     {
6332       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6333       emit_testimm(s1l,0x800000);
6334       emit_cmovne_reg(alt,addr);
6335     }
6336     if((source[i]&0x30000)==0x10000) // BC1T
6337     {
6338       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6339       emit_testimm(s1l,0x800000);
6340       emit_cmovne_reg(alt,addr);
6341     }
6342     if((source[i]&0x30000)==0x20000) // BC1FL
6343     {
6344       emit_testimm(s1l,0x800000);
6345       nottaken=(int)out;
6346       emit_jne(0);
6347     }
6348     if((source[i]&0x30000)==0x30000) // BC1TL
6349     {
6350       emit_testimm(s1l,0x800000);
6351       nottaken=(int)out;
6352       emit_jeq(0);
6353     }
6354   }
6355
6356   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6357   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6358   if(likely[i]||unconditional)
6359   {
6360     emit_movimm(ba[i],HOST_BTREG);
6361   }
6362   else if(addr!=HOST_BTREG)
6363   {
6364     emit_mov(addr,HOST_BTREG);
6365   }
6366   void *branch_addr=out;
6367   emit_jmp(0);
6368   int target_addr=start+i*4+5;
6369   void *stub=out;
6370   void *compiled_target_addr=check_addr(target_addr);
6371   emit_extjump_ds((int)branch_addr,target_addr);
6372   if(compiled_target_addr) {
6373     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6374     add_link(target_addr,stub);
6375   }
6376   else set_jump_target((int)branch_addr,(int)stub);
6377   if(likely[i]) {
6378     // Not-taken path
6379     set_jump_target((int)nottaken,(int)out);
6380     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6381     void *branch_addr=out;
6382     emit_jmp(0);
6383     int target_addr=start+i*4+8;
6384     void *stub=out;
6385     void *compiled_target_addr=check_addr(target_addr);
6386     emit_extjump_ds((int)branch_addr,target_addr);
6387     if(compiled_target_addr) {
6388       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6389       add_link(target_addr,stub);
6390     }
6391     else set_jump_target((int)branch_addr,(int)stub);
6392   }
6393 }
6394
6395 // Assemble the delay slot for the above
6396 static void pagespan_ds()
6397 {
6398   assem_debug("initial delay slot:");
6399   u_int vaddr=start+1;
6400   u_int page=(0x80000000^vaddr)>>12;
6401   u_int vpage=page;
6402   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
6403   if(page>2048) page=2048+(page&2047);
6404   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
6405   if(vpage>2048) vpage=2048+(vpage&2047);
6406   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6407   do_dirty_stub_ds();
6408   ll_add(jump_in+page,vaddr,(void *)out);
6409   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6410   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6411     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6412   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6413     emit_writeword(HOST_BTREG,(int)&branch_target);
6414   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6415   address_generation(0,&regs[0],regs[0].regmap_entry);
6416   if(itype[0]==LOAD||itype[0]==LOADLR||itype[0]==STORE||itype[0]==STORELR||itype[0]==C1LS)
6417     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,MMREG,ROREG);
6418   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39)
6419     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6420   cop1_usable=0;
6421   is_delayslot=0;
6422   switch(itype[0]) {
6423     case ALU:
6424       alu_assemble(0,&regs[0]);break;
6425     case IMM16:
6426       imm16_assemble(0,&regs[0]);break;
6427     case SHIFT:
6428       shift_assemble(0,&regs[0]);break;
6429     case SHIFTIMM:
6430       shiftimm_assemble(0,&regs[0]);break;
6431     case LOAD:
6432       load_assemble(0,&regs[0]);break;
6433     case LOADLR:
6434       loadlr_assemble(0,&regs[0]);break;
6435     case STORE:
6436       store_assemble(0,&regs[0]);break;
6437     case STORELR:
6438       storelr_assemble(0,&regs[0]);break;
6439     case COP0:
6440       cop0_assemble(0,&regs[0]);break;
6441     case COP1:
6442       cop1_assemble(0,&regs[0]);break;
6443     case C1LS:
6444       c1ls_assemble(0,&regs[0]);break;
6445     case FCONV:
6446       fconv_assemble(0,&regs[0]);break;
6447     case FLOAT:
6448       float_assemble(0,&regs[0]);break;
6449     case FCOMP:
6450       fcomp_assemble(0,&regs[0]);break;
6451     case MULTDIV:
6452       multdiv_assemble(0,&regs[0]);break;
6453     case MOV:
6454       mov_assemble(0,&regs[0]);break;
6455     case SYSCALL:
6456     case SPAN:
6457     case UJUMP:
6458     case RJUMP:
6459     case CJUMP:
6460     case SJUMP:
6461     case FJUMP:
6462       DebugMessage(M64MSG_VERBOSE, "Jump in the delay slot.  This is probably a bug.");
6463   }
6464   int btaddr=get_reg(regs[0].regmap,BTREG);
6465   if(btaddr<0) {
6466     btaddr=get_reg(regs[0].regmap,-1);
6467     emit_readword((int)&branch_target,btaddr);
6468   }
6469   assert(btaddr!=HOST_CCREG);
6470   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6471 #ifdef HOST_IMM8
6472   emit_movimm(start+4,HOST_TEMPREG);
6473   emit_cmp(btaddr,HOST_TEMPREG);
6474 #else
6475   emit_cmpimm(btaddr,start+4);
6476 #endif
6477   int branch=(int)out;
6478   emit_jeq(0);
6479   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6480   emit_jmp(jump_vaddr_reg[btaddr]);
6481   set_jump_target(branch,(int)out);
6482   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6483   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6484 }
6485
6486 // Basic liveness analysis for MIPS registers
6487 static void unneeded_registers(int istart,int iend,int r)
6488 {
6489   int i;
6490   uint64_t u,uu,b,bu;
6491   uint64_t temp_u,temp_uu;
6492   uint64_t tdep;
6493   if(iend==slen-1) {
6494     u=1;uu=1;
6495   }else{
6496     u=unneeded_reg[iend+1];
6497     uu=unneeded_reg_upper[iend+1];
6498     u=1;uu=1;
6499   }
6500   for (i=iend;i>=istart;i--)
6501   {
6502     //DebugMessage(M64MSG_VERBOSE, "unneeded registers i=%d (%d,%d) r=%d",i,istart,iend,r);
6503     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6504     {
6505       // If subroutine call, flag return address as a possible branch target
6506       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6507
6508       if(ba[i]<start || ba[i]>=(start+slen*4))
6509       {
6510         // Branch out of this block, flush all regs
6511         u=1;
6512         uu=1;
6513         /* Hexagon hack
6514         if(itype[i]==UJUMP&&rt1[i]==31)
6515         {
6516           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6517         }
6518         if(itype[i]==RJUMP&&rs1[i]==31)
6519         {
6520           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6521         }
6522         if(start>0x80000400&&start<0x80800000) {
6523           if(itype[i]==UJUMP&&rt1[i]==31)
6524           {
6525             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6526             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6527           }
6528           if(itype[i]==RJUMP&&rs1[i]==31)
6529           {
6530             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6531             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6532           }
6533         }*/
6534         branch_unneeded_reg[i]=u;
6535         branch_unneeded_reg_upper[i]=uu;
6536         // Merge in delay slot
6537         tdep=(~uu>>rt1[i+1])&1;
6538         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6539         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6540         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6541         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6542         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6543         u|=1;uu|=1;
6544         // If branch is "likely" (and conditional)
6545         // then we skip the delay slot on the fall-thru path
6546         if(likely[i]) {
6547           if(i<slen-1) {
6548             u&=unneeded_reg[i+2];
6549             uu&=unneeded_reg_upper[i+2];
6550           }
6551           else
6552           {
6553             u=1;
6554             uu=1;
6555           }
6556         }
6557       }
6558       else
6559       {
6560         // Internal branch, flag target
6561         bt[(ba[i]-start)>>2]=1;
6562         if(ba[i]<=start+i*4) {
6563           // Backward branch
6564           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6565           {
6566             // Unconditional branch
6567             temp_u=1;temp_uu=1;
6568           } else {
6569             // Conditional branch (not taken case)
6570             temp_u=unneeded_reg[i+2];
6571             temp_uu=unneeded_reg_upper[i+2];
6572           }
6573           // Merge in delay slot
6574           tdep=(~temp_uu>>rt1[i+1])&1;
6575           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6576           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6577           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6578           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6579           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6580           temp_u|=1;temp_uu|=1;
6581           // If branch is "likely" (and conditional)
6582           // then we skip the delay slot on the fall-thru path
6583           if(likely[i]) {
6584             if(i<slen-1) {
6585               temp_u&=unneeded_reg[i+2];
6586               temp_uu&=unneeded_reg_upper[i+2];
6587             }
6588             else
6589             {
6590               temp_u=1;
6591               temp_uu=1;
6592             }
6593           }
6594           tdep=(~temp_uu>>rt1[i])&1;
6595           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6596           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6597           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6598           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6599           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6600           temp_u|=1;temp_uu|=1;
6601           unneeded_reg[i]=temp_u;
6602           unneeded_reg_upper[i]=temp_uu;
6603           // Only go three levels deep.  This recursion can take an
6604           // excessive amount of time if there are a lot of nested loops.
6605           if(r<2) {
6606             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6607           }else{
6608             unneeded_reg[(ba[i]-start)>>2]=1;
6609             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6610           }
6611         } /*else*/ if(1) {
6612           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6613           {
6614             // Unconditional branch
6615             u=unneeded_reg[(ba[i]-start)>>2];
6616             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6617             branch_unneeded_reg[i]=u;
6618             branch_unneeded_reg_upper[i]=uu;
6619         //u=1;
6620         //uu=1;
6621         //branch_unneeded_reg[i]=u;
6622         //branch_unneeded_reg_upper[i]=uu;
6623             // Merge in delay slot
6624             tdep=(~uu>>rt1[i+1])&1;
6625             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6626             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6627             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6628             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6629             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6630             u|=1;uu|=1;
6631           } else {
6632             // Conditional branch
6633             b=unneeded_reg[(ba[i]-start)>>2];
6634             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6635             branch_unneeded_reg[i]=b;
6636             branch_unneeded_reg_upper[i]=bu;
6637         //b=1;
6638         //bu=1;
6639         //branch_unneeded_reg[i]=b;
6640         //branch_unneeded_reg_upper[i]=bu;
6641             // Branch delay slot
6642             tdep=(~uu>>rt1[i+1])&1;
6643             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6644             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6645             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6646             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6647             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6648             b|=1;bu|=1;
6649             // If branch is "likely" then we skip the
6650             // delay slot on the fall-thru path
6651             if(likely[i]) {
6652               u=b;
6653               uu=bu;
6654               if(i<slen-1) {
6655                 u&=unneeded_reg[i+2];
6656                 uu&=unneeded_reg_upper[i+2];
6657         //u=1;
6658         //uu=1;
6659               }
6660             } else {
6661               u&=b;
6662               uu&=bu;
6663         //u=1;
6664         //uu=1;
6665             }
6666             if(i<slen-1) {
6667               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6668               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6669         //branch_unneeded_reg[i]=1;
6670         //branch_unneeded_reg_upper[i]=1;
6671             } else {
6672               branch_unneeded_reg[i]=1;
6673               branch_unneeded_reg_upper[i]=1;
6674             }
6675           }
6676         }
6677       }
6678     }
6679     else if(itype[i]==SYSCALL)
6680     {
6681       // SYSCALL instruction (software interrupt)
6682       u=1;
6683       uu=1;
6684     }
6685     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6686     {
6687       // ERET instruction (return from interrupt)
6688       u=1;
6689       uu=1;
6690     }
6691     //u=uu=1; // DEBUG
6692     tdep=(~uu>>rt1[i])&1;
6693     // Written registers are unneeded
6694     u|=1LL<<rt1[i];
6695     u|=1LL<<rt2[i];
6696     uu|=1LL<<rt1[i];
6697     uu|=1LL<<rt2[i];
6698     // Accessed registers are needed
6699     u&=~(1LL<<rs1[i]);
6700     u&=~(1LL<<rs2[i]);
6701     uu&=~(1LL<<us1[i]);
6702     uu&=~(1LL<<us2[i]);
6703     // Source-target dependencies
6704     uu&=~(tdep<<dep1[i]);
6705     uu&=~(tdep<<dep2[i]);
6706     // R0 is always unneeded
6707     u|=1;uu|=1;
6708     // Save it
6709     unneeded_reg[i]=u;
6710     unneeded_reg_upper[i]=uu;
6711     /*
6712     DebugMessage(M64MSG_VERBOSE, "ur (%d,%d) %x: ",istart,iend,start+i*4);
6713     DebugMessage(M64MSG_VERBOSE, "U:");
6714     int r;
6715     for(r=1;r<=CCREG;r++) {
6716       if((unneeded_reg[i]>>r)&1) {
6717         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6718         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6719         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6720       }
6721     }
6722     DebugMessage(M64MSG_VERBOSE, " UU:");
6723     for(r=1;r<=CCREG;r++) {
6724       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6725         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
6726         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
6727         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
6728       }
6729     }*/
6730   }
6731 }
6732
6733 // Identify registers which are likely to contain 32-bit values
6734 // This is used to predict whether any branches will jump to a
6735 // location with 64-bit values in registers.
6736 static void provisional_32bit()
6737 {
6738   int i,j;
6739   uint64_t is32=1;
6740   uint64_t lastbranch=1;
6741
6742   for(i=0;i<slen;i++)
6743   {
6744     if(i>0) {
6745       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6746         if(i>1) is32=lastbranch;
6747         else is32=1;
6748       }
6749     }
6750     if(i>1)
6751     {
6752       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6753         if(likely[i-2]) {
6754           if(i>2) is32=lastbranch;
6755           else is32=1;
6756         }
6757       }
6758       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6759       {
6760         if(rs1[i-2]==0||rs2[i-2]==0)
6761         {
6762           if(rs1[i-2]) {
6763             is32|=1LL<<rs1[i-2];
6764           }
6765           if(rs2[i-2]) {
6766             is32|=1LL<<rs2[i-2];
6767           }
6768         }
6769       }
6770     }
6771     // If something jumps here with 64-bit values
6772     // then promote those registers to 64 bits
6773     if(bt[i])
6774     {
6775       uint64_t temp_is32=is32;
6776       for(j=i-1;j>=0;j--)
6777       {
6778         if(ba[j]==start+i*4)
6779           //temp_is32&=branch_regs[j].is32;
6780           temp_is32&=p32[j];
6781       }
6782       for(j=i;j<slen;j++)
6783       {
6784         if(ba[j]==start+i*4)
6785           temp_is32=1;
6786       }
6787       is32=temp_is32;
6788     }
6789     int type=itype[i];
6790     int op=opcode[i];
6791     int op2=opcode2[i];
6792     int rt=rt1[i];
6793     int s1=rs1[i];
6794     int s2=rs2[i];
6795     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6796       // Branches don't write registers, consider the delay slot instead.
6797       type=itype[i+1];
6798       op=opcode[i+1];
6799       op2=opcode2[i+1];
6800       rt=rt1[i+1];
6801       s1=rs1[i+1];
6802       s2=rs2[i+1];
6803       lastbranch=is32;
6804     }
6805     switch(type) {
6806       case LOAD:
6807         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6808            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6809           is32&=~(1LL<<rt);
6810         else
6811           is32|=1LL<<rt;
6812         break;
6813       case STORE:
6814       case STORELR:
6815         break;
6816       case LOADLR:
6817         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6818         if(op==0x22) is32|=1LL<<rt; // LWL
6819         break;
6820       case IMM16:
6821         if (op==0x08||op==0x09|| // ADDI/ADDIU
6822             op==0x0a||op==0x0b|| // SLTI/SLTIU
6823             op==0x0c|| // ANDI
6824             op==0x0f)  // LUI
6825         {
6826           is32|=1LL<<rt;
6827         }
6828         if(op==0x18||op==0x19) { // DADDI/DADDIU
6829           is32&=~(1LL<<rt);
6830           //if(imm[i]==0)
6831           //  is32|=((is32>>s1)&1LL)<<rt;
6832         }
6833         if(op==0x0d||op==0x0e) { // ORI/XORI
6834           uint64_t sr=((is32>>s1)&1LL);
6835           is32&=~(1LL<<rt);
6836           is32|=sr<<rt;
6837         }
6838         break;
6839       case UJUMP:
6840         break;
6841       case RJUMP:
6842         break;
6843       case CJUMP:
6844         break;
6845       case SJUMP:
6846         break;
6847       case FJUMP:
6848         break;
6849       case ALU:
6850         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6851           is32|=1LL<<rt;
6852         }
6853         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6854           is32|=1LL<<rt;
6855         }
6856         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6857           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6858           is32&=~(1LL<<rt);
6859           is32|=sr<<rt;
6860         }
6861         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6862           if(s1==0&&s2==0) {
6863             is32|=1LL<<rt;
6864           }
6865           else if(s2==0) {
6866             uint64_t sr=((is32>>s1)&1LL);
6867             is32&=~(1LL<<rt);
6868             is32|=sr<<rt;
6869           }
6870           else if(s1==0) {
6871             uint64_t sr=((is32>>s2)&1LL);
6872             is32&=~(1LL<<rt);
6873             is32|=sr<<rt;
6874           }
6875           else {
6876             is32&=~(1LL<<rt);
6877           }
6878         }
6879         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6880           if(s1==0&&s2==0) {
6881             is32|=1LL<<rt;
6882           }
6883           else if(s2==0) {
6884             uint64_t sr=((is32>>s1)&1LL);
6885             is32&=~(1LL<<rt);
6886             is32|=sr<<rt;
6887           }
6888           else {
6889             is32&=~(1LL<<rt);
6890           }
6891         }
6892         break;
6893       case MULTDIV:
6894         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6895           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6896         }
6897         else {
6898           is32|=(1LL<<HIREG)|(1LL<<LOREG);
6899         }
6900         break;
6901       case MOV:
6902         {
6903           uint64_t sr=((is32>>s1)&1LL);
6904           is32&=~(1LL<<rt);
6905           is32|=sr<<rt;
6906         }
6907         break;
6908       case SHIFT:
6909         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6910         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6911         break;
6912       case SHIFTIMM:
6913         is32|=1LL<<rt;
6914         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6915         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6916         break;
6917       case COP0:
6918         if(op2==0) is32|=1LL<<rt; // MFC0
6919         break;
6920       case COP1:
6921         if(op2==0) is32|=1LL<<rt; // MFC1
6922         if(op2==1) is32&=~(1LL<<rt); // DMFC1
6923         if(op2==2) is32|=1LL<<rt; // CFC1
6924         break;
6925       case C1LS:
6926         break;
6927       case FLOAT:
6928       case FCONV:
6929         break;
6930       case FCOMP:
6931         break;
6932       case SYSCALL:
6933         break;
6934       default:
6935         break;
6936     }
6937     is32|=1;
6938     p32[i]=is32;
6939
6940     if(i>0)
6941     {
6942       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6943       {
6944         if(rt1[i-1]==31) // JAL/JALR
6945         {
6946           // Subroutine call will return here, don't alloc any registers
6947           is32=1;
6948         }
6949         else if(i+1<slen)
6950         {
6951           // Internal branch will jump here, match registers to caller
6952           is32=0x3FFFFFFFFLL;
6953         }
6954       }
6955     }
6956   }
6957 }
6958
6959 // Identify registers which may be assumed to contain 32-bit values
6960 // and where optimizations will rely on this.
6961 // This is used to determine whether backward branches can safely
6962 // jump to a location with 64-bit values in registers.
6963 static void provisional_r32()
6964 {
6965   u_int r32=0;
6966   int i;
6967
6968   for (i=slen-1;i>=0;i--)
6969   {
6970     int hr;
6971     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6972     {
6973       if(ba[i]<start || ba[i]>=(start+slen*4))
6974       {
6975         // Branch out of this block, don't need anything
6976         r32=0;
6977       }
6978       else
6979       {
6980         // Internal branch
6981         // Need whatever matches the target
6982         // (and doesn't get overwritten by the delay slot instruction)
6983         r32=0;
6984         int t=(ba[i]-start)>>2;
6985         if(ba[i]>start+i*4) {
6986           // Forward branch
6987           //if(!(requires_32bit[t]&~regs[i].was32))
6988           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6989           if(!(pr32[t]&~regs[i].was32))
6990             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6991         }else{
6992           // Backward branch
6993           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
6994             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
6995         }
6996       }
6997       // Conditional branch may need registers for following instructions
6998       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
6999       {
7000         if(i<slen-2) {
7001           //r32|=requires_32bit[i+2];
7002           r32|=pr32[i+2];
7003           r32&=regs[i].was32;
7004           // Mark this address as a branch target since it may be called
7005           // upon return from interrupt
7006           //bt[i+2]=1;
7007         }
7008       }
7009       // Merge in delay slot
7010       if(!likely[i]) {
7011         // These are overwritten unless the branch is "likely"
7012         // and the delay slot is nullified if not taken
7013         r32&=~(1LL<<rt1[i+1]);
7014         r32&=~(1LL<<rt2[i+1]);
7015       }
7016       // Assume these are needed (delay slot)
7017       if(us1[i+1]>0)
7018       {
7019         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7020       }
7021       if(us2[i+1]>0)
7022       {
7023         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7024       }
7025       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7026       {
7027         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7028       }
7029       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7030       {
7031         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7032       }
7033     }
7034     else if(itype[i]==SYSCALL)
7035     {
7036       // SYSCALL instruction (software interrupt)
7037       r32=0;
7038     }
7039     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7040     {
7041       // ERET instruction (return from interrupt)
7042       r32=0;
7043     }
7044     // Check 32 bits
7045     r32&=~(1LL<<rt1[i]);
7046     r32&=~(1LL<<rt2[i]);
7047     if(us1[i]>0)
7048     {
7049       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7050     }
7051     if(us2[i]>0)
7052     {
7053       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7054     }
7055     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7056     {
7057       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7058     }
7059     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7060     {
7061       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7062     }
7063     //requires_32bit[i]=r32;
7064     pr32[i]=r32;
7065
7066     // Dirty registers which are 32-bit, require 32-bit input
7067     // as they will be written as 32-bit values
7068     for(hr=0;hr<HOST_REGS;hr++)
7069     {
7070       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7071         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7072           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7073           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7074           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7075         }
7076       }
7077     }
7078   }
7079 }
7080
7081 // Write back dirty registers as soon as we will no longer modify them,
7082 // so that we don't end up with lots of writes at the branches.
7083 static void clean_registers(int istart,int iend,int wr)
7084 {
7085   int i;
7086   int r;
7087   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7088   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7089   if(iend==slen-1) {
7090     will_dirty_i=will_dirty_next=0;
7091     wont_dirty_i=wont_dirty_next=0;
7092   }else{
7093     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7094     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7095   }
7096   for (i=iend;i>=istart;i--)
7097   {
7098     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7099     {
7100       if(ba[i]<start || ba[i]>=(start+slen*4))
7101       {
7102         // Branch out of this block, flush all regs
7103         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7104         {
7105           // Unconditional branch
7106           will_dirty_i=0;
7107           wont_dirty_i=0;
7108           // Merge in delay slot (will dirty)
7109           for(r=0;r<HOST_REGS;r++) {
7110             if(r!=EXCLUDE_REG) {
7111               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7112               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7113               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7114               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7115               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7116               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7117               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7118               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7119               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7120               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7121               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7122               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7123               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7124               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7125             }
7126           }
7127         }
7128         else
7129         {
7130           // Conditional branch
7131           will_dirty_i=0;
7132           wont_dirty_i=wont_dirty_next;
7133           // Merge in delay slot (will dirty)
7134           for(r=0;r<HOST_REGS;r++) {
7135             if(r!=EXCLUDE_REG) {
7136               if(!likely[i]) {
7137                 // Might not dirty if likely branch is not taken
7138                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7139                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7140                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7141                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7142                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7143                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7144                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7145                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7146                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7147                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7148                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7149                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7150                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7151                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7152               }
7153             }
7154           }
7155         }
7156         // Merge in delay slot (wont dirty)
7157         for(r=0;r<HOST_REGS;r++) {
7158           if(r!=EXCLUDE_REG) {
7159             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7160             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7161             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7162             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7163             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7164             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7165             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7166             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7167             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7168             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7169           }
7170         }
7171         if(wr) {
7172           #ifndef DESTRUCTIVE_WRITEBACK
7173           branch_regs[i].dirty&=wont_dirty_i;
7174           #endif
7175           branch_regs[i].dirty|=will_dirty_i;
7176         }
7177       }
7178       else
7179       {
7180         // Internal branch
7181         if(ba[i]<=start+i*4) {
7182           // Backward branch
7183           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7184           {
7185             // Unconditional branch
7186             temp_will_dirty=0;
7187             temp_wont_dirty=0;
7188             // Merge in delay slot (will dirty)
7189             for(r=0;r<HOST_REGS;r++) {
7190               if(r!=EXCLUDE_REG) {
7191                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7192                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7193                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7194                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7195                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7196                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7197                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7198                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7199                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7200                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7201                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7202                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7203                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7204                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7205               }
7206             }
7207           } else {
7208             // Conditional branch (not taken case)
7209             temp_will_dirty=will_dirty_next;
7210             temp_wont_dirty=wont_dirty_next;
7211             // Merge in delay slot (will dirty)
7212             for(r=0;r<HOST_REGS;r++) {
7213               if(r!=EXCLUDE_REG) {
7214                 if(!likely[i]) {
7215                   // Will not dirty if likely branch is not taken
7216                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7217                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7218                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7219                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7220                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7221                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7222                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7223                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7224                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7225                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7226                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7227                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7228                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7229                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7230                 }
7231               }
7232             }
7233           }
7234           // Merge in delay slot (wont dirty)
7235           for(r=0;r<HOST_REGS;r++) {
7236             if(r!=EXCLUDE_REG) {
7237               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7238               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7239               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7240               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7241               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7242               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7243               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7244               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7245               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7246               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7247             }
7248           }
7249           // Deal with changed mappings
7250           if(i<iend) {
7251             for(r=0;r<HOST_REGS;r++) {
7252               if(r!=EXCLUDE_REG) {
7253                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7254                   temp_will_dirty&=~(1<<r);
7255                   temp_wont_dirty&=~(1<<r);
7256                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7257                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7258                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7259                   } else {
7260                     temp_will_dirty|=1<<r;
7261                     temp_wont_dirty|=1<<r;
7262                   }
7263                 }
7264               }
7265             }
7266           }
7267           if(wr) {
7268             will_dirty[i]=temp_will_dirty;
7269             wont_dirty[i]=temp_wont_dirty;
7270             clean_registers((ba[i]-start)>>2,i-1,0);
7271           }else{
7272             // Limit recursion.  It can take an excessive amount
7273             // of time if there are a lot of nested loops.
7274             will_dirty[(ba[i]-start)>>2]=0;
7275             wont_dirty[(ba[i]-start)>>2]=-1;
7276           }
7277         }
7278         /*else*/ if(1)
7279         {
7280           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7281           {
7282             // Unconditional branch
7283             will_dirty_i=0;
7284             wont_dirty_i=0;
7285           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7286             for(r=0;r<HOST_REGS;r++) {
7287               if(r!=EXCLUDE_REG) {
7288                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7289                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7290                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7291                 }
7292                 if(branch_regs[i].regmap[r]>=0) {
7293                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7294                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7295                 }
7296               }
7297             }
7298           //}
7299             // Merge in delay slot
7300             for(r=0;r<HOST_REGS;r++) {
7301               if(r!=EXCLUDE_REG) {
7302                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7303                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7304                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7305                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7306                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7307                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7308                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7309                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7310                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7311                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7312                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7313                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7314                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7315                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7316               }
7317             }
7318           } else {
7319             // Conditional branch
7320             will_dirty_i=will_dirty_next;
7321             wont_dirty_i=wont_dirty_next;
7322           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7323             for(r=0;r<HOST_REGS;r++) {
7324               if(r!=EXCLUDE_REG) {
7325                 signed char target_reg=branch_regs[i].regmap[r];
7326                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7327                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7328                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7329                 }
7330                 else if(target_reg>=0) {
7331                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7332                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7333                 }
7334                 // Treat delay slot as part of branch too
7335                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7336                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7337                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7338                 }
7339                 else
7340                 {
7341                   will_dirty[i+1]&=~(1<<r);
7342                 }*/
7343               }
7344             }
7345           //}
7346             // Merge in delay slot
7347             for(r=0;r<HOST_REGS;r++) {
7348               if(r!=EXCLUDE_REG) {
7349                 if(!likely[i]) {
7350                   // Might not dirty if likely branch is not taken
7351                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7352                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7353                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7354                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7355                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7356                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7357                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7358                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7359                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7360                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7361                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7362                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7363                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7364                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7365                 }
7366               }
7367             }
7368           }
7369           // Merge in delay slot (won't dirty)
7370           for(r=0;r<HOST_REGS;r++) {
7371             if(r!=EXCLUDE_REG) {
7372               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7373               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7374               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7375               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7376               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7377               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7378               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7379               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7380               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7381               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7382             }
7383           }
7384           if(wr) {
7385             #ifndef DESTRUCTIVE_WRITEBACK
7386             branch_regs[i].dirty&=wont_dirty_i;
7387             #endif
7388             branch_regs[i].dirty|=will_dirty_i;
7389           }
7390         }
7391       }
7392     }
7393     else if(itype[i]==SYSCALL)
7394     {
7395       // SYSCALL instruction (software interrupt)
7396       will_dirty_i=0;
7397       wont_dirty_i=0;
7398     }
7399     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7400     {
7401       // ERET instruction (return from interrupt)
7402       will_dirty_i=0;
7403       wont_dirty_i=0;
7404     }
7405     will_dirty_next=will_dirty_i;
7406     wont_dirty_next=wont_dirty_i;
7407     for(r=0;r<HOST_REGS;r++) {
7408       if(r!=EXCLUDE_REG) {
7409         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7410         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7411         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7412         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7413         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7414         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7415         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7416         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7417         if(i>istart) {
7418           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7419           {
7420             // Don't store a register immediately after writing it,
7421             // may prevent dual-issue.
7422             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7423             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7424           }
7425         }
7426       }
7427     }
7428     // Save it
7429     will_dirty[i]=will_dirty_i;
7430     wont_dirty[i]=wont_dirty_i;
7431     // Mark registers that won't be dirtied as not dirty
7432     if(wr) {
7433       /*DebugMessage(M64MSG_VERBOSE, "wr (%d,%d) %x will:",istart,iend,start+i*4);
7434       for(r=0;r<HOST_REGS;r++) {
7435         if((will_dirty_i>>r)&1) {
7436           DebugMessage(M64MSG_VERBOSE, " r%d",r);
7437         }
7438       }*/
7439
7440       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7441         regs[i].dirty|=will_dirty_i;
7442         #ifndef DESTRUCTIVE_WRITEBACK
7443         regs[i].dirty&=wont_dirty_i;
7444         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7445         {
7446           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7447             for(r=0;r<HOST_REGS;r++) {
7448               if(r!=EXCLUDE_REG) {
7449                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7450                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7451                 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+2): %d",start+i*4,i,r); / *assert(!((wont_dirty_i>>r)&1));*/}
7452               }
7453             }
7454           }
7455         }
7456         else
7457         {
7458           if(i<iend) {
7459             for(r=0;r<HOST_REGS;r++) {
7460               if(r!=EXCLUDE_REG) {
7461                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7462                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7463                 }else {/*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch(+1): %d",start+i*4,i,r);/ *assert(!((wont_dirty_i>>r)&1));*/}
7464               }
7465             }
7466           }
7467         }
7468         #endif
7469       //}
7470     }
7471     // Deal with changed mappings
7472     temp_will_dirty=will_dirty_i;
7473     temp_wont_dirty=wont_dirty_i;
7474     for(r=0;r<HOST_REGS;r++) {
7475       if(r!=EXCLUDE_REG) {
7476         int nr;
7477         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7478           if(wr) {
7479             #ifndef DESTRUCTIVE_WRITEBACK
7480             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7481             #endif
7482             regs[i].wasdirty|=will_dirty_i&(1<<r);
7483           }
7484         }
7485         else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7486           // Register moved to a different register
7487           will_dirty_i&=~(1<<r);
7488           wont_dirty_i&=~(1<<r);
7489           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7490           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7491           if(wr) {
7492             #ifndef DESTRUCTIVE_WRITEBACK
7493             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7494             #endif
7495             regs[i].wasdirty|=will_dirty_i&(1<<r);
7496           }
7497         }
7498         else {
7499           will_dirty_i&=~(1<<r);
7500           wont_dirty_i&=~(1<<r);
7501           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7502             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7503             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7504           } else {
7505             wont_dirty_i|=1<<r;
7506             /*DebugMessage(M64MSG_VERBOSE, "i: %x (%d) mismatch: %d",start+i*4,i,r);/ *assert(!((will_dirty>>r)&1));*/
7507           }
7508         }
7509       }
7510     }
7511   }
7512 }
7513
7514 #ifdef ASSEM_DEBUG
7515   /* disassembly */
7516 static void disassemble_inst(int i)
7517 {
7518     if (bt[i]) DebugMessage(M64MSG_VERBOSE, "*"); else DebugMessage(M64MSG_VERBOSE, " ");
7519     switch(itype[i]) {
7520       case UJUMP:
7521         printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7522       case CJUMP:
7523         printf (" %x: %s r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7524       case SJUMP:
7525         printf (" %x: %s r%d,%8x",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7526       case FJUMP:
7527         printf (" %x: %s %8x",start+i*4,insn[i],ba[i]);break;
7528       case RJUMP:
7529         if ((opcode2[i]&1)&&rt1[i]!=31)
7530           printf (" %x: %s r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i]);
7531         else
7532           printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7533         break;
7534       case SPAN:
7535         printf (" %x: %s (pagespan) r%d,r%d,%8x",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7536       case IMM16:
7537         if(opcode[i]==0xf) //LUI
7538           printf (" %x: %s r%d,%4x0000",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7539         else
7540           printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7541         break;
7542       case LOAD:
7543       case LOADLR:
7544         printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7545         break;
7546       case STORE:
7547       case STORELR:
7548         printf (" %x: %s r%d,r%d+%x",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7549         break;
7550       case ALU:
7551       case SHIFT:
7552         printf (" %x: %s r%d,r%d,r%d",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7553         break;
7554       case MULTDIV:
7555         printf (" %x: %s r%d,r%d",start+i*4,insn[i],rs1[i],rs2[i]);
7556         break;
7557       case SHIFTIMM:
7558         printf (" %x: %s r%d,r%d,%d",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7559         break;
7560       case MOV:
7561         if((opcode2[i]&0x1d)==0x10)
7562           printf (" %x: %s r%d",start+i*4,insn[i],rt1[i]);
7563         else if((opcode2[i]&0x1d)==0x11)
7564           printf (" %x: %s r%d",start+i*4,insn[i],rs1[i]);
7565         else
7566           printf (" %x: %s",start+i*4,insn[i]);
7567         break;
7568       case COP0:
7569         if(opcode2[i]==0)
7570           printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7571         else if(opcode2[i]==4)
7572           printf (" %x: %s r%d,cpr0[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7573         else printf (" %x: %s",start+i*4,insn[i]);
7574         break;
7575       case COP1:
7576         if(opcode2[i]<3)
7577           printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7578         else if(opcode2[i]>3)
7579           printf (" %x: %s r%d,cpr1[%d]",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7580         else printf (" %x: %s",start+i*4,insn[i]);
7581         break;
7582       case C1LS:
7583         printf (" %x: %s cpr1[%d],r%d+%x",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7584         break;
7585       default:
7586         //printf (" %s %8x",insn[i],source[i]);
7587         printf (" %x: %s",start+i*4,insn[i]);
7588     }
7589 }
7590 #endif
7591
7592 void new_dynarec_init()
7593 {
7594   DebugMessage(M64MSG_INFO, "Init new dynarec");
7595
7596 #if NEW_DYNAREC == NEW_DYNAREC_ARM
7597   if ((base_addr = mmap ((u_char *)BASE_ADDR, 1<<TARGET_SIZE_2,
7598             PROT_READ | PROT_WRITE | PROT_EXEC,
7599             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7600             -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7601 #else
7602   if ((base_addr = mmap (NULL, 1<<TARGET_SIZE_2,
7603             PROT_READ | PROT_WRITE | PROT_EXEC,
7604             MAP_PRIVATE | MAP_ANONYMOUS,
7605             -1, 0)) <= 0) {DebugMessage(M64MSG_ERROR, "mmap() failed");}
7606 #endif
7607   out=(u_char *)base_addr;
7608
7609   rdword=&readmem_dword;
7610   fake_pc.f.r.rs=(long long int *)&readmem_dword;
7611   fake_pc.f.r.rt=(long long int *)&readmem_dword;
7612   fake_pc.f.r.rd=(long long int *)&readmem_dword;
7613   int n;
7614   for(n=0x80000;n<0x80800;n++)
7615     invalid_code[n]=1;
7616   for(n=0;n<65536;n++)
7617     hash_table[n][0]=hash_table[n][2]=-1;
7618   memset(mini_ht,-1,sizeof(mini_ht));
7619   memset(restore_candidate,0,sizeof(restore_candidate));
7620   copy=shadow;
7621   expirep=16384; // Expiry pointer, +2 blocks
7622   pending_exception=0;
7623   literalcount=0;
7624 #ifdef HOST_IMM8
7625   // Copy this into local area so we don't have to put it in every literal pool
7626   invc_ptr=invalid_code;
7627 #endif
7628   stop_after_jal=0;
7629   // TLB
7630   using_tlb=0;
7631   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7632     memory_map[n]=-1;
7633   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7634     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7635   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7636     memory_map[n]=-1;
7637   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7638     writemem[n] = write_nomem_new;
7639     writememb[n] = write_nomemb_new;
7640     writememh[n] = write_nomemh_new;
7641     writememd[n] = write_nomemd_new;
7642     readmem[n] = read_nomem_new;
7643     readmemb[n] = read_nomemb_new;
7644     readmemh[n] = read_nomemh_new;
7645     readmemd[n] = read_nomemd_new;
7646   }
7647   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7648     writemem[n] = write_rdram_new;
7649     writememb[n] = write_rdramb_new;
7650     writememh[n] = write_rdramh_new;
7651     writememd[n] = write_rdramd_new;
7652   }
7653   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7654     writemem[n] = write_nomem_new;
7655     writememb[n] = write_nomemb_new;
7656     writememh[n] = write_nomemh_new;
7657     writememd[n] = write_nomemd_new;
7658     readmem[n] = read_nomem_new;
7659     readmemb[n] = read_nomemb_new;
7660     readmemh[n] = read_nomemh_new;
7661     readmemd[n] = read_nomemd_new;
7662   }
7663   tlb_hacks();
7664   arch_init();
7665 }
7666
7667 void new_dynarec_cleanup()
7668 {
7669   int n;
7670   if (munmap (base_addr, 1<<TARGET_SIZE_2) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7671   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7672   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7673   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7674   #ifdef ROM_COPY
7675   if (munmap (ROM_COPY, 67108864) < 0) {DebugMessage(M64MSG_ERROR, "munmap() failed");}
7676   #endif
7677 }
7678
7679 int new_recompile_block(int addr)
7680 {
7681 /*
7682   if(addr==0x800cd050) {
7683     int block;
7684     for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7685     int n;
7686     for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7687   }
7688 */
7689   //if(Count==365117028) tracedebug=1;
7690   assem_debug("NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7691 #if defined (COUNT_NOTCOMPILEDS )
7692   notcompiledCount++;
7693   log_message( "notcompiledCount=%i", notcompiledCount );
7694 #endif
7695   //DebugMessage(M64MSG_VERBOSE, "NOTCOMPILED: addr = %x -> %x", (int)addr, (int)out);
7696   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (compile %x)",Count,next_interupt,addr);
7697   //if(debug)
7698   //DebugMessage(M64MSG_VERBOSE, "TRACE: count=%d next=%d (checksum %x)",Count,next_interupt,mchecksum());
7699   //DebugMessage(M64MSG_VERBOSE, "fpu mapping=%x enabled=%x",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7700   /*if(Count>=312978186) {
7701     rlist();
7702   }*/
7703   //rlist();
7704   start = (u_int)addr&~3;
7705   //assert(((u_int)addr&1)==0);
7706   if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7707     source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7708     pagelimit = 0xa4001000;
7709   }
7710   else if ((int)addr >= 0x80000000 && (int)addr < 0x80800000) {
7711     source = (u_int *)((u_int)rdram+start-0x80000000);
7712     pagelimit = 0x80800000;
7713   }
7714   else if ((signed int)addr >= (signed int)0xC0000000) {
7715     //DebugMessage(M64MSG_VERBOSE, "addr=%x mm=%x",(u_int)addr,(memory_map[start>>12]<<2));
7716     //if(tlb_LUT_r[start>>12])
7717       //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7718     if((signed int)memory_map[start>>12]>=0) {
7719       source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7720       pagelimit=(start+4096)&0xFFFFF000;
7721       int map=memory_map[start>>12];
7722       int i;
7723       for(i=0;i<5;i++) {
7724         //DebugMessage(M64MSG_VERBOSE, "start: %x next: %x",map,memory_map[pagelimit>>12]);
7725         if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7726       }
7727       assem_debug("pagelimit=%x",pagelimit);
7728       assem_debug("mapping=%x (%x)",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7729     }
7730     else {
7731       assem_debug("Compile at unmapped memory address: %x ", (int)addr);
7732       //assem_debug("start: %x next: %x",memory_map[start>>12],memory_map[(start+4096)>>12]);
7733       return 1; // Caller will invoke exception handler
7734     }
7735     //DebugMessage(M64MSG_VERBOSE, "source= %x",(int)source);
7736   }
7737   else {
7738     //DebugMessage(M64MSG_VERBOSE, "Compile at bogus memory address: %x ", (int)addr);
7739     log_message("Compile at bogus memory address: %x", (int)addr);
7740     exit(1);
7741   }
7742
7743   /* Pass 1: disassemble */
7744   /* Pass 2: register dependencies, branch targets */
7745   /* Pass 3: register allocation */
7746   /* Pass 4: branch dependencies */
7747   /* Pass 5: pre-alloc */
7748   /* Pass 6: optimize clean/dirty state */
7749   /* Pass 7: flag 32-bit registers */
7750   /* Pass 8: assembly */
7751   /* Pass 9: linker */
7752   /* Pass 10: garbage collection / free memory */
7753
7754   int i,j;
7755   int done=0;
7756   unsigned int type,op,op2;
7757
7758   //DebugMessage(M64MSG_VERBOSE, "addr = %x source = %x %x", addr,source,source[0]);
7759
7760   /* Pass 1 disassembly */
7761
7762   for(i=0;!done;i++) {
7763     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7764     minimum_free_regs[i]=0;
7765     opcode[i]=op=source[i]>>26;
7766     switch(op)
7767     {
7768       case 0x00: strcpy(insn[i],"special"); type=NI;
7769         op2=source[i]&0x3f;
7770         switch(op2)
7771         {
7772           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7773           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7774           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7775           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7776           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7777           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7778           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7779           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7780           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7781           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7782           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7783           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7784           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7785           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7786           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7787           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7788           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7789           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7790           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7791           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7792           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7793           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7794           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7795           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7796           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7797           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7798           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7799           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7800           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7801           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7802           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7803           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7804           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7805           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7806           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7807           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7808           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7809           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7810           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7811           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7812           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7813           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7814           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7815           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7816           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7817           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7818           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7819           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7820           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7821           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7822           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7823           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7824         }
7825         break;
7826       case 0x01: strcpy(insn[i],"regimm"); type=NI;
7827         op2=(source[i]>>16)&0x1f;
7828         switch(op2)
7829         {
7830           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7831           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7832           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7833           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7834           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7835           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7836           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7837           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7838           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7839           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7840           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7841           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7842           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7843           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7844         }
7845         break;
7846       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7847       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7848       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7849       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7850       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7851       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7852       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7853       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7854       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7855       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7856       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7857       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7858       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7859       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7860       case 0x10: strcpy(insn[i],"cop0"); type=NI;
7861         op2=(source[i]>>21)&0x1f;
7862         switch(op2)
7863         {
7864           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7865           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7866           case 0x10: strcpy(insn[i],"tlb"); type=NI;
7867           switch(source[i]&0x3f)
7868           {
7869             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7870             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7871             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7872             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7873             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7874           }
7875         }
7876         break;
7877       case 0x11: strcpy(insn[i],"cop1"); type=NI;
7878         op2=(source[i]>>21)&0x1f;
7879         switch(op2)
7880         {
7881           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7882           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7883           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7884           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7885           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7886           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7887           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7888           switch((source[i]>>16)&0x3)
7889           {
7890             case 0x00: strcpy(insn[i],"BC1F"); break;
7891             case 0x01: strcpy(insn[i],"BC1T"); break;
7892             case 0x02: strcpy(insn[i],"BC1FL"); break;
7893             case 0x03: strcpy(insn[i],"BC1TL"); break;
7894           }
7895           break;
7896           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7897           switch(source[i]&0x3f)
7898           {
7899             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7900             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7901             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7902             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7903             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7904             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7905             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7906             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7907             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7908             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7909             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7910             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7911             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7912             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7913             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7914             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7915             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7916             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7917             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7918             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7919             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7920             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7921             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7922             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7923             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7924             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7925             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7926             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7927             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7928             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7929             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7930             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7931             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7932             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7933             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7934           }
7935           break;
7936           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7937           switch(source[i]&0x3f)
7938           {
7939             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7940             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7941             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7942             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7943             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7944             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7945             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7946             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7947             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7948             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7949             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7950             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7951             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7952             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7953             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7954             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7955             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7956             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7957             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7958             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7959             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7960             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7961             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7962             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7963             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7964             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7965             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7966             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7967             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7968             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7969             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7970             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7971             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7972             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7973             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7974           }
7975           break;
7976           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7977           switch(source[i]&0x3f)
7978           {
7979             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7980             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7981           }
7982           break;
7983           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7984           switch(source[i]&0x3f)
7985           {
7986             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7987             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7988           }
7989           break;
7990         }
7991         break;
7992       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7993       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7994       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7995       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7996       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7997       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7998       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7999       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8000       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8001       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8002       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8003       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8004       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8005       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8006       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8007       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8008       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8009       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8010       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8011       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8012       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8013       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8014       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8015       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8016       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8017       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8018       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8019       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8020       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8021       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8022       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8023       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8024       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8025       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8026       default: strcpy(insn[i],"???"); type=NI; break;
8027     }
8028     itype[i]=type;
8029     opcode2[i]=op2;
8030     /* Get registers/immediates */
8031     lt1[i]=0;
8032     us1[i]=0;
8033     us2[i]=0;
8034     dep1[i]=0;
8035     dep2[i]=0;
8036     switch(type) {
8037       case LOAD:
8038         rs1[i]=(source[i]>>21)&0x1f;
8039         rs2[i]=0;
8040         rt1[i]=(source[i]>>16)&0x1f;
8041         rt2[i]=0;
8042         imm[i]=(short)source[i];
8043         break;
8044       case STORE:
8045       case STORELR:
8046         rs1[i]=(source[i]>>21)&0x1f;
8047         rs2[i]=(source[i]>>16)&0x1f;
8048         rt1[i]=0;
8049         rt2[i]=0;
8050         imm[i]=(short)source[i];
8051         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8052         break;
8053       case LOADLR:
8054         // LWL/LWR only load part of the register,
8055         // therefore the target register must be treated as a source too
8056         rs1[i]=(source[i]>>21)&0x1f;
8057         rs2[i]=(source[i]>>16)&0x1f;
8058         rt1[i]=(source[i]>>16)&0x1f;
8059         rt2[i]=0;
8060         imm[i]=(short)source[i];
8061         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8062         if(op==0x26) dep1[i]=rt1[i]; // LWR
8063         break;
8064       case IMM16:
8065         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8066         else rs1[i]=(source[i]>>21)&0x1f;
8067         rs2[i]=0;
8068         rt1[i]=(source[i]>>16)&0x1f;
8069         rt2[i]=0;
8070         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8071           imm[i]=(unsigned short)source[i];
8072         }else{
8073           imm[i]=(short)source[i];
8074         }
8075         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8076         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8077         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8078         break;
8079       case UJUMP:
8080         rs1[i]=0;
8081         rs2[i]=0;
8082         rt1[i]=0;
8083         rt2[i]=0;
8084         // The JAL instruction writes to r31.
8085         if (op&1) {
8086           rt1[i]=31;
8087         }
8088         rs2[i]=CCREG;
8089         break;
8090       case RJUMP:
8091         rs1[i]=(source[i]>>21)&0x1f;
8092         rs2[i]=0;
8093         rt1[i]=0;
8094         rt2[i]=0;
8095         // The JALR instruction writes to rd.
8096         if (op2&1) {
8097           rt1[i]=(source[i]>>11)&0x1f;
8098         }
8099         rs2[i]=CCREG;
8100         break;
8101       case CJUMP:
8102         rs1[i]=(source[i]>>21)&0x1f;
8103         rs2[i]=(source[i]>>16)&0x1f;
8104         rt1[i]=0;
8105         rt2[i]=0;
8106         if(op&2) { // BGTZ/BLEZ
8107           rs2[i]=0;
8108         }
8109         us1[i]=rs1[i];
8110         us2[i]=rs2[i];
8111         likely[i]=op>>4;
8112         break;
8113       case SJUMP:
8114         rs1[i]=(source[i]>>21)&0x1f;
8115         rs2[i]=CCREG;
8116         rt1[i]=0;
8117         rt2[i]=0;
8118         us1[i]=rs1[i];
8119         if(op2&0x10) { // BxxAL
8120           rt1[i]=31;
8121           // NOTE: If the branch is not taken, r31 is still overwritten
8122         }
8123         likely[i]=(op2&2)>>1;
8124         break;
8125       case FJUMP:
8126         rs1[i]=FSREG;
8127         rs2[i]=CSREG;
8128         rt1[i]=0;
8129         rt2[i]=0;
8130         likely[i]=((source[i])>>17)&1;
8131         break;
8132       case ALU:
8133         rs1[i]=(source[i]>>21)&0x1f; // source
8134         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8135         rt1[i]=(source[i]>>11)&0x1f; // destination
8136         rt2[i]=0;
8137         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8138           us1[i]=rs1[i];us2[i]=rs2[i];
8139         }
8140         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8141           dep1[i]=rs1[i];dep2[i]=rs2[i];
8142         }
8143         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8144           dep1[i]=rs1[i];dep2[i]=rs2[i];
8145         }
8146         break;
8147       case MULTDIV:
8148         rs1[i]=(source[i]>>21)&0x1f; // source
8149         rs2[i]=(source[i]>>16)&0x1f; // divisor
8150         rt1[i]=HIREG;
8151         rt2[i]=LOREG;
8152         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8153           us1[i]=rs1[i];us2[i]=rs2[i];
8154         }
8155         break;
8156       case MOV:
8157         rs1[i]=0;
8158         rs2[i]=0;
8159         rt1[i]=0;
8160         rt2[i]=0;
8161         if(op2==0x10) rs1[i]=HIREG; // MFHI
8162         if(op2==0x11) rt1[i]=HIREG; // MTHI
8163         if(op2==0x12) rs1[i]=LOREG; // MFLO
8164         if(op2==0x13) rt1[i]=LOREG; // MTLO
8165         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8166         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8167         dep1[i]=rs1[i];
8168         break;
8169       case SHIFT:
8170         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8171         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8172         rt1[i]=(source[i]>>11)&0x1f; // destination
8173         rt2[i]=0;
8174         // DSLLV/DSRLV/DSRAV are 64-bit
8175         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8176         break;
8177       case SHIFTIMM:
8178         rs1[i]=(source[i]>>16)&0x1f;
8179         rs2[i]=0;
8180         rt1[i]=(source[i]>>11)&0x1f;
8181         rt2[i]=0;
8182         imm[i]=(source[i]>>6)&0x1f;
8183         // DSxx32 instructions
8184         if(op2>=0x3c) imm[i]|=0x20;
8185         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8186         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8187         break;
8188       case COP0:
8189         rs1[i]=0;
8190         rs2[i]=0;
8191         rt1[i]=0;
8192         rt2[i]=0;
8193         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8194         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8195         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8196         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8197         break;
8198       case COP1:
8199         rs1[i]=0;
8200         rs2[i]=0;
8201         rt1[i]=0;
8202         rt2[i]=0;
8203         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8204         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8205         if(op2==5) us1[i]=rs1[i]; // DMTC1
8206         rs2[i]=CSREG;
8207         break;
8208       case C1LS:
8209         rs1[i]=(source[i]>>21)&0x1F;
8210         rs2[i]=CSREG;
8211         rt1[i]=0;
8212         rt2[i]=0;
8213         imm[i]=(short)source[i];
8214         break;
8215       case FLOAT:
8216       case FCONV:
8217         rs1[i]=0;
8218         rs2[i]=CSREG;
8219         rt1[i]=0;
8220         rt2[i]=0;
8221         break;
8222       case FCOMP:
8223         rs1[i]=FSREG;
8224         rs2[i]=CSREG;
8225         rt1[i]=FSREG;
8226         rt2[i]=0;
8227         break;
8228       case SYSCALL:
8229         rs1[i]=CCREG;
8230         rs2[i]=0;
8231         rt1[i]=0;
8232         rt2[i]=0;
8233         break;
8234       default:
8235         rs1[i]=0;
8236         rs2[i]=0;
8237         rt1[i]=0;
8238         rt2[i]=0;
8239     }
8240     /* Calculate branch target addresses */
8241     if(type==UJUMP)
8242       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8243     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8244       ba[i]=start+i*4+8; // Ignore never taken branch
8245     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8246       ba[i]=start+i*4+8; // Ignore never taken branch
8247     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8248       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8249     else ba[i]=-1;
8250     /* Is this the end of the block? */
8251     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8252       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8253         done=1;
8254         // Does the block continue due to a branch?
8255         for(j=i-1;j>=0;j--)
8256         {
8257           if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8258           if(ba[j]==start+i*4+4) done=j=0;
8259           if(ba[j]==start+i*4+8) done=j=0;
8260         }
8261       }
8262       else {
8263         if(stop_after_jal) done=1;
8264         // Stop on BREAK
8265         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8266       }
8267       // Don't recompile stuff that's already compiled
8268       if(check_addr(start+i*4+4)) done=1;
8269       // Don't get too close to the limit
8270       if(i>MAXBLOCK/2) done=1;
8271     }
8272     if(i>0&&itype[i-1]==SYSCALL&&stop_after_jal) done=1;
8273     assert(i<MAXBLOCK-1);
8274     if(start+i*4==pagelimit-4) done=1;
8275     assert(start+i*4<pagelimit);
8276     if (i==MAXBLOCK-1) done=1;
8277     // Stop if we're compiling junk
8278     if(itype[i]==NI&&opcode[i]==0x11) {
8279       done=stop_after_jal=1;
8280       DebugMessage(M64MSG_VERBOSE, "Disabled speculative precompilation");
8281     }
8282   }
8283   slen=i;
8284   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8285     if(start+i*4==pagelimit) {
8286       itype[i-1]=SPAN;
8287     }
8288   }
8289   assert(slen>0);
8290
8291   /* Pass 2 - Register dependencies and branch targets */
8292
8293   unneeded_registers(0,slen-1,0);
8294
8295   /* Pass 3 - Register allocation */
8296
8297   struct regstat current; // Current register allocations/status
8298   current.is32=1;
8299   current.dirty=0;
8300   current.u=unneeded_reg[0];
8301   current.uu=unneeded_reg_upper[0];
8302   clear_all_regs(current.regmap);
8303   alloc_reg(&current,0,CCREG);
8304   dirty_reg(&current,CCREG);
8305   current.isconst=0;
8306   current.wasconst=0;
8307   int ds=0;
8308   int cc=0;
8309   int hr;
8310
8311   provisional_32bit();
8312
8313   if((u_int)addr&1) {
8314     // First instruction is delay slot
8315     cc=-1;
8316     bt[1]=1;
8317     ds=1;
8318     unneeded_reg[0]=1;
8319     unneeded_reg_upper[0]=1;
8320     current.regmap[HOST_BTREG]=BTREG;
8321   }
8322
8323   for(i=0;i<slen;i++)
8324   {
8325     if(bt[i])
8326     {
8327       int hr;
8328       for(hr=0;hr<HOST_REGS;hr++)
8329       {
8330         // Is this really necessary?
8331         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8332       }
8333       current.isconst=0;
8334     }
8335     if(i>1)
8336     {
8337       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8338       {
8339         if(rs1[i-2]==0||rs2[i-2]==0)
8340         {
8341           if(rs1[i-2]) {
8342             current.is32|=1LL<<rs1[i-2];
8343             int hr=get_reg(current.regmap,rs1[i-2]|64);
8344             if(hr>=0) current.regmap[hr]=-1;
8345           }
8346           if(rs2[i-2]) {
8347             current.is32|=1LL<<rs2[i-2];
8348             int hr=get_reg(current.regmap,rs2[i-2]|64);
8349             if(hr>=0) current.regmap[hr]=-1;
8350           }
8351         }
8352       }
8353     }
8354     // If something jumps here with 64-bit values
8355     // then promote those registers to 64 bits
8356     if(bt[i])
8357     {
8358       uint64_t temp_is32=current.is32;
8359       for(j=i-1;j>=0;j--)
8360       {
8361         if(ba[j]==start+i*4)
8362           temp_is32&=branch_regs[j].is32;
8363       }
8364       for(j=i;j<slen;j++)
8365       {
8366         if(ba[j]==start+i*4)
8367           //temp_is32=1;
8368           temp_is32&=p32[j];
8369       }
8370       if(temp_is32!=current.is32) {
8371         //DebugMessage(M64MSG_VERBOSE, "dumping 32-bit regs (%x)",start+i*4);
8372         #ifndef DESTRUCTIVE_WRITEBACK
8373         if(ds)
8374         #endif
8375         for(hr=0;hr<HOST_REGS;hr++)
8376         {
8377           int r=current.regmap[hr];
8378           if(r>0&&r<64)
8379           {
8380             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8381               temp_is32|=1LL<<r;
8382               //DebugMessage(M64MSG_VERBOSE, "restore %d",r);
8383             }
8384           }
8385         }
8386         current.is32=temp_is32;
8387       }
8388     }
8389     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8390     regs[i].wasconst=current.isconst;
8391     regs[i].was32=current.is32;
8392     regs[i].wasdirty=current.dirty;
8393     #ifdef DESTRUCTIVE_WRITEBACK
8394     // To change a dirty register from 32 to 64 bits, we must write
8395     // it out during the previous cycle (for branches, 2 cycles)
8396     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8397     {
8398       uint64_t temp_is32=current.is32;
8399       for(j=i-1;j>=0;j--)
8400       {
8401         if(ba[j]==start+i*4+4)
8402           temp_is32&=branch_regs[j].is32;
8403       }
8404       for(j=i;j<slen;j++)
8405       {
8406         if(ba[j]==start+i*4+4)
8407           //temp_is32=1;
8408           temp_is32&=p32[j];
8409       }
8410       if(temp_is32!=current.is32) {
8411         //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8412         for(hr=0;hr<HOST_REGS;hr++)
8413         {
8414           int r=current.regmap[hr];
8415           if(r>0)
8416           {
8417             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8418               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8419               {
8420                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8421                 {
8422                   //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8423                   current.regmap[hr]=-1;
8424                   if(get_reg(current.regmap,r|64)>=0)
8425                     current.regmap[get_reg(current.regmap,r|64)]=-1;
8426                 }
8427               }
8428             }
8429           }
8430         }
8431       }
8432     }
8433     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8434     {
8435       uint64_t temp_is32=current.is32;
8436       for(j=i-1;j>=0;j--)
8437       {
8438         if(ba[j]==start+i*4+8)
8439           temp_is32&=branch_regs[j].is32;
8440       }
8441       for(j=i;j<slen;j++)
8442       {
8443         if(ba[j]==start+i*4+8)
8444           //temp_is32=1;
8445           temp_is32&=p32[j];
8446       }
8447       if(temp_is32!=current.is32) {
8448         //DebugMessage(M64MSG_VERBOSE, "pre-dumping 32-bit regs (%x)",start+i*4);
8449         for(hr=0;hr<HOST_REGS;hr++)
8450         {
8451           int r=current.regmap[hr];
8452           if(r>0)
8453           {
8454             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8455               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8456               {
8457                 //DebugMessage(M64MSG_VERBOSE, "dump %d/r%d",hr,r);
8458                 current.regmap[hr]=-1;
8459                 if(get_reg(current.regmap,r|64)>=0)
8460                   current.regmap[get_reg(current.regmap,r|64)]=-1;
8461               }
8462             }
8463           }
8464         }
8465       }
8466     }
8467     #endif
8468     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8469       if(i+1<slen) {
8470         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8471         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8472         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8473         current.u|=1;
8474         current.uu|=1;
8475       } else {
8476         current.u=1;
8477         current.uu=1;
8478       }
8479     } else {
8480       if(i+1<slen) {
8481         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8482         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8483         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8484         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8485         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8486         current.u|=1;
8487         current.uu|=1;
8488       } else { DebugMessage(M64MSG_ERROR, "oops, branch at end of block with no delay slot");exit(1); }
8489     }
8490     is_ds[i]=ds;
8491     if(ds) {
8492       ds=0; // Skip delay slot, already allocated as part of branch
8493       // ...but we need to alloc it in case something jumps here
8494       if(i+1<slen) {
8495         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8496         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8497       }else{
8498         current.u=branch_unneeded_reg[i-1];
8499         current.uu=branch_unneeded_reg_upper[i-1];
8500       }
8501       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8502       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8503       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8504       current.u|=1;
8505       current.uu|=1;
8506       struct regstat temp;
8507       memcpy(&temp,&current,sizeof(current));
8508       temp.wasdirty=temp.dirty;
8509       temp.was32=temp.is32;
8510       // TODO: Take into account unconditional branches, as below
8511       delayslot_alloc(&temp,i);
8512       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8513       regs[i].wasdirty=temp.wasdirty;
8514       regs[i].was32=temp.was32;
8515       regs[i].dirty=temp.dirty;
8516       regs[i].is32=temp.is32;
8517       regs[i].isconst=0;
8518       regs[i].wasconst=0;
8519       current.isconst=0;
8520       // Create entry (branch target) regmap
8521       for(hr=0;hr<HOST_REGS;hr++)
8522       {
8523         int r=temp.regmap[hr];
8524         if(r>=0) {
8525           if(r!=regmap_pre[i][hr]) {
8526             regs[i].regmap_entry[hr]=-1;
8527           }
8528           else
8529           {
8530             if(r<64){
8531               if((current.u>>r)&1) {
8532                 regs[i].regmap_entry[hr]=-1;
8533                 regs[i].regmap[hr]=-1;
8534                 //Don't clear regs in the delay slot as the branch might need them
8535                 //current.regmap[hr]=-1;
8536               }else
8537                 regs[i].regmap_entry[hr]=r;
8538             }
8539             else {
8540               if((current.uu>>(r&63))&1) {
8541                 regs[i].regmap_entry[hr]=-1;
8542                 regs[i].regmap[hr]=-1;
8543                 //Don't clear regs in the delay slot as the branch might need them
8544                 //current.regmap[hr]=-1;
8545               }else
8546                 regs[i].regmap_entry[hr]=r;
8547             }
8548           }
8549         } else {
8550           // First instruction expects CCREG to be allocated
8551           if(i==0&&hr==HOST_CCREG)
8552             regs[i].regmap_entry[hr]=CCREG;
8553           else
8554             regs[i].regmap_entry[hr]=-1;
8555         }
8556       }
8557     }
8558     else { // Not delay slot
8559       switch(itype[i]) {
8560         case UJUMP:
8561           //current.isconst=0; // DEBUG
8562           //current.wasconst=0; // DEBUG
8563           //regs[i].wasconst=0; // DEBUG
8564           clear_const(&current,rt1[i]);
8565           alloc_cc(&current,i);
8566           dirty_reg(&current,CCREG);
8567           if (rt1[i]==31) {
8568             alloc_reg(&current,i,31);
8569             dirty_reg(&current,31);
8570             assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8571             #ifdef REG_PREFETCH
8572             alloc_reg(&current,i,PTEMP);
8573             #endif
8574             //current.is32|=1LL<<rt1[i];
8575           }
8576           ooo[i]=1;
8577           delayslot_alloc(&current,i+1);
8578           //current.isconst=0; // DEBUG
8579           ds=1;
8580           //DebugMessage(M64MSG_VERBOSE, "i=%d, isconst=%x",i,current.isconst);
8581           break;
8582         case RJUMP:
8583           //current.isconst=0;
8584           //current.wasconst=0;
8585           //regs[i].wasconst=0;
8586           clear_const(&current,rs1[i]);
8587           clear_const(&current,rt1[i]);
8588           alloc_cc(&current,i);
8589           dirty_reg(&current,CCREG);
8590           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8591             alloc_reg(&current,i,rs1[i]);
8592             if (rt1[i]!=0) {
8593               alloc_reg(&current,i,rt1[i]);
8594               dirty_reg(&current,rt1[i]);
8595               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8596               #ifdef REG_PREFETCH
8597               alloc_reg(&current,i,PTEMP);
8598               #endif
8599             }
8600             #ifdef USE_MINI_HT
8601             if(rs1[i]==31) { // JALR
8602               alloc_reg(&current,i,RHASH);
8603               #ifndef HOST_IMM_ADDR32
8604               alloc_reg(&current,i,RHTBL);
8605               #endif
8606             }
8607             #endif
8608             delayslot_alloc(&current,i+1);
8609           } else {
8610             // The delay slot overwrites our source register,
8611             // allocate a temporary register to hold the old value.
8612             current.isconst=0;
8613             current.wasconst=0;
8614             regs[i].wasconst=0;
8615             delayslot_alloc(&current,i+1);
8616             current.isconst=0;
8617             alloc_reg(&current,i,RTEMP);
8618           }
8619           //current.isconst=0; // DEBUG
8620           ooo[i]=1;
8621           ds=1;
8622           break;
8623         case CJUMP:
8624           //current.isconst=0;
8625           //current.wasconst=0;
8626           //regs[i].wasconst=0;
8627           clear_const(&current,rs1[i]);
8628           clear_const(&current,rs2[i]);
8629           if((opcode[i]&0x3E)==4) // BEQ/BNE
8630           {
8631             alloc_cc(&current,i);
8632             dirty_reg(&current,CCREG);
8633             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8634             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8635             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8636             {
8637               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8638               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8639             }
8640             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8641                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8642               // The delay slot overwrites one of our conditions.
8643               // Allocate the branch condition registers instead.
8644               current.isconst=0;
8645               current.wasconst=0;
8646               regs[i].wasconst=0;
8647               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8648               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
8649               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8650               {
8651                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8652                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
8653               }
8654             }
8655             else
8656             {
8657               ooo[i]=1;
8658               delayslot_alloc(&current,i+1);
8659             }
8660           }
8661           else
8662           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8663           {
8664             alloc_cc(&current,i);
8665             dirty_reg(&current,CCREG);
8666             alloc_reg(&current,i,rs1[i]);
8667             if(!(current.is32>>rs1[i]&1))
8668             {
8669               alloc_reg64(&current,i,rs1[i]);
8670             }
8671             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8672               // The delay slot overwrites one of our conditions.
8673               // Allocate the branch condition registers instead.
8674               current.isconst=0;
8675               current.wasconst=0;
8676               regs[i].wasconst=0;
8677               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8678               if(!((current.is32>>rs1[i])&1))
8679               {
8680                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8681               }
8682             }
8683             else
8684             {
8685               ooo[i]=1;
8686               delayslot_alloc(&current,i+1);
8687             }
8688           }
8689           else
8690           // Don't alloc the delay slot yet because we might not execute it
8691           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8692           {
8693             current.isconst=0;
8694             current.wasconst=0;
8695             regs[i].wasconst=0;
8696             alloc_cc(&current,i);
8697             dirty_reg(&current,CCREG);
8698             alloc_reg(&current,i,rs1[i]);
8699             alloc_reg(&current,i,rs2[i]);
8700             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8701             {
8702               alloc_reg64(&current,i,rs1[i]);
8703               alloc_reg64(&current,i,rs2[i]);
8704             }
8705           }
8706           else
8707           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8708           {
8709             current.isconst=0;
8710             current.wasconst=0;
8711             regs[i].wasconst=0;
8712             alloc_cc(&current,i);
8713             dirty_reg(&current,CCREG);
8714             alloc_reg(&current,i,rs1[i]);
8715             if(!(current.is32>>rs1[i]&1))
8716             {
8717               alloc_reg64(&current,i,rs1[i]);
8718             }
8719           }
8720           ds=1;
8721           //current.isconst=0;
8722           break;
8723         case SJUMP:
8724           //current.isconst=0;
8725           //current.wasconst=0;
8726           //regs[i].wasconst=0;
8727           clear_const(&current,rs1[i]);
8728           clear_const(&current,rt1[i]);
8729           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8730           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8731           {
8732             alloc_cc(&current,i);
8733             dirty_reg(&current,CCREG);
8734             alloc_reg(&current,i,rs1[i]);
8735             if(!(current.is32>>rs1[i]&1))
8736             {
8737               alloc_reg64(&current,i,rs1[i]);
8738             }
8739             if (rt1[i]==31) { // BLTZAL/BGEZAL
8740               alloc_reg(&current,i,31);
8741               dirty_reg(&current,31);
8742               assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8743               //#ifdef REG_PREFETCH
8744               //alloc_reg(&current,i,PTEMP);
8745               //#endif
8746               //current.is32|=1LL<<rt1[i];
8747             }
8748             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8749               // The delay slot overwrites the branch condition.
8750               // Allocate the branch condition registers instead.
8751               current.isconst=0;
8752               current.wasconst=0;
8753               regs[i].wasconst=0;
8754               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
8755               if(!((current.is32>>rs1[i])&1))
8756               {
8757                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
8758               }
8759             }
8760             else
8761             {
8762               ooo[i]=1;
8763               delayslot_alloc(&current,i+1);
8764             }
8765           }
8766           else
8767           // Don't alloc the delay slot yet because we might not execute it
8768           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8769           {
8770             current.isconst=0;
8771             current.wasconst=0;
8772             regs[i].wasconst=0;
8773             alloc_cc(&current,i);
8774             dirty_reg(&current,CCREG);
8775             alloc_reg(&current,i,rs1[i]);
8776             if(!(current.is32>>rs1[i]&1))
8777             {
8778               alloc_reg64(&current,i,rs1[i]);
8779             }
8780           }
8781           ds=1;
8782           //current.isconst=0;
8783           break;
8784         case FJUMP:
8785           current.isconst=0;
8786           current.wasconst=0;
8787           regs[i].wasconst=0;
8788           if(likely[i]==0) // BC1F/BC1T
8789           {
8790             // TODO: Theoretically we can run out of registers here on x86.
8791             // The delay slot can allocate up to six, and we need to check
8792             // CSREG before executing the delay slot.  Possibly we can drop
8793             // the cycle count and then reload it after checking that the
8794             // FPU is in a usable state, or don't do out-of-order execution.
8795             alloc_cc(&current,i);
8796             dirty_reg(&current,CCREG);
8797             alloc_reg(&current,i,FSREG);
8798             alloc_reg(&current,i,CSREG);
8799             if(itype[i+1]==FCOMP) {
8800               // The delay slot overwrites the branch condition.
8801               // Allocate the branch condition registers instead.
8802               alloc_cc(&current,i);
8803               dirty_reg(&current,CCREG);
8804               alloc_reg(&current,i,CSREG);
8805               alloc_reg(&current,i,FSREG);
8806             }
8807             else {
8808               ooo[i]=1;
8809               delayslot_alloc(&current,i+1);
8810               alloc_reg(&current,i+1,CSREG);
8811             }
8812           }
8813           else
8814           // Don't alloc the delay slot yet because we might not execute it
8815           if(likely[i]) // BC1FL/BC1TL
8816           {
8817             alloc_cc(&current,i);
8818             dirty_reg(&current,CCREG);
8819             alloc_reg(&current,i,CSREG);
8820             alloc_reg(&current,i,FSREG);
8821           }
8822           ds=1;
8823           current.isconst=0;
8824           break;
8825         case IMM16:
8826           imm16_alloc(&current,i);
8827           break;
8828         case LOAD:
8829         case LOADLR:
8830           load_alloc(&current,i);
8831           break;
8832         case STORE:
8833         case STORELR:
8834           store_alloc(&current,i);
8835           break;
8836         case ALU:
8837           alu_alloc(&current,i);
8838           break;
8839         case SHIFT:
8840           shift_alloc(&current,i);
8841           break;
8842         case MULTDIV:
8843           multdiv_alloc(&current,i);
8844           break;
8845         case SHIFTIMM:
8846           shiftimm_alloc(&current,i);
8847           break;
8848         case MOV:
8849           mov_alloc(&current,i);
8850           break;
8851         case COP0:
8852           cop0_alloc(&current,i);
8853           break;
8854         case COP1:
8855           cop1_alloc(&current,i);
8856           break;
8857         case C1LS:
8858           c1ls_alloc(&current,i);
8859           break;
8860         case FCONV:
8861           fconv_alloc(&current,i);
8862           break;
8863         case FLOAT:
8864           float_alloc(&current,i);
8865           break;
8866         case FCOMP:
8867           fcomp_alloc(&current,i);
8868           break;
8869         case SYSCALL:
8870           syscall_alloc(&current,i);
8871           break;
8872         case SPAN:
8873           pagespan_alloc(&current,i);
8874           break;
8875       }
8876
8877       // Drop the upper half of registers that have become 32-bit
8878       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8879       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8880         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8881         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8882         current.uu|=1;
8883       } else {
8884         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8885         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8886         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8887         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8888         current.uu|=1;
8889       }
8890
8891       // Create entry (branch target) regmap
8892       for(hr=0;hr<HOST_REGS;hr++)
8893       {
8894         int r,or;
8895         r=current.regmap[hr];
8896         if(r>=0) {
8897           if(r!=regmap_pre[i][hr]) {
8898             // TODO: delay slot (?)
8899             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8900             if(or<0||(r&63)>=TEMPREG){
8901               regs[i].regmap_entry[hr]=-1;
8902             }
8903             else
8904             {
8905               // Just move it to a different register
8906               regs[i].regmap_entry[hr]=r;
8907               // If it was dirty before, it's still dirty
8908               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
8909             }
8910           }
8911           else
8912           {
8913             // Unneeded
8914             if(r==0){
8915               regs[i].regmap_entry[hr]=0;
8916             }
8917             else
8918             if(r<64){
8919               if((current.u>>r)&1) {
8920                 regs[i].regmap_entry[hr]=-1;
8921                 //regs[i].regmap[hr]=-1;
8922                 current.regmap[hr]=-1;
8923               }else
8924                 regs[i].regmap_entry[hr]=r;
8925             }
8926             else {
8927               if((current.uu>>(r&63))&1) {
8928                 regs[i].regmap_entry[hr]=-1;
8929                 //regs[i].regmap[hr]=-1;
8930                 current.regmap[hr]=-1;
8931               }else
8932                 regs[i].regmap_entry[hr]=r;
8933             }
8934           }
8935         } else {
8936           // Branches expect CCREG to be allocated at the target
8937           if(regmap_pre[i][hr]==CCREG)
8938             regs[i].regmap_entry[hr]=CCREG;
8939           else
8940             regs[i].regmap_entry[hr]=-1;
8941         }
8942       }
8943       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8944     }
8945     /* Branch post-alloc */
8946     if(i>0)
8947     {
8948       current.was32=current.is32;
8949       current.wasdirty=current.dirty;
8950       switch(itype[i-1]) {
8951         case UJUMP:
8952           memcpy(&branch_regs[i-1],&current,sizeof(current));
8953           branch_regs[i-1].isconst=0;
8954           branch_regs[i-1].wasconst=0;
8955           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8956           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8957           alloc_cc(&branch_regs[i-1],i-1);
8958           dirty_reg(&branch_regs[i-1],CCREG);
8959           if(rt1[i-1]==31) { // JAL
8960             alloc_reg(&branch_regs[i-1],i-1,31);
8961             dirty_reg(&branch_regs[i-1],31);
8962             branch_regs[i-1].is32|=1LL<<31;
8963           }
8964           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8965           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8966           break;
8967         case RJUMP:
8968           memcpy(&branch_regs[i-1],&current,sizeof(current));
8969           branch_regs[i-1].isconst=0;
8970           branch_regs[i-1].wasconst=0;
8971           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8972           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8973           alloc_cc(&branch_regs[i-1],i-1);
8974           dirty_reg(&branch_regs[i-1],CCREG);
8975           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8976           if(rt1[i-1]!=0) { // JALR
8977             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8978             dirty_reg(&branch_regs[i-1],rt1[i-1]);
8979             branch_regs[i-1].is32|=1LL<<rt1[i-1];
8980           }
8981           #ifdef USE_MINI_HT
8982           if(rs1[i-1]==31) { // JALR
8983             alloc_reg(&branch_regs[i-1],i-1,RHASH);
8984             #ifndef HOST_IMM_ADDR32
8985             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8986             #endif
8987           }
8988           #endif
8989           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8990           memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
8991           break;
8992         case CJUMP:
8993           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8994           {
8995             alloc_cc(&current,i-1);
8996             dirty_reg(&current,CCREG);
8997             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8998                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8999               // The delay slot overwrote one of our conditions
9000               // Delay slot goes after the test (in order)
9001               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9002               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9003               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9004               current.u|=1;
9005               current.uu|=1;
9006               delayslot_alloc(&current,i);
9007               current.isconst=0;
9008             }
9009             else
9010             {
9011               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9012               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9013               // Alloc the branch condition registers
9014               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9015               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9016               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9017               {
9018                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9019                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9020               }
9021             }
9022             memcpy(&branch_regs[i-1],&current,sizeof(current));
9023             branch_regs[i-1].isconst=0;
9024             branch_regs[i-1].wasconst=0;
9025             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9026             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9027           }
9028           else
9029           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9030           {
9031             alloc_cc(&current,i-1);
9032             dirty_reg(&current,CCREG);
9033             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9034               // The delay slot overwrote the branch condition
9035               // Delay slot goes after the test (in order)
9036               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9037               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9038               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9039               current.u|=1;
9040               current.uu|=1;
9041               delayslot_alloc(&current,i);
9042               current.isconst=0;
9043             }
9044             else
9045             {
9046               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9047               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9048               // Alloc the branch condition register
9049               alloc_reg(&current,i-1,rs1[i-1]);
9050               if(!(current.is32>>rs1[i-1]&1))
9051               {
9052                 alloc_reg64(&current,i-1,rs1[i-1]);
9053               }
9054             }
9055             memcpy(&branch_regs[i-1],&current,sizeof(current));
9056             branch_regs[i-1].isconst=0;
9057             branch_regs[i-1].wasconst=0;
9058             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9059             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9060           }
9061           else
9062           // Alloc the delay slot in case the branch is taken
9063           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9064           {
9065             memcpy(&branch_regs[i-1],&current,sizeof(current));
9066             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9067             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9068             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9069             alloc_cc(&branch_regs[i-1],i);
9070             dirty_reg(&branch_regs[i-1],CCREG);
9071             delayslot_alloc(&branch_regs[i-1],i);
9072             branch_regs[i-1].isconst=0;
9073             alloc_reg(&current,i,CCREG); // Not taken path
9074             dirty_reg(&current,CCREG);
9075             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9076           }
9077           else
9078           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9079           {
9080             memcpy(&branch_regs[i-1],&current,sizeof(current));
9081             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9082             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9083             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9084             alloc_cc(&branch_regs[i-1],i);
9085             dirty_reg(&branch_regs[i-1],CCREG);
9086             delayslot_alloc(&branch_regs[i-1],i);
9087             branch_regs[i-1].isconst=0;
9088             alloc_reg(&current,i,CCREG); // Not taken path
9089             dirty_reg(&current,CCREG);
9090             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9091           }
9092           break;
9093         case SJUMP:
9094           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9095           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9096           {
9097             alloc_cc(&current,i-1);
9098             dirty_reg(&current,CCREG);
9099             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9100               // The delay slot overwrote the branch condition
9101               // Delay slot goes after the test (in order)
9102               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9103               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9104               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9105               current.u|=1;
9106               current.uu|=1;
9107               delayslot_alloc(&current,i);
9108               current.isconst=0;
9109             }
9110             else
9111             {
9112               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9113               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9114               // Alloc the branch condition register
9115               alloc_reg(&current,i-1,rs1[i-1]);
9116               if(!(current.is32>>rs1[i-1]&1))
9117               {
9118                 alloc_reg64(&current,i-1,rs1[i-1]);
9119               }
9120             }
9121             memcpy(&branch_regs[i-1],&current,sizeof(current));
9122             branch_regs[i-1].isconst=0;
9123             branch_regs[i-1].wasconst=0;
9124             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9125             memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9126           }
9127           else
9128           // Alloc the delay slot in case the branch is taken
9129           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9130           {
9131             memcpy(&branch_regs[i-1],&current,sizeof(current));
9132             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9133             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9134             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9135             alloc_cc(&branch_regs[i-1],i);
9136             dirty_reg(&branch_regs[i-1],CCREG);
9137             delayslot_alloc(&branch_regs[i-1],i);
9138             branch_regs[i-1].isconst=0;
9139             alloc_reg(&current,i,CCREG); // Not taken path
9140             dirty_reg(&current,CCREG);
9141             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9142           }
9143           // FIXME: BLTZAL/BGEZAL
9144           if(opcode2[i-1]&0x10) { // BxxZAL
9145             alloc_reg(&branch_regs[i-1],i-1,31);
9146             dirty_reg(&branch_regs[i-1],31);
9147             branch_regs[i-1].is32|=1LL<<31;
9148           }
9149           break;
9150         case FJUMP:
9151           if(likely[i-1]==0) // BC1F/BC1T
9152           {
9153             alloc_cc(&current,i-1);
9154             dirty_reg(&current,CCREG);
9155             if(itype[i]==FCOMP) {
9156               // The delay slot overwrote the branch condition
9157               // Delay slot goes after the test (in order)
9158               delayslot_alloc(&current,i);
9159               current.isconst=0;
9160             }
9161             else
9162             {
9163               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9164               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9165               // Alloc the branch condition register
9166               alloc_reg(&current,i-1,FSREG);
9167             }
9168             memcpy(&branch_regs[i-1],&current,sizeof(current));
9169             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9170           }
9171           else // BC1FL/BC1TL
9172           {
9173             // Alloc the delay slot in case the branch is taken
9174             memcpy(&branch_regs[i-1],&current,sizeof(current));
9175             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9176             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9177             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9178             alloc_cc(&branch_regs[i-1],i);
9179             dirty_reg(&branch_regs[i-1],CCREG);
9180             delayslot_alloc(&branch_regs[i-1],i);
9181             branch_regs[i-1].isconst=0;
9182             alloc_reg(&current,i,CCREG); // Not taken path
9183             dirty_reg(&current,CCREG);
9184             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9185           }
9186           break;
9187       }
9188
9189       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9190       {
9191         if(rt1[i-1]==31) // JAL/JALR
9192         {
9193           // Subroutine call will return here, don't alloc any registers
9194           current.is32=1;
9195           current.dirty=0;
9196           clear_all_regs(current.regmap);
9197           alloc_reg(&current,i,CCREG);
9198           dirty_reg(&current,CCREG);
9199         }
9200         else if(i+1<slen)
9201         {
9202           // Internal branch will jump here, match registers to caller
9203           current.is32=0x3FFFFFFFFLL;
9204           current.dirty=0;
9205           clear_all_regs(current.regmap);
9206           alloc_reg(&current,i,CCREG);
9207           dirty_reg(&current,CCREG);
9208           for(j=i-1;j>=0;j--)
9209           {
9210             if(ba[j]==start+i*4+4) {
9211               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9212               current.is32=branch_regs[j].is32;
9213               current.dirty=branch_regs[j].dirty;
9214               break;
9215             }
9216           }
9217           while(j>=0) {
9218             if(ba[j]==start+i*4+4) {
9219               for(hr=0;hr<HOST_REGS;hr++) {
9220                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9221                   current.regmap[hr]=-1;
9222                 }
9223                 current.is32&=branch_regs[j].is32;
9224                 current.dirty&=branch_regs[j].dirty;
9225               }
9226             }
9227             j--;
9228           }
9229         }
9230       }
9231     }
9232
9233     // Count cycles in between branches
9234     ccadj[i]=cc;
9235     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL))
9236     {
9237       cc=0;
9238     }
9239     else
9240     {
9241       cc++;
9242     }
9243
9244     flush_dirty_uppers(&current);
9245     if(!is_ds[i]) {
9246       regs[i].is32=current.is32;
9247       regs[i].dirty=current.dirty;
9248       regs[i].isconst=current.isconst;
9249       memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9250     }
9251     for(hr=0;hr<HOST_REGS;hr++) {
9252       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9253         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9254           regs[i].wasconst&=~(1<<hr);
9255         }
9256       }
9257     }
9258     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9259   }
9260
9261   /* Pass 4 - Cull unused host registers */
9262
9263   uint64_t nr=0;
9264
9265   for (i=slen-1;i>=0;i--)
9266   {
9267     int hr;
9268     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9269     {
9270       if(ba[i]<start || ba[i]>=(start+slen*4))
9271       {
9272         // Branch out of this block, don't need anything
9273         nr=0;
9274       }
9275       else
9276       {
9277         // Internal branch
9278         // Need whatever matches the target
9279         nr=0;
9280         int t=(ba[i]-start)>>2;
9281         for(hr=0;hr<HOST_REGS;hr++)
9282         {
9283           if(regs[i].regmap_entry[hr]>=0) {
9284             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9285           }
9286         }
9287       }
9288       // Conditional branch may need registers for following instructions
9289       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9290       {
9291         if(i<slen-2) {
9292           nr|=needed_reg[i+2];
9293           for(hr=0;hr<HOST_REGS;hr++)
9294           {
9295             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9296             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) DebugMessage(M64MSG_VERBOSE, "%x-bogus(%d=%d)",start+i*4,hr,regmap_entry[i+2][hr]);
9297           }
9298         }
9299       }
9300       // Don't need stuff which is overwritten
9301       if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9302       if(regs[i].regmap[hr]<0) nr&=~(1<<hr);    //moved...
9303       // Merge in delay slot
9304       for(hr=0;hr<HOST_REGS;hr++)
9305       {
9306                 // Don't need stuff which is overwritten
9307 /*              if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr); //*SEB* Moved here
9308                 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);*/
9309
9310         if(!likely[i]) {
9311           // These are overwritten unless the branch is "likely"
9312           // and the delay slot is nullified if not taken
9313           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9314           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9315         }
9316         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9317         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9318         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9319         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9320         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9321         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9322         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9323         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9324         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9325           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9326           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9327         }
9328         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9329           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9330           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9331         }
9332         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9333           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9334           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9335         }
9336       }
9337     }
9338     else if(itype[i]==SYSCALL)
9339     {
9340       // SYSCALL instruction (software interrupt)
9341       nr=0;
9342     }
9343     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9344     {
9345       // ERET instruction (return from interrupt)
9346       nr=0;
9347     }
9348     else // Non-branch
9349     {
9350       if(i<slen-1) {
9351         for(hr=0;hr<HOST_REGS;hr++) {
9352           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9353           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9354           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9355           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9356         }
9357       }
9358     }
9359     for(hr=0;hr<HOST_REGS;hr++)
9360     {
9361       // Overwritten registers are not needed
9362       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9363       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9364       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9365       // Source registers are needed
9366       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9367       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9368       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9369       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9370       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9371       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9372       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9373       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9374       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9375         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9376         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9377       }
9378       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9379         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9380         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9381       }
9382       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9383         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9384         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9385       }
9386       // Don't store a register immediately after writing it,
9387       // may prevent dual-issue.
9388       // But do so if this is a branch target, otherwise we
9389       // might have to load the register before the branch.
9390       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9391         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9392            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9393           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9394           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9395         }
9396         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9397            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9398           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9399           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9400         }
9401       }
9402     }
9403     // Cycle count is needed at branches.  Assume it is needed at the target too.
9404     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9405       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9406       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9407     }
9408     // Save it
9409     needed_reg[i]=nr;
9410
9411     // Deallocate unneeded registers
9412     for(hr=0;hr<HOST_REGS;hr++)
9413     {
9414       if(!((nr>>hr)&1)) {
9415         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9416         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9417            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9418            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9419         {
9420           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9421           {
9422             if(likely[i]) {
9423               regs[i].regmap[hr]=-1;
9424               regs[i].isconst&=~(1<<hr);
9425               if(i<slen-2) {
9426                 regmap_pre[i+2][hr]=-1;
9427                 regs[i+2].wasconst&=~(1<<hr);
9428               }
9429             }
9430           }
9431         }
9432         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9433         {
9434           int d1=0,d2=0,map=0,temp=0;
9435           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9436           {
9437             d1=dep1[i+1];
9438             d2=dep2[i+1];
9439           }
9440           if(using_tlb) {
9441             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9442                itype[i+1]==STORE || itype[i+1]==STORELR ||
9443                itype[i+1]==C1LS )
9444             map=TLREG;
9445           } else
9446           if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39) {
9447             map=INVCP;
9448           }
9449           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9450              itype[i+1]==C1LS )
9451             temp=FTEMP;
9452           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9453              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9454              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9455              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9456              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9457              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9458              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9459              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9460              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9461              regs[i].regmap[hr]!=map )
9462           {
9463             regs[i].regmap[hr]=-1;
9464             regs[i].isconst&=~(1<<hr);
9465             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9466                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9467                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9468                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9469                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9470                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9471                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9472                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9473                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9474                branch_regs[i].regmap[hr]!=map)
9475             {
9476               branch_regs[i].regmap[hr]=-1;
9477               branch_regs[i].regmap_entry[hr]=-1;
9478               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9479               {
9480                 if(!likely[i]&&i<slen-2) {
9481                   regmap_pre[i+2][hr]=-1;
9482                   regs[i+2].wasconst&=~(1<<hr);
9483                 }
9484               }
9485             }
9486           }
9487         }
9488         else
9489         {
9490           // Non-branch
9491           if(i>0)
9492           {
9493             int d1=0,d2=0,map=-1,temp=-1;
9494             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9495             {
9496               d1=dep1[i];
9497               d2=dep2[i];
9498             }
9499             if(using_tlb) {
9500               if(itype[i]==LOAD || itype[i]==LOADLR ||
9501                  itype[i]==STORE || itype[i]==STORELR ||
9502                  itype[i]==C1LS )
9503               map=TLREG;
9504             } else if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39) {
9505               map=INVCP;
9506             }
9507             if(itype[i]==LOADLR || itype[i]==STORELR ||
9508                itype[i]==C1LS )
9509               temp=FTEMP;
9510             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9511                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9512                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9513                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9514                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9515                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9516             {
9517               if(i<slen-1&&!is_ds[i]) {
9518                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9519                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9520                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9521                 {
9522                   DebugMessage(M64MSG_VERBOSE, "fail: %x (%d %d!=%d)",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9523                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9524                 }
9525                 regmap_pre[i+1][hr]=-1;
9526                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9527                 regs[i+1].wasconst&=~(1<<hr);
9528               }
9529               regs[i].regmap[hr]=-1;
9530               regs[i].isconst&=~(1<<hr);
9531             }
9532           }
9533         }
9534       }
9535     }
9536   }
9537
9538   /* Pass 5 - Pre-allocate registers */
9539
9540   // If a register is allocated during a loop, try to allocate it for the
9541   // entire loop, if possible.  This avoids loading/storing registers
9542   // inside of the loop.
9543
9544   signed char f_regmap[HOST_REGS];
9545   clear_all_regs(f_regmap);
9546   for(i=0;i<slen-1;i++)
9547   {
9548     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9549     {
9550       if(ba[i]>=start && ba[i]<(start+i*4))
9551       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9552       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9553       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9554       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9555       ||itype[i+1]==FCOMP||itype[i+1]==FCONV)
9556       {
9557         int t=(ba[i]-start)>>2;
9558         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9559         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9560         for(hr=0;hr<HOST_REGS;hr++)
9561         {
9562           if(regs[i].regmap[hr]>64) {
9563             if(!((regs[i].dirty>>hr)&1))
9564               f_regmap[hr]=regs[i].regmap[hr];
9565             else f_regmap[hr]=-1;
9566           }
9567           else if(regs[i].regmap[hr]>=0) {
9568             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9569               // dealloc old register
9570               int n;
9571               for(n=0;n<HOST_REGS;n++)
9572               {
9573                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9574               }
9575               // and alloc new one
9576               f_regmap[hr]=regs[i].regmap[hr];
9577             }
9578           }
9579           if(branch_regs[i].regmap[hr]>64) {
9580             if(!((branch_regs[i].dirty>>hr)&1))
9581               f_regmap[hr]=branch_regs[i].regmap[hr];
9582             else f_regmap[hr]=-1;
9583           }
9584           else if(branch_regs[i].regmap[hr]>=0) {
9585             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9586               // dealloc old register
9587               int n;
9588               for(n=0;n<HOST_REGS;n++)
9589               {
9590                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9591               }
9592               // and alloc new one
9593               f_regmap[hr]=branch_regs[i].regmap[hr];
9594             }
9595           }
9596           if(ooo[i]) {
9597             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9598               f_regmap[hr]=branch_regs[i].regmap[hr];
9599           }else{
9600             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9601               f_regmap[hr]=branch_regs[i].regmap[hr];
9602           }
9603           // Avoid dirty->clean transition
9604           #ifdef DESTRUCTIVE_WRITEBACK
9605           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9606           #endif
9607           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9608           // case above, however it's always a good idea.  We can't hoist the
9609           // load if the register was already allocated, so there's no point
9610           // wasting time analyzing most of these cases.  It only "succeeds"
9611           // when the mapping was different and the load can be replaced with
9612           // a mov, which is of negligible benefit.  So such cases are
9613           // skipped below.
9614           if(f_regmap[hr]>0) {
9615             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9616               int r=f_regmap[hr];
9617               for(j=t;j<=i;j++)
9618               {
9619                 //DebugMessage(M64MSG_VERBOSE, "Test %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9620                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9621                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9622                 if(r>63) {
9623                   // NB This can exclude the case where the upper-half
9624                   // register is lower numbered than the lower-half
9625                   // register.  Not sure if it's worth fixing...
9626                   if(get_reg(regs[j].regmap,r&63)<0) break;
9627                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9628                   if(regs[j].is32&(1LL<<(r&63))) break;
9629                 }
9630                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9631                   //DebugMessage(M64MSG_VERBOSE, "Hit %x -> %x, %x %d/%d",start+i*4,ba[i],start+j*4,hr,r);
9632                   int k;
9633                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9634                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9635                     if(r>63) {
9636                       if(get_reg(regs[i].regmap,r&63)<0) break;
9637                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9638                     }
9639                     k=i;
9640                     while(k>1&&regs[k-1].regmap[hr]==-1) {
9641                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9642                         //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9643                         break;
9644                       }
9645                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9646                         //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9647                         break;
9648                       }
9649                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9650                         //DebugMessage(M64MSG_VERBOSE, "no-match due to branch");
9651                         break;
9652                       }
9653                       // call/ret fast path assumes no registers allocated
9654                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9655                         break;
9656                       }
9657                       if(r>63) {
9658                         // NB This can exclude the case where the upper-half
9659                         // register is lower numbered than the lower-half
9660                         // register.  Not sure if it's worth fixing...
9661                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
9662                         if(regs[k-1].is32&(1LL<<(r&63))) break;
9663                       }
9664                       k--;
9665                     }
9666                     if(i<slen-1) {
9667                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9668                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9669                         //DebugMessage(M64MSG_VERBOSE, "bad match after branch");
9670                         break;
9671                       }
9672                     }
9673                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
9674                       //DebugMessage(M64MSG_VERBOSE, "Extend r%d, %x ->",hr,start+k*4);
9675                       while(k<i) {
9676                         regs[k].regmap_entry[hr]=f_regmap[hr];
9677                         regs[k].regmap[hr]=f_regmap[hr];
9678                         regmap_pre[k+1][hr]=f_regmap[hr];
9679                         regs[k].wasdirty&=~(1<<hr);
9680                         regs[k].dirty&=~(1<<hr);
9681                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
9682                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
9683                         regs[k].wasconst&=~(1<<hr);
9684                         regs[k].isconst&=~(1<<hr);
9685                         k++;
9686                       }
9687                     }
9688                     else {
9689                       //DebugMessage(M64MSG_VERBOSE, "Fail Extend r%d, %x ->",hr,start+k*4);
9690                       break;
9691                     }
9692                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9693                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
9694                       //DebugMessage(M64MSG_VERBOSE, "OK fill %x (r%d)",start+i*4,hr);
9695                       regs[i].regmap_entry[hr]=f_regmap[hr];
9696                       regs[i].regmap[hr]=f_regmap[hr];
9697                       regs[i].wasdirty&=~(1<<hr);
9698                       regs[i].dirty&=~(1<<hr);
9699                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
9700                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
9701                       regs[i].wasconst&=~(1<<hr);
9702                       regs[i].isconst&=~(1<<hr);
9703                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9704                       branch_regs[i].wasdirty&=~(1<<hr);
9705                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
9706                       branch_regs[i].regmap[hr]=f_regmap[hr];
9707                       branch_regs[i].dirty&=~(1<<hr);
9708                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
9709                       branch_regs[i].wasconst&=~(1<<hr);
9710                       branch_regs[i].isconst&=~(1<<hr);
9711                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9712                         regmap_pre[i+2][hr]=f_regmap[hr];
9713                         regs[i+2].wasdirty&=~(1<<hr);
9714                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
9715                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9716                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
9717                       }
9718                     }
9719                   }
9720                   for(k=t;k<j;k++) {
9721                     // Alloc register clean at beginning of loop,
9722                     // but may dirty it in pass 6
9723                     regs[k].regmap_entry[hr]=f_regmap[hr];
9724                     regs[k].regmap[hr]=f_regmap[hr];
9725                     regs[k].dirty&=~(1<<hr);
9726                     regs[k].wasconst&=~(1<<hr);
9727                     regs[k].isconst&=~(1<<hr);
9728                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9729                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9730                       branch_regs[k].regmap[hr]=f_regmap[hr];
9731                       branch_regs[k].dirty&=~(1<<hr);
9732                       branch_regs[k].wasconst&=~(1<<hr);
9733                       branch_regs[k].isconst&=~(1<<hr);
9734                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9735                         regmap_pre[k+2][hr]=f_regmap[hr];
9736                         regs[k+2].wasdirty&=~(1<<hr);
9737                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9738                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
9739                       }
9740                     }
9741                     else
9742                     {
9743                       regmap_pre[k+1][hr]=f_regmap[hr];
9744                       regs[k+1].wasdirty&=~(1<<hr);
9745                     }
9746                   }
9747                   if(regs[j].regmap[hr]==f_regmap[hr])
9748                     regs[j].regmap_entry[hr]=f_regmap[hr];
9749                   break;
9750                 }
9751                 if(j==i) break;
9752                 if(regs[j].regmap[hr]>=0)
9753                   break;
9754                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9755                   //DebugMessage(M64MSG_VERBOSE, "no-match due to different register");
9756                   break;
9757                 }
9758                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9759                   //DebugMessage(M64MSG_VERBOSE, "32/64 mismatch %x %d",start+j*4,hr);
9760                   break;
9761                 }
9762                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9763                 {
9764                   // Stop on unconditional branch
9765                   break;
9766                 }
9767                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9768                 {
9769                   if(ooo[j]) {
9770                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9771                       break;
9772                   }else{
9773                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9774                       break;
9775                   }
9776                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9777                     //DebugMessage(M64MSG_VERBOSE, "no-match due to different register (branch)");
9778                     break;
9779                   }
9780                 }
9781                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9782                   //DebugMessage(M64MSG_VERBOSE, "No free regs for store %x",start+j*4);
9783                   break;
9784                 }
9785                 if(f_regmap[hr]>=64) {
9786                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9787                     break;
9788                   }
9789                   else
9790                   {
9791                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9792                       break;
9793                     }
9794                   }
9795                 }
9796               }
9797             }
9798           }
9799         }
9800       }
9801     }else{
9802       // Non branch or undetermined branch target
9803       for(hr=0;hr<HOST_REGS;hr++)
9804       {
9805         if(hr!=EXCLUDE_REG) {
9806           if(regs[i].regmap[hr]>64) {
9807             if(!((regs[i].dirty>>hr)&1))
9808               f_regmap[hr]=regs[i].regmap[hr];
9809           }
9810           else if(regs[i].regmap[hr]>=0) {
9811             if(f_regmap[hr]!=regs[i].regmap[hr]) {
9812               // dealloc old register
9813               int n;
9814               for(n=0;n<HOST_REGS;n++)
9815               {
9816                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9817               }
9818               // and alloc new one
9819               f_regmap[hr]=regs[i].regmap[hr];
9820             }
9821           }
9822         }
9823       }
9824       // Try to restore cycle count at branch targets
9825       if(bt[i]) {
9826         for(j=i;j<slen-1;j++) {
9827           if(regs[j].regmap[HOST_CCREG]!=-1) break;
9828           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9829             //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+j*4);
9830             break;
9831           }
9832         }
9833         if(regs[j].regmap[HOST_CCREG]==CCREG) {
9834           int k=i;
9835           //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x -> %x",start+k*4,start+j*4);
9836           while(k<j) {
9837             regs[k].regmap_entry[HOST_CCREG]=CCREG;
9838             regs[k].regmap[HOST_CCREG]=CCREG;
9839             regmap_pre[k+1][HOST_CCREG]=CCREG;
9840             regs[k+1].wasdirty|=1<<HOST_CCREG;
9841             regs[k].dirty|=1<<HOST_CCREG;
9842             regs[k].wasconst&=~(1<<HOST_CCREG);
9843             regs[k].isconst&=~(1<<HOST_CCREG);
9844             k++;
9845           }
9846           regs[j].regmap_entry[HOST_CCREG]=CCREG;
9847         }
9848         // Work backwards from the branch target
9849         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9850         {
9851           //DebugMessage(M64MSG_VERBOSE, "Extend backwards");
9852           int k;
9853           k=i;
9854           while(regs[k-1].regmap[HOST_CCREG]==-1) {
9855             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9856               //DebugMessage(M64MSG_VERBOSE, "no free regs for store %x",start+(k-1)*4);
9857               break;
9858             }
9859             k--;
9860           }
9861           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9862             //DebugMessage(M64MSG_VERBOSE, "Extend CC, %x ->",start+k*4);
9863             while(k<=i) {
9864               regs[k].regmap_entry[HOST_CCREG]=CCREG;
9865               regs[k].regmap[HOST_CCREG]=CCREG;
9866               regmap_pre[k+1][HOST_CCREG]=CCREG;
9867               regs[k+1].wasdirty|=1<<HOST_CCREG;
9868               regs[k].dirty|=1<<HOST_CCREG;
9869               regs[k].wasconst&=~(1<<HOST_CCREG);
9870               regs[k].isconst&=~(1<<HOST_CCREG);
9871               k++;
9872             }
9873           }
9874           else {
9875             //DebugMessage(M64MSG_VERBOSE, "Fail Extend CC, %x ->",start+k*4);
9876           }
9877         }
9878       }
9879       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9880          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9881          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9882          itype[i]!=FCONV&&itype[i]!=FCOMP)
9883       {
9884         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9885       }
9886     }
9887   }
9888
9889   // Cache memory offset or tlb map pointer if a register is available
9890   #ifndef HOST_IMM_ADDR32
9891   #ifndef RAM_OFFSET
9892   if(using_tlb)
9893   #endif
9894   {
9895     int earliest_available[HOST_REGS];
9896     int loop_start[HOST_REGS];
9897     int score[HOST_REGS];
9898     int end[HOST_REGS];
9899     int reg=using_tlb?MMREG:ROREG;
9900
9901     // Init
9902     for(hr=0;hr<HOST_REGS;hr++) {
9903       score[hr]=0;earliest_available[hr]=0;
9904       loop_start[hr]=MAXBLOCK;
9905     }
9906     for(i=0;i<slen-1;i++)
9907     {
9908       // Can't do anything if no registers are available
9909       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9910         for(hr=0;hr<HOST_REGS;hr++) {
9911           score[hr]=0;earliest_available[hr]=i+1;
9912           loop_start[hr]=MAXBLOCK;
9913         }
9914       }
9915       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9916         if(!ooo[i]) {
9917           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9918             for(hr=0;hr<HOST_REGS;hr++) {
9919               score[hr]=0;earliest_available[hr]=i+1;
9920               loop_start[hr]=MAXBLOCK;
9921             }
9922           }
9923         }else{
9924           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9925             for(hr=0;hr<HOST_REGS;hr++) {
9926               score[hr]=0;earliest_available[hr]=i+1;
9927               loop_start[hr]=MAXBLOCK;
9928             }
9929           }
9930         }
9931       }
9932       // Mark unavailable registers
9933       for(hr=0;hr<HOST_REGS;hr++) {
9934         if(regs[i].regmap[hr]>=0) {
9935           score[hr]=0;earliest_available[hr]=i+1;
9936           loop_start[hr]=MAXBLOCK;
9937         }
9938         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9939           if(branch_regs[i].regmap[hr]>=0) {
9940             score[hr]=0;earliest_available[hr]=i+2;
9941             loop_start[hr]=MAXBLOCK;
9942           }
9943         }
9944       }
9945       // No register allocations after unconditional jumps
9946       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9947       {
9948         for(hr=0;hr<HOST_REGS;hr++) {
9949           score[hr]=0;earliest_available[hr]=i+2;
9950           loop_start[hr]=MAXBLOCK;
9951         }
9952         i++; // Skip delay slot too
9953         //DebugMessage(M64MSG_VERBOSE, "skip delay slot: %x",start+i*4);
9954       }
9955       else
9956       // Possible match
9957       if(itype[i]==LOAD||itype[i]==LOADLR||
9958          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9959         for(hr=0;hr<HOST_REGS;hr++) {
9960           if(hr!=EXCLUDE_REG) {
9961             end[hr]=i-1;
9962             for(j=i;j<slen-1;j++) {
9963               if(regs[j].regmap[hr]>=0) break;
9964               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9965                 if(branch_regs[j].regmap[hr]>=0) break;
9966                 if(ooo[j]) {
9967                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9968                 }else{
9969                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9970                 }
9971               }
9972               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9973               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9974                 int t=(ba[j]-start)>>2;
9975                 if(t<j&&t>=earliest_available[hr]) {
9976                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9977                     // Score a point for hoisting loop invariant
9978                     if(t<loop_start[hr]) loop_start[hr]=t;
9979                     //DebugMessage(M64MSG_VERBOSE, "set loop_start: i=%x j=%x (%x)",start+i*4,start+j*4,start+t*4);
9980                     score[hr]++;
9981                     end[hr]=j;
9982                   }
9983                 }
9984                 else if(t<j) {
9985                   if(regs[t].regmap[hr]==reg) {
9986                     // Score a point if the branch target matches this register
9987                     score[hr]++;
9988                     end[hr]=j;
9989                   }
9990                 }
9991                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9992                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9993                   score[hr]++;
9994                   end[hr]=j;
9995                 }
9996               }
9997               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9998               {
9999                 // Stop on unconditional branch
10000                 break;
10001               }
10002               else
10003               if(itype[j]==LOAD||itype[j]==LOADLR||
10004                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10005                 score[hr]++;
10006                 end[hr]=j;
10007               }
10008             }
10009           }
10010         }
10011         // Find highest score and allocate that register
10012         int maxscore=0;
10013         for(hr=0;hr<HOST_REGS;hr++) {
10014           if(hr!=EXCLUDE_REG) {
10015             if(score[hr]>score[maxscore]) {
10016               maxscore=hr;
10017               //DebugMessage(M64MSG_VERBOSE, "highest score: %d %d (%x->%x)",score[hr],hr,start+i*4,start+end[hr]*4);
10018             }
10019           }
10020         }
10021         if(score[maxscore]>1)
10022         {
10023           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10024           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10025             //if(regs[j].regmap[maxscore]>=0) {DebugMessage(M64MSG_ERROR, "oops: %x %x was %d=%d",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10026             assert(regs[j].regmap[maxscore]<0);
10027             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10028             regs[j].regmap[maxscore]=reg;
10029             regs[j].dirty&=~(1<<maxscore);
10030             regs[j].wasconst&=~(1<<maxscore);
10031             regs[j].isconst&=~(1<<maxscore);
10032             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10033               branch_regs[j].regmap[maxscore]=reg;
10034               branch_regs[j].wasdirty&=~(1<<maxscore);
10035               branch_regs[j].dirty&=~(1<<maxscore);
10036               branch_regs[j].wasconst&=~(1<<maxscore);
10037               branch_regs[j].isconst&=~(1<<maxscore);
10038               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10039                 regmap_pre[j+2][maxscore]=reg;
10040                 regs[j+2].wasdirty&=~(1<<maxscore);
10041               }
10042               // loop optimization (loop_preload)
10043               int t=(ba[j]-start)>>2;
10044               if(t==loop_start[maxscore]) {
10045                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10046                   regs[t].regmap_entry[maxscore]=reg;
10047               }
10048             }
10049             else
10050             {
10051               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10052                 regmap_pre[j+1][maxscore]=reg;
10053                 regs[j+1].wasdirty&=~(1<<maxscore);
10054               }
10055             }
10056           }
10057           i=j-1;
10058           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10059           for(hr=0;hr<HOST_REGS;hr++) {
10060             score[hr]=0;earliest_available[hr]=i+i;
10061             loop_start[hr]=MAXBLOCK;
10062           }
10063         }
10064       }
10065     }
10066   }
10067   #endif
10068
10069   // This allocates registers (if possible) one instruction prior
10070   // to use, which can avoid a load-use penalty on certain CPUs.
10071   for(i=0;i<slen-1;i++)
10072   {
10073     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10074     {
10075       if(!bt[i+1])
10076       {
10077         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16||(itype[i]==COP1&&opcode2[i]<3))
10078         {
10079           if(rs1[i+1]) {
10080             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10081             {
10082               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10083               {
10084                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10085                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10086                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10087                 regs[i].isconst&=~(1<<hr);
10088                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10089                 constmap[i][hr]=constmap[i+1][hr];
10090                 regs[i+1].wasdirty&=~(1<<hr);
10091                 regs[i].dirty&=~(1<<hr);
10092               }
10093             }
10094           }
10095           if(rs2[i+1]) {
10096             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10097             {
10098               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10099               {
10100                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10101                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10102                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10103                 regs[i].isconst&=~(1<<hr);
10104                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10105                 constmap[i][hr]=constmap[i+1][hr];
10106                 regs[i+1].wasdirty&=~(1<<hr);
10107                 regs[i].dirty&=~(1<<hr);
10108               }
10109             }
10110           }
10111           // Preload target address for load instruction (non-constant)
10112           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10113             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10114             {
10115               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10116               {
10117                 regs[i].regmap[hr]=rs1[i+1];
10118                 regmap_pre[i+1][hr]=rs1[i+1];
10119                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10120                 regs[i].isconst&=~(1<<hr);
10121                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10122                 constmap[i][hr]=constmap[i+1][hr];
10123                 regs[i+1].wasdirty&=~(1<<hr);
10124                 regs[i].dirty&=~(1<<hr);
10125               }
10126             }
10127           }
10128           // Load source into target register
10129           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10130             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10131             {
10132               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10133               {
10134                 regs[i].regmap[hr]=rs1[i+1];
10135                 regmap_pre[i+1][hr]=rs1[i+1];
10136                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10137                 regs[i].isconst&=~(1<<hr);
10138                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10139                 constmap[i][hr]=constmap[i+1][hr];
10140                 regs[i+1].wasdirty&=~(1<<hr);
10141                 regs[i].dirty&=~(1<<hr);
10142               }
10143             }
10144           }
10145           // Preload map address
10146           #ifndef HOST_IMM_ADDR32
10147           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS) {
10148             hr=get_reg(regs[i+1].regmap,TLREG);
10149             if(hr>=0) {
10150               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10151               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10152                 int nr;
10153                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10154                 {
10155                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10156                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10157                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10158                   regs[i].isconst&=~(1<<hr);
10159                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10160                   constmap[i][hr]=constmap[i+1][hr];
10161                   regs[i+1].wasdirty&=~(1<<hr);
10162                   regs[i].dirty&=~(1<<hr);
10163                 }
10164                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10165                 {
10166                   // move it to another register
10167                   regs[i+1].regmap[hr]=-1;
10168                   regmap_pre[i+2][hr]=-1;
10169                   regs[i+1].regmap[nr]=TLREG;
10170                   regmap_pre[i+2][nr]=TLREG;
10171                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10172                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10173                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10174                   regs[i].isconst&=~(1<<nr);
10175                   regs[i+1].isconst&=~(1<<nr);
10176                   regs[i].dirty&=~(1<<nr);
10177                   regs[i+1].wasdirty&=~(1<<nr);
10178                   regs[i+1].dirty&=~(1<<nr);
10179                   regs[i+2].wasdirty&=~(1<<nr);
10180                 }
10181               }
10182             }
10183           }
10184           #endif
10185           // Address for store instruction (non-constant)
10186           if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SB/SH/SW/SD/SWC1/SDC1
10187             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10188               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10189               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10190               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10191               assert(hr>=0);
10192               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10193               {
10194                 regs[i].regmap[hr]=rs1[i+1];
10195                 regmap_pre[i+1][hr]=rs1[i+1];
10196                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10197                 regs[i].isconst&=~(1<<hr);
10198                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10199                 constmap[i][hr]=constmap[i+1][hr];
10200                 regs[i+1].wasdirty&=~(1<<hr);
10201                 regs[i].dirty&=~(1<<hr);
10202               }
10203             }
10204           }
10205           if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) { // LWC1/LDC1
10206             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10207               int nr;
10208               hr=get_reg(regs[i+1].regmap,FTEMP);
10209               assert(hr>=0);
10210               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10211               {
10212                 regs[i].regmap[hr]=rs1[i+1];
10213                 regmap_pre[i+1][hr]=rs1[i+1];
10214                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10215                 regs[i].isconst&=~(1<<hr);
10216                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10217                 constmap[i][hr]=constmap[i+1][hr];
10218                 regs[i+1].wasdirty&=~(1<<hr);
10219                 regs[i].dirty&=~(1<<hr);
10220               }
10221               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10222               {
10223                 // move it to another register
10224                 regs[i+1].regmap[hr]=-1;
10225                 regmap_pre[i+2][hr]=-1;
10226                 regs[i+1].regmap[nr]=FTEMP;
10227                 regmap_pre[i+2][nr]=FTEMP;
10228                 regs[i].regmap[nr]=rs1[i+1];
10229                 regmap_pre[i+1][nr]=rs1[i+1];
10230                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10231                 regs[i].isconst&=~(1<<nr);
10232                 regs[i+1].isconst&=~(1<<nr);
10233                 regs[i].dirty&=~(1<<nr);
10234                 regs[i+1].wasdirty&=~(1<<nr);
10235                 regs[i+1].dirty&=~(1<<nr);
10236                 regs[i+2].wasdirty&=~(1<<nr);
10237               }
10238             }
10239           }
10240           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS*/) {
10241             if(itype[i+1]==LOAD)
10242               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10243             if(itype[i+1]==LOADLR||opcode[i+1]==0x31||opcode[i+1]==0x35) // LWC1/LDC1
10244               hr=get_reg(regs[i+1].regmap,FTEMP);
10245             if(itype[i+1]==STORE||itype[i+1]==STORELR||opcode[i+1]==0x39||opcode[i+1]==0x3D) { // SWC1/SDC1
10246               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10247               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10248             }
10249             if(hr>=0&&regs[i].regmap[hr]<0) {
10250               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10251               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10252                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10253                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10254                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10255                 regs[i].isconst&=~(1<<hr);
10256                 regs[i+1].wasdirty&=~(1<<hr);
10257                 regs[i].dirty&=~(1<<hr);
10258               }
10259             }
10260           }
10261         }
10262       }
10263     }
10264   }
10265
10266   /* Pass 6 - Optimize clean/dirty state */
10267   clean_registers(0,slen-1,1);
10268
10269   /* Pass 7 - Identify 32-bit registers */
10270
10271   provisional_r32();
10272
10273   u_int r32=0;
10274
10275   for (i=slen-1;i>=0;i--)
10276   {
10277     int hr;
10278     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10279     {
10280       if(ba[i]<start || ba[i]>=(start+slen*4))
10281       {
10282         // Branch out of this block, don't need anything
10283         r32=0;
10284       }
10285       else
10286       {
10287         // Internal branch
10288         // Need whatever matches the target
10289         // (and doesn't get overwritten by the delay slot instruction)
10290         r32=0;
10291         int t=(ba[i]-start)>>2;
10292         if(ba[i]>start+i*4) {
10293           // Forward branch
10294           if(!(requires_32bit[t]&~regs[i].was32))
10295             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10296         }else{
10297           // Backward branch
10298           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10299           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10300           if(!(pr32[t]&~regs[i].was32))
10301             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10302         }
10303       }
10304       // Conditional branch may need registers for following instructions
10305       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10306       {
10307         if(i<slen-2) {
10308           r32|=requires_32bit[i+2];
10309           r32&=regs[i].was32;
10310           // Mark this address as a branch target since it may be called
10311           // upon return from interrupt
10312           bt[i+2]=1;
10313         }
10314       }
10315       // Merge in delay slot
10316       if(!likely[i]) {
10317         // These are overwritten unless the branch is "likely"
10318         // and the delay slot is nullified if not taken
10319         r32&=~(1LL<<rt1[i+1]);
10320         r32&=~(1LL<<rt2[i+1]);
10321       }
10322       // Assume these are needed (delay slot)
10323       if(us1[i+1]>0)
10324       {
10325         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10326       }
10327       if(us2[i+1]>0)
10328       {
10329         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10330       }
10331       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10332       {
10333         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10334       }
10335       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10336       {
10337         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10338       }
10339     }
10340     else if(itype[i]==SYSCALL)
10341     {
10342       // SYSCALL instruction (software interrupt)
10343       r32=0;
10344     }
10345     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10346     {
10347       // ERET instruction (return from interrupt)
10348       r32=0;
10349     }
10350     // Check 32 bits
10351     r32&=~(1LL<<rt1[i]);
10352     r32&=~(1LL<<rt2[i]);
10353     if(us1[i]>0)
10354     {
10355       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10356     }
10357     if(us2[i]>0)
10358     {
10359       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10360     }
10361     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10362     {
10363       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10364     }
10365     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10366     {
10367       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10368     }
10369     requires_32bit[i]=r32;
10370
10371     // Dirty registers which are 32-bit, require 32-bit input
10372     // as they will be written as 32-bit values
10373     for(hr=0;hr<HOST_REGS;hr++)
10374     {
10375       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
10376         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10377           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10378           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10379         }
10380       }
10381     }
10382     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10383   }
10384
10385   if(itype[slen-1]==SPAN) {
10386     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10387   }
10388
10389   /* Debug/disassembly */
10390 //  if((void*)assem_debug==(void*)printf)
10391 #if defined( ASSEM_DEBUG )
10392   for(i=0;i<slen;i++)
10393   {
10394     DebugMessage(M64MSG_VERBOSE, "U:");
10395     int r;
10396     for(r=1;r<=CCREG;r++) {
10397       if((unneeded_reg[i]>>r)&1) {
10398         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10399         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10400         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10401       }
10402     }
10403     DebugMessage(M64MSG_VERBOSE, " UU:");
10404     for(r=1;r<=CCREG;r++) {
10405       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10406         if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10407         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10408         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10409       }
10410     }
10411     DebugMessage(M64MSG_VERBOSE, " 32:");
10412     for(r=0;r<=CCREG;r++) {
10413       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10414       if((regs[i].was32>>r)&1) {
10415         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10416         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10417         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10418         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10419       }
10420     }
10421     #if NEW_DYNAREC == NEW_DYNAREC_X86
10422     DebugMessage(M64MSG_VERBOSE, "pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10423     #endif
10424     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10425     DebugMessage(M64MSG_VERBOSE, "pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10426     #endif
10427     DebugMessage(M64MSG_VERBOSE, "needs: ");
10428     if(needed_reg[i]&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10429     if((needed_reg[i]>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10430     if((needed_reg[i]>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10431     if((needed_reg[i]>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10432     if((needed_reg[i]>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10433     if((needed_reg[i]>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10434     if((needed_reg[i]>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10435     DebugMessage(M64MSG_VERBOSE, "r:");
10436     for(r=0;r<=CCREG;r++) {
10437       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10438       if((requires_32bit[i]>>r)&1) {
10439         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10440         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10441         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10442         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10443       }
10444     }
10445     /*DebugMessage(M64MSG_VERBOSE, "pr:");
10446     for(r=0;r<=CCREG;r++) {
10447       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10448       if((pr32[i]>>r)&1) {
10449         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10450         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10451         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10452         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10453       }
10454     }
10455     if(pr32[i]!=requires_32bit[i]) DebugMessage(M64MSG_ERROR, " OOPS");*/
10456     #if NEW_DYNAREC == NEW_DYNAREC_X86
10457     DebugMessage(M64MSG_VERBOSE, "entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10458     DebugMessage(M64MSG_VERBOSE, "dirty: ");
10459     if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10460     if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10461     if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10462     if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10463     if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10464     if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10465     if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10466     #endif
10467     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10468     DebugMessage(M64MSG_VERBOSE, "entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10469     DebugMessage(M64MSG_VERBOSE, "dirty: ");
10470     if(regs[i].wasdirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10471     if((regs[i].wasdirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10472     if((regs[i].wasdirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10473     if((regs[i].wasdirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10474     if((regs[i].wasdirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10475     if((regs[i].wasdirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10476     if((regs[i].wasdirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10477     if((regs[i].wasdirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10478     if((regs[i].wasdirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10479     if((regs[i].wasdirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10480     if((regs[i].wasdirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10481     if((regs[i].wasdirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10482     #endif
10483     disassemble_inst(i);
10484     //printf ("ccadj[%d] = %d",i,ccadj[i]);
10485     #if NEW_DYNAREC == NEW_DYNAREC_X86
10486     DebugMessage(M64MSG_VERBOSE, "eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10487     if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10488     if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10489     if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10490     if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10491     if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10492     if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10493     if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10494     #endif
10495     #if NEW_DYNAREC == NEW_DYNAREC_ARM
10496     DebugMessage(M64MSG_VERBOSE, "r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10497     if(regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10498     if((regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10499     if((regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10500     if((regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10501     if((regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10502     if((regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10503     if((regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10504     if((regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10505     if((regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10506     if((regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10507     if((regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10508     if((regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10509     #endif
10510     if(regs[i].isconst) {
10511       DebugMessage(M64MSG_VERBOSE, "constants: ");
10512       #if NEW_DYNAREC == NEW_DYNAREC_X86
10513       if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "eax=%x ",(int)constmap[i][0]);
10514       if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx=%x ",(int)constmap[i][1]);
10515       if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx=%x ",(int)constmap[i][2]);
10516       if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx=%x ",(int)constmap[i][3]);
10517       if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp=%x ",(int)constmap[i][5]);
10518       if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi=%x ",(int)constmap[i][6]);
10519       if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi=%x ",(int)constmap[i][7]);
10520       #endif
10521       #if NEW_DYNAREC == NEW_DYNAREC_ARM
10522       if(regs[i].isconst&1) DebugMessage(M64MSG_VERBOSE, "r0=%x ",(int)constmap[i][0]);
10523       if((regs[i].isconst>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1=%x ",(int)constmap[i][1]);
10524       if((regs[i].isconst>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2=%x ",(int)constmap[i][2]);
10525       if((regs[i].isconst>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3=%x ",(int)constmap[i][3]);
10526       if((regs[i].isconst>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4=%x ",(int)constmap[i][4]);
10527       if((regs[i].isconst>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5=%x ",(int)constmap[i][5]);
10528       if((regs[i].isconst>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6=%x ",(int)constmap[i][6]);
10529       if((regs[i].isconst>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7=%x ",(int)constmap[i][7]);
10530       if((regs[i].isconst>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8=%x ",(int)constmap[i][8]);
10531       if((regs[i].isconst>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9=%x ",(int)constmap[i][9]);
10532       if((regs[i].isconst>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10=%x ",(int)constmap[i][10]);
10533       if((regs[i].isconst>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12=%x ",(int)constmap[i][12]);
10534       #endif
10535     }
10536     DebugMessage(M64MSG_VERBOSE, " 32:");
10537     for(r=0;r<=CCREG;r++) {
10538       if((regs[i].is32>>r)&1) {
10539         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10540         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10541         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10542         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10543       }
10544     }
10545     /*DebugMessage(M64MSG_VERBOSE, " p32:");
10546     for(r=0;r<=CCREG;r++) {
10547       if((p32[i]>>r)&1) {
10548         if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10549         else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10550         else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10551         else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10552       }
10553     }
10554     if(p32[i]!=regs[i].is32) DebugMessage(M64MSG_VERBOSE, " NO MATCH");*/
10555     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10556       #if NEW_DYNAREC == NEW_DYNAREC_X86
10557       DebugMessage(M64MSG_VERBOSE, "branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10558       if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "eax ");
10559       if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "ecx ");
10560       if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "edx ");
10561       if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "ebx ");
10562       if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "ebp ");
10563       if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "esi ");
10564       if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "edi ");
10565       #endif
10566       #if NEW_DYNAREC == NEW_DYNAREC_ARM
10567       DebugMessage(M64MSG_VERBOSE, "branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10568       if(branch_regs[i].dirty&1) DebugMessage(M64MSG_VERBOSE, "r0 ");
10569       if((branch_regs[i].dirty>>1)&1) DebugMessage(M64MSG_VERBOSE, "r1 ");
10570       if((branch_regs[i].dirty>>2)&1) DebugMessage(M64MSG_VERBOSE, "r2 ");
10571       if((branch_regs[i].dirty>>3)&1) DebugMessage(M64MSG_VERBOSE, "r3 ");
10572       if((branch_regs[i].dirty>>4)&1) DebugMessage(M64MSG_VERBOSE, "r4 ");
10573       if((branch_regs[i].dirty>>5)&1) DebugMessage(M64MSG_VERBOSE, "r5 ");
10574       if((branch_regs[i].dirty>>6)&1) DebugMessage(M64MSG_VERBOSE, "r6 ");
10575       if((branch_regs[i].dirty>>7)&1) DebugMessage(M64MSG_VERBOSE, "r7 ");
10576       if((branch_regs[i].dirty>>8)&1) DebugMessage(M64MSG_VERBOSE, "r8 ");
10577       if((branch_regs[i].dirty>>9)&1) DebugMessage(M64MSG_VERBOSE, "r9 ");
10578       if((branch_regs[i].dirty>>10)&1) DebugMessage(M64MSG_VERBOSE, "r10 ");
10579       if((branch_regs[i].dirty>>12)&1) DebugMessage(M64MSG_VERBOSE, "r12 ");
10580       #endif
10581       DebugMessage(M64MSG_VERBOSE, " 32:");
10582       for(r=0;r<=CCREG;r++) {
10583         if((branch_regs[i].is32>>r)&1) {
10584           if(r==CCREG) DebugMessage(M64MSG_VERBOSE, " CC");
10585           else if(r==HIREG) DebugMessage(M64MSG_VERBOSE, " HI");
10586           else if(r==LOREG) DebugMessage(M64MSG_VERBOSE, " LO");
10587           else DebugMessage(M64MSG_VERBOSE, " r%d",r);
10588         }
10589       }
10590     }
10591   }
10592 #endif
10593
10594   /* Pass 8 - Assembly */
10595   linkcount=0;stubcount=0;
10596   ds=0;is_delayslot=0;
10597   cop1_usable=0;
10598   #ifndef DESTRUCTIVE_WRITEBACK
10599   uint64_t is32_pre=0;
10600   u_int dirty_pre=0;
10601   #endif
10602   u_int beginning=(u_int)out;
10603   if((u_int)addr&1) {
10604     ds=1;
10605     pagespan_ds();
10606   }
10607   for(i=0;i<slen;i++)
10608   {
10609     //if(ds) DebugMessage(M64MSG_VERBOSE, "ds: ");
10610 //    if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10611 #if defined( ASSEM_DEBUG )
10612           disassemble_inst(i);
10613 #endif
10614     if(ds) {
10615       ds=0; // Skip delay slot
10616       if(bt[i]) assem_debug("OOPS - branch into delay slot");
10617       instr_addr[i]=0;
10618     } else {
10619       #ifndef DESTRUCTIVE_WRITEBACK
10620       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10621       {
10622         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10623               unneeded_reg[i],unneeded_reg_upper[i]);
10624         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10625               unneeded_reg[i],unneeded_reg_upper[i]);
10626       }
10627       is32_pre=regs[i].is32;
10628       dirty_pre=regs[i].dirty;
10629       #endif
10630       // write back
10631       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10632       {
10633         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10634                       unneeded_reg[i],unneeded_reg_upper[i]);
10635         loop_preload(regmap_pre[i],regs[i].regmap_entry);
10636       }
10637       // branch target entry point
10638       instr_addr[i]=(u_int)out;
10639       assem_debug("<->");
10640       // load regs
10641       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
10642         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10643       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10644       address_generation(i,&regs[i],regs[i].regmap_entry);
10645       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10646       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10647       {
10648         // Load the delay slot registers if necessary
10649         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10650           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10651         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10652           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10653         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39)
10654           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10655       }
10656       else if(i+1<slen)
10657       {
10658         // Preload registers for following instruction
10659         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10660           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10661             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10662         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10663           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10664             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10665       }
10666       // TODO: if(is_ooo(i)) address_generation(i+1);
10667       if(itype[i]==CJUMP||itype[i]==FJUMP)
10668         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10669       if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS)
10670         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,MMREG,ROREG);
10671       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39)
10672         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10673       if(bt[i]) cop1_usable=0;
10674       // assemble
10675       switch(itype[i]) {
10676         case ALU:
10677           alu_assemble(i,&regs[i]);break;
10678         case IMM16:
10679           imm16_assemble(i,&regs[i]);break;
10680         case SHIFT:
10681           shift_assemble(i,&regs[i]);break;
10682         case SHIFTIMM:
10683           shiftimm_assemble(i,&regs[i]);break;
10684         case LOAD:
10685           load_assemble(i,&regs[i]);break;
10686         case LOADLR:
10687           loadlr_assemble(i,&regs[i]);break;
10688         case STORE:
10689           store_assemble(i,&regs[i]);break;
10690         case STORELR:
10691           storelr_assemble(i,&regs[i]);break;
10692         case COP0:
10693           cop0_assemble(i,&regs[i]);break;
10694         case COP1:
10695           cop1_assemble(i,&regs[i]);break;
10696         case C1LS:
10697           c1ls_assemble(i,&regs[i]);break;
10698         case FCONV:
10699           fconv_assemble(i,&regs[i]);break;
10700         case FLOAT:
10701           float_assemble(i,&regs[i]);break;
10702         case FCOMP:
10703           fcomp_assemble(i,&regs[i]);break;
10704         case MULTDIV:
10705           multdiv_assemble(i,&regs[i]);break;
10706         case MOV:
10707           mov_assemble(i,&regs[i]);break;
10708         case SYSCALL:
10709           syscall_assemble(i,&regs[i]);break;
10710         case UJUMP:
10711           ujump_assemble(i,&regs[i]);ds=1;break;
10712         case RJUMP:
10713           rjump_assemble(i,&regs[i]);ds=1;break;
10714         case CJUMP:
10715           cjump_assemble(i,&regs[i]);ds=1;break;
10716         case SJUMP:
10717           sjump_assemble(i,&regs[i]);ds=1;break;
10718         case FJUMP:
10719           fjump_assemble(i,&regs[i]);ds=1;break;
10720         case SPAN:
10721           pagespan_assemble(i,&regs[i]);break;
10722       }
10723       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10724         literal_pool(1024);
10725       else
10726         literal_pool_jumpover(256);
10727     }
10728   }
10729   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10730   // If the block did not end with an unconditional branch,
10731   // add a jump to the next instruction.
10732   if(i>1) {
10733     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10734       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10735       assert(i==slen);
10736       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10737         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10738         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10739           emit_loadreg(CCREG,HOST_CCREG);
10740         emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10741       }
10742       else if(!likely[i-2])
10743       {
10744         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10745         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10746       }
10747       else
10748       {
10749         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10750         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10751       }
10752       add_to_linker((int)out,start+i*4,0);
10753       emit_jmp(0);
10754     }
10755   }
10756   else
10757   {
10758     assert(i>0);
10759     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10760     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10761     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10762       emit_loadreg(CCREG,HOST_CCREG);
10763     emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10764     add_to_linker((int)out,start+i*4,0);
10765     emit_jmp(0);
10766   }
10767
10768   // TODO: delay slot stubs?
10769   // Stubs
10770   for(i=0;i<stubcount;i++)
10771   {
10772     switch(stubs[i][0])
10773     {
10774       case LOADB_STUB:
10775       case LOADH_STUB:
10776       case LOADW_STUB:
10777       case LOADD_STUB:
10778       case LOADBU_STUB:
10779       case LOADHU_STUB:
10780         do_readstub(i);break;
10781       case STOREB_STUB:
10782       case STOREH_STUB:
10783       case STOREW_STUB:
10784       case STORED_STUB:
10785         do_writestub(i);break;
10786       case CC_STUB:
10787         do_ccstub(i);break;
10788       case INVCODE_STUB:
10789         do_invstub(i);break;
10790       case FP_STUB:
10791         do_cop1stub(i);break;
10792       case STORELR_STUB:
10793         do_unalignedwritestub(i);break;
10794     }
10795   }
10796
10797   /* Pass 9 - Linker */
10798   for(i=0;i<linkcount;i++)
10799   {
10800     assem_debug("%8x -> %8x",link_addr[i][0],link_addr[i][1]);
10801     literal_pool(64);
10802     if(!link_addr[i][2])
10803     {
10804       void *stub=out;
10805       void *addr=check_addr(link_addr[i][1]);
10806       emit_extjump(link_addr[i][0],link_addr[i][1]);
10807       if(addr) {
10808         set_jump_target(link_addr[i][0],(int)addr);
10809         add_link(link_addr[i][1],stub);
10810       }
10811       else set_jump_target(link_addr[i][0],(int)stub);
10812     }
10813     else
10814     {
10815       // Internal branch
10816       int target=(link_addr[i][1]-start)>>2;
10817       assert(target>=0&&target<slen);
10818       assert(instr_addr[target]);
10819       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10820       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10821       //#else
10822       set_jump_target(link_addr[i][0],instr_addr[target]);
10823       //#endif
10824     }
10825   }
10826   // External Branch Targets (jump_in)
10827   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10828   for(i=0;i<slen;i++)
10829   {
10830     if(bt[i]||i==0)
10831     {
10832       if(instr_addr[i]) // TODO - delay slots (=null)
10833       {
10834         u_int vaddr=start+i*4;
10835         u_int page=(0x80000000^vaddr)>>12;
10836         u_int vpage=page;
10837         if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[page^0x80000]^0x80000000)>>12;
10838         if(page>2048) page=2048+(page&2047);
10839         if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
10840         if(vpage>2048) vpage=2048+(vpage&2047);
10841         literal_pool(256);
10842         //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10843         if(!requires_32bit[i])
10844         {
10845           assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10846           assem_debug("jump_in: %x",start+i*4);
10847           ll_add(jump_dirty+vpage,vaddr,(void *)out);
10848           int entry_point=do_dirty_stub(i);
10849           ll_add(jump_in+page,vaddr,(void *)entry_point);
10850           // If there was an existing entry in the hash table,
10851           // replace it with the new address.
10852           // Don't add new entries.  We'll insert the
10853           // ones that actually get used in check_addr().
10854           u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10855           if(ht_bin[0]==vaddr) {
10856             ht_bin[1]=entry_point;
10857           }
10858           if(ht_bin[2]==vaddr) {
10859             ht_bin[3]=entry_point;
10860           }
10861         }
10862         else
10863         {
10864           u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10865           assem_debug("%8x (%d) <- %8x",instr_addr[i],i,start+i*4);
10866           assem_debug("jump_in: %x (restricted - %x)",start+i*4,r);
10867           //int entry_point=(int)out;
10868           ////assem_debug("entry_point: %x",entry_point);
10869           //load_regs_entry(i);
10870           //if(entry_point==(int)out)
10871           //  entry_point=instr_addr[i];
10872           //else
10873           //  emit_jmp(instr_addr[i]);
10874           //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10875           ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10876           int entry_point=do_dirty_stub(i);
10877           ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10878         }
10879       }
10880     }
10881   }
10882   // Write out the literal pool if necessary
10883   literal_pool(0);
10884   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10885   // Align code
10886   if(((u_int)out)&7) emit_addnop(13);
10887   #endif
10888   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10889   //DebugMessage(M64MSG_VERBOSE, "shadow buffer: %x-%x",(int)copy,(int)copy+slen*4);
10890   memcpy(copy,source,slen*4);
10891   copy+=slen*4;
10892
10893   #if NEW_DYNAREC == NEW_DYNAREC_ARM
10894   __clear_cache((void *)beginning,out);
10895   //cacheflush((void *)beginning,out,0);
10896   #endif
10897
10898   // If we're within 256K of the end of the buffer,
10899   // start over from the beginning. (Is 256K enough?)
10900   if(out > (u_char *)(base_addr+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE-JUMP_TABLE_SIZE))
10901     out=(u_char *)base_addr;
10902
10903   // Trap writes to any of the pages we compiled
10904   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10905     invalid_code[i]=0;
10906     memory_map[i]|=0x40000000;
10907     if((signed int)start>=(signed int)0xC0000000) {
10908       assert(using_tlb);
10909       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10910       invalid_code[j]=0;
10911       memory_map[j]|=0x40000000;
10912       //DebugMessage(M64MSG_VERBOSE, "write protect physical page: %x (virtual %x)",j<<12,start);
10913     }
10914   }
10915
10916   /* Pass 10 - Free memory by expiring oldest blocks */
10917
10918   int end=((((intptr_t)out-(intptr_t)base_addr)>>(TARGET_SIZE_2-16))+16384)&65535;
10919   while(expirep!=end)
10920   {
10921     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10922     int base=(int)base_addr+((expirep>>13)<<shift); // Base address of this block
10923     inv_debug("EXP: Phase %d\n",expirep);
10924     switch((expirep>>11)&3)
10925     {
10926       case 0:
10927         // Clear jump_in and jump_dirty
10928         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10929         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10930         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10931         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10932         break;
10933       case 1:
10934         // Clear pointers
10935         ll_kill_pointers(jump_out[expirep&2047],base,shift);
10936         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10937         break;
10938       case 2:
10939         // Clear hash table
10940         for(i=0;i<32;i++) {
10941           u_int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10942           if((ht_bin[3]>>shift)==(base>>shift) ||
10943              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10944             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10945             ht_bin[2]=ht_bin[3]=-1;
10946           }
10947           if((ht_bin[1]>>shift)==(base>>shift) ||
10948              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10949             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10950             ht_bin[0]=ht_bin[2];
10951             ht_bin[1]=ht_bin[3];
10952             ht_bin[2]=ht_bin[3]=-1;
10953           }
10954         }
10955         break;
10956       case 3:
10957         // Clear jump_out
10958         #if NEW_DYNAREC == NEW_DYNAREC_ARM
10959         if((expirep&2047)==0)
10960           do_clear_cache();
10961         #endif
10962         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10963         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10964         break;
10965     }
10966     expirep=(expirep+1)&65535;
10967   }
10968   return 0;
10969 }
10970
10971 void TLBWI_new(void)
10972 {
10973   unsigned int i;
10974   /* Remove old entries */
10975   unsigned int old_start_even=tlb_e[Index&0x3F].start_even;
10976   unsigned int old_end_even=tlb_e[Index&0x3F].end_even;
10977   unsigned int old_start_odd=tlb_e[Index&0x3F].start_odd;
10978   unsigned int old_end_odd=tlb_e[Index&0x3F].end_odd;
10979   for (i=old_start_even>>12; i<=old_end_even>>12; i++)
10980   {
10981     if(i<0x80000||i>0xBFFFF)
10982     {
10983       invalidate_block(i);
10984       memory_map[i]=-1;
10985     }
10986   }
10987   for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
10988   {
10989     if(i<0x80000||i>0xBFFFF)
10990     {
10991       invalidate_block(i);
10992       memory_map[i]=-1;
10993     }
10994   }
10995   cached_interpreter_table.TLBWI();
10996   //DebugMessage(M64MSG_VERBOSE, "TLBWI: index=%d",Index);
10997   //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_even=%x end_even=%x phys_even=%x v=%d d=%d",tlb_e[Index&0x3F].start_even,tlb_e[Index&0x3F].end_even,tlb_e[Index&0x3F].phys_even,tlb_e[Index&0x3F].v_even,tlb_e[Index&0x3F].d_even);
10998   //DebugMessage(M64MSG_VERBOSE, "TLBWI: start_odd=%x end_odd=%x phys_odd=%x v=%d d=%d",tlb_e[Index&0x3F].start_odd,tlb_e[Index&0x3F].end_odd,tlb_e[Index&0x3F].phys_odd,tlb_e[Index&0x3F].v_odd,tlb_e[Index&0x3F].d_odd);
10999   /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
11000      for fast look up. */
11001   for (i=tlb_e[Index&0x3F].start_even>>12; i<=tlb_e[Index&0x3F].end_even>>12; i++)
11002   {
11003     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11004     if(i<0x80000||i>0xBFFFF)
11005     {
11006       if(tlb_LUT_r[i]) {
11007         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11008         // FIXME: should make sure the physical page is invalid too
11009         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11010           memory_map[i]|=0x40000000; // Write protect
11011         }else{
11012           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11013         }
11014         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11015         // Tell the dynamic recompiler to generate tlb lookup code
11016         using_tlb=1;
11017       }
11018       else memory_map[i]=-1;
11019     }
11020     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11021   }
11022   for (i=tlb_e[Index&0x3F].start_odd>>12; i<=tlb_e[Index&0x3F].end_odd>>12; i++)
11023   {
11024     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11025     if(i<0x80000||i>0xBFFFF)
11026     {
11027       if(tlb_LUT_r[i]) {
11028         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11029         // FIXME: should make sure the physical page is invalid too
11030         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11031           memory_map[i]|=0x40000000; // Write protect
11032         }else{
11033           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11034         }
11035         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11036         // Tell the dynamic recompiler to generate tlb lookup code
11037         using_tlb=1;
11038       }
11039       else memory_map[i]=-1;
11040     }
11041     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11042   }
11043 }
11044
11045 void TLBWR_new(void)
11046 {
11047   unsigned int i;
11048   Random = (Count/2 % (32 - Wired)) + Wired;
11049   /* Remove old entries */
11050   unsigned int old_start_even=tlb_e[Random&0x3F].start_even;
11051   unsigned int old_end_even=tlb_e[Random&0x3F].end_even;
11052   unsigned int old_start_odd=tlb_e[Random&0x3F].start_odd;
11053   unsigned int old_end_odd=tlb_e[Random&0x3F].end_odd;
11054   for (i=old_start_even>>12; i<=old_end_even>>12; i++)
11055   {
11056     if(i<0x80000||i>0xBFFFF)
11057     {
11058       invalidate_block(i);
11059       memory_map[i]=-1;
11060     }
11061   }
11062   for (i=old_start_odd>>12; i<=old_end_odd>>12; i++)
11063   {
11064     if(i<0x80000||i>0xBFFFF)
11065     {
11066       invalidate_block(i);
11067       memory_map[i]=-1;
11068     }
11069   }
11070   cached_interpreter_table.TLBWR();
11071   /* Combine tlb_LUT_r, tlb_LUT_w, and invalid_code into a single table
11072      for fast look up. */
11073   for (i=tlb_e[Random&0x3F].start_even>>12; i<=tlb_e[Random&0x3F].end_even>>12; i++)
11074   {
11075     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11076     if(i<0x80000||i>0xBFFFF)
11077     {
11078       if(tlb_LUT_r[i]) {
11079         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11080         // FIXME: should make sure the physical page is invalid too
11081         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11082           memory_map[i]|=0x40000000; // Write protect
11083         }else{
11084           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11085         }
11086         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11087         // Tell the dynamic recompiler to generate tlb lookup code
11088         using_tlb=1;
11089       }
11090       else memory_map[i]=-1;
11091     }
11092     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11093   }
11094   for (i=tlb_e[Random&0x3F].start_odd>>12; i<=tlb_e[Random&0x3F].end_odd>>12; i++)
11095   {
11096     //DebugMessage(M64MSG_VERBOSE, "%x: r:%8x w:%8x",i,tlb_LUT_r[i],tlb_LUT_w[i]);
11097     if(i<0x80000||i>0xBFFFF)
11098     {
11099       if(tlb_LUT_r[i]) {
11100         memory_map[i]=((tlb_LUT_r[i]&0xFFFFF000)-(i<<12)+(unsigned int)rdram-0x80000000)>>2;
11101         // FIXME: should make sure the physical page is invalid too
11102         if(!tlb_LUT_w[i]||!invalid_code[i]) {
11103           memory_map[i]|=0x40000000; // Write protect
11104         }else{
11105           assert(tlb_LUT_r[i]==tlb_LUT_w[i]);
11106         }
11107         if(!using_tlb) DebugMessage(M64MSG_VERBOSE, "Enabled TLB");
11108         // Tell the dynamic recompiler to generate tlb lookup code
11109         using_tlb=1;
11110       }
11111       else memory_map[i]=-1;
11112     }
11113     //DebugMessage(M64MSG_VERBOSE, "memory_map[%x]: %8x (+%8x)",i,memory_map[i],memory_map[i]<<2);
11114   }
11115 }