DYNAREC: More work on DIV, no effect

diff --git a/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.c b/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.c
index 88fc797..6d2f0b1 100755 (executable)
--- a/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.c
+++ b/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.c
@@ -4096,7 +4096,7 @@ static void multdiv_assemble_arm(int i,struct regstat *i_regs)
       }
       if(opcode2[i]==0x1A) // DIV
       {
       }
       if(opcode2[i]==0x1A) // DIV
       {

-               #if 1
+               #if 0

         signed char m1l=get_reg(i_regs->regmap,rs1[i]);
         signed char m2l=get_reg(i_regs->regmap,rs2[i]);
         assert(m1l>=0);
         signed char m1l=get_reg(i_regs->regmap,rs1[i]);
         signed char m2l=get_reg(i_regs->regmap,rs2[i]);
         assert(m1l>=0);


@@ -4142,7 +4142,23 @@ static void multdiv_assemble_arm(int i,struct regstat *i_regs)
       }
       if(opcode2[i]==0x1B) // DIVU
       {
       }
       if(opcode2[i]==0x1B) // DIVU
       {

-        signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
+           #if 0
+               signed char m1l=get_reg(i_regs->regmap,rs1[i]);
+               signed char m2l=get_reg(i_regs->regmap,rs2[i]);
+               assert(m1l>=0);
+               assert(m2l>=0);
+               save_regs(0x100f);
+               if(m1l!=0) emit_mov(m1l,0);
+               if(m2l<1) emit_readword((int)&dynarec_local,1);
+               else if(m2l>1) emit_mov(m2l,1);
+               emit_call((int)&divu32);
+               restore_regs(0x100f);
+               signed char hil=get_reg(i_regs->regmap,HIREG);
+               if(hil>=0) emit_loadreg(HIREG,hil);
+               signed char lol=get_reg(i_regs->regmap,LOREG);
+               if(lol>=0) emit_loadreg(LOREG,lol);
+               #else
+               signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend

         signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
         assert(d1>=0);
         assert(d2>=0);
         signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
         assert(d1>=0);
         assert(d2>=0);


@@ -4162,6 +4178,7 @@ static void multdiv_assemble_arm(int i,struct regstat *i_regs)
         emit_adcs(quotient,quotient,quotient);
         emit_shrcc_imm(d2,1,d2);
         emit_jcc((int)out-16); // -4
         emit_adcs(quotient,quotient,quotient);
         emit_shrcc_imm(d2,1,d2);
         emit_jcc((int)out-16); // -4

+               #endif

       }
     }
     else // 64-bit
       }
     }
     else // 64-bit

diff --git a/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.h b/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.h
old mode 100644 (file)
new mode 100755 (executable)
index a9db4f8..8b3f0e4
--- a/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.h
+++ b/source/mupen64plus-core/src/r4300/new_dynarec/assem_arm.h
@@ -8,6 +8,7 @@
 #define CORTEX_A8_BRANCH_PREDICTION_HACK 1
 #define USE_MINI_HT 1
 //#define REG_PREFETCH 1
 #define CORTEX_A8_BRANCH_PREDICTION_HACK 1
 #define USE_MINI_HT 1
 //#define REG_PREFETCH 1

+//#define IMM_PREFETCH 1

 #define HAVE_CONDITIONAL_CALL 1
 #define RAM_OFFSET 1
 
 #define HAVE_CONDITIONAL_CALL 1
 #define RAM_OFFSET 1
 

diff --git a/source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c b/source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c
index 53e569f..e76e4c9 100755 (executable)
--- a/source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c
+++ b/source/mupen64plus-core/src/r4300/new_dynarec/new_dynarec.c
@@ -272,7 +272,7 @@ static int verify_dirty(void *addr);
 //#define DEBUG_CYCLE_COUNT 1
 
 // Uncomment these two lines to generate debug output:
 //#define DEBUG_CYCLE_COUNT 1
 
 // Uncomment these two lines to generate debug output:

-//#define ASSEM_DEBUG 1
+#//define ASSEM_DEBUG 1

 //#define INV_DEBUG 1
 
 // Uncomment this line to output the number of NOTCOMPILED blocks as they occur:
 //#define INV_DEBUG 1
 
 // Uncomment this line to output the number of NOTCOMPILED blocks as they occur:


@@ -1762,6 +1762,7 @@ void multdiv_alloc(struct regstat *current,int i)
       current->uu&=~(1LL<<HIREG);
       current->uu&=~(1LL<<LOREG);
       alloc_reg64(current,i,HIREG);
       current->uu&=~(1LL<<HIREG);
       current->uu&=~(1LL<<LOREG);
       alloc_reg64(current,i,HIREG);

+         alloc_reg64(current,i,LOREG);

       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); //*SEB* Why commenting this line? uncommenting make SM64 freeze after title (before mario head and spinning stars)
       alloc_reg64(current,i,rs1[i]);
       alloc_reg64(current,i,rs2[i]);
       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG); //*SEB* Why commenting this line? uncommenting make SM64 freeze after title (before mario head and spinning stars)
       alloc_reg64(current,i,rs1[i]);
       alloc_reg64(current,i,rs2[i]);


@@ -1778,10 +1779,18 @@ void multdiv_alloc(struct regstat *current,int i)
     // Multiply by zero is zero.
     // MIPS does not have a divide by zero exception.
     // The result is undefined, we return zero.
     // Multiply by zero is zero.
     // MIPS does not have a divide by zero exception.
     // The result is undefined, we return zero.

-       alloc_reg(current,i,HIREG);
-       alloc_reg(current,i,LOREG);
-       current->is32|=1LL<<HIREG;
-       current->is32|=1LL<<LOREG;
+       if((opcode2[i]&4)==0) // 32-bit
+       {
+               alloc_reg(current,i,HIREG);
+               alloc_reg(current,i,LOREG);
+               current->is32|=1LL<<HIREG;
+               current->is32|=1LL<<LOREG;
+       } else {
+               alloc_reg64(current,i,HIREG);
+               alloc_reg64(current,i,LOREG);
+               current->is32&=~(1LL<<HIREG);
+               current->is32&=~(1LL<<LOREG);
+       }

        dirty_reg(current,HIREG);
        dirty_reg(current,LOREG);
   }
        dirty_reg(current,HIREG);
        dirty_reg(current,LOREG);
   }