[pcsx_rearmed.git] / frontend / plat_pollux.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2009-2011
 *
 * This work is licensed under the terms of the GNU GPLv2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <unistd.h>
#include <linux/fb.h>
#include <sys/mman.h>

#include "common/input.h"
#include "common/menu.h"
#include "warm/warm.h"
#include "plugin_lib.h"
#include "cspace.h"
#include "main.h"
#include "menu.h"
#include "plat.h"

static int fbdev = -1, memdev = -1, battdev = -1;
static volatile unsigned short *memregs;
static volatile unsigned int   *memregl;
static void *fb_vaddrs[2];
static unsigned int fb_paddrs[2];
static int fb_work_buf;
static int cpu_clock_allowed;

static unsigned short *psx_vram;
static unsigned int psx_vram_padds[512];
static int psx_offset, psx_step, psx_width, psx_height, psx_bpp;
static int fb_offset_x, fb_offset_y;

// TODO: get rid of this
struct vout_fbdev;
struct vout_fbdev *layer_fb;
int g_layer_x, g_layer_y, g_layer_w, g_layer_h;

int omap_enable_layer(int enabled)
{
	return 0;
}

static void *fb_flip(void)
{
	memregl[0x406C>>2] = fb_paddrs[fb_work_buf];
	memregl[0x4058>>2] |= 0x10;
	fb_work_buf ^= 1;
	return fb_vaddrs[fb_work_buf];
}

static void pollux_changemode(int bpp, int is_bgr)
{
	int code = 0, bytes = 2;
	unsigned int r;

	printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");

	memregl[0x4004>>2] = 0x00ef013f;
	memregl[0x4000>>2] |= 1 << 3;

	switch (bpp)
	{
		case 8:
			code = 0x443a;
			bytes = 1;
			break;
		case 16:
			code = is_bgr ? 0xc342 : 0x4432;
			bytes = 2;
			break;
		case 24:
			code = is_bgr ? 0xc653 : 0x4653;
			bytes = 3;
			break;
		default:
			printf("unhandled bpp request: %d\n", bpp);
			return;
	}

	memregl[0x405c>>2] = bytes;
	memregl[0x4060>>2] = 320 * bytes;

	r = memregl[0x4058>>2];
	r = (r & 0xffff) | (code << 16) | 0x10;
	memregl[0x4058>>2] = r;
}

/* note: both PLLs are programmed the same way,
 * the databook incorrectly states that PLL1 differs */
static int decode_pll(unsigned int reg)
{
	long long v;
	int p, m, s;

	p = (reg >> 18) & 0x3f;
	m = (reg >> 8) & 0x3ff;
	s = reg & 0xff;

	if (p == 0)
		p = 1;

	v = 27000000; // master clock
	v = v * m / (p << s);
	return v;
}

int plat_cpu_clock_get(void)
{
	return decode_pll(memregl[0xf004>>2]) / 1000000;
}

int plat_cpu_clock_apply(int mhz)
{
	int adiv, mdiv, pdiv, sdiv = 0;
	int i, vf000, vf004;

	if (!cpu_clock_allowed)
		return -1;
	if (mhz == plat_cpu_clock_get())
		return 0;

	// m = MDIV, p = PDIV, s = SDIV
	#define SYS_CLK_FREQ 27
	pdiv = 9;
	mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
	if (mdiv & ~0x3ff)
		return -1;
	vf004 = (pdiv<<18) | (mdiv<<8) | sdiv;

	// attempt to keep the AHB divider close to 250, but not higher
	for (adiv = 1; mhz / adiv > 250; adiv++)
		;

	vf000 = memregl[0xf000>>2];
	vf000 = (vf000 & ~0x3c0) | ((adiv - 1) << 6);
	memregl[0xf000>>2] = vf000;
	memregl[0xf004>>2] = vf004;
	memregl[0xf07c>>2] |= 0x8000;
	for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
		;

	printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);

	// stupid pll share hack - must restart audio
	extern long SPUopen(void);
	extern long SPUclose(void);
	SPUclose();
	SPUopen();

	return 0;
}

int plat_get_bat_capacity(void)
{
	unsigned short magic_val = 0;

	if (battdev < 0)
		return -1;
	if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
		return -1;
	switch (magic_val) {
	default:
	case 1:	return 100;
	case 2: return 66;
	case 3: return 40;
	case 4: return 0;
	}
}

#define TIMER_BASE3 0x1980
#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]

static __attribute__((unused)) unsigned int timer_get(void)
{
	TIMER_REG(0x08) |= 0x48;  /* run timer, latch value */
	return TIMER_REG(0);
}

static void timer_cleanup(void)
{
	TIMER_REG(0x40) = 0x0c;	/* be sure clocks are on */
	TIMER_REG(0x08) = 0x23;	/* stop the timer, clear irq in case it's pending */
	TIMER_REG(0x00) = 0;	/* clear counter */
	TIMER_REG(0x40) = 0;	/* clocks off */
	TIMER_REG(0x44) = 0;	/* dividers back to default */
}

void plat_video_menu_enter(int is_rom_loaded)
{
	if (pl_vout_buf != NULL) {
		if (psx_bpp == 16)
			// have to do rgb conversion for menu bg
			bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 320*240*2);
		else
			memset(pl_vout_buf, 0, 320*240*2);
	}

	pollux_changemode(16, 0);
}

void plat_video_menu_begin(void)
{
}

void plat_video_menu_end(void)
{
	g_menuscreen_ptr = fb_flip();
}

void plat_video_menu_leave(void)
{
	if (psx_vram == NULL) {
		fprintf(stderr, "GPU plugin did not provide vram\n");
		exit(1);
	}

	in_set_config_int(in_name_to_id("evdev:pollux-analog"),
			IN_CFG_ABS_DEAD_ZONE, analog_deadzone);

	memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
	g_menuscreen_ptr = fb_flip();
	memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);

	pollux_changemode(psx_bpp, 1);
}

static void pl_vout_set_raw_vram(void *vram)
{
	int i;

	psx_vram = vram;

	if (vram == NULL)
		return;

	if ((long)psx_vram & 0x7ff)
		fprintf(stderr, "GPU plugin did not align vram\n");

	for (i = 0; i < 512; i++) {
		psx_vram[i * 1024] = 0; // touch
		psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
	}
}

static void *pl_vout_set_mode(int w, int h, int bpp)
{
	static int old_w, old_h, old_bpp;
	int poff_w, poff_h;

	if (!w || !h || !bpp || (w == old_w && h == old_h && bpp == old_bpp))
		return NULL;

	printf("psx mode: %dx%d@%d\n", w, h, bpp);

	psx_step = 1;
	if (h > 256) {
		psx_step = 2;
		h /= 2;
	}

	poff_w = poff_h = 0;
	if (w > 320) {
		poff_w = w / 2 - 320/2;
		w = 320;
	}
	if (h > 240) {
		poff_h = h / 2 - 240/2;
		h = 240;
	}
	fb_offset_x = 320/2 - w / 2;
	fb_offset_y = 240/2 - h / 2;

	psx_offset = poff_h * 1024 + poff_w;
	psx_width = w;
	psx_height = h;
	psx_bpp = bpp;

	if (fb_offset_x || fb_offset_y) {
		// not fullscreen, must clear borders
		memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
		g_menuscreen_ptr = fb_flip();
		memset(g_menuscreen_ptr, 0, 320*240 * psx_bpp/8);
	}

	pollux_changemode(bpp, 1);

	return NULL;
}

static void spend_cycles(int loops)
{
	asm volatile (
		"   mov  r0,%0    ;\n"
		"0: subs r0,r0,#1 ;\n"
		"   bgt  0b"
		:: "r" (loops) : "cc", "r0");
}

#define DMA_BASE6 0x0300
#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]

/* this takes ~1.5ms, while ldm/stm ~1.95ms */
static void raw_flip_dma(int x, int y)
{
	unsigned int dst = fb_paddrs[fb_work_buf] +
			(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
	int spsx_line = y + (psx_offset >> 10);
	int spsx_offset = (x + psx_offset) & 0x3f8;
	int dst_stride = 320 * psx_bpp / 8;
	int len = psx_width * psx_bpp / 8;
	//unsigned int st = timer_get();
	int i;

	warm_cache_op_all(WOP_D_CLEAN);

	dst &= ~7;
	len &= ~7;

	if (DMA_REG(0x0c) & 0x90000) {
		printf("already runnig DMA?\n");
		DMA_REG(0x0c) = 0x100000;
	}
	if ((DMA_REG(0x2c) & 0x0f) < 5) {
		printf("DMA queue busy?\n");
		DMA_REG(0x24) = 1;
	}

	for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
		while ((DMA_REG(0x2c) & 0x0f) < 4)
			spend_cycles(10);

		// XXX: it seems we must always set all regs, what is autoincrement there for?
		DMA_REG(0x20) = 1;		// queue wait cmd
		DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
		DMA_REG(0x14) = dst;		// DMA dst
		DMA_REG(0x18) = len - 1;	// len
		DMA_REG(0x1c) = 0x80000;	// go
	}

	//printf("d %d\n", timer_get() - st);

	if (psx_bpp == 16) {
		pl_vout_buf = g_menuscreen_ptr;
		pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
	}

	g_menuscreen_ptr = fb_flip();
	pl_flip_cnt++;
}

static void raw_flip_soft(int x, int y)
{
	unsigned short *src = psx_vram + y * 1024 + x + psx_offset;
	unsigned char *dst = (unsigned char *)g_menuscreen_ptr +
			(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
	int dst_stride = 320 * psx_bpp / 8;
	int len = psx_width * psx_bpp / 8;
	//unsigned int st = timer_get();
	int i;

	for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride)
		memcpy(dst, src, len);

	//printf("s %d\n", timer_get() - st);

	if (psx_bpp == 16) {
		pl_vout_buf = g_menuscreen_ptr;
		pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
	}

	g_menuscreen_ptr = fb_flip();
	pl_flip_cnt++;
}

static void *pl_vout_flip(void)
{
	return NULL;
}

void plat_init(void)
{
	const char *main_fb_name = "/dev/fb0";
	struct fb_fix_screeninfo fbfix;
	int rate, timer_div, timer_div2;
	int fbdev, ret, warm_ret;

	memdev = open("/dev/mem", O_RDWR);
	if (memdev == -1) {
		perror("open(/dev/mem) failed");
		exit(1);
	}

	memregs	= mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
	if (memregs == MAP_FAILED) {
		perror("mmap(memregs) failed");
		exit(1);
	}
	memregl = (volatile void *)memregs;

	fbdev = open(main_fb_name, O_RDWR);
	if (fbdev == -1) {
		fprintf(stderr, "%s: ", main_fb_name);
		perror("open");
		exit(1);
	}

	ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
	if (ret == -1) {
		perror("ioctl(fbdev) failed");
		exit(1);
	}
	printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
	fb_paddrs[0] = fbfix.smem_start;
	fb_paddrs[1] = fb_paddrs[0] + 320*240*4; // leave space for 24bpp

	fb_vaddrs[0] = mmap(0, 320*240*2*4, PROT_READ|PROT_WRITE,
				MAP_SHARED, memdev, fb_paddrs[0]);
	if (fb_vaddrs[0] == MAP_FAILED) {
		perror("mmap(fb_vaddrs) failed");
		exit(1);
	}
	fb_vaddrs[1] = (char *)fb_vaddrs[0] + 320*240*4;

	pollux_changemode(16, 0);
	g_menuscreen_w = 320;
	g_menuscreen_h = 240;
	g_menuscreen_ptr = fb_flip();

	g_menubg_ptr = calloc(320*240*2, 1);
	if (g_menubg_ptr == NULL) {
		fprintf(stderr, "OOM\n");
		exit(1);
	}

	warm_ret = warm_init();
	warm_change_cb_upper(WCB_B_BIT, 1);

	/* some firmwares have sys clk on PLL0, we can't adjust CPU clock
	 * by reprogramming the PLL0 then, as it overclocks system bus */
	if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
		cpu_clock_allowed = 1;
	else {
		cpu_clock_allowed = 0;
		fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
			memregl[0xf000>>2]);
	}

	/* find what PLL1 runs at, for the timer */
	rate = decode_pll(memregl[0xf008>>2]);
	printf("PLL1 @ %dHz\n", rate);

	/* setup timer */
	timer_div = (rate + 500000) / 1000000;
	timer_div2 = 0;
	while (timer_div > 256) {
		timer_div /= 2;
		timer_div2++;
	}
	if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
		int timer_rate = (rate >> timer_div2) / timer_div;
		if (TIMER_REG(0x08) & 8) {
			fprintf(stderr, "warning: timer in use, overriding!\n");
			timer_cleanup();
		}
		if (timer_rate != 1000000)
			fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);

		timer_div2 = (timer_div2 + 3) & 3;
		TIMER_REG(0x44) = ((timer_div - 1) << 4) | 2;	/* using PLL1 */
		TIMER_REG(0x40) = 0x0c;				/* clocks on */
		TIMER_REG(0x08) = 0x68 | timer_div2;		/* run timer, clear irq, latch value */
	}
	else
		fprintf(stderr, "warning: could not make use of timer\n");

	/* setup DMA */
	DMA_REG(0x0c) = 0x20000; // pending IRQ clear

	battdev = open("/dev/pollux_batt", O_RDONLY);
	if (battdev < 0)
		perror("Warning: could't open pollux_batt");

	// hmh
	plat_rescan_inputs();

	pl_rearmed_cbs.pl_vout_flip = pl_vout_flip;
	pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft;
	pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode;
	pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;

	psx_width = 320;
	psx_height = 240;
	psx_bpp = 16;
}

void plat_finish(void)
{
	warm_finish();
	timer_cleanup();
	pollux_changemode(16, 0);
	fb_work_buf = 0;
	fb_flip();

	if (battdev >= 0)
		close(battdev);
	munmap(fb_vaddrs[0], 320*240*2*2);
	close(fbdev);
	munmap((void *)memregs, 0x20000);
	close(memdev);
}

void in_update_analogs(void)
{
}

/* Caanoo stuff, perhaps move later */
#include <linux/input.h>

struct in_default_bind in_evdev_defbinds[] = {
	{ KEY_UP,	IN_BINDTYPE_PLAYER12, DKEY_UP },
	{ KEY_DOWN,	IN_BINDTYPE_PLAYER12, DKEY_DOWN },
	{ KEY_LEFT,	IN_BINDTYPE_PLAYER12, DKEY_LEFT },
	{ KEY_RIGHT,	IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
	{ BTN_TOP,	IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
	{ BTN_THUMB,	IN_BINDTYPE_PLAYER12, DKEY_CROSS },
	{ BTN_THUMB2,	IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
	{ BTN_TRIGGER,	IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
	{ BTN_BASE3,	IN_BINDTYPE_PLAYER12, DKEY_START },
	{ BTN_BASE4,	IN_BINDTYPE_PLAYER12, DKEY_SELECT },
	{ BTN_TOP2,	IN_BINDTYPE_PLAYER12, DKEY_L1 },
	{ BTN_PINKIE,	IN_BINDTYPE_PLAYER12, DKEY_R1 },
	{ BTN_BASE,	IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
	{ 0, 0, 0 },
};

static const char * const caanoo_keys[KEY_MAX + 1] = {
	[0 ... KEY_MAX] = NULL,
	[KEY_UP]        = "Up",
	[KEY_LEFT]      = "Left",
	[KEY_RIGHT]     = "Right",
	[KEY_DOWN]      = "Down",
	[BTN_TRIGGER]   = "A",
	[BTN_THUMB]     = "X",
	[BTN_THUMB2]    = "B",
	[BTN_TOP]       = "Y",
	[BTN_TOP2]      = "L",
	[BTN_PINKIE]    = "R",
	[BTN_BASE]      = "Home",
	[BTN_BASE2]     = "Lock",
	[BTN_BASE3]     = "I",
	[BTN_BASE4]     = "II",
	[BTN_BASE5]     = "Push",
};

int plat_rescan_inputs(void)
{
	in_probe();
	in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
		      caanoo_keys, sizeof(caanoo_keys));
	return 0;
}
Commit	Line	Data
55b0eeea	1	/*
	2	* (C) Gražvydas "notaz" Ignotas, 2009-2011
	3	*
	4	* This work is licensed under the terms of the GNU GPLv2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#include <stdio.h>
	9	#include <stdlib.h>
	10	#include <string.h>
	11	#include <sys/types.h>
	12	#include <sys/stat.h>
	13	#include <fcntl.h>
	14	#include <sys/ioctl.h>
	15	#include <unistd.h>
	16	#include <linux/fb.h>
	17	#include <sys/mman.h>
	18
	19	#include "common/input.h"
	20	#include "common/menu.h"
	21	#include "warm/warm.h"
	22	#include "plugin_lib.h"
	23	#include "cspace.h"
	24	#include "main.h"
	25	#include "menu.h"
	26	#include "plat.h"
	27
	28	static int fbdev = -1, memdev = -1, battdev = -1;
	29	static volatile unsigned short *memregs;
	30	static volatile unsigned int *memregl;
	31	static void *fb_vaddrs[2];
	32	static unsigned int fb_paddrs[2];
	33	static int fb_work_buf;
	34	static int cpu_clock_allowed;
	35
	36	static unsigned short *psx_vram;
	37	static unsigned int psx_vram_padds[512];
	38	static int psx_offset, psx_step, psx_width, psx_height, psx_bpp;
41f55c9f	39	static int fb_offset_x, fb_offset_y;
55b0eeea	40
	41	// TODO: get rid of this
	42	struct vout_fbdev;
	43	struct vout_fbdev *layer_fb;
	44	int g_layer_x, g_layer_y, g_layer_w, g_layer_h;
	45
	46	int omap_enable_layer(int enabled)
	47	{
	48	return 0;
	49	}
	50
	51	static void *fb_flip(void)
	52	{
	53	memregl[0x406C>>2] = fb_paddrs[fb_work_buf];
	54	memregl[0x4058>>2] \|= 0x10;
	55	fb_work_buf ^= 1;
	56	return fb_vaddrs[fb_work_buf];
	57	}
	58
	59	static void pollux_changemode(int bpp, int is_bgr)
	60	{
	61	int code = 0, bytes = 2;
	62	unsigned int r;
	63
	64	printf("changemode: %dbpp %s\n", bpp, is_bgr ? "bgr" : "rgb");
	65
	66	memregl[0x4004>>2] = 0x00ef013f;
	67	memregl[0x4000>>2] \|= 1 << 3;
	68
	69	switch (bpp)
	70	{
	71	case 8:
	72	code = 0x443a;
	73	bytes = 1;
	74	break;
	75	case 16:
	76	code = is_bgr ? 0xc342 : 0x4432;
	77	bytes = 2;
	78	break;
	79	case 24:
	80	code = is_bgr ? 0xc653 : 0x4653;
	81	bytes = 3;
	82	break;
	83	default:
	84	printf("unhandled bpp request: %d\n", bpp);
	85	return;
	86	}
	87
	88	memregl[0x405c>>2] = bytes;
	89	memregl[0x4060>>2] = 320 * bytes;
	90
	91	r = memregl[0x4058>>2];
	92	r = (r & 0xffff) \| (code << 16) \| 0x10;
	93	memregl[0x4058>>2] = r;
	94	}
	95
	96	/* note: both PLLs are programmed the same way,
	97	* the databook incorrectly states that PLL1 differs */
	98	static int decode_pll(unsigned int reg)
	99	{
	100	long long v;
	101	int p, m, s;
	102
	103	p = (reg >> 18) & 0x3f;
104	m = (reg >> 8) & 0x3ff;
105	s = reg & 0xff;
106
107	if (p == 0)
108	p = 1;
109
110	v = 27000000; // master clock
111	v = v * m / (p << s);
112	return v;
113	}
114
115	int plat_cpu_clock_get(void)
116	{
117	return decode_pll(memregl[0xf004>>2]) / 1000000;
118	}
119
120	int plat_cpu_clock_apply(int mhz)
121	{
122	int adiv, mdiv, pdiv, sdiv = 0;
123	int i, vf000, vf004;
124
125	if (!cpu_clock_allowed)
126	return -1;
127	if (mhz == plat_cpu_clock_get())
128	return 0;
129
130	// m = MDIV, p = PDIV, s = SDIV
131	#define SYS_CLK_FREQ 27
132	pdiv = 9;
133	mdiv = (mhz * pdiv) / SYS_CLK_FREQ;
134	if (mdiv & ~0x3ff)
135	return -1;
136	vf004 = (pdiv<<18) \| (mdiv<<8) \| sdiv;
137
138	// attempt to keep the AHB divider close to 250, but not higher
139	for (adiv = 1; mhz / adiv > 250; adiv++)
140	;
141
142	vf000 = memregl[0xf000>>2];
143	vf000 = (vf000 & ~0x3c0) \| ((adiv - 1) << 6);
144	memregl[0xf000>>2] = vf000;
145	memregl[0xf004>>2] = vf004;
146	memregl[0xf07c>>2] \|= 0x8000;
147	for (i = 0; (memregl[0xf07c>>2] & 0x8000) && i < 0x100000; i++)
148	;
149
150	printf("clock set to %dMHz, AHB set to %dMHz\n", mhz, mhz / adiv);
151
152	// stupid pll share hack - must restart audio
153	extern long SPUopen(void);
154	extern long SPUclose(void);
155	SPUclose();
156	SPUopen();
157
158	return 0;
159	}
160
161	int plat_get_bat_capacity(void)
162	{
163	unsigned short magic_val = 0;
164
165	if (battdev < 0)
166	return -1;
167	if (read(battdev, &magic_val, sizeof(magic_val)) != sizeof(magic_val))
168	return -1;
169	switch (magic_val) {
170	default:
171	case 1: return 100;
172	case 2: return 66;
173	case 3: return 40;
174	case 4: return 0;
175	}
176	}
177
178	#define TIMER_BASE3 0x1980
179	#define TIMER_REG(x) memregl[(TIMER_BASE3 + x) >> 2]
180
181	static __attribute__((unused)) unsigned int timer_get(void)
182	{
183	TIMER_REG(0x08) \|= 0x48; /* run timer, latch value */
184	return TIMER_REG(0);
185	}
186
187	static void timer_cleanup(void)
188	{
189	TIMER_REG(0x40) = 0x0c; /* be sure clocks are on */
190	TIMER_REG(0x08) = 0x23; /* stop the timer, clear irq in case it's pending */
191	TIMER_REG(0x00) = 0; /* clear counter */
192	TIMER_REG(0x40) = 0; /* clocks off */
193	TIMER_REG(0x44) = 0; /* dividers back to default */
194	}
195
196	void plat_video_menu_enter(int is_rom_loaded)
197	{
198	if (pl_vout_buf != NULL) {
199	if (psx_bpp == 16)
200	// have to do rgb conversion for menu bg
201	bgr555_to_rgb565(pl_vout_buf, pl_vout_buf, 3202402);
202	else
203	memset(pl_vout_buf, 0, 3202402);
204	}
205
206	pollux_changemode(16, 0);
207	}
208
209	void plat_video_menu_begin(void)
210	{
211	}
212
213	void plat_video_menu_end(void)
214	{
215	g_menuscreen_ptr = fb_flip();
216	}
217
218	void plat_video_menu_leave(void)
219	{
55b0eeea	220	if (psx_vram == NULL) {
	221	fprintf(stderr, "GPU plugin did not provide vram\n");
	222	exit(1);
	223	}
	224
	225	in_set_config_int(in_name_to_id("evdev:pollux-analog"),
	226	IN_CFG_ABS_DEAD_ZONE, analog_deadzone);
41f55c9f	227
	228	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	229	g_menuscreen_ptr = fb_flip();
	230	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	231
	232	pollux_changemode(psx_bpp, 1);
55b0eeea	233	}
	234
	235	static void pl_vout_set_raw_vram(void *vram)
	236	{
	237	int i;
	238
	239	psx_vram = vram;
	240
	241	if (vram == NULL)
	242	return;
	243
	244	if ((long)psx_vram & 0x7ff)
	245	fprintf(stderr, "GPU plugin did not align vram\n");
	246
	247	for (i = 0; i < 512; i++) {
	248	psx_vram[i * 1024] = 0; // touch
	249	psx_vram_padds[i] = warm_virt2phys(&psx_vram[i * 1024]);
	250	}
	251	}
	252
	253	static void *pl_vout_set_mode(int w, int h, int bpp)
	254	{
	255	static int old_w, old_h, old_bpp;
55b0eeea	256	int poff_w, poff_h;
	257
	258	if (!w \|\| !h \|\| !bpp \|\| (w == old_w && h == old_h && bpp == old_bpp))
	259	return NULL;
	260
	261	printf("psx mode: %dx%d@%d\n", w, h, bpp);
	262
	263	psx_step = 1;
	264	if (h > 256) {
	265	psx_step = 2;
	266	h /= 2;
	267	}
	268
	269	poff_w = poff_h = 0;
	270	if (w > 320) {
	271	poff_w = w / 2 - 320/2;
	272	w = 320;
	273	}
	274	if (h > 240) {
	275	poff_h = h / 2 - 240/2;
	276	h = 240;
	277	}
41f55c9f	278	fb_offset_x = 320/2 - w / 2;
41f55c9f	279	fb_offset_y = 240/2 - h / 2;
55b0eeea	280
	281	psx_offset = poff_h * 1024 + poff_w;
	282	psx_width = w;
	283	psx_height = h;
	284	psx_bpp = bpp;
41f55c9f	285
	286	if (fb_offset_x \|\| fb_offset_y) {
	287	// not fullscreen, must clear borders
	288	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	289	g_menuscreen_ptr = fb_flip();
	290	memset(g_menuscreen_ptr, 0, 320240 psx_bpp/8);
	291	}
55b0eeea	292
	293	pollux_changemode(bpp, 1);
	294
	295	return NULL;
	296	}
	297
	298	static void spend_cycles(int loops)
	299	{
	300	asm volatile (
	301	" mov r0,%0 ;\n"
	302	"0: subs r0,r0,#1 ;\n"
	303	" bgt 0b"
	304	:: "r" (loops) : "cc", "r0");
	305	}
	306
	307	#define DMA_BASE6 0x0300
	308	#define DMA_REG(x) memregl[(DMA_BASE6 + x) >> 2]
	309
	310	/* this takes ~1.5ms, while ldm/stm ~1.95ms */
	311	static void raw_flip_dma(int x, int y)
	312	{
41f55c9f	313	unsigned int dst = fb_paddrs[fb_work_buf] +
41f55c9f	314	(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
55b0eeea	315	int spsx_line = y + (psx_offset >> 10);
	316	int spsx_offset = (x + psx_offset) & 0x3f8;
	317	int dst_stride = 320 * psx_bpp / 8;
	318	int len = psx_width * psx_bpp / 8;
	319	//unsigned int st = timer_get();
	320	int i;
	321
	322	warm_cache_op_all(WOP_D_CLEAN);
	323
	324	dst &= ~7;
	325	len &= ~7;
	326
	327	if (DMA_REG(0x0c) & 0x90000) {
	328	printf("already runnig DMA?\n");
	329	DMA_REG(0x0c) = 0x100000;
	330	}
	331	if ((DMA_REG(0x2c) & 0x0f) < 5) {
	332	printf("DMA queue busy?\n");
	333	DMA_REG(0x24) = 1;
	334	}
	335
	336	for (i = psx_height; i > 0; i--, spsx_line += psx_step, dst += dst_stride) {
	337	while ((DMA_REG(0x2c) & 0x0f) < 4)
	338	spend_cycles(10);
	339
	340	// XXX: it seems we must always set all regs, what is autoincrement there for?
	341	DMA_REG(0x20) = 1; // queue wait cmd
	342	DMA_REG(0x10) = psx_vram_padds[spsx_line & 511] + spsx_offset * 2; // DMA src
	343	DMA_REG(0x14) = dst; // DMA dst
	344	DMA_REG(0x18) = len - 1; // len
	345	DMA_REG(0x1c) = 0x80000; // go
	346	}
	347
	348	//printf("d %d\n", timer_get() - st);
	349
	350	if (psx_bpp == 16) {
	351	pl_vout_buf = g_menuscreen_ptr;
41f55c9f	352	pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
55b0eeea	353	}
	354
	355	g_menuscreen_ptr = fb_flip();
	356	pl_flip_cnt++;
	357	}
	358
	359	static void raw_flip_soft(int x, int y)
	360	{
	361	unsigned short src = psx_vram + y 1024 + x + psx_offset;
41f55c9f	362	unsigned char dst = (unsigned char )g_menuscreen_ptr +
41f55c9f	363	(fb_offset_y * 320 + fb_offset_x) * psx_bpp / 8;
55b0eeea	364	int dst_stride = 320 * psx_bpp / 8;
	365	int len = psx_width * psx_bpp / 8;
	366	//unsigned int st = timer_get();
	367	int i;
	368
	369	for (i = psx_height; i > 0; i--, src += psx_step * 1024, dst += dst_stride)
	370	memcpy(dst, src, len);
	371
	372	//printf("s %d\n", timer_get() - st);
	373
	374	if (psx_bpp == 16) {
	375	pl_vout_buf = g_menuscreen_ptr;
41f55c9f	376	pl_print_hud(320, fb_offset_y + psx_height, fb_offset_x);
55b0eeea	377	}
	378
	379	g_menuscreen_ptr = fb_flip();
	380	pl_flip_cnt++;
	381	}
	382
41f55c9f	383	static void *pl_vout_flip(void)
	384	{
	385	return NULL;
	386	}
	387
55b0eeea	388	void plat_init(void)
	389	{
	390	const char *main_fb_name = "/dev/fb0";
	391	struct fb_fix_screeninfo fbfix;
	392	int rate, timer_div, timer_div2;
	393	int fbdev, ret, warm_ret;
	394
	395	memdev = open("/dev/mem", O_RDWR);
	396	if (memdev == -1) {
	397	perror("open(/dev/mem) failed");
	398	exit(1);
	399	}
	400
	401	memregs = mmap(0, 0x20000, PROT_READ\|PROT_WRITE, MAP_SHARED, memdev, 0xc0000000);
	402	if (memregs == MAP_FAILED) {
	403	perror("mmap(memregs) failed");
	404	exit(1);
	405	}
	406	memregl = (volatile void *)memregs;
	407
	408	fbdev = open(main_fb_name, O_RDWR);
	409	if (fbdev == -1) {
	410	fprintf(stderr, "%s: ", main_fb_name);
	411	perror("open");
	412	exit(1);
	413	}
	414
	415	ret = ioctl(fbdev, FBIOGET_FSCREENINFO, &fbfix);
	416	if (ret == -1) {
	417	perror("ioctl(fbdev) failed");
	418	exit(1);
	419	}
	420	printf("framebuffer: \"%s\" @ %08lx\n", fbfix.id, fbfix.smem_start);
	421	fb_paddrs[0] = fbfix.smem_start;
	422	fb_paddrs[1] = fb_paddrs[0] + 3202404; // leave space for 24bpp
	423
	424	fb_vaddrs[0] = mmap(0, 3202402*4, PROT_READ\|PROT_WRITE,
	425	MAP_SHARED, memdev, fb_paddrs[0]);
	426	if (fb_vaddrs[0] == MAP_FAILED) {
	427	perror("mmap(fb_vaddrs) failed");
	428	exit(1);
	429	}
	430	fb_vaddrs[1] = (char )fb_vaddrs[0] + 320240*4;
	431
	432	pollux_changemode(16, 0);
	433	g_menuscreen_w = 320;
	434	g_menuscreen_h = 240;
	435	g_menuscreen_ptr = fb_flip();
	436
	437	g_menubg_ptr = calloc(3202402, 1);
	438	if (g_menubg_ptr == NULL) {
	439	fprintf(stderr, "OOM\n");
	440	exit(1);
	441	}
	442
	443	warm_ret = warm_init();
	444	warm_change_cb_upper(WCB_B_BIT, 1);
	445
	446	/* some firmwares have sys clk on PLL0, we can't adjust CPU clock
	447	* by reprogramming the PLL0 then, as it overclocks system bus */
	448	if ((memregl[0xf000>>2] & 0x03000030) == 0x01000000)
	449	cpu_clock_allowed = 1;
	450	else {
	451	cpu_clock_allowed = 0;
452	fprintf(stderr, "unexpected PLL config (%08x), overclocking disabled\n",
453	memregl[0xf000>>2]);
454	}
455
456	/* find what PLL1 runs at, for the timer */
457	rate = decode_pll(memregl[0xf008>>2]);
458	printf("PLL1 @ %dHz\n", rate);
459
460	/* setup timer */
461	timer_div = (rate + 500000) / 1000000;
462	timer_div2 = 0;
463	while (timer_div > 256) {
464	timer_div /= 2;
465	timer_div2++;
466	}
467	if (1 <= timer_div && timer_div <= 256 && timer_div2 < 4) {
468	int timer_rate = (rate >> timer_div2) / timer_div;
469	if (TIMER_REG(0x08) & 8) {
470	fprintf(stderr, "warning: timer in use, overriding!\n");
471	timer_cleanup();
472	}
473	if (timer_rate != 1000000)
474	fprintf(stderr, "warning: timer drift %d us\n", timer_rate - 1000000);
475
476	timer_div2 = (timer_div2 + 3) & 3;
477	TIMER_REG(0x44) = ((timer_div - 1) << 4) \| 2; /* using PLL1 */
478	TIMER_REG(0x40) = 0x0c; /* clocks on */
479	TIMER_REG(0x08) = 0x68 \| timer_div2; /* run timer, clear irq, latch value */
480	}
481	else
482	fprintf(stderr, "warning: could not make use of timer\n");
483
484	/* setup DMA */
485	DMA_REG(0x0c) = 0x20000; // pending IRQ clear
486
487	battdev = open("/dev/pollux_batt", O_RDONLY);
488	if (battdev < 0)
489	perror("Warning: could't open pollux_batt");
490
491	// hmh
492	plat_rescan_inputs();
493
41f55c9f	494	pl_rearmed_cbs.pl_vout_flip = pl_vout_flip;
55b0eeea	495	pl_rearmed_cbs.pl_vout_raw_flip = warm_ret == 0 ? raw_flip_dma : raw_flip_soft;
	496	pl_rearmed_cbs.pl_vout_set_mode = pl_vout_set_mode;
	497	pl_rearmed_cbs.pl_vout_set_raw_vram = pl_vout_set_raw_vram;
	498
	499	psx_width = 320;
	500	psx_height = 240;
	501	psx_bpp = 16;
	502	}
	503
	504	void plat_finish(void)
	505	{
	506	warm_finish();
	507	timer_cleanup();
	508	pollux_changemode(16, 0);
	509	fb_work_buf = 0;
	510	fb_flip();
	511
	512	if (battdev >= 0)
	513	close(battdev);
	514	munmap(fb_vaddrs[0], 3202402*2);
	515	close(fbdev);
	516	munmap((void *)memregs, 0x20000);
	517	close(memdev);
	518	}
	519
	520	void in_update_analogs(void)
	521	{
	522	}
	523
	524	/* Caanoo stuff, perhaps move later */
	525	#include <linux/input.h>
	526
	527	struct in_default_bind in_evdev_defbinds[] = {
	528	{ KEY_UP, IN_BINDTYPE_PLAYER12, DKEY_UP },
	529	{ KEY_DOWN, IN_BINDTYPE_PLAYER12, DKEY_DOWN },
	530	{ KEY_LEFT, IN_BINDTYPE_PLAYER12, DKEY_LEFT },
	531	{ KEY_RIGHT, IN_BINDTYPE_PLAYER12, DKEY_RIGHT },
	532	{ BTN_TOP, IN_BINDTYPE_PLAYER12, DKEY_TRIANGLE },
	533	{ BTN_THUMB, IN_BINDTYPE_PLAYER12, DKEY_CROSS },
	534	{ BTN_THUMB2, IN_BINDTYPE_PLAYER12, DKEY_CIRCLE },
	535	{ BTN_TRIGGER, IN_BINDTYPE_PLAYER12, DKEY_SQUARE },
	536	{ BTN_BASE3, IN_BINDTYPE_PLAYER12, DKEY_START },
	537	{ BTN_BASE4, IN_BINDTYPE_PLAYER12, DKEY_SELECT },
	538	{ BTN_TOP2, IN_BINDTYPE_PLAYER12, DKEY_L1 },
	539	{ BTN_PINKIE, IN_BINDTYPE_PLAYER12, DKEY_R1 },
	540	{ BTN_BASE, IN_BINDTYPE_EMU, SACTION_ENTER_MENU },
	541	{ 0, 0, 0 },
	542	};
	543
	544	static const char * const caanoo_keys[KEY_MAX + 1] = {
	545	[0 ... KEY_MAX] = NULL,
	546	[KEY_UP] = "Up",
	547	[KEY_LEFT] = "Left",
	548	[KEY_RIGHT] = "Right",
	549	[KEY_DOWN] = "Down",
	550	[BTN_TRIGGER] = "A",
	551	[BTN_THUMB] = "X",
	552	[BTN_THUMB2] = "B",
	553	[BTN_TOP] = "Y",
	554	[BTN_TOP2] = "L",
	555	[BTN_PINKIE] = "R",
	556	[BTN_BASE] = "Home",
	557	[BTN_BASE2] = "Lock",
	558	[BTN_BASE3] = "I",
559	[BTN_BASE4] = "II",
560	[BTN_BASE5] = "Push",
561	};
562
563	int plat_rescan_inputs(void)
564	{
565	in_probe();
566	in_set_config(in_name_to_id("evdev:pollux-analog"), IN_CFG_KEY_NAMES,
567	caanoo_keys, sizeof(caanoo_keys));
568	return 0;
569	}