psxcounters: avoid doing excessive updates
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / assem_arm.c
<
CommitLineData
57871462 1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
c6c3b1b3 2 * Mupen64plus/PCSX - assem_arm.c *
20d507ba 3 * Copyright (C) 2009-2011 Ari64 *
c6c3b1b3 4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
57871462 5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
21
22extern int cycle_count;
23extern int last_count;
24extern int pcaddr;
25extern int pending_exception;
26extern int branch_target;
27extern uint64_t readmem_dword;
3d624f89 28#ifdef MUPEN64
57871462 29extern precomp_instr fake_pc;
3d624f89 30#endif
57871462 31extern void *dynarec_local;
32extern u_int memory_map[1048576];
33extern u_int mini_ht[32][2];
34extern u_int rounding_modes[4];
35
36void indirect_jump_indexed();
37void indirect_jump();
38void do_interrupt();
39void jump_vaddr_r0();
40void jump_vaddr_r1();
41void jump_vaddr_r2();
42void jump_vaddr_r3();
43void jump_vaddr_r4();
44void jump_vaddr_r5();
45void jump_vaddr_r6();
46void jump_vaddr_r7();
47void jump_vaddr_r8();
48void jump_vaddr_r9();
49void jump_vaddr_r10();
50void jump_vaddr_r12();
51
52const u_int jump_vaddr_reg[16] = {
53 (int)jump_vaddr_r0,
54 (int)jump_vaddr_r1,
55 (int)jump_vaddr_r2,
56 (int)jump_vaddr_r3,
57 (int)jump_vaddr_r4,
58 (int)jump_vaddr_r5,
59 (int)jump_vaddr_r6,
60 (int)jump_vaddr_r7,
61 (int)jump_vaddr_r8,
62 (int)jump_vaddr_r9,
63 (int)jump_vaddr_r10,
64 0,
65 (int)jump_vaddr_r12,
66 0,
67 0,
68 0};
69
0bbd1454 70void invalidate_addr_r0();
71void invalidate_addr_r1();
72void invalidate_addr_r2();
73void invalidate_addr_r3();
74void invalidate_addr_r4();
75void invalidate_addr_r5();
76void invalidate_addr_r6();
77void invalidate_addr_r7();
78void invalidate_addr_r8();
79void invalidate_addr_r9();
80void invalidate_addr_r10();
81void invalidate_addr_r12();
82
83const u_int invalidate_addr_reg[16] = {
84 (int)invalidate_addr_r0,
85 (int)invalidate_addr_r1,
86 (int)invalidate_addr_r2,
87 (int)invalidate_addr_r3,
88 (int)invalidate_addr_r4,
89 (int)invalidate_addr_r5,
90 (int)invalidate_addr_r6,
91 (int)invalidate_addr_r7,
92 (int)invalidate_addr_r8,
93 (int)invalidate_addr_r9,
94 (int)invalidate_addr_r10,
95 0,
96 (int)invalidate_addr_r12,
97 0,
98 0,
99 0};
100
57871462 101#include "fpu.h"
102
dd3a91a1 103unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
104
57871462 105/* Linker */
106
107void set_jump_target(int addr,u_int target)
108{
109 u_char *ptr=(u_char *)addr;
110 u_int *ptr2=(u_int *)ptr;
111 if(ptr[3]==0xe2) {
112 assert((target-(u_int)ptr2-8)<1024);
113 assert((addr&3)==0);
114 assert((target&3)==0);
115 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
116 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
117 }
118 else if(ptr[3]==0x72) {
119 // generated by emit_jno_unlikely
120 if((target-(u_int)ptr2-8)<1024) {
121 assert((addr&3)==0);
122 assert((target&3)==0);
123 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
124 }
125 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
126 assert((addr&3)==0);
127 assert((target&3)==0);
128 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
129 }
130 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
131 }
132 else {
133 assert((ptr[3]&0x0e)==0xa);
134 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
135 }
136}
137
138// This optionally copies the instruction from the target of the branch into
139// the space before the branch. Works, but the difference in speed is
140// usually insignificant.
141void set_jump_target_fillslot(int addr,u_int target,int copy)
142{
143 u_char *ptr=(u_char *)addr;
144 u_int *ptr2=(u_int *)ptr;
145 assert(!copy||ptr2[-1]==0xe28dd000);
146 if(ptr[3]==0xe2) {
147 assert(!copy);
148 assert((target-(u_int)ptr2-8)<4096);
149 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
150 }
151 else {
152 assert((ptr[3]&0x0e)==0xa);
153 u_int target_insn=*(u_int *)target;
154 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
155 copy=0;
156 }
157 if((target_insn&0x0c100000)==0x04100000) { // Load
158 copy=0;
159 }
160 if(target_insn&0x08000000) {
161 copy=0;
162 }
163 if(copy) {
164 ptr2[-1]=target_insn;
165 target+=4;
166 }
167 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
168 }
169}
170
171/* Literal pool */
172add_literal(int addr,int val)
173{
15776b68 174 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
57871462 175 literals[literalcount][0]=addr;
176 literals[literalcount][1]=val;
177 literalcount++;
178}
179
f76eeef9 180void *kill_pointer(void *stub)
57871462 181{
182 int *ptr=(int *)(stub+4);
183 assert((*ptr&0x0ff00000)==0x05900000);
184 u_int offset=*ptr&0xfff;
185 int **l_ptr=(void *)ptr+offset+8;
186 int *i_ptr=*l_ptr;
187 set_jump_target((int)i_ptr,(int)stub);
f76eeef9 188 return i_ptr;
57871462 189}
190
f968d35d 191// find where external branch is liked to using addr of it's stub:
192// get address that insn one after stub loads (dyna_linker arg1),
193// treat it as a pointer to branch insn,
194// return addr where that branch jumps to
57871462 195int get_pointer(void *stub)
196{
197 //printf("get_pointer(%x)\n",(int)stub);
198 int *ptr=(int *)(stub+4);
f968d35d 199 assert((*ptr&0x0fff0000)==0x059f0000);
57871462 200 u_int offset=*ptr&0xfff;
201 int **l_ptr=(void *)ptr+offset+8;
202 int *i_ptr=*l_ptr;
203 assert((*i_ptr&0x0f000000)==0x0a000000);
204 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
205}
206
207// Find the "clean" entry point from a "dirty" entry point
208// by skipping past the call to verify_code
209u_int get_clean_addr(int addr)
210{
211 int *ptr=(int *)addr;
212 #ifdef ARMv5_ONLY
213 ptr+=4;
214 #else
215 ptr+=6;
216 #endif
217 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
218 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
219 ptr++;
220 if((*ptr&0xFF000000)==0xea000000) {
221 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
222 }
223 return (u_int)ptr;
224}
225
226int verify_dirty(int addr)
227{
228 u_int *ptr=(u_int *)addr;
229 #ifdef ARMv5_ONLY
230 // get from literal pool
15776b68 231 assert((*ptr&0xFFFF0000)==0xe59f0000);
57871462 232 u_int offset=*ptr&0xfff;
233 u_int *l_ptr=(void *)ptr+offset+8;
234 u_int source=l_ptr[0];
235 u_int copy=l_ptr[1];
236 u_int len=l_ptr[2];
237 ptr+=4;
238 #else
239 // ARMv7 movw/movt
240 assert((*ptr&0xFFF00000)==0xe3000000);
241 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
242 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
243 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
244 ptr+=6;
245 #endif
246 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
247 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
63cb0298 248#ifndef DISABLE_TLB
cfcba99a 249 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
57871462 250 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
251 unsigned int page=source>>12;
252 unsigned int map_value=memory_map[page];
253 if(map_value>=0x80000000) return 0;
254 while(page<((source+len-1)>>12)) {
255 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
256 }
257 source = source+(map_value<<2);
258 }
63cb0298 259#endif
57871462 260 //printf("verify_dirty: %x %x %x\n",source,copy,len);
261 return !memcmp((void *)source,(void *)copy,len);
262}
263
264// This doesn't necessarily find all clean entry points, just
265// guarantees that it's not dirty
266int isclean(int addr)
267{
268 #ifdef ARMv5_ONLY
269 int *ptr=((u_int *)addr)+4;
270 #else
271 int *ptr=((u_int *)addr)+6;
272 #endif
273 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
274 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
275 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
276 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
277 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
278 return 1;
279}
280
281void get_bounds(int addr,u_int *start,u_int *end)
282{
283 u_int *ptr=(u_int *)addr;
284 #ifdef ARMv5_ONLY
285 // get from literal pool
15776b68 286 assert((*ptr&0xFFFF0000)==0xe59f0000);
57871462 287 u_int offset=*ptr&0xfff;
288 u_int *l_ptr=(void *)ptr+offset+8;
289 u_int source=l_ptr[0];
290 //u_int copy=l_ptr[1];
291 u_int len=l_ptr[2];
292 ptr+=4;
293 #else
294 // ARMv7 movw/movt
295 assert((*ptr&0xFFF00000)==0xe3000000);
296 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
297 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
298 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
299 ptr+=6;
300 #endif
301 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
302 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
63cb0298 303#ifndef DISABLE_TLB
cfcba99a 304 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
57871462 305 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
306 if(memory_map[source>>12]>=0x80000000) source = 0;
307 else source = source+(memory_map[source>>12]<<2);
308 }
63cb0298 309#endif
57871462 310 *start=source;
311 *end=source+len;
312}
313
314/* Register allocation */
315
316// Note: registers are allocated clean (unmodified state)
317// if you intend to modify the register, you must call dirty_reg().
318void alloc_reg(struct regstat *cur,int i,signed char reg)
319{
320 int r,hr;
321 int preferred_reg = (reg&7);
322 if(reg==CCREG) preferred_reg=HOST_CCREG;
323 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
324
325 // Don't allocate unused registers
326 if((cur->u>>reg)&1) return;
327
328 // see if it's already allocated
329 for(hr=0;hr<HOST_REGS;hr++)
330 {
331 if(cur->regmap[hr]==reg) return;
332 }
333
334 // Keep the same mapping if the register was already allocated in a loop
335 preferred_reg = loop_reg(i,reg,preferred_reg);
336
337 // Try to allocate the preferred register
338 if(cur->regmap[preferred_reg]==-1) {
339 cur->regmap[preferred_reg]=reg;
340 cur->dirty&=~(1<<preferred_reg);
341 cur->isconst&=~(1<<preferred_reg);
342 return;
343 }
344 r=cur->regmap[preferred_reg];
345 if(r<64&&((cur->u>>r)&1)) {
346 cur->regmap[preferred_reg]=reg;
347 cur->dirty&=~(1<<preferred_reg);
348 cur->isconst&=~(1<<preferred_reg);
349 return;
350 }
351 if(r>=64&&((cur->uu>>(r&63))&1)) {
352 cur->regmap[preferred_reg]=reg;
353 cur->dirty&=~(1<<preferred_reg);
354 cur->isconst&=~(1<<preferred_reg);
355 return;
356 }
357
358 // Clear any unneeded registers
359 // We try to keep the mapping consistent, if possible, because it
360 // makes branches easier (especially loops). So we try to allocate
361 // first (see above) before removing old mappings. If this is not
362 // possible then go ahead and clear out the registers that are no
363 // longer needed.
364 for(hr=0;hr<HOST_REGS;hr++)
365 {
366 r=cur->regmap[hr];
367 if(r>=0) {
368 if(r<64) {
369 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
370 }
371 else
372 {
373 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
374 }
375 }
376 }
377 // Try to allocate any available register, but prefer
378 // registers that have not been used recently.
379 if(i>0) {
380 for(hr=0;hr<HOST_REGS;hr++) {
381 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
382 if(regs[i-1].regmap[hr]!=rs1[i-1]&&regs[i-1].regmap[hr]!=rs2[i-1]&&regs[i-1].regmap[hr]!=rt1[i-1]&&regs[i-1].regmap[hr]!=rt2[i-1]) {
383 cur->regmap[hr]=reg;
384 cur->dirty&=~(1<<hr);
385 cur->isconst&=~(1<<hr);
386 return;
387 }
388 }
389 }
390 }
391 // Try to allocate any available register
392 for(hr=0;hr<HOST_REGS;hr++) {
393 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
394 cur->regmap[hr]=reg;
395 cur->dirty&=~(1<<hr);
396 cur->isconst&=~(1<<hr);
397 return;
398 }
399 }
400
401 // Ok, now we have to evict someone
402 // Pick a register we hopefully won't need soon
403 u_char hsn[MAXREG+1];
404 memset(hsn,10,sizeof(hsn));
405 int j;
406 lsn(hsn,i,&preferred_reg);
407 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
408 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
409 if(i>0) {
410 // Don't evict the cycle count at entry points, otherwise the entry
411 // stub will have to write it.
412 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
413 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
414 for(j=10;j>=3;j--)
415 {
416 // Alloc preferred register if available
417 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
418 for(hr=0;hr<HOST_REGS;hr++) {
419 // Evict both parts of a 64-bit register
420 if((cur->regmap[hr]&63)==r) {
421 cur->regmap[hr]=-1;
422 cur->dirty&=~(1<<hr);
423 cur->isconst&=~(1<<hr);
424 }
425 }
426 cur->regmap[preferred_reg]=reg;
427 return;
428 }
429 for(r=1;r<=MAXREG;r++)
430 {
431 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
432 for(hr=0;hr<HOST_REGS;hr++) {
433 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
434 if(cur->regmap[hr]==r+64) {
435 cur->regmap[hr]=reg;
436 cur->dirty&=~(1<<hr);
437 cur->isconst&=~(1<<hr);
438 return;
439 }
440 }
441 }
442 for(hr=0;hr<HOST_REGS;hr++) {
443 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
444 if(cur->regmap[hr]==r) {
445 cur->regmap[hr]=reg;
446 cur->dirty&=~(1<<hr);
447 cur->isconst&=~(1<<hr);
448 return;
449 }
450 }
451 }
452 }
453 }
454 }
455 }
456 for(j=10;j>=0;j--)
457 {
458 for(r=1;r<=MAXREG;r++)
459 {
460 if(hsn[r]==j) {
461 for(hr=0;hr<HOST_REGS;hr++) {
462 if(cur->regmap[hr]==r+64) {
463 cur->regmap[hr]=reg;
464 cur->dirty&=~(1<<hr);
465 cur->isconst&=~(1<<hr);
466 return;
467 }
468 }
469 for(hr=0;hr<HOST_REGS;hr++) {
470 if(cur->regmap[hr]==r) {
471 cur->regmap[hr]=reg;
472 cur->dirty&=~(1<<hr);
473 cur->isconst&=~(1<<hr);
474 return;
475 }
476 }
477 }
478 }
479 }
480 printf("This shouldn't happen (alloc_reg)");exit(1);
481}
482
483void alloc_reg64(struct regstat *cur,int i,signed char reg)
484{
485 int preferred_reg = 8+(reg&1);
486 int r,hr;
487
488 // allocate the lower 32 bits
489 alloc_reg(cur,i,reg);
490
491 // Don't allocate unused registers
492 if((cur->uu>>reg)&1) return;
493
494 // see if the upper half is already allocated
495 for(hr=0;hr<HOST_REGS;hr++)
496 {
497 if(cur->regmap[hr]==reg+64) return;
498 }
499
500 // Keep the same mapping if the register was already allocated in a loop
501 preferred_reg = loop_reg(i,reg,preferred_reg);
502
503 // Try to allocate the preferred register
504 if(cur->regmap[preferred_reg]==-1) {
505 cur->regmap[preferred_reg]=reg|64;
506 cur->dirty&=~(1<<preferred_reg);
507 cur->isconst&=~(1<<preferred_reg);
508 return;
509 }
510 r=cur->regmap[preferred_reg];
511 if(r<64&&((cur->u>>r)&1)) {
512 cur->regmap[preferred_reg]=reg|64;
513 cur->dirty&=~(1<<preferred_reg);
514 cur->isconst&=~(1<<preferred_reg);
515 return;
516 }
517 if(r>=64&&((cur->uu>>(r&63))&1)) {
518 cur->regmap[preferred_reg]=reg|64;
519 cur->dirty&=~(1<<preferred_reg);
520 cur->isconst&=~(1<<preferred_reg);
521 return;
522 }
523
524 // Clear any unneeded registers
525 // We try to keep the mapping consistent, if possible, because it
526 // makes branches easier (especially loops). So we try to allocate
527 // first (see above) before removing old mappings. If this is not
528 // possible then go ahead and clear out the registers that are no
529 // longer needed.
530 for(hr=HOST_REGS-1;hr>=0;hr--)
531 {
532 r=cur->regmap[hr];
533 if(r>=0) {
534 if(r<64) {
535 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
536 }
537 else
538 {
539 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
540 }
541 }
542 }
543 // Try to allocate any available register, but prefer
544 // registers that have not been used recently.
545 if(i>0) {
546 for(hr=0;hr<HOST_REGS;hr++) {
547 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
548 if(regs[i-1].regmap[hr]!=rs1[i-1]&&regs[i-1].regmap[hr]!=rs2[i-1]&&regs[i-1].regmap[hr]!=rt1[i-1]&&regs[i-1].regmap[hr]!=rt2[i-1]) {
549 cur->regmap[hr]=reg|64;
550 cur->dirty&=~(1<<hr);
551 cur->isconst&=~(1<<hr);
552 return;
553 }
554 }
555 }
556 }
557 // Try to allocate any available register
558 for(hr=0;hr<HOST_REGS;hr++) {
559 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
560 cur->regmap[hr]=reg|64;
561 cur->dirty&=~(1<<hr);
562 cur->isconst&=~(1<<hr);
563 return;
564 }
565 }
566
567 // Ok, now we have to evict someone
568 // Pick a register we hopefully won't need soon
569 u_char hsn[MAXREG+1];
570 memset(hsn,10,sizeof(hsn));
571 int j;
572 lsn(hsn,i,&preferred_reg);
573 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
574 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
575 if(i>0) {
576 // Don't evict the cycle count at entry points, otherwise the entry
577 // stub will have to write it.
578 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
579 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
580 for(j=10;j>=3;j--)
581 {
582 // Alloc preferred register if available
583 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
584 for(hr=0;hr<HOST_REGS;hr++) {
585 // Evict both parts of a 64-bit register
586 if((cur->regmap[hr]&63)==r) {
587 cur->regmap[hr]=-1;
588 cur->dirty&=~(1<<hr);
589 cur->isconst&=~(1<<hr);
590 }
591 }
592 cur->regmap[preferred_reg]=reg|64;
593 return;
594 }
595 for(r=1;r<=MAXREG;r++)
596 {
597 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
598 for(hr=0;hr<HOST_REGS;hr++) {
599 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
600 if(cur->regmap[hr]==r+64) {
601 cur->regmap[hr]=reg|64;
602 cur->dirty&=~(1<<hr);
603 cur->isconst&=~(1<<hr);
604 return;
605 }
606 }
607 }
608 for(hr=0;hr<HOST_REGS;hr++) {
609 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
610 if(cur->regmap[hr]==r) {
611 cur->regmap[hr]=reg|64;
612 cur->dirty&=~(1<<hr);
613 cur->isconst&=~(1<<hr);
614 return;
615 }
616 }
617 }
618 }
619 }
620 }
621 }
622 for(j=10;j>=0;j--)
623 {
624 for(r=1;r<=MAXREG;r++)
625 {
626 if(hsn[r]==j) {
627 for(hr=0;hr<HOST_REGS;hr++) {
628 if(cur->regmap[hr]==r+64) {
629 cur->regmap[hr]=reg|64;
630 cur->dirty&=~(1<<hr);
631 cur->isconst&=~(1<<hr);
632 return;
633 }
634 }
635 for(hr=0;hr<HOST_REGS;hr++) {
636 if(cur->regmap[hr]==r) {
637 cur->regmap[hr]=reg|64;
638 cur->dirty&=~(1<<hr);
639 cur->isconst&=~(1<<hr);
640 return;
641 }
642 }
643 }
644 }
645 }
646 printf("This shouldn't happen");exit(1);
647}
648
649// Allocate a temporary register. This is done without regard to
650// dirty status or whether the register we request is on the unneeded list
651// Note: This will only allocate one register, even if called multiple times
652void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
653{
654 int r,hr;
655 int preferred_reg = -1;
656
657 // see if it's already allocated
658 for(hr=0;hr<HOST_REGS;hr++)
659 {
660 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
661 }
662
663 // Try to allocate any available register
664 for(hr=HOST_REGS-1;hr>=0;hr--) {
665 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
666 cur->regmap[hr]=reg;
667 cur->dirty&=~(1<<hr);
668 cur->isconst&=~(1<<hr);
669 return;
670 }
671 }
672
673 // Find an unneeded register
674 for(hr=HOST_REGS-1;hr>=0;hr--)
675 {
676 r=cur->regmap[hr];
677 if(r>=0) {
678 if(r<64) {
679 if((cur->u>>r)&1) {
680 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
681 cur->regmap[hr]=reg;
682 cur->dirty&=~(1<<hr);
683 cur->isconst&=~(1<<hr);
684 return;
685 }
686 }
687 }
688 else
689 {
690 if((cur->uu>>(r&63))&1) {
691 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
692 cur->regmap[hr]=reg;
693 cur->dirty&=~(1<<hr);
694 cur->isconst&=~(1<<hr);
695 return;
696 }
697 }
698 }
699 }
700 }
701
702 // Ok, now we have to evict someone
703 // Pick a register we hopefully won't need soon
704 // TODO: we might want to follow unconditional jumps here
705 // TODO: get rid of dupe code and make this into a function
706 u_char hsn[MAXREG+1];
707 memset(hsn,10,sizeof(hsn));
708 int j;
709 lsn(hsn,i,&preferred_reg);
710 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
711 if(i>0) {
712 // Don't evict the cycle count at entry points, otherwise the entry
713 // stub will have to write it.
714 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
715 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
716 for(j=10;j>=3;j--)
717 {
718 for(r=1;r<=MAXREG;r++)
719 {
720 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
721 for(hr=0;hr<HOST_REGS;hr++) {
722 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
723 if(cur->regmap[hr]==r+64) {
724 cur->regmap[hr]=reg;
725 cur->dirty&=~(1<<hr);
726 cur->isconst&=~(1<<hr);
727 return;
728 }
729 }
730 }
731 for(hr=0;hr<HOST_REGS;hr++) {
732 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
733 if(cur->regmap[hr]==r) {
734 cur->regmap[hr]=reg;
735 cur->dirty&=~(1<<hr);
736 cur->isconst&=~(1<<hr);
737 return;
738 }
739 }
740 }
741 }
742 }
743 }
744 }
745 for(j=10;j>=0;j--)
746 {
747 for(r=1;r<=MAXREG;r++)
748 {
749 if(hsn[r]==j) {
750 for(hr=0;hr<HOST_REGS;hr++) {
751 if(cur->regmap[hr]==r+64) {
752 cur->regmap[hr]=reg;
753 cur->dirty&=~(1<<hr);
754 cur->isconst&=~(1<<hr);
755 return;
756 }
757 }
758 for(hr=0;hr<HOST_REGS;hr++) {
759 if(cur->regmap[hr]==r) {
760 cur->regmap[hr]=reg;
761 cur->dirty&=~(1<<hr);
762 cur->isconst&=~(1<<hr);
763 return;
764 }
765 }
766 }
767 }
768 }
769 printf("This shouldn't happen");exit(1);
770}
771// Allocate a specific ARM register.
772void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
773{
774 int n;
f776eb14 775 int dirty=0;
57871462 776
777 // see if it's already allocated (and dealloc it)
778 for(n=0;n<HOST_REGS;n++)
779 {
f776eb14 780 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
781 dirty=(cur->dirty>>n)&1;
782 cur->regmap[n]=-1;
783 }
57871462 784 }
785
786 cur->regmap[hr]=reg;
787 cur->dirty&=~(1<<hr);
f776eb14 788 cur->dirty|=dirty<<hr;
57871462 789 cur->isconst&=~(1<<hr);
790}
791
792// Alloc cycle count into dedicated register
793alloc_cc(struct regstat *cur,int i)
794{
795 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
796}
797
798/* Special alloc */
799
800
801/* Assembler */
802
803char regname[16][4] = {
804 "r0",
805 "r1",
806 "r2",
807 "r3",
808 "r4",
809 "r5",
810 "r6",
811 "r7",
812 "r8",
813 "r9",
814 "r10",
815 "fp",
816 "r12",
817 "sp",
818 "lr",
819 "pc"};
820
821void output_byte(u_char byte)
822{
823 *(out++)=byte;
824}
825void output_modrm(u_char mod,u_char rm,u_char ext)
826{
827 assert(mod<4);
828 assert(rm<8);
829 assert(ext<8);
830 u_char byte=(mod<<6)|(ext<<3)|rm;
831 *(out++)=byte;
832}
833void output_sib(u_char scale,u_char index,u_char base)
834{
835 assert(scale<4);
836 assert(index<8);
837 assert(base<8);
838 u_char byte=(scale<<6)|(index<<3)|base;
839 *(out++)=byte;
840}
841void output_w32(u_int word)
842{
843 *((u_int *)out)=word;
844 out+=4;
845}
846u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
847{
848 assert(rd<16);
849 assert(rn<16);
850 assert(rm<16);
851 return((rn<<16)|(rd<<12)|rm);
852}
853u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
854{
855 assert(rd<16);
856 assert(rn<16);
857 assert(imm<256);
858 assert((shift&1)==0);
859 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
860}
861u_int genimm(u_int imm,u_int *encoded)
862{
c2e3bd42 863 *encoded=0;
864 if(imm==0) return 1;
57871462 865 int i=32;
866 while(i>0)
867 {
868 if(imm<256) {
869 *encoded=((i&30)<<7)|imm;
870 return 1;
871 }
872 imm=(imm>>2)|(imm<<30);i-=2;
873 }
874 return 0;
875}
cfbd3c6e 876void genimm_checked(u_int imm,u_int *encoded)
877{
878 u_int ret=genimm(imm,encoded);
879 assert(ret);
880}
57871462 881u_int genjmp(u_int addr)
882{
883 int offset=addr-(int)out-8;
e80343e2 884 if(offset<-33554432||offset>=33554432) {
885 if (addr>2) {
886 printf("genjmp: out of range: %08x\n", offset);
887 exit(1);
888 }
889 return 0;
890 }
57871462 891 return ((u_int)offset>>2)&0xffffff;
892}
893
894void emit_mov(int rs,int rt)
895{
896 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
897 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
898}
899
900void emit_movs(int rs,int rt)
901{
902 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
903 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
904}
905
906void emit_add(int rs1,int rs2,int rt)
907{
908 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
909 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
910}
911
912void emit_adds(int rs1,int rs2,int rt)
913{
914 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
915 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
916}
917
918void emit_adcs(int rs1,int rs2,int rt)
919{
920 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
921 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
922}
923
924void emit_sbc(int rs1,int rs2,int rt)
925{
926 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
927 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
928}
929
930void emit_sbcs(int rs1,int rs2,int rt)
931{
932 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
933 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
934}
935
936void emit_neg(int rs, int rt)
937{
938 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
939 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
940}
941
942void emit_negs(int rs, int rt)
943{
944 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
945 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
946}
947
948void emit_sub(int rs1,int rs2,int rt)
949{
950 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
951 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
952}
953
954void emit_subs(int rs1,int rs2,int rt)
955{
956 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
957 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
958}
959
960void emit_zeroreg(int rt)
961{
962 assem_debug("mov %s,#0\n",regname[rt]);
963 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
964}
965
790ee18e 966void emit_loadlp(u_int imm,u_int rt)
967{
968 add_literal((int)out,imm);
969 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
970 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
971}
972void emit_movw(u_int imm,u_int rt)
973{
974 assert(imm<65536);
975 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
976 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
977}
978void emit_movt(u_int imm,u_int rt)
979{
980 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
981 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
982}
983void emit_movimm(u_int imm,u_int rt)
984{
985 u_int armval;
986 if(genimm(imm,&armval)) {
987 assem_debug("mov %s,#%d\n",regname[rt],imm);
988 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
989 }else if(genimm(~imm,&armval)) {
990 assem_debug("mvn %s,#%d\n",regname[rt],imm);
991 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
992 }else if(imm<65536) {
993 #ifdef ARMv5_ONLY
994 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
995 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
996 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
997 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
998 #else
999 emit_movw(imm,rt);
1000 #endif
1001 }else{
1002 #ifdef ARMv5_ONLY
1003 emit_loadlp(imm,rt);
1004 #else
1005 emit_movw(imm&0x0000FFFF,rt);
1006 emit_movt(imm&0xFFFF0000,rt);
1007 #endif
1008 }
1009}
1010void emit_pcreladdr(u_int rt)
1011{
1012 assem_debug("add %s,pc,#?\n",regname[rt]);
1013 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1014}
1015
57871462 1016void emit_loadreg(int r, int hr)
1017{
3d624f89 1018#ifdef FORCE32
1019 if(r&64) {
1020 printf("64bit load in 32bit mode!\n");
7f2607ea 1021 assert(0);
1022 return;
3d624f89 1023 }
1024#endif
57871462 1025 if((r&63)==0)
1026 emit_zeroreg(hr);
1027 else {
3d624f89 1028 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
57871462 1029 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1030 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1031 if(r==CCREG) addr=(int)&cycle_count;
1032 if(r==CSREG) addr=(int)&Status;
1033 if(r==FSREG) addr=(int)&FCR31;
1034 if(r==INVCP) addr=(int)&invc_ptr;
1035 u_int offset = addr-(u_int)&dynarec_local;
1036 assert(offset<4096);
1037 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1038 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1039 }
1040}
1041void emit_storereg(int r, int hr)
1042{
3d624f89 1043#ifdef FORCE32
1044 if(r&64) {
1045 printf("64bit store in 32bit mode!\n");
7f2607ea 1046 assert(0);
1047 return;
3d624f89 1048 }
1049#endif
1050 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
57871462 1051 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1052 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1053 if(r==CCREG) addr=(int)&cycle_count;
1054 if(r==FSREG) addr=(int)&FCR31;
1055 u_int offset = addr-(u_int)&dynarec_local;
1056 assert(offset<4096);
1057 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1058 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1059}
1060
1061void emit_test(int rs, int rt)
1062{
1063 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1064 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1065}
1066
1067void emit_testimm(int rs,int imm)
1068{
1069 u_int armval;
5a05d80c 1070 assem_debug("tst %s,#%d\n",regname[rs],imm);
cfbd3c6e 1071 genimm_checked(imm,&armval);
57871462 1072 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1073}
1074
b9b61529 1075void emit_testeqimm(int rs,int imm)
1076{
1077 u_int armval;
1078 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
cfbd3c6e 1079 genimm_checked(imm,&armval);
b9b61529 1080 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1081}
1082
57871462 1083void emit_not(int rs,int rt)
1084{
1085 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1086 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1087}
1088
b9b61529 1089void emit_mvnmi(int rs,int rt)
1090{
1091 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1092 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1093}
1094
57871462 1095void emit_and(u_int rs1,u_int rs2,u_int rt)
1096{
1097 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1098 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1099}
1100
1101void emit_or(u_int rs1,u_int rs2,u_int rt)
1102{
1103 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1104 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1105}
1106void emit_or_and_set_flags(int rs1,int rs2,int rt)
1107{
1108 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1109 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1110}
1111
f70d384d 1112void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1113{
1114 assert(rs<16);
1115 assert(rt<16);
1116 assert(imm<32);
1117 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1118 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1119}
1120
576bbd8f 1121void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1122{
1123 assert(rs<16);
1124 assert(rt<16);
1125 assert(imm<32);
1126 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1127 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1128}
1129
57871462 1130void emit_xor(u_int rs1,u_int rs2,u_int rt)
1131{
1132 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1133 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1134}
1135
57871462 1136void emit_addimm(u_int rs,int imm,u_int rt)
1137{
1138 assert(rs<16);
1139 assert(rt<16);
1140 if(imm!=0) {
57871462 1141 u_int armval;
1142 if(genimm(imm,&armval)) {
1143 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1144 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1145 }else if(genimm(-imm,&armval)) {
1146 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],imm);
1147 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1148 }else if(imm<0) {
ffb0b9e0 1149 assert(imm>-65536);
57871462 1150 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1151 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1152 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1153 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1154 }else{
ffb0b9e0 1155 assert(imm<65536);
57871462 1156 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1157 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1158 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1159 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1160 }
1161 }
1162 else if(rs!=rt) emit_mov(rs,rt);
1163}
1164
1165void emit_addimm_and_set_flags(int imm,int rt)
1166{
1167 assert(imm>-65536&&imm<65536);
1168 u_int armval;
1169 if(genimm(imm,&armval)) {
1170 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1171 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1172 }else if(genimm(-imm,&armval)) {
1173 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1174 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1175 }else if(imm<0) {
1176 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1177 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1178 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1179 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1180 }else{
1181 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1182 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1183 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1184 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1185 }
1186}
1187void emit_addimm_no_flags(u_int imm,u_int rt)
1188{
1189 emit_addimm(rt,imm,rt);
1190}
1191
1192void emit_addnop(u_int r)
1193{
1194 assert(r<16);
1195 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1196 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1197}
1198
1199void emit_adcimm(u_int rs,int imm,u_int rt)
1200{
1201 u_int armval;
cfbd3c6e 1202 genimm_checked(imm,&armval);
57871462 1203 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1204 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1205}
1206/*void emit_sbcimm(int imm,u_int rt)
1207{
1208 u_int armval;
cfbd3c6e 1209 genimm_checked(imm,&armval);
57871462 1210 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1211 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1212}*/
1213void emit_sbbimm(int imm,u_int rt)
1214{
1215 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1216 assert(rt<8);
1217 if(imm<128&&imm>=-128) {
1218 output_byte(0x83);
1219 output_modrm(3,rt,3);
1220 output_byte(imm);
1221 }
1222 else
1223 {
1224 output_byte(0x81);
1225 output_modrm(3,rt,3);
1226 output_w32(imm);
1227 }
1228}
1229void emit_rscimm(int rs,int imm,u_int rt)
1230{
1231 assert(0);
1232 u_int armval;
cfbd3c6e 1233 genimm_checked(imm,&armval);
57871462 1234 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1235 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1236}
1237
1238void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1239{
1240 // TODO: if(genimm(imm,&armval)) ...
1241 // else
1242 emit_movimm(imm,HOST_TEMPREG);
1243 emit_adds(HOST_TEMPREG,rsl,rtl);
1244 emit_adcimm(rsh,0,rth);
1245}
1246
1247void emit_sbb(int rs1,int rs2)
1248{
1249 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1250 output_byte(0x19);
1251 output_modrm(3,rs1,rs2);
1252}
1253
1254void emit_andimm(int rs,int imm,int rt)
1255{
1256 u_int armval;
790ee18e 1257 if(imm==0) {
1258 emit_zeroreg(rt);
1259 }else if(genimm(imm,&armval)) {
57871462 1260 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1261 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1262 }else if(genimm(~imm,&armval)) {
1263 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1264 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1265 }else if(imm==65535) {
1266 #ifdef ARMv5_ONLY
1267 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1268 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1269 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1270 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1271 #else
1272 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1273 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1274 #endif
1275 }else{
1276 assert(imm>0&&imm<65535);
1277 #ifdef ARMv5_ONLY
1278 assem_debug("mov r14,#%d\n",imm&0xFF00);
1279 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1280 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1281 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1282 #else
1283 emit_movw(imm,HOST_TEMPREG);
1284 #endif
1285 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1286 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1287 }
1288}
1289
1290void emit_orimm(int rs,int imm,int rt)
1291{
1292 u_int armval;
790ee18e 1293 if(imm==0) {
1294 if(rs!=rt) emit_mov(rs,rt);
1295 }else if(genimm(imm,&armval)) {
57871462 1296 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1297 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1298 }else{
1299 assert(imm>0&&imm<65536);
1300 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1301 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1302 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1303 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1304 }
1305}
1306
1307void emit_xorimm(int rs,int imm,int rt)
1308{
57871462 1309 u_int armval;
790ee18e 1310 if(imm==0) {
1311 if(rs!=rt) emit_mov(rs,rt);
1312 }else if(genimm(imm,&armval)) {
57871462 1313 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1314 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1315 }else{
514ed0d9 1316 assert(imm>0&&imm<65536);
57871462 1317 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1318 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1319 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1320 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1321 }
1322}
1323
1324void emit_shlimm(int rs,u_int imm,int rt)
1325{
1326 assert(imm>0);
1327 assert(imm<32);
1328 //if(imm==1) ...
1329 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1330 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1331}
1332
c6c3b1b3 1333void emit_lsls_imm(int rs,int imm,int rt)
1334{
1335 assert(imm>0);
1336 assert(imm<32);
1337 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1338 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1339}
1340
57871462 1341void emit_shrimm(int rs,u_int imm,int rt)
1342{
1343 assert(imm>0);
1344 assert(imm<32);
1345 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1346 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1347}
1348
1349void emit_sarimm(int rs,u_int imm,int rt)
1350{
1351 assert(imm>0);
1352 assert(imm<32);
1353 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1354 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1355}
1356
1357void emit_rorimm(int rs,u_int imm,int rt)
1358{
1359 assert(imm>0);
1360 assert(imm<32);
1361 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1362 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1363}
1364
1365void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1366{
1367 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1368 assert(imm>0);
1369 assert(imm<32);
1370 //if(imm==1) ...
1371 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1372 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1373 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1374 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1375}
1376
1377void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1378{
1379 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1380 assert(imm>0);
1381 assert(imm<32);
1382 //if(imm==1) ...
1383 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1384 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1385 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1386 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1387}
1388
b9b61529 1389void emit_signextend16(int rs,int rt)
1390{
1391 #ifdef ARMv5_ONLY
1392 emit_shlimm(rs,16,rt);
1393 emit_sarimm(rt,16,rt);
1394 #else
1395 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1396 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1397 #endif
1398}
1399
c6c3b1b3 1400void emit_signextend8(int rs,int rt)
1401{
1402 #ifdef ARMv5_ONLY
1403 emit_shlimm(rs,24,rt);
1404 emit_sarimm(rt,24,rt);
1405 #else
1406 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1407 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1408 #endif
1409}
1410
57871462 1411void emit_shl(u_int rs,u_int shift,u_int rt)
1412{
1413 assert(rs<16);
1414 assert(rt<16);
1415 assert(shift<16);
1416 //if(imm==1) ...
1417 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1418 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1419}
1420void emit_shr(u_int rs,u_int shift,u_int rt)
1421{
1422 assert(rs<16);
1423 assert(rt<16);
1424 assert(shift<16);
1425 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1426 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1427}
1428void emit_sar(u_int rs,u_int shift,u_int rt)
1429{
1430 assert(rs<16);
1431 assert(rt<16);
1432 assert(shift<16);
1433 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1434 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1435}
1436void emit_shlcl(int r)
1437{
1438 assem_debug("shl %%%s,%%cl\n",regname[r]);
1439 assert(0);
1440}
1441void emit_shrcl(int r)
1442{
1443 assem_debug("shr %%%s,%%cl\n",regname[r]);
1444 assert(0);
1445}
1446void emit_sarcl(int r)
1447{
1448 assem_debug("sar %%%s,%%cl\n",regname[r]);
1449 assert(0);
1450}
1451
1452void emit_shldcl(int r1,int r2)
1453{
1454 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1455 assert(0);
1456}
1457void emit_shrdcl(int r1,int r2)
1458{
1459 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1460 assert(0);
1461}
1462void emit_orrshl(u_int rs,u_int shift,u_int rt)
1463{
1464 assert(rs<16);
1465 assert(rt<16);
1466 assert(shift<16);
1467 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1468 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1469}
1470void emit_orrshr(u_int rs,u_int shift,u_int rt)
1471{
1472 assert(rs<16);
1473 assert(rt<16);
1474 assert(shift<16);
1475 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1476 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1477}
1478
1479void emit_cmpimm(int rs,int imm)
1480{
1481 u_int armval;
1482 if(genimm(imm,&armval)) {
5a05d80c 1483 assem_debug("cmp %s,#%d\n",regname[rs],imm);
57871462 1484 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1485 }else if(genimm(-imm,&armval)) {
5a05d80c 1486 assem_debug("cmn %s,#%d\n",regname[rs],imm);
57871462 1487 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1488 }else if(imm>0) {
1489 assert(imm<65536);
1490 #ifdef ARMv5_ONLY
1491 emit_movimm(imm,HOST_TEMPREG);
1492 #else
1493 emit_movw(imm,HOST_TEMPREG);
1494 #endif
1495 assem_debug("cmp %s,r14\n",regname[rs]);
1496 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1497 }else{
1498 assert(imm>-65536);
1499 #ifdef ARMv5_ONLY
1500 emit_movimm(-imm,HOST_TEMPREG);
1501 #else
1502 emit_movw(-imm,HOST_TEMPREG);
1503 #endif
1504 assem_debug("cmn %s,r14\n",regname[rs]);
1505 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1506 }
1507}
1508
1509void emit_cmovne(u_int *addr,int rt)
1510{
1511 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1512 assert(0);
1513}
1514void emit_cmovl(u_int *addr,int rt)
1515{
1516 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1517 assert(0);
1518}
1519void emit_cmovs(u_int *addr,int rt)
1520{
1521 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1522 assert(0);
1523}
1524void emit_cmovne_imm(int imm,int rt)
1525{
1526 assem_debug("movne %s,#%d\n",regname[rt],imm);
1527 u_int armval;
cfbd3c6e 1528 genimm_checked(imm,&armval);
57871462 1529 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1530}
1531void emit_cmovl_imm(int imm,int rt)
1532{
1533 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1534 u_int armval;
cfbd3c6e 1535 genimm_checked(imm,&armval);
57871462 1536 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1537}
1538void emit_cmovb_imm(int imm,int rt)
1539{
1540 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1541 u_int armval;
cfbd3c6e 1542 genimm_checked(imm,&armval);
57871462 1543 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1544}
1545void emit_cmovs_imm(int imm,int rt)
1546{
1547 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1548 u_int armval;
cfbd3c6e 1549 genimm_checked(imm,&armval);
57871462 1550 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1551}
1552void emit_cmove_reg(int rs,int rt)
1553{
1554 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1555 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1556}
1557void emit_cmovne_reg(int rs,int rt)
1558{
1559 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1560 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1561}
1562void emit_cmovl_reg(int rs,int rt)
1563{
1564 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1565 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1566}
1567void emit_cmovs_reg(int rs,int rt)
1568{
1569 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1570 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1571}
1572
1573void emit_slti32(int rs,int imm,int rt)
1574{
1575 if(rs!=rt) emit_zeroreg(rt);
1576 emit_cmpimm(rs,imm);
1577 if(rs==rt) emit_movimm(0,rt);
1578 emit_cmovl_imm(1,rt);
1579}
1580void emit_sltiu32(int rs,int imm,int rt)
1581{
1582 if(rs!=rt) emit_zeroreg(rt);
1583 emit_cmpimm(rs,imm);
1584 if(rs==rt) emit_movimm(0,rt);
1585 emit_cmovb_imm(1,rt);
1586}
1587void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1588{
1589 assert(rsh!=rt);
1590 emit_slti32(rsl,imm,rt);
1591 if(imm>=0)
1592 {
1593 emit_test(rsh,rsh);
1594 emit_cmovne_imm(0,rt);
1595 emit_cmovs_imm(1,rt);
1596 }
1597 else
1598 {
1599 emit_cmpimm(rsh,-1);
1600 emit_cmovne_imm(0,rt);
1601 emit_cmovl_imm(1,rt);
1602 }
1603}
1604void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1605{
1606 assert(rsh!=rt);
1607 emit_sltiu32(rsl,imm,rt);
1608 if(imm>=0)
1609 {
1610 emit_test(rsh,rsh);
1611 emit_cmovne_imm(0,rt);
1612 }
1613 else
1614 {
1615 emit_cmpimm(rsh,-1);
1616 emit_cmovne_imm(1,rt);
1617 }
1618}
1619
1620void emit_cmp(int rs,int rt)
1621{
1622 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1623 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1624}
1625void emit_set_gz32(int rs, int rt)
1626{
1627 //assem_debug("set_gz32\n");
1628 emit_cmpimm(rs,1);
1629 emit_movimm(1,rt);
1630 emit_cmovl_imm(0,rt);
1631}
1632void emit_set_nz32(int rs, int rt)
1633{
1634 //assem_debug("set_nz32\n");
1635 if(rs!=rt) emit_movs(rs,rt);
1636 else emit_test(rs,rs);
1637 emit_cmovne_imm(1,rt);
1638}
1639void emit_set_gz64_32(int rsh, int rsl, int rt)
1640{
1641 //assem_debug("set_gz64\n");
1642 emit_set_gz32(rsl,rt);
1643 emit_test(rsh,rsh);
1644 emit_cmovne_imm(1,rt);
1645 emit_cmovs_imm(0,rt);
1646}
1647void emit_set_nz64_32(int rsh, int rsl, int rt)
1648{
1649 //assem_debug("set_nz64\n");
1650 emit_or_and_set_flags(rsh,rsl,rt);
1651 emit_cmovne_imm(1,rt);
1652}
1653void emit_set_if_less32(int rs1, int rs2, int rt)
1654{
1655 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1656 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1657 emit_cmp(rs1,rs2);
1658 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1659 emit_cmovl_imm(1,rt);
1660}
1661void emit_set_if_carry32(int rs1, int rs2, int rt)
1662{
1663 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1664 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1665 emit_cmp(rs1,rs2);
1666 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1667 emit_cmovb_imm(1,rt);
1668}
1669void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1670{
1671 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1672 assert(u1!=rt);
1673 assert(u2!=rt);
1674 emit_cmp(l1,l2);
1675 emit_movimm(0,rt);
1676 emit_sbcs(u1,u2,HOST_TEMPREG);
1677 emit_cmovl_imm(1,rt);
1678}
1679void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1680{
1681 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1682 assert(u1!=rt);
1683 assert(u2!=rt);
1684 emit_cmp(l1,l2);
1685 emit_movimm(0,rt);
1686 emit_sbcs(u1,u2,HOST_TEMPREG);
1687 emit_cmovb_imm(1,rt);
1688}
1689
1690void emit_call(int a)
1691{
1692 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1693 u_int offset=genjmp(a);
1694 output_w32(0xeb000000|offset);
1695}
1696void emit_jmp(int a)
1697{
1698 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1699 u_int offset=genjmp(a);
1700 output_w32(0xea000000|offset);
1701}
1702void emit_jne(int a)
1703{
1704 assem_debug("bne %x\n",a);
1705 u_int offset=genjmp(a);
1706 output_w32(0x1a000000|offset);
1707}
1708void emit_jeq(int a)
1709{
1710 assem_debug("beq %x\n",a);
1711 u_int offset=genjmp(a);
1712 output_w32(0x0a000000|offset);
1713}
1714void emit_js(int a)
1715{
1716 assem_debug("bmi %x\n",a);
1717 u_int offset=genjmp(a);
1718 output_w32(0x4a000000|offset);
1719}
1720void emit_jns(int a)
1721{
1722 assem_debug("bpl %x\n",a);
1723 u_int offset=genjmp(a);
1724 output_w32(0x5a000000|offset);
1725}
1726void emit_jl(int a)
1727{
1728 assem_debug("blt %x\n",a);
1729 u_int offset=genjmp(a);
1730 output_w32(0xba000000|offset);
1731}
1732void emit_jge(int a)
1733{
1734 assem_debug("bge %x\n",a);
1735 u_int offset=genjmp(a);
1736 output_w32(0xaa000000|offset);
1737}
1738void emit_jno(int a)
1739{
1740 assem_debug("bvc %x\n",a);
1741 u_int offset=genjmp(a);
1742 output_w32(0x7a000000|offset);
1743}
1744void emit_jc(int a)
1745{
1746 assem_debug("bcs %x\n",a);
1747 u_int offset=genjmp(a);
1748 output_w32(0x2a000000|offset);
1749}
1750void emit_jcc(int a)
1751{
1752 assem_debug("bcc %x\n",a);
1753 u_int offset=genjmp(a);
1754 output_w32(0x3a000000|offset);
1755}
1756
1757void emit_pushimm(int imm)
1758{
1759 assem_debug("push $%x\n",imm);
1760 assert(0);
1761}
1762void emit_pusha()
1763{
1764 assem_debug("pusha\n");
1765 assert(0);
1766}
1767void emit_popa()
1768{
1769 assem_debug("popa\n");
1770 assert(0);
1771}
1772void emit_pushreg(u_int r)
1773{
1774 assem_debug("push %%%s\n",regname[r]);
1775 assert(0);
1776}
1777void emit_popreg(u_int r)
1778{
1779 assem_debug("pop %%%s\n",regname[r]);
1780 assert(0);
1781}
1782void emit_callreg(u_int r)
1783{
c6c3b1b3 1784 assert(r<15);
1785 assem_debug("blx %s\n",regname[r]);
1786 output_w32(0xe12fff30|r);
57871462 1787}
1788void emit_jmpreg(u_int r)
1789{
1790 assem_debug("mov pc,%s\n",regname[r]);
1791 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1792}
1793
1794void emit_readword_indexed(int offset, int rs, int rt)
1795{
1796 assert(offset>-4096&&offset<4096);
1797 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1798 if(offset>=0) {
1799 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1800 }else{
1801 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1802 }
1803}
1804void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1805{
1806 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1807 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1808}
c6c3b1b3 1809void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1810{
1811 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1812 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1813}
1814void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1815{
1816 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1817 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1818}
1819void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1820{
1821 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1822 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1823}
1824void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1825{
1826 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1827 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1828}
1829void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1830{
1831 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1832 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1833}
57871462 1834void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1835{
1836 if(map<0) emit_readword_indexed(addr, rs, rt);
1837 else {
1838 assert(addr==0);
1839 emit_readword_dualindexedx4(rs, map, rt);
1840 }
1841}
1842void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1843{
1844 if(map<0) {
1845 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1846 emit_readword_indexed(addr+4, rs, rl);
1847 }else{
1848 assert(rh!=rs);
1849 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1850 emit_addimm(map,1,map);
1851 emit_readword_indexed_tlb(addr, rs, map, rl);
1852 }
1853}
1854void emit_movsbl_indexed(int offset, int rs, int rt)
1855{
1856 assert(offset>-256&&offset<256);
1857 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1858 if(offset>=0) {
1859 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1860 }else{
1861 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1862 }
1863}
1864void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1865{
1866 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1867 else {
1868 if(addr==0) {
1869 emit_shlimm(map,2,map);
1870 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1871 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1872 }else{
1873 assert(addr>-256&&addr<256);
1874 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1875 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1876 emit_movsbl_indexed(addr, rt, rt);
1877 }
1878 }
1879}
1880void emit_movswl_indexed(int offset, int rs, int rt)
1881{
1882 assert(offset>-256&&offset<256);
1883 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1884 if(offset>=0) {
1885 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1886 }else{
1887 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1888 }
1889}
1890void emit_movzbl_indexed(int offset, int rs, int rt)
1891{
1892 assert(offset>-4096&&offset<4096);
1893 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1894 if(offset>=0) {
1895 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1896 }else{
1897 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1898 }
1899}
1900void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1901{
1902 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1903 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1904}
1905void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1906{
1907 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1908 else {
1909 if(addr==0) {
1910 emit_movzbl_dualindexedx4(rs, map, rt);
1911 }else{
1912 emit_addimm(rs,addr,rt);
1913 emit_movzbl_dualindexedx4(rt, map, rt);
1914 }
1915 }
1916}
1917void emit_movzwl_indexed(int offset, int rs, int rt)
1918{
1919 assert(offset>-256&&offset<256);
1920 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1921 if(offset>=0) {
1922 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1923 }else{
1924 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1925 }
1926}
1927void emit_readword(int addr, int rt)
1928{
1929 u_int offset = addr-(u_int)&dynarec_local;
1930 assert(offset<4096);
1931 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1932 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1933}
1934void emit_movsbl(int addr, int rt)
1935{
1936 u_int offset = addr-(u_int)&dynarec_local;
1937 assert(offset<256);
1938 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1939 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1940}
1941void emit_movswl(int addr, int rt)
1942{
1943 u_int offset = addr-(u_int)&dynarec_local;
1944 assert(offset<256);
1945 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1946 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1947}
1948void emit_movzbl(int addr, int rt)
1949{
1950 u_int offset = addr-(u_int)&dynarec_local;
1951 assert(offset<4096);
1952 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1953 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1954}
1955void emit_movzwl(int addr, int rt)
1956{
1957 u_int offset = addr-(u_int)&dynarec_local;
1958 assert(offset<256);
1959 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1960 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1961}
1962void emit_movzwl_reg(int rs, int rt)
1963{
1964 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1965 assert(0);
1966}
1967
1968void emit_xchg(int rs, int rt)
1969{
1970 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1971 assert(0);
1972}
1973void emit_writeword_indexed(int rt, int offset, int rs)
1974{
1975 assert(offset>-4096&&offset<4096);
1976 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1977 if(offset>=0) {
1978 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1979 }else{
1980 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1981 }
1982}
1983void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1984{
1985 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1986 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1987}
1988void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1989{
1990 if(map<0) emit_writeword_indexed(rt, addr, rs);
1991 else {
1992 assert(addr==0);
1993 emit_writeword_dualindexedx4(rt, rs, map);
1994 }
1995}
1996void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1997{
1998 if(map<0) {
1999 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2000 emit_writeword_indexed(rl, addr+4, rs);
2001 }else{
2002 assert(rh>=0);
2003 if(temp!=rs) emit_addimm(map,1,temp);
2004 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2005 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2006 else {
2007 emit_addimm(rs,4,rs);
2008 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2009 }
2010 }
2011}
2012void emit_writehword_indexed(int rt, int offset, int rs)
2013{
2014 assert(offset>-256&&offset<256);
2015 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2016 if(offset>=0) {
2017 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2018 }else{
2019 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2020 }
2021}
2022void emit_writebyte_indexed(int rt, int offset, int rs)
2023{
2024 assert(offset>-4096&&offset<4096);
2025 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2026 if(offset>=0) {
2027 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2028 }else{
2029 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2030 }
2031}
2032void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2033{
2034 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2035 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2036}
2037void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2038{
2039 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2040 else {
2041 if(addr==0) {
2042 emit_writebyte_dualindexedx4(rt, rs, map);
2043 }else{
2044 emit_addimm(rs,addr,temp);
2045 emit_writebyte_dualindexedx4(rt, temp, map);
2046 }
2047 }
2048}
b96d3df7 2049void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2050{
2051 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2052 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2053}
2054void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2055{
2056 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2057 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2058}
2059void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2060{
2061 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2062 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2063}
57871462 2064void emit_writeword(int rt, int addr)
2065{
2066 u_int offset = addr-(u_int)&dynarec_local;
2067 assert(offset<4096);
2068 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2069 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2070}
2071void emit_writehword(int rt, int addr)
2072{
2073 u_int offset = addr-(u_int)&dynarec_local;
2074 assert(offset<256);
2075 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2076 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2077}
2078void emit_writebyte(int rt, int addr)
2079{
2080 u_int offset = addr-(u_int)&dynarec_local;
2081 assert(offset<4096);
74426039 2082 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
57871462 2083 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2084}
2085void emit_writeword_imm(int imm, int addr)
2086{
2087 assem_debug("movl $%x,%x\n",imm,addr);
2088 assert(0);
2089}
2090void emit_writebyte_imm(int imm, int addr)
2091{
2092 assem_debug("movb $%x,%x\n",imm,addr);
2093 assert(0);
2094}
2095
2096void emit_mul(int rs)
2097{
2098 assem_debug("mul %%%s\n",regname[rs]);
2099 assert(0);
2100}
2101void emit_imul(int rs)
2102{
2103 assem_debug("imul %%%s\n",regname[rs]);
2104 assert(0);
2105}
2106void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2107{
2108 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2109 assert(rs1<16);
2110 assert(rs2<16);
2111 assert(hi<16);
2112 assert(lo<16);
2113 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2114}
2115void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2116{
2117 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2118 assert(rs1<16);
2119 assert(rs2<16);
2120 assert(hi<16);
2121 assert(lo<16);
2122 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2123}
2124
2125void emit_div(int rs)
2126{
2127 assem_debug("div %%%s\n",regname[rs]);
2128 assert(0);
2129}
2130void emit_idiv(int rs)
2131{
2132 assem_debug("idiv %%%s\n",regname[rs]);
2133 assert(0);
2134}
2135void emit_cdq()
2136{
2137 assem_debug("cdq\n");
2138 assert(0);
2139}
2140
2141void emit_clz(int rs,int rt)
2142{
2143 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2144 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2145}
2146
2147void emit_subcs(int rs1,int rs2,int rt)
2148{
2149 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2150 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2151}
2152
2153void emit_shrcc_imm(int rs,u_int imm,int rt)
2154{
2155 assert(imm>0);
2156 assert(imm<32);
2157 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2158 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2159}
2160
2161void emit_negmi(int rs, int rt)
2162{
2163 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2164 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2165}
2166
2167void emit_negsmi(int rs, int rt)
2168{
2169 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2170 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2171}
2172
2173void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2174{
2175 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2176 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2177}
2178
2179void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2180{
2181 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2182 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2183}
2184
2185void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2186{
2187 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2188 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2189}
2190
2191void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2192{
2193 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2194 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2195}
2196
2197void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2198{
2199 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2200 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2201}
2202
2203void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2204{
2205 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2206 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2207}
2208
2209void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2210{
2211 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2212 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2213}
2214
2215void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2216{
2217 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2218 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2219}
2220
2221void emit_teq(int rs, int rt)
2222{
2223 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2224 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2225}
2226
2227void emit_rsbimm(int rs, int imm, int rt)
2228{
2229 u_int armval;
cfbd3c6e 2230 genimm_checked(imm,&armval);
57871462 2231 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2232 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2233}
2234
2235// Load 2 immediates optimizing for small code size
2236void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2237{
2238 emit_movimm(imm1,rt1);
2239 u_int armval;
2240 if(genimm(imm2-imm1,&armval)) {
2241 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2242 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2243 }else if(genimm(imm1-imm2,&armval)) {
2244 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2245 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2246 }
2247 else emit_movimm(imm2,rt2);
2248}
2249
2250// Conditionally select one of two immediates, optimizing for small code size
2251// This will only be called if HAVE_CMOV_IMM is defined
2252void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2253{
2254 u_int armval;
2255 if(genimm(imm2-imm1,&armval)) {
2256 emit_movimm(imm1,rt);
2257 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2258 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2259 }else if(genimm(imm1-imm2,&armval)) {
2260 emit_movimm(imm1,rt);
2261 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2262 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2263 }
2264 else {
2265 #ifdef ARMv5_ONLY
2266 emit_movimm(imm1,rt);
2267 add_literal((int)out,imm2);
2268 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2269 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2270 #else
2271 emit_movw(imm1&0x0000FFFF,rt);
2272 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2273 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2274 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2275 }
2276 emit_movt(imm1&0xFFFF0000,rt);
2277 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2278 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2279 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2280 }
2281 #endif
2282 }
2283}
2284
2285// special case for checking invalid_code
2286void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2287{
2288 assert(0);
2289}
2290
2291// special case for checking invalid_code
2292void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2293{
2294 assert(imm<128&&imm>=0);
2295 assert(r>=0&&r<16);
2296 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2297 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2298 emit_cmpimm(HOST_TEMPREG,imm);
2299}
2300
2301// special case for tlb mapping
2302void emit_addsr12(int rs1,int rs2,int rt)
2303{
2304 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2305 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2306}
2307
0bbd1454 2308void emit_callne(int a)
2309{
2310 assem_debug("blne %x\n",a);
2311 u_int offset=genjmp(a);
2312 output_w32(0x1b000000|offset);
2313}
2314
57871462 2315// Used to preload hash table entries
2316void emit_prefetch(void *addr)
2317{
2318 assem_debug("prefetch %x\n",(int)addr);
2319 output_byte(0x0F);
2320 output_byte(0x18);
2321 output_modrm(0,5,1);
2322 output_w32((int)addr);
2323}
2324void emit_prefetchreg(int r)
2325{
2326 assem_debug("pld %s\n",regname[r]);
2327 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2328}
2329
2330// Special case for mini_ht
2331void emit_ldreq_indexed(int rs, u_int offset, int rt)
2332{
2333 assert(offset<4096);
2334 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2335 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2336}
2337
2338void emit_flds(int r,int sr)
2339{
2340 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2341 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2342}
2343
2344void emit_vldr(int r,int vr)
2345{
2346 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2347 output_w32(0xed900b00|(vr<<12)|(r<<16));
2348}
2349
2350void emit_fsts(int sr,int r)
2351{
2352 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2353 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2354}
2355
2356void emit_vstr(int vr,int r)
2357{
2358 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2359 output_w32(0xed800b00|(vr<<12)|(r<<16));
2360}
2361
2362void emit_ftosizs(int s,int d)
2363{
2364 assem_debug("ftosizs s%d,s%d\n",d,s);
2365 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2366}
2367
2368void emit_ftosizd(int s,int d)
2369{
2370 assem_debug("ftosizd s%d,d%d\n",d,s);
2371 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2372}
2373
2374void emit_fsitos(int s,int d)
2375{
2376 assem_debug("fsitos s%d,s%d\n",d,s);
2377 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2378}
2379
2380void emit_fsitod(int s,int d)
2381{
2382 assem_debug("fsitod d%d,s%d\n",d,s);
2383 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2384}
2385
2386void emit_fcvtds(int s,int d)
2387{
2388 assem_debug("fcvtds d%d,s%d\n",d,s);
2389 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2390}
2391
2392void emit_fcvtsd(int s,int d)
2393{
2394 assem_debug("fcvtsd s%d,d%d\n",d,s);
2395 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2396}
2397
2398void emit_fsqrts(int s,int d)
2399{
2400 assem_debug("fsqrts d%d,s%d\n",d,s);
2401 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2402}
2403
2404void emit_fsqrtd(int s,int d)
2405{
2406 assem_debug("fsqrtd s%d,d%d\n",d,s);
2407 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2408}
2409
2410void emit_fabss(int s,int d)
2411{
2412 assem_debug("fabss d%d,s%d\n",d,s);
2413 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2414}
2415
2416void emit_fabsd(int s,int d)
2417{
2418 assem_debug("fabsd s%d,d%d\n",d,s);
2419 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2420}
2421
2422void emit_fnegs(int s,int d)
2423{
2424 assem_debug("fnegs d%d,s%d\n",d,s);
2425 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2426}
2427
2428void emit_fnegd(int s,int d)
2429{
2430 assem_debug("fnegd s%d,d%d\n",d,s);
2431 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2432}
2433
2434void emit_fadds(int s1,int s2,int d)
2435{
2436 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2437 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2438}
2439
2440void emit_faddd(int s1,int s2,int d)
2441{
2442 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2443 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2444}
2445
2446void emit_fsubs(int s1,int s2,int d)
2447{
2448 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2449 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2450}
2451
2452void emit_fsubd(int s1,int s2,int d)
2453{
2454 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2455 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2456}
2457
2458void emit_fmuls(int s1,int s2,int d)
2459{
2460 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2461 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2462}
2463
2464void emit_fmuld(int s1,int s2,int d)
2465{
2466 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2467 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2468}
2469
2470void emit_fdivs(int s1,int s2,int d)
2471{
2472 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2473 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2474}
2475
2476void emit_fdivd(int s1,int s2,int d)
2477{
2478 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2479 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2480}
2481
2482void emit_fcmps(int x,int y)
2483{
2484 assem_debug("fcmps s14, s15\n");
2485 output_w32(0xeeb47a67);
2486}
2487
2488void emit_fcmpd(int x,int y)
2489{
2490 assem_debug("fcmpd d6, d7\n");
2491 output_w32(0xeeb46b47);
2492}
2493
2494void emit_fmstat()
2495{
2496 assem_debug("fmstat\n");
2497 output_w32(0xeef1fa10);
2498}
2499
2500void emit_bicne_imm(int rs,int imm,int rt)
2501{
2502 u_int armval;
cfbd3c6e 2503 genimm_checked(imm,&armval);
57871462 2504 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2505 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2506}
2507
2508void emit_biccs_imm(int rs,int imm,int rt)
2509{
2510 u_int armval;
cfbd3c6e 2511 genimm_checked(imm,&armval);
57871462 2512 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2513 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2514}
2515
2516void emit_bicvc_imm(int rs,int imm,int rt)
2517{
2518 u_int armval;
cfbd3c6e 2519 genimm_checked(imm,&armval);
57871462 2520 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2521 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2522}
2523
2524void emit_bichi_imm(int rs,int imm,int rt)
2525{
2526 u_int armval;
cfbd3c6e 2527 genimm_checked(imm,&armval);
57871462 2528 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2529 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2530}
2531
2532void emit_orrvs_imm(int rs,int imm,int rt)
2533{
2534 u_int armval;
cfbd3c6e 2535 genimm_checked(imm,&armval);
57871462 2536 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2537 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2538}
2539
b9b61529 2540void emit_orrne_imm(int rs,int imm,int rt)
2541{
2542 u_int armval;
cfbd3c6e 2543 genimm_checked(imm,&armval);
b9b61529 2544 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2545 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2546}
2547
2548void emit_andne_imm(int rs,int imm,int rt)
2549{
2550 u_int armval;
cfbd3c6e 2551 genimm_checked(imm,&armval);
b9b61529 2552 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2553 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2554}
2555
57871462 2556void emit_jno_unlikely(int a)
2557{
2558 //emit_jno(a);
2559 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2560 output_w32(0x72800000|rd_rn_rm(15,15,0));
2561}
2562
2563// Save registers before function call
2564void save_regs(u_int reglist)
2565{
2566 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2567 if(!reglist) return;
2568 assem_debug("stmia fp,{");
2569 if(reglist&1) assem_debug("r0, ");
2570 if(reglist&2) assem_debug("r1, ");
2571 if(reglist&4) assem_debug("r2, ");
2572 if(reglist&8) assem_debug("r3, ");
2573 if(reglist&0x1000) assem_debug("r12");
2574 assem_debug("}\n");
2575 output_w32(0xe88b0000|reglist);
2576}
2577// Restore registers after function call
2578void restore_regs(u_int reglist)
2579{
2580 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2581 if(!reglist) return;
2582 assem_debug("ldmia fp,{");
2583 if(reglist&1) assem_debug("r0, ");
2584 if(reglist&2) assem_debug("r1, ");
2585 if(reglist&4) assem_debug("r2, ");
2586 if(reglist&8) assem_debug("r3, ");
2587 if(reglist&0x1000) assem_debug("r12");
2588 assem_debug("}\n");
2589 output_w32(0xe89b0000|reglist);
2590}
2591
2592// Write back consts using r14 so we don't disturb the other registers
2593void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2594{
2595 int hr;
2596 for(hr=0;hr<HOST_REGS;hr++) {
2597 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2598 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2599 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2600 int value=constmap[i][hr];
2601 if(value==0) {
2602 emit_zeroreg(HOST_TEMPREG);
2603 }
2604 else {
2605 emit_movimm(value,HOST_TEMPREG);
2606 }
2607 emit_storereg(i_regmap[hr],HOST_TEMPREG);
24385cae 2608#ifndef FORCE32
57871462 2609 if((i_is32>>i_regmap[hr])&1) {
2610 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2611 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2612 }
24385cae 2613#endif
57871462 2614 }
2615 }
2616 }
2617 }
2618}
2619
2620/* Stubs/epilogue */
2621
2622void literal_pool(int n)
2623{
2624 if(!literalcount) return;
2625 if(n) {
2626 if((int)out-literals[0][0]<4096-n) return;
2627 }
2628 u_int *ptr;
2629 int i;
2630 for(i=0;i<literalcount;i++)
2631 {
2632 ptr=(u_int *)literals[i][0];
2633 u_int offset=(u_int)out-(u_int)ptr-8;
2634 assert(offset<4096);
2635 assert(!(offset&3));
2636 *ptr|=offset;
2637 output_w32(literals[i][1]);
2638 }
2639 literalcount=0;
2640}
2641
2642void literal_pool_jumpover(int n)
2643{
2644 if(!literalcount) return;
2645 if(n) {
2646 if((int)out-literals[0][0]<4096-n) return;
2647 }
2648 int jaddr=(int)out;
2649 emit_jmp(0);
2650 literal_pool(0);
2651 set_jump_target(jaddr,(int)out);
2652}
2653
2654emit_extjump2(int addr, int target, int linker)
2655{
2656 u_char *ptr=(u_char *)addr;
2657 assert((ptr[3]&0x0e)==0xa);
2658 emit_loadlp(target,0);
2659 emit_loadlp(addr,1);
24385cae 2660 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
57871462 2661 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2662//DEBUG >
2663#ifdef DEBUG_CYCLE_COUNT
2664 emit_readword((int)&last_count,ECX);
2665 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2666 emit_readword((int)&next_interupt,ECX);
2667 emit_writeword(HOST_CCREG,(int)&Count);
2668 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2669 emit_writeword(ECX,(int)&last_count);
2670#endif
2671//DEBUG <
2672 emit_jmp(linker);
2673}
2674
2675emit_extjump(int addr, int target)
2676{
2677 emit_extjump2(addr, target, (int)dyna_linker);
2678}
2679emit_extjump_ds(int addr, int target)
2680{
2681 emit_extjump2(addr, target, (int)dyna_linker_ds);
2682}
2683
13e35c04 2684// put rt_val into rt, potentially making use of rs with value rs_val
2685static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2686{
2687 u_int xor=rs_val^rt_val;
2688 u_int xs;
2689 for(xs=xor;xs!=0&&(xs&3)==0;xs>>=2)
2690 ;
2691 if(xs<0x100)
2692 emit_xorimm(rs,xor,rt);
2693 else
2694 emit_movimm(rt_val,rt);
2695}
cbbab9cd 2696
b96d3df7 2697// trashes r2
2698static void pass_args(int a0, int a1)
2699{
2700 if(a0==1&&a1==0) {
2701 // must swap
2702 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2703 }
2704 else if(a0!=0&&a1==0) {
2705 emit_mov(a1,1);
2706 if (a0>=0) emit_mov(a0,0);
2707 }
2708 else {
2709 if(a0>=0&&a0!=0) emit_mov(a0,0);
2710 if(a1>=0&&a1!=1) emit_mov(a1,1);
2711 }
2712}
2713
57871462 2714do_readstub(int n)
2715{
2716 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2717 literal_pool(256);
2718 set_jump_target(stubs[n][1],(int)out);
2719 int type=stubs[n][0];
2720 int i=stubs[n][3];
2721 int rs=stubs[n][4];
2722 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2723 u_int reglist=stubs[n][7];
2724 signed char *i_regmap=i_regs->regmap;
2725 int addr=get_reg(i_regmap,AGEN1+(i&1));
2726 int rth,rt;
2727 int ds;
b9b61529 2728 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
57871462 2729 rth=get_reg(i_regmap,FTEMP|64);
2730 rt=get_reg(i_regmap,FTEMP);
2731 }else{
2732 rth=get_reg(i_regmap,rt1[i]|64);
2733 rt=get_reg(i_regmap,rt1[i]);
2734 }
2735 assert(rs>=0);
c6c3b1b3 2736#ifdef PCSX
2737 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2738 reglist|=(1<<rs);
2739 for(r=0;r<=12;r++) {
2740 if(((1<<r)&0x13ff)&&((1<<r)&reglist)==0) {
2741 temp=r; break;
2742 }
2743 }
2744 if(rt>=0)
2745 reglist&=~(1<<rt);
2746 if(temp==-1) {
2747 save_regs(reglist);
2748 regs_saved=1;
2749 temp=(rs==0)?2:0;
2750 }
2751 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2752 temp2=1;
2753 emit_readword((int)&mem_rtab,temp);
2754 emit_shrimm(rs,12,temp2);
2755 emit_readword_dualindexedx4(temp,temp2,temp2);
2756 emit_lsls_imm(temp2,1,temp2);
2757 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2758 switch(type) {
2759 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2760 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2761 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2762 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2763 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2764 }
2765 }
2766 if(regs_saved) {
2767 restore_jump=(int)out;
2768 emit_jcc(0); // jump to reg restore
2769 }
2770 else
2771 emit_jcc(stubs[n][2]); // return address
2772
2773 if(!regs_saved)
2774 save_regs(reglist);
2775 int handler=0;
2776 if(type==LOADB_STUB||type==LOADBU_STUB)
2777 handler=(int)jump_handler_read8;
2778 if(type==LOADH_STUB||type==LOADHU_STUB)
2779 handler=(int)jump_handler_read16;
2780 if(type==LOADW_STUB)
2781 handler=(int)jump_handler_read32;
2782 assert(handler!=0);
b96d3df7 2783 pass_args(rs,temp2);
c6c3b1b3 2784 int cc=get_reg(i_regmap,CCREG);
2785 if(cc<0)
2786 emit_loadreg(CCREG,2);
2573466a 2787 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
c6c3b1b3 2788 emit_call(handler);
2789 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2790 switch(type) {
2791 case LOADB_STUB: emit_signextend8(0,rt); break;
2792 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2793 case LOADH_STUB: emit_signextend16(0,rt); break;
2794 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2795 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2796 }
2797 }
2798 if(restore_jump)
2799 set_jump_target(restore_jump,(int)out);
2800 restore_regs(reglist);
2801 emit_jmp(stubs[n][2]); // return address
2802#else // !PCSX
57871462 2803 if(addr<0) addr=rt;
535d208a 2804 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
57871462 2805 assert(addr>=0);
2806 int ftable=0;
2807 if(type==LOADB_STUB||type==LOADBU_STUB)
2808 ftable=(int)readmemb;
2809 if(type==LOADH_STUB||type==LOADHU_STUB)
2810 ftable=(int)readmemh;
2811 if(type==LOADW_STUB)
2812 ftable=(int)readmem;
24385cae 2813#ifndef FORCE32
57871462 2814 if(type==LOADD_STUB)
2815 ftable=(int)readmemd;
24385cae 2816#endif
2817 assert(ftable!=0);
57871462 2818 emit_writeword(rs,(int)&address);
2819 //emit_pusha();
2820 save_regs(reglist);
97a238a6 2821#ifndef PCSX
57871462 2822 ds=i_regs!=&regs[i];
2823 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2824 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2825 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2826 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2827 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
97a238a6 2828#endif
57871462 2829 emit_shrimm(rs,16,1);
2830 int cc=get_reg(i_regmap,CCREG);
2831 if(cc<0) {
2832 emit_loadreg(CCREG,2);
2833 }
2834 emit_movimm(ftable,0);
2835 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
f51dc36c 2836#ifndef PCSX
57871462 2837 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
f51dc36c 2838#endif
57871462 2839 //emit_readword((int)&last_count,temp);
2840 //emit_add(cc,temp,cc);
2841 //emit_writeword(cc,(int)&Count);
2842 //emit_mov(15,14);
2843 emit_call((int)&indirect_jump_indexed);
2844 //emit_callreg(rs);
2845 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
f51dc36c 2846#ifndef PCSX
57871462 2847 // We really shouldn't need to update the count here,
2848 // but not doing so causes random crashes...
2849 emit_readword((int)&Count,HOST_TEMPREG);
2850 emit_readword((int)&next_interupt,2);
2851 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2852 emit_writeword(2,(int)&last_count);
2853 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2854 if(cc<0) {
2855 emit_storereg(CCREG,HOST_TEMPREG);
2856 }
f51dc36c 2857#endif
57871462 2858 //emit_popa();
2859 restore_regs(reglist);
2860 //if((cc=get_reg(regmap,CCREG))>=0) {
2861 // emit_loadreg(CCREG,cc);
2862 //}
f18c0f46 2863 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2864 assert(rt>=0);
2865 if(type==LOADB_STUB)
2866 emit_movsbl((int)&readmem_dword,rt);
2867 if(type==LOADBU_STUB)
2868 emit_movzbl((int)&readmem_dword,rt);
2869 if(type==LOADH_STUB)
2870 emit_movswl((int)&readmem_dword,rt);
2871 if(type==LOADHU_STUB)
2872 emit_movzwl((int)&readmem_dword,rt);
2873 if(type==LOADW_STUB)
2874 emit_readword((int)&readmem_dword,rt);
2875 if(type==LOADD_STUB) {
2876 emit_readword((int)&readmem_dword,rt);
2877 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2878 }
57871462 2879 }
2880 emit_jmp(stubs[n][2]); // return address
c6c3b1b3 2881#endif // !PCSX
57871462 2882}
2883
c6c3b1b3 2884#ifdef PCSX
2885// return memhandler, or get directly accessable address and return 0
2886u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2887{
2888 u_int l1,l2=0;
2889 l1=((u_int *)table)[addr>>12];
2890 if((l1&(1<<31))==0) {
2891 u_int v=l1<<1;
2892 *addr_host=v+addr;
2893 return 0;
2894 }
2895 else {
2896 l1<<=1;
2897 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2898 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
b96d3df7 2899 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
c6c3b1b3 2900 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2901 else
2902 l2=((u_int *)l1)[(addr&0xfff)/4];
2903 if((l2&(1<<31))==0) {
2904 u_int v=l2<<1;
2905 *addr_host=v+(addr&0xfff);
2906 return 0;
2907 }
2908 return l2<<1;
2909 }
2910}
2911#endif
2912
57871462 2913inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2914{
2915 int rs=get_reg(regmap,target);
2916 int rth=get_reg(regmap,target|64);
2917 int rt=get_reg(regmap,target);
535d208a 2918 if(rs<0) rs=get_reg(regmap,-1);
57871462 2919 assert(rs>=0);
c6c3b1b3 2920#ifdef PCSX
2921 u_int handler,host_addr=0;
c6c3b1b3 2922 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2923 if (handler==0) {
2924 if(rt<0)
2925 return;
13e35c04 2926 if(addr!=host_addr)
2927 emit_movimm_from(addr,rs,host_addr,rs);
c6c3b1b3 2928 switch(type) {
2929 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2930 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2931 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2932 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2933 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2934 default: assert(0);
2935 }
2936 return;
2937 }
2938
2939 // call a memhandler
2940 if(rt>=0)
2941 reglist&=~(1<<rt);
2942 save_regs(reglist);
2943 if(target==0)
2944 emit_movimm(addr,0);
2945 else if(rs!=0)
2946 emit_mov(rs,0);
2947 int cc=get_reg(regmap,CCREG);
2948 if(cc<0)
2949 emit_loadreg(CCREG,2);
2950 emit_readword((int)&last_count,3);
2573466a 2951 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
c6c3b1b3 2952 emit_add(2,3,3);
2953 emit_writeword(3,(int)&Count);
2954
2955 int offset=(int)handler-(int)out-8;
2956 if(offset<-33554432||offset>=33554432) {
2957 // unreachable memhandler, a plugin func perhaps
2958 emit_movimm(handler,1);
2959 emit_callreg(1);
2960 }
2961 else
2962 emit_call(handler);
2963 if(rt>=0) {
2964 switch(type) {
2965 case LOADB_STUB: emit_signextend8(0,rt); break;
2966 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2967 case LOADH_STUB: emit_signextend16(0,rt); break;
2968 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2969 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2970 default: assert(0);
2971 }
2972 }
2973 restore_regs(reglist);
2974#else // if !PCSX
57871462 2975 int ftable=0;
2976 if(type==LOADB_STUB||type==LOADBU_STUB)
2977 ftable=(int)readmemb;
2978 if(type==LOADH_STUB||type==LOADHU_STUB)
2979 ftable=(int)readmemh;
2980 if(type==LOADW_STUB)
2981 ftable=(int)readmem;
24385cae 2982#ifndef FORCE32
57871462 2983 if(type==LOADD_STUB)
2984 ftable=(int)readmemd;
24385cae 2985#endif
2986 assert(ftable!=0);
fd99c415 2987 if(target==0)
2988 emit_movimm(addr,rs);
57871462 2989 emit_writeword(rs,(int)&address);
2990 //emit_pusha();
2991 save_regs(reglist);
0c1fe38b 2992#ifndef PCSX
2993 if((signed int)addr>=(signed int)0xC0000000) {
2994 // Theoretically we can have a pagefault here, if the TLB has never
2995 // been enabled and the address is outside the range 80000000..BFFFFFFF
2996 // Write out the registers so the pagefault can be handled. This is
2997 // a very rare case and likely represents a bug.
2998 int ds=regmap!=regs[i].regmap;
2999 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3000 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3001 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3002 }
3003#endif
57871462 3004 //emit_shrimm(rs,16,1);
3005 int cc=get_reg(regmap,CCREG);
3006 if(cc<0) {
3007 emit_loadreg(CCREG,2);
3008 }
3009 //emit_movimm(ftable,0);
3010 emit_movimm(((u_int *)ftable)[addr>>16],0);
3011 //emit_readword((int)&last_count,12);
2573466a 3012 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
f51dc36c 3013#ifndef PCSX
57871462 3014 if((signed int)addr>=(signed int)0xC0000000) {
3015 // Pagefault address
3016 int ds=regmap!=regs[i].regmap;
3017 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3018 }
f51dc36c 3019#endif
57871462 3020 //emit_add(12,2,2);
3021 //emit_writeword(2,(int)&Count);
3022 //emit_call(((u_int *)ftable)[addr>>16]);
3023 emit_call((int)&indirect_jump);
f51dc36c 3024#ifndef PCSX
57871462 3025 // We really shouldn't need to update the count here,
3026 // but not doing so causes random crashes...
3027 emit_readword((int)&Count,HOST_TEMPREG);
3028 emit_readword((int)&next_interupt,2);
2573466a 3029 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
57871462 3030 emit_writeword(2,(int)&last_count);
3031 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3032 if(cc<0) {
3033 emit_storereg(CCREG,HOST_TEMPREG);
3034 }
f51dc36c 3035#endif
57871462 3036 //emit_popa();
3037 restore_regs(reglist);
fd99c415 3038 if(rt>=0) {
3039 if(type==LOADB_STUB)
3040 emit_movsbl((int)&readmem_dword,rt);
3041 if(type==LOADBU_STUB)
3042 emit_movzbl((int)&readmem_dword,rt);
3043 if(type==LOADH_STUB)
3044 emit_movswl((int)&readmem_dword,rt);
3045 if(type==LOADHU_STUB)
3046 emit_movzwl((int)&readmem_dword,rt);
3047 if(type==LOADW_STUB)
3048 emit_readword((int)&readmem_dword,rt);
3049 if(type==LOADD_STUB) {
3050 emit_readword((int)&readmem_dword,rt);
3051 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
3052 }
57871462 3053 }
c6c3b1b3 3054#endif // !PCSX
57871462 3055}
3056
3057do_writestub(int n)
3058{
3059 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
3060 literal_pool(256);
3061 set_jump_target(stubs[n][1],(int)out);
3062 int type=stubs[n][0];
3063 int i=stubs[n][3];
3064 int rs=stubs[n][4];
3065 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3066 u_int reglist=stubs[n][7];
3067 signed char *i_regmap=i_regs->regmap;
3068 int addr=get_reg(i_regmap,AGEN1+(i&1));
3069 int rth,rt,r;
3070 int ds;
b9b61529 3071 if(itype[i]==C1LS||itype[i]==C2LS) {
57871462 3072 rth=get_reg(i_regmap,FTEMP|64);
3073 rt=get_reg(i_regmap,r=FTEMP);
3074 }else{
3075 rth=get_reg(i_regmap,rs2[i]|64);
3076 rt=get_reg(i_regmap,r=rs2[i]);
3077 }
3078 assert(rs>=0);
3079 assert(rt>=0);
b96d3df7 3080#ifdef PCSX
3081 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3082 int reglist2=reglist|(1<<rs)|(1<<rt);
3083 for(rtmp=0;rtmp<=12;rtmp++) {
3084 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)&reglist2)==0) {
3085 temp=rtmp; break;
3086 }
3087 }
3088 if(temp==-1) {
3089 save_regs(reglist);
3090 regs_saved=1;
3091 for(rtmp=0;rtmp<=3;rtmp++)
3092 if(rtmp!=rs&&rtmp!=rt)
3093 {temp=rtmp;break;}
3094 }
3095 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3096 temp2=3;
3097 emit_readword((int)&mem_wtab,temp);
3098 emit_shrimm(rs,12,temp2);
3099 emit_readword_dualindexedx4(temp,temp2,temp2);
3100 emit_lsls_imm(temp2,1,temp2);
3101 switch(type) {
3102 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3103 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3104 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3105 default: assert(0);
3106 }
3107 if(regs_saved) {
3108 restore_jump=(int)out;
3109 emit_jcc(0); // jump to reg restore
3110 }
3111 else
3112 emit_jcc(stubs[n][2]); // return address (invcode check)
3113
3114 if(!regs_saved)
3115 save_regs(reglist);
3116 int handler=0;
3117 switch(type) {
3118 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3119 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3120 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3121 }
3122 assert(handler!=0);
3123 pass_args(rs,rt);
3124 if(temp2!=3)
3125 emit_mov(temp2,3);
3126 int cc=get_reg(i_regmap,CCREG);
3127 if(cc<0)
3128 emit_loadreg(CCREG,2);
2573466a 3129 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
b96d3df7 3130 // returns new cycle_count
3131 emit_call(handler);
2573466a 3132 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
b96d3df7 3133 if(cc<0)
3134 emit_storereg(CCREG,2);
3135 if(restore_jump)
3136 set_jump_target(restore_jump,(int)out);
3137 restore_regs(reglist);
3138 ra=stubs[n][2];
3139 if(!restore_jump) ra+=4*3; // skip invcode check
3140 emit_jmp(ra);
3141#else // if !PCSX
57871462 3142 if(addr<0) addr=get_reg(i_regmap,-1);
3143 assert(addr>=0);
3144 int ftable=0;
3145 if(type==STOREB_STUB)
3146 ftable=(int)writememb;
3147 if(type==STOREH_STUB)
3148 ftable=(int)writememh;
3149 if(type==STOREW_STUB)
3150 ftable=(int)writemem;
24385cae 3151#ifndef FORCE32
57871462 3152 if(type==STORED_STUB)
3153 ftable=(int)writememd;
24385cae 3154#endif
3155 assert(ftable!=0);
57871462 3156 emit_writeword(rs,(int)&address);
3157 //emit_shrimm(rs,16,rs);
3158 //emit_movmem_indexedx4(ftable,rs,rs);
3159 if(type==STOREB_STUB)
3160 emit_writebyte(rt,(int)&byte);
3161 if(type==STOREH_STUB)
3162 emit_writehword(rt,(int)&hword);
3163 if(type==STOREW_STUB)
3164 emit_writeword(rt,(int)&word);
3165 if(type==STORED_STUB) {
3d624f89 3166#ifndef FORCE32
57871462 3167 emit_writeword(rt,(int)&dword);
3168 emit_writeword(r?rth:rt,(int)&dword+4);
3d624f89 3169#else
3170 printf("STORED_STUB\n");
3171#endif
57871462 3172 }
3173 //emit_pusha();
3174 save_regs(reglist);
97a238a6 3175#ifndef PCSX
57871462 3176 ds=i_regs!=&regs[i];
3177 int real_rs=get_reg(i_regmap,rs1[i]);
3178 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3179 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3180 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3181 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
97a238a6 3182#endif
57871462 3183 emit_shrimm(rs,16,1);
3184 int cc=get_reg(i_regmap,CCREG);
3185 if(cc<0) {
3186 emit_loadreg(CCREG,2);
3187 }
3188 emit_movimm(ftable,0);
3189 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
f51dc36c 3190#ifndef PCSX
57871462 3191 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
f51dc36c 3192#endif
57871462 3193 //emit_readword((int)&last_count,temp);
3194 //emit_addimm(cc,2*stubs[n][5]+2,cc);
3195 //emit_add(cc,temp,cc);
3196 //emit_writeword(cc,(int)&Count);
3197 emit_call((int)&indirect_jump_indexed);
3198 //emit_callreg(rs);
3199 emit_readword((int)&Count,HOST_TEMPREG);
3200 emit_readword((int)&next_interupt,2);
3201 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3202 emit_writeword(2,(int)&last_count);
3203 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3204 if(cc<0) {
3205 emit_storereg(CCREG,HOST_TEMPREG);
3206 }
3207 //emit_popa();
3208 restore_regs(reglist);
3209 //if((cc=get_reg(regmap,CCREG))>=0) {
3210 // emit_loadreg(CCREG,cc);
3211 //}
3212 emit_jmp(stubs[n][2]); // return address
b96d3df7 3213#endif // !PCSX
57871462 3214}
3215
3216inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3217{
3218 int rs=get_reg(regmap,-1);
3219 int rth=get_reg(regmap,target|64);
3220 int rt=get_reg(regmap,target);
3221 assert(rs>=0);
3222 assert(rt>=0);
cbbab9cd 3223#ifdef PCSX
b96d3df7 3224 u_int handler,host_addr=0;
b96d3df7 3225 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3226 if (handler==0) {
13e35c04 3227 if(addr!=host_addr)
3228 emit_movimm_from(addr,rs,host_addr,rs);
b96d3df7 3229 switch(type) {
3230 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3231 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3232 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3233 default: assert(0);
3234 }
3235 return;
3236 }
3237
3238 // call a memhandler
3239 save_regs(reglist);
13e35c04 3240 pass_args(rs,rt);
b96d3df7 3241 int cc=get_reg(regmap,CCREG);
3242 if(cc<0)
3243 emit_loadreg(CCREG,2);
2573466a 3244 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
b96d3df7 3245 emit_movimm(handler,3);
3246 // returns new cycle_count
3247 emit_call((int)jump_handler_write_h);
2573466a 3248 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
b96d3df7 3249 if(cc<0)
3250 emit_storereg(CCREG,2);
3251 restore_regs(reglist);
3252#else // if !pcsx
57871462 3253 int ftable=0;
3254 if(type==STOREB_STUB)
3255 ftable=(int)writememb;
3256 if(type==STOREH_STUB)
3257 ftable=(int)writememh;
3258 if(type==STOREW_STUB)
3259 ftable=(int)writemem;
24385cae 3260#ifndef FORCE32
57871462 3261 if(type==STORED_STUB)
3262 ftable=(int)writememd;
24385cae 3263#endif
3264 assert(ftable!=0);
57871462 3265 emit_writeword(rs,(int)&address);
3266 //emit_shrimm(rs,16,rs);
3267 //emit_movmem_indexedx4(ftable,rs,rs);
3268 if(type==STOREB_STUB)
3269 emit_writebyte(rt,(int)&byte);
3270 if(type==STOREH_STUB)
3271 emit_writehword(rt,(int)&hword);
3272 if(type==STOREW_STUB)
3273 emit_writeword(rt,(int)&word);
3274 if(type==STORED_STUB) {
3d624f89 3275#ifndef FORCE32
57871462 3276 emit_writeword(rt,(int)&dword);
3277 emit_writeword(target?rth:rt,(int)&dword+4);
3d624f89 3278#else
3279 printf("STORED_STUB\n");
3280#endif
57871462 3281 }
3282 //emit_pusha();
3283 save_regs(reglist);
0c1fe38b 3284#ifndef PCSX
3285 // rearmed note: load_all_consts prevents BIOS boot, some bug?
3286 if((signed int)addr>=(signed int)0xC0000000) {
3287 // Theoretically we can have a pagefault here, if the TLB has never
3288 // been enabled and the address is outside the range 80000000..BFFFFFFF
3289 // Write out the registers so the pagefault can be handled. This is
3290 // a very rare case and likely represents a bug.
3291 int ds=regmap!=regs[i].regmap;
3292 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3293 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3294 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3295 }
3296#endif
57871462 3297 //emit_shrimm(rs,16,1);
3298 int cc=get_reg(regmap,CCREG);
3299 if(cc<0) {
3300 emit_loadreg(CCREG,2);
3301 }
3302 //emit_movimm(ftable,0);
3303 emit_movimm(((u_int *)ftable)[addr>>16],0);
3304 //emit_readword((int)&last_count,12);
2573466a 3305 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
f51dc36c 3306#ifndef PCSX
57871462 3307 if((signed int)addr>=(signed int)0xC0000000) {
3308 // Pagefault address
3309 int ds=regmap!=regs[i].regmap;
3310 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3311 }
f51dc36c 3312#endif
57871462 3313 //emit_add(12,2,2);
3314 //emit_writeword(2,(int)&Count);
3315 //emit_call(((u_int *)ftable)[addr>>16]);
3316 emit_call((int)&indirect_jump);
3317 emit_readword((int)&Count,HOST_TEMPREG);
3318 emit_readword((int)&next_interupt,2);
2573466a 3319 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
57871462 3320 emit_writeword(2,(int)&last_count);
3321 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3322 if(cc<0) {
3323 emit_storereg(CCREG,HOST_TEMPREG);
3324 }
3325 //emit_popa();
3326 restore_regs(reglist);
b96d3df7 3327#endif
57871462 3328}
3329
3330do_unalignedwritestub(int n)
3331{
b7918751 3332 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3333 literal_pool(256);
57871462 3334 set_jump_target(stubs[n][1],(int)out);
b7918751 3335
3336 int i=stubs[n][3];
3337 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3338 int addr=stubs[n][5];
3339 u_int reglist=stubs[n][7];
3340 signed char *i_regmap=i_regs->regmap;
3341 int temp2=get_reg(i_regmap,FTEMP);
3342 int rt;
3343 int ds, real_rs;
3344 rt=get_reg(i_regmap,rs2[i]);
3345 assert(rt>=0);
3346 assert(addr>=0);
3347 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3348 reglist|=(1<<addr);
3349 reglist&=~(1<<temp2);
3350
b96d3df7 3351#if 1
3352 // don't bother with it and call write handler
3353 save_regs(reglist);
3354 pass_args(addr,rt);
3355 int cc=get_reg(i_regmap,CCREG);
3356 if(cc<0)
3357 emit_loadreg(CCREG,2);
2573466a 3358 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
b96d3df7 3359 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2573466a 3360 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
b96d3df7 3361 if(cc<0)
3362 emit_storereg(CCREG,2);
3363 restore_regs(reglist);
3364 emit_jmp(stubs[n][2]); // return address
3365#else
b7918751 3366 emit_andimm(addr,0xfffffffc,temp2);
3367 emit_writeword(temp2,(int)&address);
3368
3369 save_regs(reglist);
97a238a6 3370#ifndef PCSX
b7918751 3371 ds=i_regs!=&regs[i];
3372 real_rs=get_reg(i_regmap,rs1[i]);
3373 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3374 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3375 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3376 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
97a238a6 3377#endif
b7918751 3378 emit_shrimm(addr,16,1);
3379 int cc=get_reg(i_regmap,CCREG);
3380 if(cc<0) {
3381 emit_loadreg(CCREG,2);
3382 }
3383 emit_movimm((u_int)readmem,0);
3384 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
f51dc36c 3385#ifndef PCSX
3386 // pagefault address
3387 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3388#endif
b7918751 3389 emit_call((int)&indirect_jump_indexed);
3390 restore_regs(reglist);
3391
3392 emit_readword((int)&readmem_dword,temp2);
3393 int temp=addr; //hmh
3394 emit_shlimm(addr,3,temp);
3395 emit_andimm(temp,24,temp);
3396#ifdef BIG_ENDIAN_MIPS
3397 if (opcode[i]==0x2e) // SWR
3398#else
3399 if (opcode[i]==0x2a) // SWL
3400#endif
3401 emit_xorimm(temp,24,temp);
3402 emit_movimm(-1,HOST_TEMPREG);
55439448 3403 if (opcode[i]==0x2a) { // SWL
b7918751 3404 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3405 emit_orrshr(rt,temp,temp2);
3406 }else{
3407 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);