[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.c

/*
 * (C) Gražvydas "notaz" Ignotas, 2010-2011
 *
 * This work is licensed under the terms of GNU GPL version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include <stdio.h>

#include "emu_if.h"
#include "pcsxmem.h"
#include "../psxhle.h"
#include "../r3000a.h"
#include "../cdrom.h"
#include "../psxdma.h"
#include "../mdec.h"
#include "../gte_arm.h"
#include "../gte_neon.h"
#define FLAGLESS
#include "../gte.h"

#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))

//#define evprintf printf
#define evprintf(...)

char invalid_code[0x100000];
u32 event_cycles[PSXINT_COUNT];

static void schedule_timeslice(void)
{
	u32 i, c = psxRegs.cycle;
	s32 min, dif;

	min = psxNextsCounter + psxNextCounter - c;
	for (i = 0; i < ARRAY_SIZE(event_cycles); i++) {
		dif = event_cycles[i] - c;
		//evprintf("  ev %d\n", dif);
		if (0 < dif && dif < min)
			min = dif;
	}
	next_interupt = c + min;

#if 0
	static u32 cnt, last_cycle;
	static u64 sum;
	if (last_cycle) {
		cnt++;
		sum += psxRegs.cycle - last_cycle;
		if ((cnt & 0xff) == 0)
			printf("%u\n", (u32)(sum / cnt));
	}
	last_cycle = psxRegs.cycle;
#endif
}

typedef void (irq_func)();

static irq_func * const irq_funcs[] = {
	[PSXINT_SIO]	= sioInterrupt,
	[PSXINT_CDR]	= cdrInterrupt,
	[PSXINT_CDREAD]	= cdrReadInterrupt,
	[PSXINT_GPUDMA]	= gpuInterrupt,
	[PSXINT_MDECOUTDMA] = mdec1Interrupt,
	[PSXINT_SPUDMA]	= spuInterrupt,
	[PSXINT_MDECINDMA] = mdec0Interrupt,
	[PSXINT_GPUOTCDMA] = gpuotcInterrupt,
	[PSXINT_CDRDMA] = cdrDmaInterrupt,
	[PSXINT_CDRLID] = cdrLidSeekInterrupt,
	[PSXINT_CDRPLAY] = cdrPlayInterrupt,
};

/* local dupe of psxBranchTest, using event_cycles */
static void irq_test(void)
{
	u32 irqs = psxRegs.interrupt;
	u32 cycle = psxRegs.cycle;
	u32 irq, irq_bits;

	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
		psxRcntUpdate();

	// irq_funcs() may queue more irqs
	psxRegs.interrupt = 0;

	for (irq = 0, irq_bits = irqs; irq_bits != 0; irq++, irq_bits >>= 1) {
		if (!(irq_bits & 1))
			continue;
		if ((s32)(cycle - event_cycles[irq]) >= 0) {
			irqs &= ~(1 << irq);
			irq_funcs[irq]();
		}
	}
	psxRegs.interrupt |= irqs;

	if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
		psxException(0x400, 0);
		pending_exception = 1;
	}
}

void gen_interupt()
{
	evprintf("  +ge %08x, %u->%u\n", psxRegs.pc, psxRegs.cycle, next_interupt);

	irq_test();
	//psxBranchTest();
	//pending_exception = 1;

	schedule_timeslice();

	evprintf("  -ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
		next_interupt, next_interupt - psxRegs.cycle);
}

// from interpreter
extern void MTC0(int reg, u32 val);

void pcsx_mtc0(u32 reg, u32 val)
{
	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
	MTC0(reg, val);
	gen_interupt();
}

void pcsx_mtc0_ds(u32 reg, u32 val)
{
	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
	MTC0(reg, val);
}

void new_dyna_save(void)
{
	// psxRegs.intCycle is always maintained, no need to convert
}

void new_dyna_restore(void)
{
	int i;
	for (i = 0; i < PSXINT_COUNT; i++)
		event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
}

void *gte_handlers[64];

void *gte_handlers_nf[64] = {
	NULL      , gteRTPS_nf , NULL       , NULL      , NULL     , NULL       , gteNCLIP_nf, NULL      , // 00
	NULL      , NULL       , NULL       , NULL      , gteOP_nf , NULL       , NULL       , NULL      , // 08
	gteDPCS_nf, gteINTPL_nf, gteMVMVA_nf, gteNCDS_nf, gteCDP_nf, NULL       , gteNCDT_nf , NULL      , // 10
	NULL      , NULL       , NULL       , gteNCCS_nf, gteCC_nf , NULL       , gteNCS_nf  , NULL      , // 18
	gteNCT_nf , NULL       , NULL       , NULL      , NULL     , NULL       , NULL       , NULL      , // 20
	gteSQR_nf , gteDCPL_nf , gteDPCT_nf , NULL      , NULL     , gteAVSZ3_nf, gteAVSZ4_nf, NULL      , // 28 
	gteRTPT_nf, NULL       , NULL       , NULL      , NULL     , NULL       , NULL       , NULL      , // 30
	NULL      , NULL       , NULL       , NULL      , NULL     , gteGPF_nf  , gteGPL_nf  , gteNCCT_nf, // 38
};

const char *gte_regnames[64] = {
	NULL  , "RTPS" , NULL   , NULL  , NULL , NULL   , "NCLIP", NULL  , // 00
	NULL  , NULL   , NULL   , NULL  , "OP" , NULL   , NULL   , NULL  , // 08
	"DPCS", "INTPL", "MVMVA", "NCDS", "CDP", NULL   , "NCDT" , NULL  , // 10
	NULL  , NULL   , NULL   , "NCCS", "CC" , NULL   , "NCS"  , NULL  , // 18
	"NCT" , NULL   , NULL   , NULL  , NULL , NULL   , NULL   , NULL  , // 20
	"SQR" , "DCPL" , "DPCT" , NULL  , NULL , "AVSZ3", "AVSZ4", NULL  , // 28 
	"RTPT", NULL   , NULL   , NULL  , NULL , NULL   , NULL   , NULL  , // 30
	NULL  , NULL   , NULL   , NULL  , NULL , "GPF"  , "GPL"  , "NCCT", // 38
};

/* from gte.txt.. not sure if this is any good. */
const char gte_cycletab[64] = {
	/*   1   2   3   4   5   6   7   8   9   a   b   c   d   e   f */
	 0, 15,  0,  0,  0,  0,  8,  0,  0,  0,  0,  0,  6,  0,  0,  0,
	 8,  8,  8, 19, 13,  0, 44,  0,  0,  0,  0, 17, 11,  0, 14,  0,
	30,  0,  0,  0,  0,  0,  0,  0,  5,  8, 17,  0,  0,  5,  6,  0,
	23,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  5,  5, 39,
};

static int ari64_init()
{
	extern void (*psxCP2[64])();
	extern void psxNULL();
	size_t i;

	new_dynarec_init();
	new_dyna_pcsx_mem_init();

	for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
		if (psxCP2[i] != psxNULL)
			gte_handlers[i] = psxCP2[i];

#if !defined(DRC_DBG) && !defined(PCNT)
#ifdef __arm__
	gte_handlers[0x06] = gteNCLIP_arm;
	gte_handlers_nf[0x01] = gteRTPS_nf_arm;
	gte_handlers_nf[0x30] = gteRTPT_nf_arm;
#endif
#ifdef __ARM_NEON__
	// compiler's _nf version is still a lot slower then neon
	// _nf_arm RTPS is roughly the same, RTPT slower
	gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
	gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
	gte_handlers[0x12] = gte_handlers_nf[0x12] = gteMVMVA_neon;
#endif
#endif
#ifdef DRC_DBG
	memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
#endif
	psxH_ptr = psxH;

	return 0;
}

static void ari64_reset()
{
	printf("ari64_reset\n");
	new_dyna_pcsx_mem_reset();
	invalidate_all_pages();
	new_dyna_restore();
	pending_exception = 1;
}

// execute until predefined leave points
// (HLE softcall exit and BIOS fastboot end)
static void ari64_execute_until()
{
	schedule_timeslice();

	evprintf("ari64_execute %08x, %u->%u (%d)\n", psxRegs.pc,
		psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);

	new_dyna_start();

	evprintf("ari64_execute end %08x, %u->%u (%d)\n", psxRegs.pc,
		psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
}

static void ari64_execute()
{
	while (!stop) {
		ari64_execute_until();
		evprintf("drc left @%08x\n", psxRegs.pc);
	}
}

static void ari64_clear(u32 addr, u32 size)
{
	u32 start, end, main_ram;

	size *= 4; /* PCSX uses DMA units */

	evprintf("ari64_clear %08x %04x\n", addr, size);

	/* check for RAM mirrors */
	main_ram = (addr & 0xffe00000) == 0x80000000;

	start = addr >> 12;
	end = (addr + size) >> 12;

	for (; start <= end; start++)
		if (!main_ram || !invalid_code[start])
			invalidate_block(start);
}

static void ari64_shutdown()
{
	new_dynarec_cleanup();
}

extern void intExecute();
extern void intExecuteT();
extern void intExecuteBlock();
extern void intExecuteBlockT();
#ifndef DRC_DBG
#define intExecuteT intExecute
#define intExecuteBlockT intExecuteBlock
#endif

R3000Acpu psxRec = {
	ari64_init,
	ari64_reset,
#if defined(__arm__)
	ari64_execute,
	ari64_execute_until,
#else
	intExecuteT,
	intExecuteBlockT,
#endif
	ari64_clear,
	ari64_shutdown
};

// TODO: rm
#ifndef DRC_DBG
void do_insn_trace() {}
void do_insn_cmp() {}
#endif

#if defined(__x86_64__) || defined(__i386__)
unsigned int address, readmem_word, word;
unsigned short hword;
unsigned char byte;
int pending_exception, stop;
unsigned int next_interupt;
int new_dynarec_did_compile;
int cycle_multiplier;
void *psxH_ptr;
void new_dynarec_init() {}
void new_dyna_start() {}
void new_dynarec_cleanup() {}
void new_dynarec_clear_full() {}
void invalidate_all_pages() {}
void invalidate_block(unsigned int block) {}
void new_dyna_pcsx_mem_init(void) {}
void new_dyna_pcsx_mem_reset(void) {}
#endif

#ifdef DRC_DBG

#include <stddef.h>
static FILE *f;
extern u32 last_io_addr;

static void dump_mem(const char *fname, void *mem, size_t size)
{
	FILE *f1 = fopen(fname, "wb");
	if (f1 == NULL)
		f1 = fopen(strrchr(fname, '/') + 1, "wb");
	fwrite(mem, 1, size, f1);
	fclose(f1);
}

static u32 memcheck_read(u32 a)
{
	if ((a >> 16) == 0x1f80)
		// scratchpad/IO
		return *(u32 *)(psxH + (a & 0xfffc));

	if ((a >> 16) == 0x1f00)
		// parallel
		return *(u32 *)(psxP + (a & 0xfffc));

//	if ((a & ~0xe0600000) < 0x200000)
	// RAM
	return *(u32 *)(psxM + (a & 0x1ffffc));
}

void do_insn_trace(void)
{
	static psxRegisters oldregs;
	static u32 old_io_addr = (u32)-1;
	static u32 old_io_data = 0xbad0c0de;
	u32 *allregs_p = (void *)&psxRegs;
	u32 *allregs_o = (void *)&oldregs;
	u32 io_data;
	int i;
	u8 byte;

//last_io_addr = 0x5e2c8;
	if (f == NULL)
		f = fopen("tracelog", "wb");

	oldregs.code = psxRegs.code; // don't care
	for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
		if (allregs_p[i] != allregs_o[i]) {
			fwrite(&i, 1, 1, f);
			fwrite(&allregs_p[i], 1, 4, f);
			allregs_o[i] = allregs_p[i];
		}
	}
	if (old_io_addr != last_io_addr) {
		byte = 0xfd;
		fwrite(&byte, 1, 1, f);
		fwrite(&last_io_addr, 1, 4, f);
		old_io_addr = last_io_addr;
	}
	io_data = memcheck_read(last_io_addr);
	if (old_io_data != io_data) {
		byte = 0xfe;
		fwrite(&byte, 1, 1, f);
		fwrite(&io_data, 1, 4, f);
		old_io_data = io_data;
	}
	byte = 0xff;
	fwrite(&byte, 1, 1, f);

#if 0
	if (psxRegs.cycle == 190230) {
		dump_mem("/mnt/ntz/dev/pnd/tmp/psxram_i.dump", psxM, 0x200000);
		dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs_i.dump", psxH, 0x10000);
		printf("dumped\n");
		exit(1);
	}
#endif
}

static const char *regnames[offsetof(psxRegisters, intCycle) / 4] = {
	"r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
	"r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
	"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
	"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
	"lo",  "hi",
	"C0_0",  "C0_1",  "C0_2",  "C0_3",  "C0_4",  "C0_5",  "C0_6",  "C0_7",
	"C0_8",  "C0_9",  "C0_10", "C0_11", "C0_12", "C0_13", "C0_14", "C0_15",
	"C0_16", "C0_17", "C0_18", "C0_19", "C0_20", "C0_21", "C0_22", "C0_23",
	"C0_24", "C0_25", "C0_26", "C0_27", "C0_28", "C0_29", "C0_30", "C0_31",

	"C2D0",  "C2D1",  "C2D2",  "C2D3",  "C2D4",  "C2D5",  "C2D6",  "C2D7",
	"C2D8",  "C2D9",  "C2D10", "C2D11", "C2D12", "C2D13", "C2D14", "C2D15",
	"C2D16", "C2D17", "C2D18", "C2D19", "C2D20", "C2D21", "C2D22", "C2D23",
	"C2D24", "C2D25", "C2D26", "C2D27", "C2D28", "C2D29", "C2D30", "C2D31",

	"C2C0",  "C2C1",  "C2C2",  "C2C3",  "C2C4",  "C2C5",  "C2C6",  "C2C7",
	"C2C8",  "C2C9",  "C2C10", "C2C11", "C2C12", "C2C13", "C2C14", "C2C15",
	"C2C16", "C2C17", "C2C18", "C2C19", "C2C20", "C2C21", "C2C22", "C2C23",
	"C2C24", "C2C25", "C2C26", "C2C27", "C2C28", "C2C29", "C2C30", "C2C31",

	"PC", "code", "cycle", "interrupt",
};

static struct {
	int reg;
	u32 val, val_expect;
	u32 pc, cycle;
} miss_log[64];
static int miss_log_i;
#define miss_log_len (sizeof(miss_log)/sizeof(miss_log[0]))
#define miss_log_mask (miss_log_len-1)

static void miss_log_add(int reg, u32 val, u32 val_expect, u32 pc, u32 cycle)
{
	miss_log[miss_log_i].reg = reg;
	miss_log[miss_log_i].val = val;
	miss_log[miss_log_i].val_expect = val_expect;
	miss_log[miss_log_i].pc = pc;
	miss_log[miss_log_i].cycle = cycle;
	miss_log_i = (miss_log_i + 1) & miss_log_mask;
}

void breakme() {}

void do_insn_cmp(void)
{
	static psxRegisters rregs;
	static u32 mem_addr, mem_val;
	u32 *allregs_p = (void *)&psxRegs;
	u32 *allregs_e = (void *)&rregs;
	static u32 ppc, failcount;
	int i, ret, bad = 0;
	u8 code;

	if (f == NULL)
		f = fopen("tracelog", "rb");

	while (1) {
		if ((ret = fread(&code, 1, 1, f)) <= 0)
			break;
		if (ret <= 0)
			break;
		if (code == 0xff)
			break;
		if (code == 0xfd) {
			if ((ret = fread(&mem_addr, 1, 4, f)) <= 0)
				break;
			continue;
		}
		if (code == 0xfe) {
			if ((ret = fread(&mem_val, 1, 4, f)) <= 0)
				break;
			continue;
		}
		if ((ret = fread(&allregs_e[code], 1, 4, f)) <= 0)
			break;
	}

	if (ret <= 0) {
		printf("EOF?\n");
		goto end;
	}

	psxRegs.code = rregs.code; // don't care
	psxRegs.cycle = rregs.cycle;
	psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count

//if (psxRegs.cycle == 166172) breakme();

	if (memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle)) == 0 &&
			mem_val == memcheck_read(mem_addr)
	   ) {
		failcount = 0;
		goto ok;
	}

	for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
		if (allregs_p[i] != allregs_e[i]) {
			miss_log_add(i, allregs_p[i], allregs_e[i], psxRegs.pc, psxRegs.cycle);
			bad++;
		}
	}

	if (mem_val != memcheck_read(mem_addr)) {
		printf("bad mem @%08x: %08x %08x\n", mem_addr, memcheck_read(mem_addr), mem_val);
		goto end;
	}

	if (psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) {
		static int last_mcycle;
		if (last_mcycle != psxRegs.cycle >> 20) {
			printf("%u\n", psxRegs.cycle);
			last_mcycle = psxRegs.cycle >> 20;
		}
		failcount++;
		goto ok;
	}

end:
	for (i = 0; i < miss_log_len; i++, miss_log_i = (miss_log_i + 1) & miss_log_mask)
		printf("bad %5s: %08x %08x, pc=%08x, cycle %u\n",
			regnames[miss_log[miss_log_i].reg], miss_log[miss_log_i].val,
			miss_log[miss_log_i].val_expect, miss_log[miss_log_i].pc, miss_log[miss_log_i].cycle);
	printf("-- %d\n", bad);
	for (i = 0; i < 8; i++)
		printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
			i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
	printf("PC: %08x/%08x, cycle %u\n", psxRegs.pc, ppc, psxRegs.cycle);
	dump_mem("/mnt/ntz/dev/pnd/tmp/psxram.dump", psxM, 0x200000);
	dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);
	exit(1);
ok:
	psxRegs.cycle = rregs.cycle + 2; // sync timing
	ppc = psxRegs.pc;
}

#endif
Commit	Line	Data
7e605697	1	/*
009faf24	2	* (C) Gražvydas "notaz" Ignotas, 2010-2011
7e605697	3	*
	4	* This work is licensed under the terms of GNU GPL version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
f95a77f7	8	#include <stdio.h>
	9
	10	#include "emu_if.h"
7e605697	11	#include "pcsxmem.h"
7139f3c8	12	#include "../psxhle.h"
d28b54b1	13	#include "../r3000a.h"
52082bc1	14	#include "../cdrom.h"
	15	#include "../psxdma.h"
	16	#include "../mdec.h"
59774ed0	17	#include "../gte_arm.h"
009faf24	18	#include "../gte_neon.h"
59774ed0	19	#define FLAGLESS
59774ed0	20	#include "../gte.h"
7139f3c8	21
ae602c19	22	#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
ae602c19	23
7139f3c8	24	//#define evprintf printf
	25	#define evprintf(...)
	26
f95a77f7	27	char invalid_code[0x100000];
d28b54b1	28	u32 event_cycles[PSXINT_COUNT];
f95a77f7	29
654e8cfb	30	static void schedule_timeslice(void)
f95a77f7	31	{
654e8cfb	32	u32 i, c = psxRegs.cycle;
	33	s32 min, dif;
	34
	35	min = psxNextsCounter + psxNextCounter - c;
	36	for (i = 0; i < ARRAY_SIZE(event_cycles); i++) {
	37	dif = event_cycles[i] - c;
	38	//evprintf(" ev %d\n", dif);
	39	if (0 < dif && dif < min)
	40	min = dif;
	41	}
	42	next_interupt = c + min;
	43
	44	#if 0
	45	static u32 cnt, last_cycle;
	46	static u64 sum;
	47	if (last_cycle) {
	48	cnt++;
	49	sum += psxRegs.cycle - last_cycle;
	50	if ((cnt & 0xff) == 0)
	51	printf("%u\n", (u32)(sum / cnt));
	52	}
	53	last_cycle = psxRegs.cycle;
	54	#endif
	55	}
ae602c19	56
52082bc1	57	typedef void (irq_func)();
	58
	59	static irq_func * const irq_funcs[] = {
	60	[PSXINT_SIO] = sioInterrupt,
	61	[PSXINT_CDR] = cdrInterrupt,
	62	[PSXINT_CDREAD] = cdrReadInterrupt,
	63	[PSXINT_GPUDMA] = gpuInterrupt,
	64	[PSXINT_MDECOUTDMA] = mdec1Interrupt,
	65	[PSXINT_SPUDMA] = spuInterrupt,
528ad661	66	[PSXINT_MDECINDMA] = mdec0Interrupt,
57a757ce	67	[PSXINT_GPUOTCDMA] = gpuotcInterrupt,
9f8b032d	68	[PSXINT_CDRDMA] = cdrDmaInterrupt,
9f8b032d	69	[PSXINT_CDRLID] = cdrLidSeekInterrupt,
7f457614	70	[PSXINT_CDRPLAY] = cdrPlayInterrupt,
52082bc1	71	};
	72
	73	/* local dupe of psxBranchTest, using event_cycles */
	74	static void irq_test(void)
	75	{
	76	u32 irqs = psxRegs.interrupt;
	77	u32 cycle = psxRegs.cycle;
	78	u32 irq, irq_bits;
	79
	80	if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
	81	psxRcntUpdate();
	82
	83	// irq_funcs() may queue more irqs
	84	psxRegs.interrupt = 0;
	85
	86	for (irq = 0, irq_bits = irqs; irq_bits != 0; irq++, irq_bits >>= 1) {
	87	if (!(irq_bits & 1))
	88	continue;
	89	if ((s32)(cycle - event_cycles[irq]) >= 0) {
	90	irqs &= ~(1 << irq);
	91	irq_funcs[irq]();
	92	}
	93	}
	94	psxRegs.interrupt \|= irqs;
	95
	96	if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
	97	psxException(0x400, 0);
	98	pending_exception = 1;
	99	}
	100	}
	101
654e8cfb	102	void gen_interupt()
654e8cfb	103	{
654e8cfb	104	evprintf(" +ge %08x, %u->%u\n", psxRegs.pc, psxRegs.cycle, next_interupt);
7139f3c8	105
52082bc1	106	irq_test();
	107	//psxBranchTest();
	108	//pending_exception = 1;
7139f3c8	109
654e8cfb	110	schedule_timeslice();
ae602c19	111
654e8cfb	112	evprintf(" -ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
654e8cfb	113	next_interupt, next_interupt - psxRegs.cycle);
f95a77f7	114	}
f95a77f7	115
fca1aef2	116	// from interpreter
	117	extern void MTC0(int reg, u32 val);
	118
63cb0298	119	void pcsx_mtc0(u32 reg, u32 val)
28bc5688	120	{
63cb0298	121	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
63cb0298	122	MTC0(reg, val);
fca1aef2	123	gen_interupt();
fca1aef2	124	}
28bc5688	125
63cb0298	126	void pcsx_mtc0_ds(u32 reg, u32 val)
fca1aef2	127	{
63cb0298	128	evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
63cb0298	129	MTC0(reg, val);
28bc5688	130	}
28bc5688	131
52082bc1	132	void new_dyna_save(void)
	133	{
	134	// psxRegs.intCycle is always maintained, no need to convert
	135	}
	136
	137	void new_dyna_restore(void)
	138	{
	139	int i;
9f8b032d	140	for (i = 0; i < PSXINT_COUNT; i++)
52082bc1	141	event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
	142	}
	143
b9b61529	144	void *gte_handlers[64];
b9b61529	145
59774ed0	146	void *gte_handlers_nf[64] = {
	147	NULL , gteRTPS_nf , NULL , NULL , NULL , NULL , gteNCLIP_nf, NULL , // 00
	148	NULL , NULL , NULL , NULL , gteOP_nf , NULL , NULL , NULL , // 08
	149	gteDPCS_nf, gteINTPL_nf, gteMVMVA_nf, gteNCDS_nf, gteCDP_nf, NULL , gteNCDT_nf , NULL , // 10
	150	NULL , NULL , NULL , gteNCCS_nf, gteCC_nf , NULL , gteNCS_nf , NULL , // 18
	151	gteNCT_nf , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
	152	gteSQR_nf , gteDCPL_nf , gteDPCT_nf , NULL , NULL , gteAVSZ3_nf, gteAVSZ4_nf, NULL , // 28
	153	gteRTPT_nf, NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
	154	NULL , NULL , NULL , NULL , NULL , gteGPF_nf , gteGPL_nf , gteNCCT_nf, // 38
	155	};
	156
bedfea38	157	const char *gte_regnames[64] = {
	158	NULL , "RTPS" , NULL , NULL , NULL , NULL , "NCLIP", NULL , // 00
	159	NULL , NULL , NULL , NULL , "OP" , NULL , NULL , NULL , // 08
	160	"DPCS", "INTPL", "MVMVA", "NCDS", "CDP", NULL , "NCDT" , NULL , // 10
	161	NULL , NULL , NULL , "NCCS", "CC" , NULL , "NCS" , NULL , // 18
	162	"NCT" , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
	163	"SQR" , "DCPL" , "DPCT" , NULL , NULL , "AVSZ3", "AVSZ4", NULL , // 28
	164	"RTPT", NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
	165	NULL , NULL , NULL , NULL , NULL , "GPF" , "GPL" , "NCCT", // 38
	166	};
	167
b9b61529	168	/* from gte.txt.. not sure if this is any good. */
	169	const char gte_cycletab[64] = {
	170	/* 1 2 3 4 5 6 7 8 9 a b c d e f */
	171	0, 15, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 6, 0, 0, 0,
	172	8, 8, 8, 19, 13, 0, 44, 0, 0, 0, 0, 17, 11, 0, 14, 0,
	173	30, 0, 0, 0, 0, 0, 0, 0, 5, 8, 17, 0, 0, 5, 6, 0,
	174	23, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 39,
	175	};
f95a77f7	176
	177	static int ari64_init()
	178	{
b9b61529	179	extern void (*psxCP2[64])();
b9b61529	180	extern void psxNULL();
f95a77f7	181	size_t i;
b9b61529	182
f95a77f7	183	new_dynarec_init();
7e605697	184	new_dyna_pcsx_mem_init();
7139f3c8	185
ae602c19	186	for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
b9b61529	187	if (psxCP2[i] != psxNULL)
b9b61529	188	gte_handlers[i] = psxCP2[i];
59774ed0	189
	190	#if !defined(DRC_DBG) && !defined(PCNT)
	191	#ifdef __arm__
	192	gte_handlers[0x06] = gteNCLIP_arm;
0c2ca3ba	193	gte_handlers_nf[0x01] = gteRTPS_nf_arm;
0c2ca3ba	194	gte_handlers_nf[0x30] = gteRTPT_nf_arm;
59774ed0	195	#endif
a80ae4a0	196	#ifdef __ARM_NEON__
59774ed0	197	// compiler's _nf version is still a lot slower then neon
0c2ca3ba	198	// _nf_arm RTPS is roughly the same, RTPT slower
59774ed0	199	gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
	200	gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
	201	gte_handlers[0x12] = gte_handlers_nf[0x12] = gteMVMVA_neon;
a80ae4a0	202	#endif
d3f3bf09	203	#endif
	204	#ifdef DRC_DBG
	205	memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
009faf24	206	#endif
7e605697	207	psxH_ptr = psxH;
7e605697	208
b9b61529	209	return 0;
f95a77f7	210	}
	211
	212	static void ari64_reset()
	213	{
f95a77f7	214	printf("ari64_reset\n");
7e605697	215	new_dyna_pcsx_mem_reset();
4b421010	216	invalidate_all_pages();
7f457614	217	new_dyna_restore();
4b421010	218	pending_exception = 1;
f95a77f7	219	}
f95a77f7	220
e4eb18c1	221	// execute until predefined leave points
	222	// (HLE softcall exit and BIOS fastboot end)
	223	static void ari64_execute_until()
f95a77f7	224	{
654e8cfb	225	schedule_timeslice();
	226
	227	evprintf("ari64_execute %08x, %u->%u (%d)\n", psxRegs.pc,
	228	psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
7139f3c8	229
b9b61529	230	new_dyna_start();
654e8cfb	231
	232	evprintf("ari64_execute end %08x, %u->%u (%d)\n", psxRegs.pc,
	233	psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
f95a77f7	234	}
f95a77f7	235
e4eb18c1	236	static void ari64_execute()
	237	{
	238	while (!stop) {
	239	ari64_execute_until();
	240	evprintf("drc left @%08x\n", psxRegs.pc);
	241	}
	242	}
	243
4b421010	244	static void ari64_clear(u32 addr, u32 size)
f95a77f7	245	{
0ce47d46	246	u32 start, end, main_ram;
4b421010	247
76739a08	248	size = 4; / PCSX uses DMA units */
76739a08	249
4b421010	250	evprintf("ari64_clear %08x %04x\n", addr, size);
	251
	252	/* check for RAM mirrors */
0ce47d46	253	main_ram = (addr & 0xffe00000) == 0x80000000;
4b421010	254
	255	start = addr >> 12;
	256	end = (addr + size) >> 12;
	257
	258	for (; start <= end; start++)
0ce47d46	259	if (!main_ram \|\| !invalid_code[start])
4b421010	260	invalidate_block(start);
f95a77f7	261	}
	262
	263	static void ari64_shutdown()
	264	{
	265	new_dynarec_cleanup();
	266	}
	267
7139f3c8	268	extern void intExecute();
	269	extern void intExecuteT();
	270	extern void intExecuteBlock();
	271	extern void intExecuteBlockT();
	272	#ifndef DRC_DBG
	273	#define intExecuteT intExecute
	274	#define intExecuteBlockT intExecuteBlock
	275	#endif
	276
f95a77f7	277	R3000Acpu psxRec = {
	278	ari64_init,
	279	ari64_reset,
2185e39b	280	#if defined(__arm__)
f95a77f7	281	ari64_execute,
e4eb18c1	282	ari64_execute_until,
7139f3c8	283	#else
	284	intExecuteT,
	285	intExecuteBlockT,
	286	#endif
f95a77f7	287	ari64_clear,
	288	ari64_shutdown
	289	};
7139f3c8	290
	291	// TODO: rm
	292	#ifndef DRC_DBG
	293	void do_insn_trace() {}
	294	void do_insn_cmp() {}
	295	#endif
	296
	297	#if defined(__x86_64__) \|\| defined(__i386__)
	298	unsigned int address, readmem_word, word;
	299	unsigned short hword;
	300	unsigned char byte;
ccf51908	301	int pending_exception, stop;
7139f3c8	302	unsigned int next_interupt;
2f546f9a	303	int new_dynarec_did_compile;
2573466a	304	int cycle_multiplier;
7e605697	305	void *psxH_ptr;
7139f3c8	306	void new_dynarec_init() {}
3eb78778	307	void new_dyna_start() {}
7139f3c8	308	void new_dynarec_cleanup() {}
2c886904	309	void new_dynarec_clear_full() {}
ccf51908	310	void invalidate_all_pages() {}
ccf51908	311	void invalidate_block(unsigned int block) {}
7e605697	312	void new_dyna_pcsx_mem_init(void) {}
7e605697	313	void new_dyna_pcsx_mem_reset(void) {}
7139f3c8	314	#endif
	315
	316	#ifdef DRC_DBG
	317
	318	#include <stddef.h>
	319	static FILE *f;
	320	extern u32 last_io_addr;
	321
	322	static void dump_mem(const char fname, void mem, size_t size)
	323	{
	324	FILE *f1 = fopen(fname, "wb");
3eb78778	325	if (f1 == NULL)
3eb78778	326	f1 = fopen(strrchr(fname, '/') + 1, "wb");
7139f3c8	327	fwrite(mem, 1, size, f1);
	328	fclose(f1);
	329	}
	330
2185e39b	331	static u32 memcheck_read(u32 a)
	332	{
	333	if ((a >> 16) == 0x1f80)
	334	// scratchpad/IO
	335	return (u32 )(psxH + (a & 0xfffc));
	336
	337	if ((a >> 16) == 0x1f00)
	338	// parallel
	339	return (u32 )(psxP + (a & 0xfffc));
	340
	341	// if ((a & ~0xe0600000) < 0x200000)
	342	// RAM
	343	return (u32 )(psxM + (a & 0x1ffffc));
	344	}
	345
7139f3c8	346	void do_insn_trace(void)
	347	{
	348	static psxRegisters oldregs;
	349	static u32 old_io_addr = (u32)-1;
	350	static u32 old_io_data = 0xbad0c0de;
	351	u32 allregs_p = (void )&psxRegs;
	352	u32 allregs_o = (void )&oldregs;
2185e39b	353	u32 io_data;
7139f3c8	354	int i;
	355	u8 byte;
	356
	357	//last_io_addr = 0x5e2c8;
	358	if (f == NULL)
	359	f = fopen("tracelog", "wb");
	360
	361	oldregs.code = psxRegs.code; // don't care
	362	for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
	363	if (allregs_p[i] != allregs_o[i]) {
	364	fwrite(&i, 1, 1, f);
	365	fwrite(&allregs_p[i], 1, 4, f);
	366	allregs_o[i] = allregs_p[i];
	367	}
	368	}
	369	if (old_io_addr != last_io_addr) {
	370	byte = 0xfd;
	371	fwrite(&byte, 1, 1, f);
	372	fwrite(&last_io_addr, 1, 4, f);
	373	old_io_addr = last_io_addr;
	374	}
2185e39b	375	io_data = memcheck_read(last_io_addr);
2185e39b	376	if (old_io_data != io_data) {
7139f3c8	377	byte = 0xfe;
7139f3c8	378	fwrite(&byte, 1, 1, f);
2185e39b	379	fwrite(&io_data, 1, 4, f);
2185e39b	380	old_io_data = io_data;
7139f3c8	381	}
	382	byte = 0xff;
	383	fwrite(&byte, 1, 1, f);
	384
	385	#if 0
	386	if (psxRegs.cycle == 190230) {
	387	dump_mem("/mnt/ntz/dev/pnd/tmp/psxram_i.dump", psxM, 0x200000);
	388	dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs_i.dump", psxH, 0x10000);
	389	printf("dumped\n");
	390	exit(1);
	391	}
	392	#endif
	393	}
	394
	395	static const char *regnames[offsetof(psxRegisters, intCycle) / 4] = {
	396	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	397	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
	398	"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
	399	"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
	400	"lo", "hi",
	401	"C0_0", "C0_1", "C0_2", "C0_3", "C0_4", "C0_5", "C0_6", "C0_7",
	402	"C0_8", "C0_9", "C0_10", "C0_11", "C0_12", "C0_13", "C0_14", "C0_15",
	403	"C0_16", "C0_17", "C0_18", "C0_19", "C0_20", "C0_21", "C0_22", "C0_23",
	404	"C0_24", "C0_25", "C0_26", "C0_27", "C0_28", "C0_29", "C0_30", "C0_31",
	405
	406	"C2D0", "C2D1", "C2D2", "C2D3", "C2D4", "C2D5", "C2D6", "C2D7",
	407	"C2D8", "C2D9", "C2D10", "C2D11", "C2D12", "C2D13", "C2D14", "C2D15",
	408	"C2D16", "C2D17", "C2D18", "C2D19", "C2D20", "C2D21", "C2D22", "C2D23",
	409	"C2D24", "C2D25", "C2D26", "C2D27", "C2D28", "C2D29", "C2D30", "C2D31",
	410
	411	"C2C0", "C2C1", "C2C2", "C2C3", "C2C4", "C2C5", "C2C6", "C2C7",
	412	"C2C8", "C2C9", "C2C10", "C2C11", "C2C12", "C2C13", "C2C14", "C2C15",
	413	"C2C16", "C2C17", "C2C18", "C2C19", "C2C20", "C2C21", "C2C22", "C2C23",
	414	"C2C24", "C2C25", "C2C26", "C2C27", "C2C28", "C2C29", "C2C30", "C2C31",
	415
	416	"PC", "code", "cycle", "interrupt",
	417	};
	418
3eb78778	419	static struct {
	420	int reg;
	421	u32 val, val_expect;
	422	u32 pc, cycle;
	423	} miss_log[64];
	424	static int miss_log_i;
	425	#define miss_log_len (sizeof(miss_log)/sizeof(miss_log[0]))
	426	#define miss_log_mask (miss_log_len-1)
	427
	428	static void miss_log_add(int reg, u32 val, u32 val_expect, u32 pc, u32 cycle)
	429	{
	430	miss_log[miss_log_i].reg = reg;
	431	miss_log[miss_log_i].val = val;
	432	miss_log[miss_log_i].val_expect = val_expect;
	433	miss_log[miss_log_i].pc = pc;
	434	miss_log[miss_log_i].cycle = cycle;
	435	miss_log_i = (miss_log_i + 1) & miss_log_mask;
	436	}
	437
7139f3c8	438	void breakme() {}
	439
	440	void do_insn_cmp(void)
	441	{
	442	static psxRegisters rregs;
	443	static u32 mem_addr, mem_val;
	444	u32 allregs_p = (void )&psxRegs;
	445	u32 allregs_e = (void )&rregs;
	446	static u32 ppc, failcount;
	447	int i, ret, bad = 0;
	448	u8 code;
	449
	450	if (f == NULL)
	451	f = fopen("tracelog", "rb");
	452
	453	while (1) {
	454	if ((ret = fread(&code, 1, 1, f)) <= 0)
	455	break;
	456	if (ret <= 0)
	457	break;
	458	if (code == 0xff)
	459	break;
	460	if (code == 0xfd) {
	461	if ((ret = fread(&mem_addr, 1, 4, f)) <= 0)
	462	break;
	463	continue;
	464	}
	465	if (code == 0xfe) {
	466	if ((ret = fread(&mem_val, 1, 4, f)) <= 0)
	467	break;
	468	continue;
	469	}
	470	if ((ret = fread(&allregs_e[code], 1, 4, f)) <= 0)
	471	break;
	472	}
	473
	474	if (ret <= 0) {
	475	printf("EOF?\n");
	476	goto end;
	477	}
	478
	479	psxRegs.code = rregs.code; // don't care
2185e39b	480	psxRegs.cycle = rregs.cycle;
2185e39b	481	psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count
7139f3c8	482
7139f3c8	483	//if (psxRegs.cycle == 166172) breakme();
7139f3c8	484
7139f3c8	485	if (memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle)) == 0 &&
2185e39b	486	mem_val == memcheck_read(mem_addr)
7139f3c8	487	) {
	488	failcount = 0;
	489	goto ok;
	490	}
	491
	492	for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
	493	if (allregs_p[i] != allregs_e[i]) {
3eb78778	494	miss_log_add(i, allregs_p[i], allregs_e[i], psxRegs.pc, psxRegs.cycle);
7139f3c8	495	bad++;
	496	}
	497	}
	498
2185e39b	499	if (mem_val != memcheck_read(mem_addr)) {
2185e39b	500	printf("bad mem @%08x: %08x %08x\n", mem_addr, memcheck_read(mem_addr), mem_val);
7139f3c8	501	goto end;
	502	}
	503
	504	if (psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) {
3eb78778	505	static int last_mcycle;
	506	if (last_mcycle != psxRegs.cycle >> 20) {
	507	printf("%u\n", psxRegs.cycle);
	508	last_mcycle = psxRegs.cycle >> 20;
	509	}
7139f3c8	510	failcount++;
	511	goto ok;
	512	}
	513
	514	end:
3eb78778	515	for (i = 0; i < miss_log_len; i++, miss_log_i = (miss_log_i + 1) & miss_log_mask)
	516	printf("bad %5s: %08x %08x, pc=%08x, cycle %u\n",
	517	regnames[miss_log[miss_log_i].reg], miss_log[miss_log_i].val,
	518	miss_log[miss_log_i].val_expect, miss_log[miss_log_i].pc, miss_log[miss_log_i].cycle);
	519	printf("-- %d\n", bad);
	520	for (i = 0; i < 8; i++)
	521	printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
87c06e51	522	i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
7139f3c8	523	printf("PC: %08x/%08x, cycle %u\n", psxRegs.pc, ppc, psxRegs.cycle);
	524	dump_mem("/mnt/ntz/dev/pnd/tmp/psxram.dump", psxM, 0x200000);
	525	dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);
	526	exit(1);
	527	ok:
	528	psxRegs.cycle = rregs.cycle + 2; // sync timing
	529	ppc = psxRegs.pc;
	530	}
	531
	532	#endif