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remove all the hack options
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.c
CommitLineData
7e605697 1/*
009faf24 2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
7e605697 3 *
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
6 */
7
f95a77f7 8#include <stdio.h>
9
10#include "emu_if.h"
7e605697 11#include "pcsxmem.h"
7139f3c8 12#include "../psxhle.h"
61ad2a61 13#include "../psxinterpreter.h"
d28b54b1 14#include "../r3000a.h"
52082bc1 15#include "../cdrom.h"
16#include "../psxdma.h"
17#include "../mdec.h"
59774ed0 18#include "../gte_arm.h"
009faf24 19#include "../gte_neon.h"
59774ed0 20#define FLAGLESS
21#include "../gte.h"
7139f3c8 22
ae602c19 23#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
24
7139f3c8 25//#define evprintf printf
26#define evprintf(...)
27
f95a77f7 28char invalid_code[0x100000];
d28b54b1 29u32 event_cycles[PSXINT_COUNT];
f95a77f7 30
654e8cfb 31static void schedule_timeslice(void)
f95a77f7 32{
654e8cfb 33 u32 i, c = psxRegs.cycle;
5b8c000f 34 u32 irqs = psxRegs.interrupt;
654e8cfb 35 s32 min, dif;
36
5b8c000f 37 min = PSXCLK;
38 for (i = 0; irqs != 0; i++, irqs >>= 1) {
39 if (!(irqs & 1))
40 continue;
654e8cfb 41 dif = event_cycles[i] - c;
42 //evprintf(" ev %d\n", dif);
43 if (0 < dif && dif < min)
44 min = dif;
45 }
46 next_interupt = c + min;
654e8cfb 47}
ae602c19 48
d9a02493 49static void unusedInterrupt()
50{
51}
52
52082bc1 53typedef void (irq_func)();
54
55static irq_func * const irq_funcs[] = {
56 [PSXINT_SIO] = sioInterrupt,
57 [PSXINT_CDR] = cdrInterrupt,
480e570b 58 [PSXINT_CDREAD] = cdrPlayReadInterrupt,
52082bc1 59 [PSXINT_GPUDMA] = gpuInterrupt,
60 [PSXINT_MDECOUTDMA] = mdec1Interrupt,
61 [PSXINT_SPUDMA] = spuInterrupt,
528ad661 62 [PSXINT_MDECINDMA] = mdec0Interrupt,
57a757ce 63 [PSXINT_GPUOTCDMA] = gpuotcInterrupt,
9f8b032d 64 [PSXINT_CDRDMA] = cdrDmaInterrupt,
65 [PSXINT_CDRLID] = cdrLidSeekInterrupt,
d9a02493 66 [PSXINT_CDRPLAY_OLD] = unusedInterrupt,
2b30c129 67 [PSXINT_SPU_UPDATE] = spuUpdate,
5b8c000f 68 [PSXINT_RCNT] = psxRcntUpdate,
52082bc1 69};
70
71/* local dupe of psxBranchTest, using event_cycles */
72static void irq_test(void)
73{
52082bc1 74 u32 cycle = psxRegs.cycle;
75 u32 irq, irq_bits;
76
079ab0c6 77 for (irq = 0, irq_bits = psxRegs.interrupt; irq_bits != 0; irq++, irq_bits >>= 1) {
52082bc1 78 if (!(irq_bits & 1))
79 continue;
80 if ((s32)(cycle - event_cycles[irq]) >= 0) {
079ab0c6 81 // note: irq_funcs() also modify psxRegs.interrupt
82 psxRegs.interrupt &= ~(1u << irq);
52082bc1 83 irq_funcs[irq]();
84 }
85 }
52082bc1 86
87 if ((psxHu32(0x1070) & psxHu32(0x1074)) && (Status & 0x401) == 0x401) {
88 psxException(0x400, 0);
89 pending_exception = 1;
90 }
91}
92
654e8cfb 93void gen_interupt()
94{
55a695d9 95 evprintf(" +ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
96 next_interupt, next_interupt - psxRegs.cycle);
7139f3c8 97
52082bc1 98 irq_test();
99 //psxBranchTest();
100 //pending_exception = 1;
7139f3c8 101
654e8cfb 102 schedule_timeslice();
ae602c19 103
654e8cfb 104 evprintf(" -ge %08x, %u->%u (%d)\n", psxRegs.pc, psxRegs.cycle,
105 next_interupt, next_interupt - psxRegs.cycle);
f95a77f7 106}
107
63cb0298 108void pcsx_mtc0(u32 reg, u32 val)
28bc5688 109{
63cb0298 110 evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
4cc373dd 111 MTC0(&psxRegs, reg, val);
fca1aef2 112 gen_interupt();
15d0ba02 113 if (Cause & Status & 0x0300) // possible sw irq
114 pending_exception = 1;
fca1aef2 115}
28bc5688 116
63cb0298 117void pcsx_mtc0_ds(u32 reg, u32 val)
fca1aef2 118{
63cb0298 119 evprintf("MTC0 %d #%x @%08x %u\n", reg, val, psxRegs.pc, psxRegs.cycle);
4cc373dd 120 MTC0(&psxRegs, reg, val);
28bc5688 121}
122
03f55e6b 123void new_dyna_before_save(void)
52082bc1 124{
5b8c000f 125 psxRegs.interrupt &= ~(1 << PSXINT_RCNT); // old savestate compat
126
52082bc1 127 // psxRegs.intCycle is always maintained, no need to convert
128}
129
5b8c000f 130void new_dyna_after_save(void)
131{
132 psxRegs.interrupt |= 1 << PSXINT_RCNT;
133}
134
03f55e6b 135static void new_dyna_restore(void)
52082bc1 136{
137 int i;
9f8b032d 138 for (i = 0; i < PSXINT_COUNT; i++)
52082bc1 139 event_cycles[i] = psxRegs.intCycle[i].sCycle + psxRegs.intCycle[i].cycle;
b1be1eee 140
5b8c000f 141 event_cycles[PSXINT_RCNT] = psxNextsCounter + psxNextCounter;
142 psxRegs.interrupt |= 1 << PSXINT_RCNT;
143 psxRegs.interrupt &= (1 << PSXINT_COUNT) - 1;
144
b1be1eee 145 new_dyna_pcsx_mem_load_state();
52082bc1 146}
147
03f55e6b 148void new_dyna_freeze(void *f, int mode)
149{
150 const char header_save[8] = "ariblks";
151 uint32_t addrs[1024 * 4];
152 int32_t size = 0;
153 int bytes;
154 char header[8];
155
156 if (mode != 0) { // save
157 size = new_dynarec_save_blocks(addrs, sizeof(addrs));
158 if (size == 0)
159 return;
160
161 SaveFuncs.write(f, header_save, sizeof(header_save));
162 SaveFuncs.write(f, &size, sizeof(size));
163 SaveFuncs.write(f, addrs, size);
164 }
165 else {
166 new_dyna_restore();
167
168 bytes = SaveFuncs.read(f, header, sizeof(header));
169 if (bytes != sizeof(header) || strcmp(header, header_save)) {
170 if (bytes > 0)
171 SaveFuncs.seek(f, -bytes, SEEK_CUR);
172 return;
173 }
174 SaveFuncs.read(f, &size, sizeof(size));
175 if (size <= 0)
176 return;
177 if (size > sizeof(addrs)) {
178 bytes = size - sizeof(addrs);
179 SaveFuncs.seek(f, bytes, SEEK_CUR);
180 size = sizeof(addrs);
181 }
182 bytes = SaveFuncs.read(f, addrs, size);
183 if (bytes != size)
184 return;
185
2d3c4d02 186 if (psxCpu != &psxInt)
187 new_dynarec_load_blocks(addrs, size);
03f55e6b 188 }
189
190 //printf("drc: %d block info entries %s\n", size/8, mode ? "saved" : "loaded");
191}
192
d6348639 193#ifndef DRC_DISABLE
194
2167bef6 195/* GTE stuff */
b9b61529 196void *gte_handlers[64];
197
59774ed0 198void *gte_handlers_nf[64] = {
199 NULL , gteRTPS_nf , NULL , NULL , NULL , NULL , gteNCLIP_nf, NULL , // 00
200 NULL , NULL , NULL , NULL , gteOP_nf , NULL , NULL , NULL , // 08
201 gteDPCS_nf, gteINTPL_nf, gteMVMVA_nf, gteNCDS_nf, gteCDP_nf, NULL , gteNCDT_nf , NULL , // 10
202 NULL , NULL , NULL , gteNCCS_nf, gteCC_nf , NULL , gteNCS_nf , NULL , // 18
203 gteNCT_nf , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
204 gteSQR_nf , gteDCPL_nf , gteDPCT_nf , NULL , NULL , gteAVSZ3_nf, gteAVSZ4_nf, NULL , // 28
205 gteRTPT_nf, NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
206 NULL , NULL , NULL , NULL , NULL , gteGPF_nf , gteGPL_nf , gteNCCT_nf, // 38
207};
208
bedfea38 209const char *gte_regnames[64] = {
210 NULL , "RTPS" , NULL , NULL , NULL , NULL , "NCLIP", NULL , // 00
211 NULL , NULL , NULL , NULL , "OP" , NULL , NULL , NULL , // 08
212 "DPCS", "INTPL", "MVMVA", "NCDS", "CDP", NULL , "NCDT" , NULL , // 10
213 NULL , NULL , NULL , "NCCS", "CC" , NULL , "NCS" , NULL , // 18
214 "NCT" , NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 20
215 "SQR" , "DCPL" , "DPCT" , NULL , NULL , "AVSZ3", "AVSZ4", NULL , // 28
216 "RTPT", NULL , NULL , NULL , NULL , NULL , NULL , NULL , // 30
217 NULL , NULL , NULL , NULL , NULL , "GPF" , "GPL" , "NCCT", // 38
218};
219
2167bef6 220#define GCBIT(x) \
221 (1ll << (32+x))
222#define GDBIT(x) \
223 (1ll << (x))
224#define GCBITS3(b0,b1,b2) \
225 (GCBIT(b0) | GCBIT(b1) | GCBIT(b2))
226#define GDBITS2(b0,b1) \
227 (GDBIT(b0) | GDBIT(b1))
228#define GDBITS3(b0,b1,b2) \
229 (GDBITS2(b0,b1) | GDBIT(b2))
230#define GDBITS4(b0,b1,b2,b3) \
231 (GDBITS3(b0,b1,b2) | GDBIT(b3))
232#define GDBITS5(b0,b1,b2,b3,b4) \
233 (GDBITS4(b0,b1,b2,b3) | GDBIT(b4))
234#define GDBITS6(b0,b1,b2,b3,b4,b5) \
235 (GDBITS5(b0,b1,b2,b3,b4) | GDBIT(b5))
236#define GDBITS7(b0,b1,b2,b3,b4,b5,b6) \
237 (GDBITS6(b0,b1,b2,b3,b4,b5) | GDBIT(b6))
238#define GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) \
239 (GDBITS7(b0,b1,b2,b3,b4,b5,b6) | GDBIT(b7))
240#define GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) \
241 (GDBITS8(b0,b1,b2,b3,b4,b5,b6,b7) | GDBIT(b8))
242#define GDBITS10(b0,b1,b2,b3,b4,b5,b6,b7,b8,b9) \
243 (GDBITS9(b0,b1,b2,b3,b4,b5,b6,b7,b8) | GDBIT(b9))
244
245const uint64_t gte_reg_reads[64] = {
246 [GTE_RTPS] = 0x1f0000ff00000000ll | GDBITS7(0,1,13,14,17,18,19),
247 [GTE_NCLIP] = GDBITS3(12,13,14),
248 [GTE_OP] = GCBITS3(0,2,4) | GDBITS3(9,10,11),
249 [GTE_DPCS] = GCBITS3(21,22,23) | GDBITS4(6,8,21,22),
250 [GTE_INTPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
db481db4 251 [GTE_MVMVA] = 0x00ffffff00000000ll | GDBITS9(0,1,2,3,4,5,9,10,11), // XXX: maybe decode further?
252 [GTE_NCDS] = 0x00ffff0000000000ll | GDBITS6(0,1,6,8,21,22),
253 [GTE_CDP] = 0x00ffe00000000000ll | GDBITS7(6,8,9,10,11,21,22),
2167bef6 254 [GTE_NCDT] = 0x00ffff0000000000ll | GDBITS8(0,1,2,3,4,5,6,8),
db481db4 255 [GTE_NCCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
2167bef6 256 [GTE_CC] = 0x001fe00000000000ll | GDBITS6(6,9,10,11,21,22),
db481db4 257 [GTE_NCS] = 0x001fff0000000000ll | GDBITS5(0,1,6,21,22),
2167bef6 258 [GTE_NCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
259 [GTE_SQR] = GDBITS3(9,10,11),
260 [GTE_DCPL] = GCBITS3(21,22,23) | GDBITS7(6,8,9,10,11,21,22),
261 [GTE_DPCT] = GCBITS3(21,22,23) | GDBITS4(8,20,21,22),
262 [GTE_AVSZ3] = GCBIT(29) | GDBITS3(17,18,19),
263 [GTE_AVSZ4] = GCBIT(30) | GDBITS4(16,17,18,19),
264 [GTE_RTPT] = 0x1f0000ff00000000ll | GDBITS7(0,1,2,3,4,5,19),
265 [GTE_GPF] = GDBITS7(6,8,9,10,11,21,22),
266 [GTE_GPL] = GDBITS10(6,8,9,10,11,21,22,25,26,27),
267 [GTE_NCCT] = 0x001fff0000000000ll | GDBITS7(0,1,2,3,4,5,6),
268};
269
270// note: this excludes gteFLAG that is always written to
271const uint64_t gte_reg_writes[64] = {
272 [GTE_RTPS] = 0x0f0f7f00ll,
273 [GTE_NCLIP] = GDBIT(24),
274 [GTE_OP] = GDBITS6(9,10,11,25,26,27),
275 [GTE_DPCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
276 [GTE_INTPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
277 [GTE_MVMVA] = GDBITS6(9,10,11,25,26,27),
278 [GTE_NCDS] = GDBITS9(9,10,11,20,21,22,25,26,27),
279 [GTE_CDP] = GDBITS9(9,10,11,20,21,22,25,26,27),
280 [GTE_NCDT] = GDBITS9(9,10,11,20,21,22,25,26,27),
281 [GTE_NCCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
282 [GTE_CC] = GDBITS9(9,10,11,20,21,22,25,26,27),
283 [GTE_NCS] = GDBITS9(9,10,11,20,21,22,25,26,27),
284 [GTE_NCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
285 [GTE_SQR] = GDBITS6(9,10,11,25,26,27),
286 [GTE_DCPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
287 [GTE_DPCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
288 [GTE_AVSZ3] = GDBITS2(7,24),
289 [GTE_AVSZ4] = GDBITS2(7,24),
290 [GTE_RTPT] = 0x0f0f7f00ll,
291 [GTE_GPF] = GDBITS9(9,10,11,20,21,22,25,26,27),
292 [GTE_GPL] = GDBITS9(9,10,11,20,21,22,25,26,27),
293 [GTE_NCCT] = GDBITS9(9,10,11,20,21,22,25,26,27),
294};
295
f95a77f7 296static int ari64_init()
297{
d6348639 298 static u32 scratch_buf[8*8*2] __attribute__((aligned(64)));
f95a77f7 299 size_t i;
b9b61529 300
f95a77f7 301 new_dynarec_init();
7e605697 302 new_dyna_pcsx_mem_init();
7139f3c8 303
ae602c19 304 for (i = 0; i < ARRAY_SIZE(gte_handlers); i++)
4cc373dd 305 if (psxCP2[i] != gteNULL)
b9b61529 306 gte_handlers[i] = psxCP2[i];
59774ed0 307
665f33e1 308#if defined(__arm__) && !defined(DRC_DBG)
59774ed0 309 gte_handlers[0x06] = gteNCLIP_arm;
665f33e1 310#ifdef HAVE_ARMV5
0c2ca3ba 311 gte_handlers_nf[0x01] = gteRTPS_nf_arm;
312 gte_handlers_nf[0x30] = gteRTPT_nf_arm;
59774ed0 313#endif
a80ae4a0 314#ifdef __ARM_NEON__
054175e9 315 // compiler's _nf version is still a lot slower than neon
0c2ca3ba 316 // _nf_arm RTPS is roughly the same, RTPT slower
59774ed0 317 gte_handlers[0x01] = gte_handlers_nf[0x01] = gteRTPS_neon;
318 gte_handlers[0x30] = gte_handlers_nf[0x30] = gteRTPT_neon;
a80ae4a0 319#endif
d3f3bf09 320#endif
321#ifdef DRC_DBG
322 memcpy(gte_handlers_nf, gte_handlers, sizeof(gte_handlers_nf));
009faf24 323#endif
7e605697 324 psxH_ptr = psxH;
054175e9 325 zeromem_ptr = zero_mem;
c6d5790c 326 scratch_buf_ptr = scratch_buf;
7e605697 327
b9b61529 328 return 0;
f95a77f7 329}
330
331static void ari64_reset()
332{
f95a77f7 333 printf("ari64_reset\n");
7e605697 334 new_dyna_pcsx_mem_reset();
104df9d3 335 new_dynarec_invalidate_all_pages();
7f457614 336 new_dyna_restore();
4b421010 337 pending_exception = 1;
f95a77f7 338}
339
e4eb18c1 340// execute until predefined leave points
341// (HLE softcall exit and BIOS fastboot end)
342static void ari64_execute_until()
f95a77f7 343{
654e8cfb 344 schedule_timeslice();
345
346 evprintf("ari64_execute %08x, %u->%u (%d)\n", psxRegs.pc,
347 psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
7139f3c8 348
be516ebe 349 new_dyna_start(dynarec_local);
654e8cfb 350
351 evprintf("ari64_execute end %08x, %u->%u (%d)\n", psxRegs.pc,
352 psxRegs.cycle, next_interupt, next_interupt - psxRegs.cycle);
f95a77f7 353}
354
e4eb18c1 355static void ari64_execute()
356{
357 while (!stop) {
358 ari64_execute_until();
359 evprintf("drc left @%08x\n", psxRegs.pc);
360 }
361}
362
4b421010 363static void ari64_clear(u32 addr, u32 size)
f95a77f7 364{
58ebb94c 365 size *= 4; /* PCSX uses DMA units (words) */
76739a08 366
4b421010 367 evprintf("ari64_clear %08x %04x\n", addr, size);
368
104df9d3 369 new_dynarec_invalidate_range(addr, addr + size);
f95a77f7 370}
371
943a507a 372static void ari64_notify(int note, void *data) {
373 /*
374 Should be fixed when ARM dynarec has proper icache emulation.
375 switch (note)
376 {
377 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
378 break;
379 case R3000ACPU_NOTIFY_CACHE_ISOLATED:
380 Sent from psxDma3().
381 case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
382 default:
383 break;
384 }
385 */
386}
943a507a 387
32631e6a 388static void ari64_apply_config()
389{
61ad2a61 390 intApplyConfig();
391
32631e6a 392 if (Config.DisableStalls)
393 new_dynarec_hacks |= NDHACK_NO_STALLS;
394 else
395 new_dynarec_hacks &= ~NDHACK_NO_STALLS;
396
397 if (cycle_multiplier != cycle_multiplier_old
398 || new_dynarec_hacks != new_dynarec_hacks_old)
399 {
400 new_dynarec_clear_full();
401 }
402}
403
f95a77f7 404static void ari64_shutdown()
405{
406 new_dynarec_cleanup();
92879b62 407 new_dyna_pcsx_mem_shutdown();
f95a77f7 408}
409
410R3000Acpu psxRec = {
411 ari64_init,
412 ari64_reset,
413 ari64_execute,
e4eb18c1 414 ari64_execute_until,
f95a77f7 415 ari64_clear,
943a507a 416 ari64_notify,
32631e6a 417 ari64_apply_config,
f95a77f7 418 ari64_shutdown
419};
7139f3c8 420
d6348639 421#else // if DRC_DISABLE
7139f3c8 422
054175e9 423unsigned int address;
ccf51908 424int pending_exception, stop;
7139f3c8 425unsigned int next_interupt;
2f546f9a 426int new_dynarec_did_compile;
2573466a 427int cycle_multiplier;
17ce04cc 428int cycle_multiplier_override;
32631e6a 429int cycle_multiplier_old;
d62c125a 430int new_dynarec_hacks_pergame;
32631e6a 431int new_dynarec_hacks_old;
0ff8c62c 432int new_dynarec_hacks;
7e605697 433void *psxH_ptr;
054175e9 434void *zeromem_ptr;
435u8 zero_mem[0x1000];
0069615f 436void *mem_rtab;
c6d5790c 437void *scratch_buf_ptr;
d6348639 438void new_dynarec_init() {}
be516ebe 439void new_dyna_start(void *context) {}
7139f3c8 440void new_dynarec_cleanup() {}
2c886904 441void new_dynarec_clear_full() {}
104df9d3 442void new_dynarec_invalidate_all_pages() {}
c8e482ed 443void new_dynarec_invalidate_range(unsigned int start, unsigned int end) {}
7e605697 444void new_dyna_pcsx_mem_init(void) {}
445void new_dyna_pcsx_mem_reset(void) {}
b1be1eee 446void new_dyna_pcsx_mem_load_state(void) {}
92879b62 447void new_dyna_pcsx_mem_shutdown(void) {}
03f55e6b 448int new_dynarec_save_blocks(void *save, int size) { return 0; }
449void new_dynarec_load_blocks(const void *save, int size) {}
7139f3c8 450#endif
451
452#ifdef DRC_DBG
453
454#include <stddef.h>
455static FILE *f;
2330734f 456u32 irq_test_cycle;
457u32 handler_cycle;
458u32 last_io_addr;
7139f3c8 459
079ab0c6 460void dump_mem(const char *fname, void *mem, size_t size)
7139f3c8 461{
462 FILE *f1 = fopen(fname, "wb");
3eb78778 463 if (f1 == NULL)
464 f1 = fopen(strrchr(fname, '/') + 1, "wb");
7139f3c8 465 fwrite(mem, 1, size, f1);
466 fclose(f1);
467}
468
2185e39b 469static u32 memcheck_read(u32 a)
470{
471 if ((a >> 16) == 0x1f80)
472 // scratchpad/IO
473 return *(u32 *)(psxH + (a & 0xfffc));
474
475 if ((a >> 16) == 0x1f00)
476 // parallel
477 return *(u32 *)(psxP + (a & 0xfffc));
478
479// if ((a & ~0xe0600000) < 0x200000)
480 // RAM
481 return *(u32 *)(psxM + (a & 0x1ffffc));
482}
483
dd114d7d 484#if 0
7139f3c8 485void do_insn_trace(void)
486{
487 static psxRegisters oldregs;
19776aef 488 static u32 event_cycles_o[PSXINT_COUNT];
7139f3c8 489 u32 *allregs_p = (void *)&psxRegs;
490 u32 *allregs_o = (void *)&oldregs;
2185e39b 491 u32 io_data;
7139f3c8 492 int i;
493 u8 byte;
494
19776aef 495 //last_io_addr = 0x5e2c8;
7139f3c8 496 if (f == NULL)
497 f = fopen("tracelog", "wb");
498
19776aef 499 // log reg changes
7139f3c8 500 oldregs.code = psxRegs.code; // don't care
501 for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
502 if (allregs_p[i] != allregs_o[i]) {
503 fwrite(&i, 1, 1, f);
504 fwrite(&allregs_p[i], 1, 4, f);
505 allregs_o[i] = allregs_p[i];
506 }
507 }
19776aef 508 // log event changes
509 for (i = 0; i < PSXINT_COUNT; i++) {
510 if (event_cycles[i] != event_cycles_o[i]) {
2330734f 511 byte = 0xf8;
19776aef 512 fwrite(&byte, 1, 1, f);
513 fwrite(&i, 1, 1, f);
514 fwrite(&event_cycles[i], 1, 4, f);
515 event_cycles_o[i] = event_cycles[i];
516 }
517 }
2330734f 518 #define SAVE_IF_CHANGED(code_, name_) { \
519 static u32 old_##name_ = 0xbad0c0de; \
520 if (old_##name_ != name_) { \
521 byte = code_; \
522 fwrite(&byte, 1, 1, f); \
523 fwrite(&name_, 1, 4, f); \
524 old_##name_ = name_; \
525 } \
7139f3c8 526 }
2330734f 527 SAVE_IF_CHANGED(0xfb, irq_test_cycle);
528 SAVE_IF_CHANGED(0xfc, handler_cycle);
529 SAVE_IF_CHANGED(0xfd, last_io_addr);
2185e39b 530 io_data = memcheck_read(last_io_addr);
2330734f 531 SAVE_IF_CHANGED(0xfe, io_data);
7139f3c8 532 byte = 0xff;
533 fwrite(&byte, 1, 1, f);
534
535#if 0
536 if (psxRegs.cycle == 190230) {
537 dump_mem("/mnt/ntz/dev/pnd/tmp/psxram_i.dump", psxM, 0x200000);
538 dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs_i.dump", psxH, 0x10000);
539 printf("dumped\n");
540 exit(1);
541 }
542#endif
543}
dd114d7d 544#endif
7139f3c8 545
546static const char *regnames[offsetof(psxRegisters, intCycle) / 4] = {
547 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
548 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
549 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
550 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
551 "lo", "hi",
552 "C0_0", "C0_1", "C0_2", "C0_3", "C0_4", "C0_5", "C0_6", "C0_7",
553 "C0_8", "C0_9", "C0_10", "C0_11", "C0_12", "C0_13", "C0_14", "C0_15",
554 "C0_16", "C0_17", "C0_18", "C0_19", "C0_20", "C0_21", "C0_22", "C0_23",
555 "C0_24", "C0_25", "C0_26", "C0_27", "C0_28", "C0_29", "C0_30", "C0_31",
556
557 "C2D0", "C2D1", "C2D2", "C2D3", "C2D4", "C2D5", "C2D6", "C2D7",
558 "C2D8", "C2D9", "C2D10", "C2D11", "C2D12", "C2D13", "C2D14", "C2D15",
559 "C2D16", "C2D17", "C2D18", "C2D19", "C2D20", "C2D21", "C2D22", "C2D23",
560 "C2D24", "C2D25", "C2D26", "C2D27", "C2D28", "C2D29", "C2D30", "C2D31",
561
562 "C2C0", "C2C1", "C2C2", "C2C3", "C2C4", "C2C5", "C2C6", "C2C7",
563 "C2C8", "C2C9", "C2C10", "C2C11", "C2C12", "C2C13", "C2C14", "C2C15",
564 "C2C16", "C2C17", "C2C18", "C2C19", "C2C20", "C2C21", "C2C22", "C2C23",
565 "C2C24", "C2C25", "C2C26", "C2C27", "C2C28", "C2C29", "C2C30", "C2C31",
566
567 "PC", "code", "cycle", "interrupt",
568};
569
3eb78778 570static struct {
571 int reg;
572 u32 val, val_expect;
573 u32 pc, cycle;
574} miss_log[64];
575static int miss_log_i;
576#define miss_log_len (sizeof(miss_log)/sizeof(miss_log[0]))
577#define miss_log_mask (miss_log_len-1)
578
579static void miss_log_add(int reg, u32 val, u32 val_expect, u32 pc, u32 cycle)
580{
581 miss_log[miss_log_i].reg = reg;
582 miss_log[miss_log_i].val = val;
583 miss_log[miss_log_i].val_expect = val_expect;
584 miss_log[miss_log_i].pc = pc;
585 miss_log[miss_log_i].cycle = cycle;
586 miss_log_i = (miss_log_i + 1) & miss_log_mask;
587}
588
7139f3c8 589void breakme() {}
590
591void do_insn_cmp(void)
592{
2330734f 593 extern int last_count;
7139f3c8 594 static psxRegisters rregs;
595 static u32 mem_addr, mem_val;
2330734f 596 static u32 irq_test_cycle_intr;
597 static u32 handler_cycle_intr;
7139f3c8 598 u32 *allregs_p = (void *)&psxRegs;
599 u32 *allregs_e = (void *)&rregs;
600 static u32 ppc, failcount;
2330734f 601 int i, ret, bad = 0, fatal = 0, which_event = -1;
19776aef 602 u32 ev_cycles = 0;
7139f3c8 603 u8 code;
604
605 if (f == NULL)
606 f = fopen("tracelog", "rb");
607
608 while (1) {
609 if ((ret = fread(&code, 1, 1, f)) <= 0)
610 break;
611 if (ret <= 0)
612 break;
613 if (code == 0xff)
614 break;
19776aef 615 switch (code) {
2330734f 616 case 0xf8:
19776aef 617 which_event = 0;
618 fread(&which_event, 1, 1, f);
619 fread(&ev_cycles, 1, 4, f);
7139f3c8 620 continue;
2330734f 621 case 0xfb:
622 fread(&irq_test_cycle_intr, 1, 4, f);
623 continue;
624 case 0xfc:
625 fread(&handler_cycle_intr, 1, 4, f);
626 continue;
19776aef 627 case 0xfd:
628 fread(&mem_addr, 1, 4, f);
629 continue;
630 case 0xfe:
631 fread(&mem_val, 1, 4, f);
7139f3c8 632 continue;
633 }
2330734f 634 assert(code < offsetof(psxRegisters, intCycle) / 4);
19776aef 635 fread(&allregs_e[code], 1, 4, f);
7139f3c8 636 }
637
638 if (ret <= 0) {
639 printf("EOF?\n");
2330734f 640 exit(1);
7139f3c8 641 }
642
643 psxRegs.code = rregs.code; // don't care
2330734f 644 psxRegs.cycle += last_count;
079ab0c6 645 //psxRegs.cycle = rregs.cycle; // needs reload in _cmp
2185e39b 646 psxRegs.CP0.r[9] = rregs.CP0.r[9]; // Count
7139f3c8 647
19776aef 648 //if (psxRegs.cycle == 166172) breakme();
7139f3c8 649
2330734f 650 if (which_event >= 0 && event_cycles[which_event] != ev_cycles) {
55a695d9 651 printf("bad ev_cycles #%d: %u %u / %u\n", which_event,
652 event_cycles[which_event], ev_cycles, psxRegs.cycle);
2330734f 653 fatal = 1;
654 }
655
656 if (irq_test_cycle > irq_test_cycle_intr) {
657 printf("bad irq_test_cycle: %u %u\n", irq_test_cycle, irq_test_cycle_intr);
658 fatal = 1;
659 }
660
661 if (handler_cycle != handler_cycle_intr) {
662 printf("bad handler_cycle: %u %u\n", handler_cycle, handler_cycle_intr);
663 fatal = 1;
664 }
665
666 if (mem_val != memcheck_read(mem_addr)) {
667 printf("bad mem @%08x: %08x %08x\n", mem_addr, memcheck_read(mem_addr), mem_val);
668 fatal = 1;
669 }
670
671 if (!fatal && !memcmp(&psxRegs, &rregs, offsetof(psxRegisters, intCycle))) {
7139f3c8 672 failcount = 0;
673 goto ok;
674 }
675
676 for (i = 0; i < offsetof(psxRegisters, intCycle) / 4; i++) {
677 if (allregs_p[i] != allregs_e[i]) {
3eb78778 678 miss_log_add(i, allregs_p[i], allregs_e[i], psxRegs.pc, psxRegs.cycle);
7139f3c8 679 bad++;
3968e69e 680 if (i > 32+2)
2330734f 681 fatal = 1;
7139f3c8 682 }
683 }
684
2330734f 685 if (!fatal && psxRegs.pc == rregs.pc && bad < 6 && failcount < 32) {
3eb78778 686 static int last_mcycle;
687 if (last_mcycle != psxRegs.cycle >> 20) {
688 printf("%u\n", psxRegs.cycle);
689 last_mcycle = psxRegs.cycle >> 20;
690 }
7139f3c8 691 failcount++;
692 goto ok;
693 }
694
3eb78778 695 for (i = 0; i < miss_log_len; i++, miss_log_i = (miss_log_i + 1) & miss_log_mask)
696 printf("bad %5s: %08x %08x, pc=%08x, cycle %u\n",
697 regnames[miss_log[miss_log_i].reg], miss_log[miss_log_i].val,
698 miss_log[miss_log_i].val_expect, miss_log[miss_log_i].pc, miss_log[miss_log_i].cycle);
699 printf("-- %d\n", bad);
700 for (i = 0; i < 8; i++)
701 printf("r%d=%08x r%2d=%08x r%2d=%08x r%2d=%08x\n", i, allregs_p[i],
87c06e51 702 i+8, allregs_p[i+8], i+16, allregs_p[i+16], i+24, allregs_p[i+24]);
079ab0c6 703 printf("PC: %08x/%08x, cycle %u, next %u\n", psxRegs.pc, ppc, psxRegs.cycle, next_interupt);
704 //dump_mem("/tmp/psxram.dump", psxM, 0x200000);
705 //dump_mem("/mnt/ntz/dev/pnd/tmp/psxregs.dump", psxH, 0x10000);
7139f3c8 706 exit(1);
707ok:
2330734f 708 //psxRegs.cycle = rregs.cycle + 2; // sync timing
7139f3c8 709 ppc = psxRegs.pc;
710}
711
712#endif
ARM optimized PCSX fork