drc: simplify cache flush for some platforms
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec_config.h
CommitLineData
d148d265 1
be516ebe 2#ifdef __arm__
d148d265 3#define CORTEX_A8_BRANCH_PREDICTION_HACK 1
be516ebe 4#endif
5
d148d265 6#define USE_MINI_HT 1
7//#define REG_PREFETCH 1
8
3039c914 9#if defined(__MACH__) || defined(HAVE_LIBNX)
1e212a25 10#define NO_WRITE_EXEC 1
d148d265 11#endif
3039c914 12#if defined(VITA) || defined(HAVE_LIBNX)
1e212a25 13#define BASE_ADDR_DYNAMIC 1
d148d265 14#endif
3039c914 15#if defined(HAVE_LIBNX)
16#define NDRC_WRITE_OFFSET 1
17#endif
af700b41 18#if defined(HAVE_LIBNX) || defined(_3DS)
19#define NDRC_CACHE_FLUSH_ALL 1
20#endif