[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_drc_chk

diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
index 300a84c8..e4343533 100644
--- a/libpcsxcore/new_dynarec/new_dynarec.c
+++ b/libpcsxcore/new_dynarec/new_dynarec.c
@@ -345,7 +345,7 @@ static struct compile_info
   #define stat_clear(s)
 #endif
 
-  #define HACK_ENABLED(x) ((ndrc_g.hacks | ndrc_g.hacks_pergame) & (x))
+  #define HACK_ENABLED(x) ((NDHACK_NO_STALLS|NDHACK_NO_COMPAT_HACKS) & (x))
 
   /* registers that may be allocated */
   /* 1-31 gpr */
@@ -626,6 +626,7 @@ static int cycle_multiplier_active;
 
 static int CLOCK_ADJUST(int x)
 {
+  return x * 2;
   int m = cycle_multiplier_active;
   int s = (x >> 31) | 1;
   return (x * m + s * 50) / 100;
@@ -837,6 +838,9 @@ static noinline u_int generate_exception(u_int pc)
 static void noinline *get_addr(struct ht_entry *ht, const u_int vaddr,
   enum ndrc_compile_mode compile_mode)
 {
+#ifdef DRC_DBG
+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
+#endif
   u_int start_page = get_page_prev(vaddr);
   u_int i, page, end_page = get_page(vaddr);
   void *found_clean = NULL;
@@ -7421,7 +7425,7 @@ static noinline void pass2b_unneeded_regs(int istart, int iend, int r)
     // R0 is always unneeded
     u|=1;
     // Save it
-    unneeded_reg[i]=u;
+    unneeded_reg[i]=1;//u;
     gte_unneeded[i]=gte_u;
     /*
     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
@@ -8574,6 +8578,7 @@ static noinline void pass5a_preallocate1(void)
 // to use, which can avoid a load-use penalty on certain CPUs.
 static noinline void pass5b_preallocate2(void)
 {
+ return;
   int i, hr, limit = min(slen - 1, MAXBLOCK - 2);
   for (i = 0; i < limit; i++)
   {
@@ -9602,6 +9607,10 @@ static int noinline new_recompile_block(u_int addr)
 
 #ifdef ASSEM_PRINT
   fflush(stdout);
+#endif
+#ifdef DRC_DBG
+printf("new_recompile_block done\n");
+fflush(stdout);
 #endif
   stat_inc(stat_bc_direct);
   return 0;
diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
index 98e2c6be..edba031e 100644
--- a/libpcsxcore/new_dynarec/pcsxmem.c
+++ b/libpcsxcore/new_dynarec/pcsxmem.c
@@ -238,6 +238,8 @@ static void write_biu(u32 value)
 		return;
 	}
 
+extern u32 handler_cycle;
+handler_cycle = psxRegs.cycle;
 	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
 	psxRegs.biuReg = value;
 }
diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
index 064c06b6..07e2afb5 100644
--- a/libpcsxcore/psxcounters.c
+++ b/libpcsxcore/psxcounters.c
@@ -455,9 +455,12 @@ void psxRcntUpdate()
 
 /******************************************************************************/
 
+extern u32 handler_cycle;
+
 void psxRcntWcount( u32 index, u32 value )
 {
     verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWcount( index, value );
     psxRcntSet();
@@ -466,6 +469,7 @@ void psxRcntWcount( u32 index, u32 value )
 void psxRcntWmode( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     _psxRcntWmode( index, value );
     _psxRcntWcount( index, 0 );
@@ -477,6 +481,7 @@ void psxRcntWmode( u32 index, u32 value )
 void psxRcntWtarget( u32 index, u32 value )
 {
     verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
+handler_cycle = psxRegs.cycle;
 
     rcnts[index].target = value;
 
@@ -490,6 +495,7 @@ u32 psxRcntRcount0()
 {
     u32 index = 0;
     u32 count;
+handler_cycle = psxRegs.cycle;
 
     if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
         (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
diff --git a/libpcsxcore/psxevents.c b/libpcsxcore/psxevents.c
index 1e2d01f6..0ee15974 100644
--- a/libpcsxcore/psxevents.c
+++ b/libpcsxcore/psxevents.c
@@ -77,11 +77,13 @@ void irq_test(psxCP0Regs *cp0)
 		}
 	}
 
-	cp0->n.Cause &= ~0x400;
+	u32 c2 = cp0->n.Cause & ~0x400;
 	if (psxHu32(0x1070) & psxHu32(0x1074))
-		cp0->n.Cause |= 0x400;
-	if (((cp0->n.Cause | 1) & cp0->n.SR & 0x401) == 0x401)
+		c2 |= 0x400;
+	if (((c2 | 1) & cp0->n.SR & 0x401) == 0x401) {
+		cp0->n.Cause = c2;
 		psxException(0, 0, cp0);
+	}
 }
 
 void gen_interupt(psxCP0Regs *cp0)
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 68d79321..50a38f8d 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -243,7 +243,7 @@ static inline void addCycle(psxRegisters *regs)
 {
 	assert(regs->subCycleStep >= 0x10000);
 	regs->subCycle += regs->subCycleStep;
-	regs->cycle += regs->subCycle >> 16;
+	regs->cycle += 2; //regs->subCycle >> 16;
 	regs->subCycle &= 0xffff;
 }
 
@@ -440,7 +440,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
 		regs->CP0.n.Target = pc_final;
 	regs->branching = 0;
 
+	psxRegs.cycle += 2;
 	psxBranchTest();
+	psxRegs.cycle -= 2;
 }
 
 static void doBranchReg(psxRegisters *regs, u32 tar) {
@@ -973,7 +975,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
 	}
 }
 
-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
 
 // no exception
 static inline void psxNULLne(psxRegisters *regs) {
@@ -1132,6 +1134,7 @@ OP(psxHLE) {
 	dloadFlush(regs_);
 	psxHLEt[hleCode]();
 	regs_->branchSeen = 1;
+	regs_->cycle -= 2;
 }
 
 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
@@ -1182,18 +1185,20 @@ static void intReset() {
 static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	u32 pc = regs->pc;
 
-	addCycle(regs);
+	//addCycle(regs);
 	dloadStep(regs);
 
 	if (execBreakCheck(regs, pc))
@@ -1202,6 +1207,8 @@ static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
 	regs->pc += 4;
 	regs->code = fetch(regs, memRLUT, pc);
 	psxBSC[regs->code >> 26](regs, regs->code);
+	psxRegs.cycle += 2;
+	fetchNoCache(regs, memRLUT, regs->pc); // bus err check
 }
 
 static void intExecute(psxRegisters *regs) {
@@ -1218,20 +1225,28 @@ static void intExecuteBp(psxRegisters *regs) {
 		execIbp(memRLUT, regs);
 }
 
+ extern int last_count;
+ void do_insn_cmp(void);
 static void intExecuteBlock(psxRegisters *regs, enum blockExecCaller caller) {
 	u8 **memRLUT = psxMemRLUT;
 
+ last_count = 0;
 	regs->branchSeen = 0;
-	while (!regs->branchSeen)
+	while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) {
+		do_insn_cmp();
 		execI_(memRLUT, regs);
+	}
 }
 
 static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) {
 	u8 **memRLUT = psxMemRLUT;
 
+ last_count = 0;
 	regs->branchSeen = 0;
-	while (!regs->branchSeen)
+	while (!regs->branchSeen || (regs->dloadReg[0] || regs->dloadReg[1])) {
+		do_insn_cmp();
 		execIbp(memRLUT, regs);
+	}
 }
 
 static void intClear(u32 Addr, u32 Size) {
@@ -1263,7 +1278,7 @@ static void setupCop(u32 sr)
 	else
 		psxBSC[17] = psxCOPd;
 	if (sr & (1u << 30))
-		psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
+		psxBSC[18] = psxCOP2;
 	else
 		psxBSC[18] = psxCOPd;
 	if (sr & (1u << 31))
@@ -1282,7 +1297,7 @@ void intApplyConfig() {
 	assert(psxSPC[26] == psxDIV   || psxSPC[26] == psxDIV_stall);
 	assert(psxSPC[27] == psxDIVU  || psxSPC[27] == psxDIVU_stall);
 
-	if (Config.DisableStalls) {
+	if (1) {
 		psxBSC[18] = psxCOP2;
 		psxBSC[50] = gteLWC2;
 		psxBSC[58] = gteSWC2;
@@ -1365,8 +1380,12 @@ static void intShutdown() {
 // single step (may do several ops in case of a branch or load delay)
 // called by asm/dynarec
 void execI(psxRegisters *regs) {
+ printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, regs->next_interupt);
+ last_count = 0;
 	do {
 		execIbp(psxMemRLUT, regs);
+		if (regs->dloadReg[0] || regs->dloadReg[1])
+			do_insn_cmp();
 	} while (regs->dloadReg[0] || regs->dloadReg[1]);
 }
Commit	Line	Data
a151a8d8	1	diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
254b3eec	2	index 300a84c8..e4343533 100644
a151a8d8	3	--- a/libpcsxcore/new_dynarec/new_dynarec.c
a151a8d8	4	+++ b/libpcsxcore/new_dynarec/new_dynarec.c
254b3eec	5	@@ -345,7 +345,7 @@ static struct compile_info
4f674a2f	6	#define stat_clear(s)
4f674a2f	7	#endif
2330734f	8
4f674a2f	9	- #define HACK_ENABLED(x) ((ndrc_g.hacks \| ndrc_g.hacks_pergame) & (x))
254b3eec	10	+ #define HACK_ENABLED(x) ((NDHACK_NO_STALLS\|NDHACK_NO_COMPAT_HACKS) & (x))
2330734f	11
4f674a2f	12	/* registers that may be allocated */
4f674a2f	13	/* 1-31 gpr */
254b3eec	14	@@ -626,6 +626,7 @@ static int cycle_multiplier_active;
2330734f	15
	16	static int CLOCK_ADJUST(int x)
	17	{
	18	+ return x * 2;
55a695d9	19	int m = cycle_multiplier_active;
	20	int s = (x >> 31) \| 1;
	21	return (x * m + s * 50) / 100;
254b3eec	22	@@ -837,6 +838,9 @@ static noinline u_int generate_exception(u_int pc)
	23	static void noinline get_addr(struct ht_entry ht, const u_int vaddr,
	24	enum ndrc_compile_mode compile_mode)
a151a8d8	25	{
	26	+#ifdef DRC_DBG
	27	+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
	28	+#endif
55a695d9	29	u_int start_page = get_page_prev(vaddr);
	30	u_int i, page, end_page = get_page(vaddr);
	31	void *found_clean = NULL;
254b3eec	32	@@ -7421,7 +7425,7 @@ static noinline void pass2b_unneeded_regs(int istart, int iend, int r)
a151a8d8	33	// R0 is always unneeded
d1e4ebd9	34	u\|=1;
a151a8d8	35	// Save it
	36	- unneeded_reg[i]=u;
	37	+ unneeded_reg[i]=1;//u;
a151a8d8	38	gte_unneeded[i]=gte_u;
a151a8d8	39	/*
d1e4ebd9	40	printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
254b3eec	41	@@ -8574,6 +8578,7 @@ static noinline void pass5a_preallocate1(void)
4f674a2f	42	// to use, which can avoid a load-use penalty on certain CPUs.
55a695d9	43	static noinline void pass5b_preallocate2(void)
55a695d9	44	{
55a695d9	45	+ return;
4f674a2f	46	int i, hr, limit = min(slen - 1, MAXBLOCK - 2);
4f674a2f	47	for (i = 0; i < limit; i++)
a151a8d8	48	{
254b3eec	49	@@ -9602,6 +9607,10 @@ static int noinline new_recompile_block(u_int addr)
55a695d9	50
37387d8b	51	#ifdef ASSEM_PRINT
	52	fflush(stdout);
	53	+#endif
a151a8d8	54	+#ifdef DRC_DBG
	55	+printf("new_recompile_block done\n");
	56	+fflush(stdout);
37387d8b	57	#endif
55a695d9	58	stat_inc(stat_bc_direct);
a151a8d8	59	return 0;
2330734f	60	diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
254b3eec	61	index 98e2c6be..edba031e 100644
2330734f	62	--- a/libpcsxcore/new_dynarec/pcsxmem.c
2330734f	63	+++ b/libpcsxcore/new_dynarec/pcsxmem.c
254b3eec	64	@@ -238,6 +238,8 @@ static void write_biu(u32 value)
2330734f	65	return;
a5cd72d0	66	}
2330734f	67
	68	+extern u32 handler_cycle;
	69	+handler_cycle = psxRegs.cycle;
a5cd72d0	70	memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
	71	psxRegs.biuReg = value;
	72	}
2330734f	73	diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
254b3eec	74	index 064c06b6..07e2afb5 100644
2330734f	75	--- a/libpcsxcore/psxcounters.c
2330734f	76	+++ b/libpcsxcore/psxcounters.c
254b3eec	77	@@ -455,9 +455,12 @@ void psxRcntUpdate()
2330734f	78
	79	/******************************************************************************/
	80
	81	+extern u32 handler_cycle;
	82	+
	83	void psxRcntWcount( u32 index, u32 value )
	84	{
	85	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	86	+handler_cycle = psxRegs.cycle;
	87
	88	_psxRcntWcount( index, value );
	89	psxRcntSet();
254b3eec	90	@@ -466,6 +469,7 @@ void psxRcntWcount( u32 index, u32 value )
2330734f	91	void psxRcntWmode( u32 index, u32 value )
	92	{
	93	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	94	+handler_cycle = psxRegs.cycle;
	95
	96	_psxRcntWmode( index, value );
	97	_psxRcntWcount( index, 0 );
254b3eec	98	@@ -477,6 +481,7 @@ void psxRcntWmode( u32 index, u32 value )
2330734f	99	void psxRcntWtarget( u32 index, u32 value )
	100	{
	101	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	102	+handler_cycle = psxRegs.cycle;
	103
	104	rcnts[index].target = value;
	105
254b3eec	106	@@ -490,6 +495,7 @@ u32 psxRcntRcount0()
2330734f	107	{
7da5c7ad	108	u32 index = 0;
2330734f	109	u32 count;
	110	+handler_cycle = psxRegs.cycle;
	111
7da5c7ad	112	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
7da5c7ad	113	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
4f674a2f	114	diff --git a/libpcsxcore/psxevents.c b/libpcsxcore/psxevents.c
254b3eec	115	index 1e2d01f6..0ee15974 100644
4f674a2f	116	--- a/libpcsxcore/psxevents.c
4f674a2f	117	+++ b/libpcsxcore/psxevents.c
254b3eec	118	@@ -77,11 +77,13 @@ void irq_test(psxCP0Regs *cp0)
4f674a2f	119	}
	120	}
	121
	122	- cp0->n.Cause &= ~0x400;
	123	+ u32 c2 = cp0->n.Cause & ~0x400;
	124	if (psxHu32(0x1070) & psxHu32(0x1074))
	125	- cp0->n.Cause \|= 0x400;
254b3eec	126	- if (((cp0->n.Cause \| 1) & cp0->n.SR & 0x401) == 0x401)
4f674a2f	127	+ c2 \|= 0x400;
	128	+ if (((c2 \| 1) & cp0->n.SR & 0x401) == 0x401) {
	129	+ cp0->n.Cause = c2;
	130	psxException(0, 0, cp0);
254b3eec	131	+ }
	132	}
	133
	134	void gen_interupt(psxCP0Regs *cp0)
a5cd72d0	135	diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
254b3eec	136	index 68d79321..50a38f8d 100644
a5cd72d0	137	--- a/libpcsxcore/psxinterpreter.c
a5cd72d0	138	+++ b/libpcsxcore/psxinterpreter.c
254b3eec	139	@@ -243,7 +243,7 @@ static inline void addCycle(psxRegisters *regs)
a5cd72d0	140	{
	141	assert(regs->subCycleStep >= 0x10000);
	142	regs->subCycle += regs->subCycleStep;
	143	- regs->cycle += regs->subCycle >> 16;
	144	+ regs->cycle += 2; //regs->subCycle >> 16;
	145	regs->subCycle &= 0xffff;
	146	}
	147
254b3eec	148	@@ -440,7 +440,9 @@ static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
4f674a2f	149	regs->CP0.n.Target = pc_final;
	150	regs->branching = 0;
	151
	152	+ psxRegs.cycle += 2;
	153	psxBranchTest();
	154	+ psxRegs.cycle -= 2;
	155	}
	156
	157	static void doBranchReg(psxRegisters *regs, u32 tar) {
254b3eec	158	@@ -973,7 +975,7 @@ void MTC0(psxRegisters *regs_, int reg, u32 val) {
4f674a2f	159	}
	160	}
	161
	162	-OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
	163	+OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); psxBranchTest(); }
	164
	165	// no exception
	166	static inline void psxNULLne(psxRegisters *regs) {
254b3eec	167	@@ -1132,6 +1134,7 @@ OP(psxHLE) {
4f674a2f	168	dloadFlush(regs_);
4f674a2f	169	psxHLEt[hleCode]();
254b3eec	170	regs_->branchSeen = 1;
254b3eec	171	+ regs_->cycle -= 2;
4f674a2f	172	}
	173
	174	static void (INT_ATTR psxBSC[64])(psxRegisters regs_, u32 code) = {
254b3eec	175	@@ -1182,18 +1185,20 @@ static void intReset() {
4f674a2f	176	static inline void execI_(u8 *memRLUT, psxRegisters regs) {
	177	u32 pc = regs->pc;
	178
	179	- addCycle(regs);
	180	+ //addCycle(regs);
	181	dloadStep(regs);
	182
	183	regs->pc += 4;
	184	regs->code = fetch(regs, memRLUT, pc);
	185	psxBSC[regs->code >> 26](regs, regs->code);
	186	+ psxRegs.cycle += 2;
	187	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
	188	}
	189
	190	static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
	191	u32 pc = regs->pc;
	192
	193	- addCycle(regs);
	194	+ //addCycle(regs);
	195	dloadStep(regs);
	196
	197	if (execBreakCheck(regs, pc))
254b3eec	198	@@ -1202,6 +1207,8 @@ static inline void execIbp(u8 *memRLUT, psxRegisters regs) {
4f674a2f	199	regs->pc += 4;
	200	regs->code = fetch(regs, memRLUT, pc);
	201	psxBSC[regs->code >> 26](regs, regs->code);
	202	+ psxRegs.cycle += 2;
	203	+ fetchNoCache(regs, memRLUT, regs->pc); // bus err check
	204	}
	205
254b3eec	206	static void intExecute(psxRegisters *regs) {
	207	@@ -1218,20 +1225,28 @@ static void intExecuteBp(psxRegisters *regs) {
	208	execIbp(memRLUT, regs);
4f674a2f	209	}
	210
	211	+ extern int last_count;
	212	+ void do_insn_cmp(void);
254b3eec	213	static void intExecuteBlock(psxRegisters *regs, enum blockExecCaller caller) {
4f674a2f	214	u8 **memRLUT = psxMemRLUT;
	215
	216	+ last_count = 0;
254b3eec	217	regs->branchSeen = 0;
	218	- while (!regs->branchSeen)
	219	+ while (!regs->branchSeen \|\| (regs->dloadReg[0] \|\| regs->dloadReg[1])) {
4f674a2f	220	+ do_insn_cmp();
254b3eec	221	execI_(memRLUT, regs);
4f674a2f	222	+ }
	223	}
	224
254b3eec	225	static void intExecuteBlockBp(psxRegisters *regs, enum blockExecCaller caller) {
4f674a2f	226	u8 **memRLUT = psxMemRLUT;
	227
	228	+ last_count = 0;
254b3eec	229	regs->branchSeen = 0;
	230	- while (!regs->branchSeen)
	231	+ while (!regs->branchSeen \|\| (regs->dloadReg[0] \|\| regs->dloadReg[1])) {
4f674a2f	232	+ do_insn_cmp();
254b3eec	233	execIbp(memRLUT, regs);
4f674a2f	234	+ }
	235	}
	236
	237	static void intClear(u32 Addr, u32 Size) {
254b3eec	238	@@ -1263,7 +1278,7 @@ static void setupCop(u32 sr)
4f674a2f	239	else
	240	psxBSC[17] = psxCOPd;
	241	if (sr & (1u << 30))
	242	- psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
	243	+ psxBSC[18] = psxCOP2;
	244	else
	245	psxBSC[18] = psxCOPd;
	246	if (sr & (1u << 31))
254b3eec	247	@@ -1282,7 +1297,7 @@ void intApplyConfig() {
4f674a2f	248	assert(psxSPC[26] == psxDIV \|\| psxSPC[26] == psxDIV_stall);
	249	assert(psxSPC[27] == psxDIVU \|\| psxSPC[27] == psxDIVU_stall);
	250
	251	- if (Config.DisableStalls) {
	252	+ if (1) {
	253	psxBSC[18] = psxCOP2;
	254	psxBSC[50] = gteLWC2;
	255	psxBSC[58] = gteSWC2;
254b3eec	256	@@ -1365,8 +1380,12 @@ static void intShutdown() {
a5cd72d0	257	// single step (may do several ops in case of a branch or load delay)
4f13a577	258	// called by asm/dynarec
a5cd72d0	259	void execI(psxRegisters *regs) {
254b3eec	260	+ printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, regs->next_interupt);
a5cd72d0	261	+ last_count = 0;
	262	do {
	263	execIbp(psxMemRLUT, regs);
	264	+ if (regs->dloadReg[0] \|\| regs->dloadReg[1])
	265	+ do_insn_cmp();
	266	} while (regs->dloadReg[0] \|\| regs->dloadReg[1]);
	267	}
	268