drc: optional address error exception support
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_drc_chk
CommitLineData
a151a8d8 1diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
277718fa 2index b71f8a8f..0a26f6f6 100644
a151a8d8 3--- a/libpcsxcore/new_dynarec/new_dynarec.c
4+++ b/libpcsxcore/new_dynarec/new_dynarec.c
277718fa 5@@ -318,7 +318,7 @@ static struct compile_info
2330734f 6 int new_dynarec_hacks_old;
7 int new_dynarec_did_compile;
8
9- #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
10+ #define HACK_ENABLED(x) ((NDHACK_NO_STALLS) & (x))
11
12 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
13 extern int last_count; // last absolute target, often = next_interupt
277718fa 14@@ -598,6 +598,7 @@ static int cycle_multiplier_active;
2330734f 15
16 static int CLOCK_ADJUST(int x)
17 {
18+ return x * 2;
55a695d9 19 int m = cycle_multiplier_active;
20 int s = (x >> 31) | 1;
21 return (x * m + s * 50) / 100;
277718fa 22@@ -750,6 +751,9 @@ static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
a151a8d8 23 // This is called from the recompiled JR/JALR instructions
55a695d9 24 static void noinline *get_addr(u_int vaddr, int can_compile)
a151a8d8 25 {
26+#ifdef DRC_DBG
27+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
28+#endif
55a695d9 29 u_int start_page = get_page_prev(vaddr);
30 u_int i, page, end_page = get_page(vaddr);
31 void *found_clean = NULL;
277718fa 32@@ -7180,7 +7184,7 @@ static noinline void pass2_unneeded_regs(int istart,int iend,int r)
a151a8d8 33 // R0 is always unneeded
d1e4ebd9 34 u|=1;
a151a8d8 35 // Save it
36- unneeded_reg[i]=u;
37+ unneeded_reg[i]=1;//u;
a151a8d8 38 gte_unneeded[i]=gte_u;
39 /*
d1e4ebd9 40 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
277718fa 41@@ -8329,6 +8333,7 @@ static noinline void pass5a_preallocate1(void)
55a695d9 42 static noinline void pass5b_preallocate2(void)
43 {
44 int i, hr;
45+ return;
a151a8d8 46 for(i=0;i<slen-1;i++)
47 {
37387d8b 48 if (!i || !dops[i-1].is_jump)
277718fa 49@@ -9138,6 +9143,14 @@ static int new_recompile_block(u_int addr)
55a695d9 50 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
2330734f 51
277718fa 52 ds = assemble(i, &regs[i], cinfo[i].ccadj);
a151a8d8 53+#ifdef DRC_DBG
37387d8b 54+ // write-out non-consts, consts are likely different because of get_final_value()
277718fa 55+ if (!dops[i].is_jump && (regs[i].dirty&~regs[i].loadedconst)) {
56+ assem_debug("/ drc_dbg_wb\n");
37387d8b 57+ wb_dirtys(regs[i].regmap,regs[i].dirty&~regs[i].loadedconst);
277718fa 58+ assem_debug("\\ drc_dbg_wb\n");
59+ }
a151a8d8 60+#endif
2330734f 61
37387d8b 62 if (dops[i].is_ujump)
a151a8d8 63 literal_pool(1024);
277718fa 64@@ -9330,6 +9343,10 @@ static int new_recompile_block(u_int addr)
55a695d9 65
37387d8b 66 #ifdef ASSEM_PRINT
67 fflush(stdout);
68+#endif
a151a8d8 69+#ifdef DRC_DBG
70+printf("new_recompile_block done\n");
71+fflush(stdout);
37387d8b 72 #endif
55a695d9 73 stat_inc(stat_bc_direct);
a151a8d8 74 return 0;
2330734f 75diff --git a/libpcsxcore/new_dynarec/pcsxmem.c b/libpcsxcore/new_dynarec/pcsxmem.c
a5cd72d0 76index 190f8fc7..5feb7a02 100644
2330734f 77--- a/libpcsxcore/new_dynarec/pcsxmem.c
78+++ b/libpcsxcore/new_dynarec/pcsxmem.c
a5cd72d0 79@@ -289,6 +289,8 @@ static void write_biu(u32 value)
2330734f 80 return;
a5cd72d0 81 }
2330734f 82
83+extern u32 handler_cycle;
84+handler_cycle = psxRegs.cycle;
a5cd72d0 85 memprintf("write_biu %08x @%08x %u\n", value, psxRegs.pc, psxRegs.cycle);
86 psxRegs.biuReg = value;
87 }
2330734f 88diff --git a/libpcsxcore/psxcounters.c b/libpcsxcore/psxcounters.c
a5cd72d0 89index 18bd6a4e..bc2eb3f6 100644
2330734f 90--- a/libpcsxcore/psxcounters.c
91+++ b/libpcsxcore/psxcounters.c
a5cd72d0 92@@ -389,9 +389,12 @@ void psxRcntUpdate()
2330734f 93
94 /******************************************************************************/
95
96+extern u32 handler_cycle;
97+
98 void psxRcntWcount( u32 index, u32 value )
99 {
100 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
101+handler_cycle = psxRegs.cycle;
102
103 _psxRcntWcount( index, value );
104 psxRcntSet();
a5cd72d0 105@@ -400,6 +403,7 @@ void psxRcntWcount( u32 index, u32 value )
2330734f 106 void psxRcntWmode( u32 index, u32 value )
107 {
108 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
109+handler_cycle = psxRegs.cycle;
110
111 _psxRcntWmode( index, value );
112 _psxRcntWcount( index, 0 );
a5cd72d0 113@@ -411,6 +415,7 @@ void psxRcntWmode( u32 index, u32 value )
2330734f 114 void psxRcntWtarget( u32 index, u32 value )
115 {
116 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
117+handler_cycle = psxRegs.cycle;
118
119 rcnts[index].target = value;
120
a5cd72d0 121@@ -423,6 +428,7 @@ void psxRcntWtarget( u32 index, u32 value )
2330734f 122 u32 psxRcntRcount( u32 index )
123 {
124 u32 count;
125+handler_cycle = psxRegs.cycle;
126
127 count = _psxRcntRcount( index );
128
a5cd72d0 129diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
130index e212d8a9..b98b694e 100644
131--- a/libpcsxcore/psxinterpreter.c
132+++ b/libpcsxcore/psxinterpreter.c
133@@ -237,7 +237,7 @@ static inline void addCycle(psxRegisters *regs)
134 {
135 assert(regs->subCycleStep >= 0x10000);
136 regs->subCycle += regs->subCycleStep;
137- regs->cycle += regs->subCycle >> 16;
138+ regs->cycle += 2; //regs->subCycle >> 16;
139 regs->subCycle &= 0xffff;
140 }
141
142@@ -1341,8 +1341,14 @@ static void intShutdown() {
143
144 // single step (may do several ops in case of a branch or load delay)
145 void execI(psxRegisters *regs) {
146+ extern int last_count;
147+ void do_insn_cmp(void);
148+ printf("execI %08x c %u, ni %u\n", regs->pc, regs->cycle, next_interupt);
149+ last_count = 0;
150 do {
151 execIbp(psxMemRLUT, regs);
152+ if (regs->dloadReg[0] || regs->dloadReg[1])
153+ do_insn_cmp();
154 } while (regs->dloadReg[0] || regs->dloadReg[1]);
155 }
156