[pcsx_rearmed.git] / libpcsxcore / psxcounters.c

/***************************************************************************
 *   Copyright (C) 2010 by Blade_Arma                                      *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

/*
 * Internal PSX counters.
 */

#include "psxcounters.h"
#include "gpu.h"
//#include "debug.h"
#define DebugVSync()

/******************************************************************************/

enum
{
    RcSyncModeEnable  = 0x0001, // 0
    Rc01BlankPause    = 0 << 1, // 1,2
    Rc01UnblankReset  = 1 << 1, // 1,2
    Rc01UnblankReset2 = 2 << 1, // 1,2
    Rc2Stop           = 0 << 1, // 1,2
    Rc2Stop2          = 3 << 1, // 1,2
    RcCountToTarget   = 0x0008, // 3
    RcIrqOnTarget     = 0x0010, // 4
    RcIrqOnOverflow   = 0x0020, // 5
    RcIrqRegenerate   = 0x0040, // 6
    RcUnknown7        = 0x0080, // 7    ?
    Rc0PixelClock     = 0x0100, // 8    fake implementation
    Rc1HSyncClock     = 0x0100, // 8
    Rc2Unknown8       = 0x0100, // 8    ?
    Rc0Unknown9       = 0x0200, // 9    ?
    Rc1Unknown9       = 0x0200, // 9    ?
    Rc2OneEighthClock = 0x0200, // 9
    RcUnknown10       = 0x0400, // 10   ?
    RcCountEqTarget   = 0x0800, // 11
    RcOverflow        = 0x1000, // 12
    RcUnknown13       = 0x2000, // 13   ? (always zero)
    RcUnknown14       = 0x4000, // 14   ? (always zero)
    RcUnknown15       = 0x8000, // 15   ? (always zero)
};

#define CounterQuantity           ( 4 )
//static const u32 CounterQuantity  = 4;

static const u32 CountToOverflow  = 0;
static const u32 CountToTarget    = 1;

static const u32 FrameRate[]      = { 60, 50 };
static const u32 HSyncTotal[]     = { 263, 314 }; // actually one more on odd lines for PAL
#define VBlankStart 240

#define VERBOSE_LEVEL 0

/******************************************************************************/
#ifdef DRC_DISABLE
Rcnt rcnts[ CounterQuantity ];
#endif
u32 hSyncCount = 0;
u32 frame_counter = 0;
static u32 hsync_steps = 0;

u32 psxNextCounter = 0, psxNextsCounter = 0;

/******************************************************************************/

static inline
void setIrq( u32 irq )
{
    psxHu32ref(0x1070) |= SWAPu32(irq);
}

static
void verboseLog( u32 level, const char *str, ... )
{
#if VERBOSE_LEVEL > 0
    if( level <= VERBOSE_LEVEL )
    {
        va_list va;
        char buf[ 4096 ];

        va_start( va, str );
        vsprintf( buf, str, va );
        va_end( va );

        printf( "%s", buf );
        fflush( stdout );
    }
#endif
}

/******************************************************************************/

static inline
void _psxRcntWcount( u32 index, u32 value )
{
    if( value > 0xffff )
    {
        verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
        value &= 0xffff;
    }

    rcnts[index].cycleStart  = psxRegs.cycle;
    rcnts[index].cycleStart -= value * rcnts[index].rate;

    // TODO: <=.
    if( value < rcnts[index].target )
    {
        rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
        rcnts[index].counterState = CountToTarget;
    }
    else
    {
        rcnts[index].cycle = 0x10000 * rcnts[index].rate;
        rcnts[index].counterState = CountToOverflow;
    }
}

static inline
u32 _psxRcntRcount( u32 index )
{
    u32 count;

    count  = psxRegs.cycle;
    count -= rcnts[index].cycleStart;
    if (rcnts[index].rate > 1)
        count /= rcnts[index].rate;

    if( count > 0x10000 )
    {
        verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
    }
    count &= 0xffff;

    return count;
}

static
void _psxRcntWmode( u32 index, u32 value )
{
    rcnts[index].mode = value;

    switch( index )
    {
        case 0:
            if( value & Rc0PixelClock )
            {
                rcnts[index].rate = 5;
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 1:
            if( value & Rc1HSyncClock )
            {
                rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
            }
            else
            {
                rcnts[index].rate = 1;
            }
        break;
        case 2:
            if( value & Rc2OneEighthClock )
            {
                rcnts[index].rate = 8;
            }
            else
            {
                rcnts[index].rate = 1;
            }

            // TODO: wcount must work.
            if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
                (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
            {
                rcnts[index].rate = 0xffffffff;
            }
        break;
    }
}

/******************************************************************************/

static
void psxRcntSet()
{
    s32 countToUpdate;
    u32 i;

    psxNextsCounter = psxRegs.cycle;
    psxNextCounter  = 0x7fffffff;

    for( i = 0; i < CounterQuantity; ++i )
    {
        countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);

        if( countToUpdate < 0 )
        {
            psxNextCounter = 0;
            break;
        }

        if( countToUpdate < (s32)psxNextCounter )
        {
            psxNextCounter = countToUpdate;
        }
    }

    psxRegs.interrupt |= (1 << PSXINT_RCNT);
    new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
}

/******************************************************************************/

static
void psxRcntReset( u32 index )
{
    u32 rcycles;

    rcnts[index].mode |= RcUnknown10;

    if( rcnts[index].counterState == CountToTarget )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        if( rcnts[index].mode & RcCountToTarget )
        {
            rcycles -= rcnts[index].target * rcnts[index].rate;
            rcnts[index].cycleStart = psxRegs.cycle - rcycles;
        }
        else
        {
            rcnts[index].cycle = 0x10000 * rcnts[index].rate;
            rcnts[index].counterState = CountToOverflow;
        }

        if( rcnts[index].mode & RcIrqOnTarget )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcCountEqTarget;

        if( rcycles < 0x10000 * rcnts[index].rate )
            return;
    }

    if( rcnts[index].counterState == CountToOverflow )
    {
        rcycles = psxRegs.cycle - rcnts[index].cycleStart;
        rcycles -= 0x10000 * rcnts[index].rate;

        rcnts[index].cycleStart = psxRegs.cycle - rcycles;

        if( rcycles < rcnts[index].target * rcnts[index].rate )
        {
            rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
            rcnts[index].counterState = CountToTarget;
        }

        if( rcnts[index].mode & RcIrqOnOverflow )
        {
            if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
            {
                verboseLog( 3, "[RCNT %i] irq\n", index );
                setIrq( rcnts[index].irq );
                rcnts[index].irqState = 1;
            }
        }

        rcnts[index].mode |= RcOverflow;
    }
}

static void scheduleRcntBase(void)
{
    // Schedule next call, in hsyncs
    if (hSyncCount < VBlankStart)
        hsync_steps = VBlankStart - hSyncCount;
    else
        hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;

    if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
    {
        rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
    }
    else
    {
        // clk / 50 / 314 ~= 2157.25
        // clk / 60 / 263 ~= 2146.31
        u32 mult = Config.PsxType ? 8836089 : 8791293;
        rcnts[3].cycle = hsync_steps * mult >> 12;
    }
}

void psxRcntUpdate()
{
    u32 cycle, cycles_passed;

    cycle = psxRegs.cycle;

    // rcnt 0.
    cycles_passed = cycle - rcnts[0].cycleStart;
    while( cycles_passed >= rcnts[0].cycle )
    {
        if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
             (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
            && cycles_passed > PSXCLK / 60 / 263)
        {
            u32 q = cycles_passed / (PSXCLK / 60 / 263 + 1u);
            rcnts[0].cycleStart += q * (PSXCLK / 60) / 263u;
            break;
        }
        else
            psxRcntReset( 0 );

        cycles_passed = cycle - rcnts[0].cycleStart;
    }

    // rcnt 1.
    while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
    {
        psxRcntReset( 1 );
    }

    // rcnt 2.
    while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
    {
        psxRcntReset( 2 );
    }

    // rcnt base.
    if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
    {
        hSyncCount += hsync_steps;

        // VSync irq.
        if( hSyncCount == VBlankStart )
        {
            HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
            GPU_vBlank( 1, 0 );
            setIrq( 0x01 );

            EmuUpdate();
            GPU_updateLace();

            if( SPU_async )
            {
                SPU_async( cycle, 1 );
            }
        }
        
        // Update lace.
        if( hSyncCount >= HSyncTotal[Config.PsxType] )
        {
            u32 status, field = 0, i;
            rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
            hSyncCount = 0;
            frame_counter++;

            gpuSyncPluginSR();
            status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
            if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
                field = frame_counter & 1;
                status |= field << 31;
                status ^= field << 13;
            }
            HW_GPU_STATUS = SWAP32(status);
            GPU_vBlank(0, field);

            for (i = 0; i < 2; i++)
            {
                if ((rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
                    (rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
                {
                    rcnts[i].cycleStart = rcnts[3].cycleStart;
                }
            }
        }

        scheduleRcntBase();
    }

    psxRcntSet();

#if 0 //ndef NDEBUG
    DebugVSync();
#endif
}

/******************************************************************************/

void psxRcntWcount( u32 index, u32 value )
{
    verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );

    _psxRcntWcount( index, value );
    psxRcntSet();
}

void psxRcntWmode( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );

    _psxRcntWmode( index, value );
    _psxRcntWcount( index, 0 );

    rcnts[index].irqState = 0;
    psxRcntSet();
}

void psxRcntWtarget( u32 index, u32 value )
{
    verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );

    rcnts[index].target = value;

    _psxRcntWcount( index, _psxRcntRcount( index ) );
    psxRcntSet();
}

/******************************************************************************/

u32 psxRcntRcount0()
{
    u32 index = 0;
    u32 count;

    if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
        (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
    {
        count = psxRegs.cycle - rcnts[index].cycleStart;
        count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
        rcnts[index].cycleStart = psxRegs.cycle - count;
    }
    else
        count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount1()
{
    u32 index = 1;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRcount2()
{
    u32 index = 2;
    u32 count;

    count = _psxRcntRcount( index );

    verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);

    return count;
}

u32 psxRcntRmode( u32 index )
{
    u16 mode;

    mode = rcnts[index].mode;
    rcnts[index].mode &= 0xe7ff;

    verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );

    return mode;
}

u32 psxRcntRtarget( u32 index )
{
    verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );

    return rcnts[index].target;
}

/******************************************************************************/

void psxRcntInit()
{
    s32 i;

    // rcnt 0.
    rcnts[0].rate   = 1;
    rcnts[0].irq    = 0x10;

    // rcnt 1.
    rcnts[1].rate   = 1;
    rcnts[1].irq    = 0x20;

    // rcnt 2.
    rcnts[2].rate   = 1;
    rcnts[2].irq    = 0x40;

    // rcnt base.
    rcnts[3].rate   = 1;
    rcnts[3].mode   = RcCountToTarget;
    rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));

    for( i = 0; i < CounterQuantity; ++i )
    {
        _psxRcntWcount( i, 0 );
    }

    hSyncCount = 0;
    hsync_steps = 1;

    psxRcntSet();
}

/******************************************************************************/

s32 psxRcntFreeze( void *f, s32 Mode )
{
    u32 spuSyncCount = 0;
    u32 count;
    s32 i;

    gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
    gzfreeze( &hSyncCount, sizeof(hSyncCount) );
    gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
    gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
    gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );

    if (Mode == 0)
    {
        // don't trust things from a savestate
        rcnts[3].rate = 1;
        for( i = 0; i < CounterQuantity; ++i )
        {
            _psxRcntWmode( i, rcnts[i].mode );
            count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
            _psxRcntWcount( i, count );
        }
        scheduleRcntBase();
        psxRcntSet();
    }

    return 0;
}

/******************************************************************************/
// vim:ts=4:shiftwidth=4:expandtab
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2010 by Blade_Arma *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	/*
	21	* Internal PSX counters.
	22	*/
	23
	24	#include "psxcounters.h"
ddbaf678	25	#include "gpu.h"
7d7672a5	26	//#include "debug.h"
7d7672a5	27	#define DebugVSync()
ef79bbde P	28
	29	/******************************************************************************/
	30
ef79bbde P	31	enum
ef79bbde P	32	{
11d23573	33	RcSyncModeEnable = 0x0001, // 0
	34	Rc01BlankPause = 0 << 1, // 1,2
	35	Rc01UnblankReset = 1 << 1, // 1,2
	36	Rc01UnblankReset2 = 2 << 1, // 1,2
	37	Rc2Stop = 0 << 1, // 1,2
	38	Rc2Stop2 = 3 << 1, // 1,2
ef79bbde P	39	RcCountToTarget = 0x0008, // 3
	40	RcIrqOnTarget = 0x0010, // 4
	41	RcIrqOnOverflow = 0x0020, // 5
	42	RcIrqRegenerate = 0x0040, // 6
	43	RcUnknown7 = 0x0080, // 7 ?
	44	Rc0PixelClock = 0x0100, // 8 fake implementation
	45	Rc1HSyncClock = 0x0100, // 8
	46	Rc2Unknown8 = 0x0100, // 8 ?
	47	Rc0Unknown9 = 0x0200, // 9 ?
	48	Rc1Unknown9 = 0x0200, // 9 ?
	49	Rc2OneEighthClock = 0x0200, // 9
	50	RcUnknown10 = 0x0400, // 10 ?
	51	RcCountEqTarget = 0x0800, // 11
	52	RcOverflow = 0x1000, // 12
	53	RcUnknown13 = 0x2000, // 13 ? (always zero)
	54	RcUnknown14 = 0x4000, // 14 ? (always zero)
	55	RcUnknown15 = 0x8000, // 15 ? (always zero)
	56	};
	57
	58	#define CounterQuantity ( 4 )
	59	//static const u32 CounterQuantity = 4;
	60
	61	static const u32 CountToOverflow = 0;
	62	static const u32 CountToTarget = 1;
	63
	64	static const u32 FrameRate[] = { 60, 50 };
91f412c2	65	static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
0486fdc9	66	#define VBlankStart 240
ef79bbde	67
9f7ee52e	68	#define VERBOSE_LEVEL 0
ef79bbde P	69
ef79bbde P	70	/******************************************************************************/
41e82ad4	71	#ifdef DRC_DISABLE
b1be1eee	72	Rcnt rcnts[ CounterQuantity ];
41e82ad4	73	#endif
24de2dd4	74	u32 hSyncCount = 0;
24de2dd4	75	u32 frame_counter = 0;
61ef5cf4	76	static u32 hsync_steps = 0;
ef79bbde P	77
	78	u32 psxNextCounter = 0, psxNextsCounter = 0;
	79
	80	/******************************************************************************/
	81
	82	static inline
	83	void setIrq( u32 irq )
	84	{
	85	psxHu32ref(0x1070) \|= SWAPu32(irq);
	86	}
	87
	88	static
9f7ee52e	89	void verboseLog( u32 level, const char *str, ... )
ef79bbde	90	{
9f7ee52e	91	#if VERBOSE_LEVEL > 0
3cf51e08	92	if( level <= VERBOSE_LEVEL )
ef79bbde P	93	{
	94	va_list va;
	95	char buf[ 4096 ];
	96
	97	va_start( va, str );
	98	vsprintf( buf, str, va );
	99	va_end( va );
	100
ab948f7e	101	printf( "%s", buf );
ef79bbde P	102	fflush( stdout );
ef79bbde P	103	}
9f7ee52e	104	#endif
ef79bbde P	105	}
	106
	107	/******************************************************************************/
	108
	109	static inline
	110	void _psxRcntWcount( u32 index, u32 value )
	111	{
	112	if( value > 0xffff )
	113	{
	114	verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
	115	value &= 0xffff;
	116	}
	117
	118	rcnts[index].cycleStart = psxRegs.cycle;
	119	rcnts[index].cycleStart -= value * rcnts[index].rate;
	120
	121	// TODO: <=.
	122	if( value < rcnts[index].target )
	123	{
	124	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	125	rcnts[index].counterState = CountToTarget;
	126	}
	127	else
	128	{
8ca6b0a6	129	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
ef79bbde P	130	rcnts[index].counterState = CountToOverflow;
	131	}
	132	}
	133
	134	static inline
	135	u32 _psxRcntRcount( u32 index )
	136	{
	137	u32 count;
	138
	139	count = psxRegs.cycle;
	140	count -= rcnts[index].cycleStart;
61ef5cf4	141	if (rcnts[index].rate > 1)
61ef5cf4	142	count /= rcnts[index].rate;
ef79bbde	143
8ca6b0a6	144	if( count > 0x10000 )
ef79bbde	145	{
8ca6b0a6	146	verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
ef79bbde	147	}
8ca6b0a6	148	count &= 0xffff;
ef79bbde P	149
	150	return count;
	151	}
	152
a29f182f	153	static
	154	void _psxRcntWmode( u32 index, u32 value )
	155	{
	156	rcnts[index].mode = value;
	157
	158	switch( index )
	159	{
	160	case 0:
	161	if( value & Rc0PixelClock )
	162	{
	163	rcnts[index].rate = 5;
	164	}
	165	else
	166	{
	167	rcnts[index].rate = 1;
	168	}
	169	break;
	170	case 1:
	171	if( value & Rc1HSyncClock )
	172	{
	173	rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	174	}
	175	else
	176	{
	177	rcnts[index].rate = 1;
	178	}
	179	break;
	180	case 2:
	181	if( value & Rc2OneEighthClock )
	182	{
	183	rcnts[index].rate = 8;
	184	}
	185	else
	186	{
	187	rcnts[index].rate = 1;
	188	}
	189
	190	// TODO: wcount must work.
11d23573	191	if( (value & 7) == (RcSyncModeEnable \| Rc2Stop) \|\|
11d23573	192	(value & 7) == (RcSyncModeEnable \| Rc2Stop2) )
a29f182f	193	{
	194	rcnts[index].rate = 0xffffffff;
	195	}
	196	break;
	197	}
	198	}
	199
ef79bbde P	200	/******************************************************************************/
	201
	202	static
	203	void psxRcntSet()
	204	{
	205	s32 countToUpdate;
	206	u32 i;
	207
	208	psxNextsCounter = psxRegs.cycle;
	209	psxNextCounter = 0x7fffffff;
	210
	211	for( i = 0; i < CounterQuantity; ++i )
	212	{
	213	countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
	214
	215	if( countToUpdate < 0 )
	216	{
	217	psxNextCounter = 0;
	218	break;
	219	}
	220
	221	if( countToUpdate < (s32)psxNextCounter )
	222	{
	223	psxNextCounter = countToUpdate;
	224	}
	225	}
5b8c000f	226
	227	psxRegs.interrupt \|= (1 << PSXINT_RCNT);
	228	new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
ef79bbde P	229	}
	230
	231	/******************************************************************************/
	232
	233	static
	234	void psxRcntReset( u32 index )
	235	{
8ca6b0a6	236	u32 rcycles;
ef79bbde	237
53c361f0	238	rcnts[index].mode \|= RcUnknown10;
53c361f0	239
ef79bbde P	240	if( rcnts[index].counterState == CountToTarget )
ef79bbde P	241	{
8ca6b0a6	242	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
ef79bbde	243	if( rcnts[index].mode & RcCountToTarget )
8ca6b0a6	244	{
	245	rcycles -= rcnts[index].target * rcnts[index].rate;
	246	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
	247	}
	248	else
	249	{
	250	rcnts[index].cycle = 0x10000 * rcnts[index].rate;
	251	rcnts[index].counterState = CountToOverflow;
	252	}
ef79bbde P	253
	254	if( rcnts[index].mode & RcIrqOnTarget )
	255	{
	256	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	257	{
8ca6b0a6	258	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	259	setIrq( rcnts[index].irq );
	260	rcnts[index].irqState = 1;
	261	}
	262	}
	263
	264	rcnts[index].mode \|= RcCountEqTarget;
53c361f0	265
8ca6b0a6	266	if( rcycles < 0x10000 * rcnts[index].rate )
53c361f0	267	return;
ef79bbde	268	}
53c361f0	269
53c361f0	270	if( rcnts[index].counterState == CountToOverflow )
ef79bbde	271	{
8ca6b0a6	272	rcycles = psxRegs.cycle - rcnts[index].cycleStart;
	273	rcycles -= 0x10000 * rcnts[index].rate;
	274
	275	rcnts[index].cycleStart = psxRegs.cycle - rcycles;
ef79bbde	276
8ca6b0a6	277	if( rcycles < rcnts[index].target * rcnts[index].rate )
	278	{
	279	rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
	280	rcnts[index].counterState = CountToTarget;
	281	}
ef79bbde P	282
	283	if( rcnts[index].mode & RcIrqOnOverflow )
	284	{
	285	if( (rcnts[index].mode & RcIrqRegenerate) \|\| (!rcnts[index].irqState) )
	286	{
8ca6b0a6	287	verboseLog( 3, "[RCNT %i] irq\n", index );
ef79bbde P	288	setIrq( rcnts[index].irq );
	289	rcnts[index].irqState = 1;
	290	}
	291	}
	292
	293	rcnts[index].mode \|= RcOverflow;
	294	}
ef79bbde P	295	}
ef79bbde P	296
ff2c2822	297	static void scheduleRcntBase(void)
	298	{
	299	// Schedule next call, in hsyncs
	300	if (hSyncCount < VBlankStart)
	301	hsync_steps = VBlankStart - hSyncCount;
	302	else
	303	hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
	304
	305	if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
	306	{
	307	rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
	308	}
	309	else
	310	{
	311	// clk / 50 / 314 ~= 2157.25
	312	// clk / 60 / 263 ~= 2146.31
	313	u32 mult = Config.PsxType ? 8836089 : 8791293;
	314	rcnts[3].cycle = hsync_steps * mult >> 12;
	315	}
	316	}
	317
ef79bbde P	318	void psxRcntUpdate()
ef79bbde P	319	{
11d23573	320	u32 cycle, cycles_passed;
ef79bbde P	321
	322	cycle = psxRegs.cycle;
	323
	324	// rcnt 0.
11d23573	325	cycles_passed = cycle - rcnts[0].cycleStart;
11d23573	326	while( cycles_passed >= rcnts[0].cycle )
ef79bbde	327	{
11d23573	328	if (((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	329	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	330	&& cycles_passed > PSXCLK / 60 / 263)
	331	{
	332	u32 q = cycles_passed / (PSXCLK / 60 / 263 + 1u);
	333	rcnts[0].cycleStart += q * (PSXCLK / 60) / 263u;
	334	break;
	335	}
	336	else
	337	psxRcntReset( 0 );
	338
	339	cycles_passed = cycle - rcnts[0].cycleStart;
ef79bbde P	340	}
	341
	342	// rcnt 1.
e7851504	343	while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
ef79bbde P	344	{
	345	psxRcntReset( 1 );
	346	}
	347
	348	// rcnt 2.
e7851504	349	while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
ef79bbde P	350	{
	351	psxRcntReset( 2 );
	352	}
	353
	354	// rcnt base.
	355	if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
	356	{
61ef5cf4	357	hSyncCount += hsync_steps;
ef79bbde	358
ef79bbde	359	// VSync irq.
0486fdc9	360	if( hSyncCount == VBlankStart )
ef79bbde	361	{
086adfff	362	HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
72e5023f	363	GPU_vBlank( 1, 0 );
8bbbd091	364	setIrq( 0x01 );
	365
	366	EmuUpdate();
	367	GPU_updateLace();
d618a240	368
	369	if( SPU_async )
	370	{
	371	SPU_async( cycle, 1 );
	372	}
ef79bbde P	373	}
ef79bbde P	374
d014a471	375	// Update lace.
d014a471	376	if( hSyncCount >= HSyncTotal[Config.PsxType] )
ef79bbde	377	{
11d23573	378	u32 status, field = 0, i;
ff2c2822	379	rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
ef79bbde	380	hSyncCount = 0;
ddbaf678	381	frame_counter++;
ef79bbde	382
0486fdc9	383	gpuSyncPluginSR();
db57cbb8	384	status = SWAP32(HW_GPU_STATUS) \| PSXGPU_FIELD;
	385	if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
	386	field = frame_counter & 1;
	387	status \|= field << 31;
	388	status ^= field << 13;
	389	}
	390	HW_GPU_STATUS = SWAP32(status);
	391	GPU_vBlank(0, field);
11d23573	392
	393	for (i = 0; i < 2; i++)
	394	{
	395	if ((rcnts[i].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	396	(rcnts[i].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	397	{
	398	rcnts[i].cycleStart = rcnts[3].cycleStart;
	399	}
	400	}
ef79bbde	401	}
61ef5cf4	402
ff2c2822	403	scheduleRcntBase();
ef79bbde P	404	}
ef79bbde P	405
95df1a04	406	psxRcntSet();
95df1a04	407
7a8d521f	408	#if 0 //ndef NDEBUG
ef79bbde	409	DebugVSync();
61ef5cf4	410	#endif
ef79bbde P	411	}
	412
	413	/******************************************************************************/
	414
	415	void psxRcntWcount( u32 index, u32 value )
	416	{
	417	verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
	418
ef79bbde P	419	_psxRcntWcount( index, value );
	420	psxRcntSet();
	421	}
	422
	423	void psxRcntWmode( u32 index, u32 value )
	424	{
	425	verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
	426
a29f182f	427	_psxRcntWmode( index, value );
ef79bbde	428	_psxRcntWcount( index, 0 );
a29f182f	429
a29f182f	430	rcnts[index].irqState = 0;
ef79bbde P	431	psxRcntSet();
	432	}
	433
	434	void psxRcntWtarget( u32 index, u32 value )
	435	{
	436	verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
	437
ef79bbde P	438	rcnts[index].target = value;
	439
	440	_psxRcntWcount( index, _psxRcntRcount( index ) );
	441	psxRcntSet();
	442	}
	443
	444	/******************************************************************************/
	445
11d23573	446	u32 psxRcntRcount0()
	447	{
	448	u32 index = 0;
	449	u32 count;
	450
	451	if ((rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset) \|\|
	452	(rcnts[0].mode & 7) == (RcSyncModeEnable \| Rc01UnblankReset2))
	453	{
	454	count = psxRegs.cycle - rcnts[index].cycleStart;
	455	count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
	456	rcnts[index].cycleStart = psxRegs.cycle - count;
	457	}
	458	else
	459	count = _psxRcntRcount( index );
	460
	461	verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	462
	463	return count;
	464	}
	465
	466	u32 psxRcntRcount1()
	467	{
	468	u32 index = 1;
	469	u32 count;
	470
	471	count = _psxRcntRcount( index );
	472
	473	verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
	474
	475	return count;
	476	}
	477
	478	u32 psxRcntRcount2()
ef79bbde	479	{
11d23573	480	u32 index = 2;
ef79bbde P	481	u32 count;
ef79bbde P	482
ef79bbde P	483	count = _psxRcntRcount( index );
ef79bbde P	484
11d23573	485	verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
ef79bbde P	486
	487	return count;
	488	}
	489
	490	u32 psxRcntRmode( u32 index )
	491	{
	492	u16 mode;
	493
ef79bbde P	494	mode = rcnts[index].mode;
	495	rcnts[index].mode &= 0xe7ff;
	496
	497	verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
	498
	499	return mode;
	500	}
	501
	502	u32 psxRcntRtarget( u32 index )
	503	{
	504	verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
	505
	506	return rcnts[index].target;
	507	}
	508
	509	/******************************************************************************/
	510
	511	void psxRcntInit()
	512	{
	513	s32 i;
	514
	515	// rcnt 0.
	516	rcnts[0].rate = 1;
	517	rcnts[0].irq = 0x10;
	518
	519	// rcnt 1.
	520	rcnts[1].rate = 1;
	521	rcnts[1].irq = 0x20;
	522
	523	// rcnt 2.
	524	rcnts[2].rate = 1;
	525	rcnts[2].irq = 0x40;
	526
	527	// rcnt base.
	528	rcnts[3].rate = 1;
	529	rcnts[3].mode = RcCountToTarget;
	530	rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
	531
	532	for( i = 0; i < CounterQuantity; ++i )
	533	{
	534	_psxRcntWcount( i, 0 );
	535	}
	536
c62b43c9	537	hSyncCount = 0;
61ef5cf4	538	hsync_steps = 1;
c62b43c9	539
ef79bbde P	540	psxRcntSet();
	541	}
	542
	543	/******************************************************************************/
	544
496d88d4	545	s32 psxRcntFreeze( void *f, s32 Mode )
ef79bbde	546	{
d618a240	547	u32 spuSyncCount = 0;
a29f182f	548	u32 count;
	549	s32 i;
	550
41e82ad4	551	gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
ef79bbde P	552	gzfreeze( &hSyncCount, sizeof(hSyncCount) );
	553	gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
	554	gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
	555	gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
	556
61ef5cf4	557	if (Mode == 0)
a29f182f	558	{
a29f182f	559	// don't trust things from a savestate
e43c9382	560	rcnts[3].rate = 1;
a29f182f	561	for( i = 0; i < CounterQuantity; ++i )
	562	{
	563	_psxRcntWmode( i, rcnts[i].mode );
	564	count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
	565	_psxRcntWcount( i, count );
	566	}
ff2c2822	567	scheduleRcntBase();
a29f182f	568	psxRcntSet();
a29f182f	569	}
4f55097d	570
ef79bbde P	571	return 0;
	572	}
	573
	574	/******************************************************************************/
ff2c2822	575	// vim:ts=4:shiftwidth=4:expandtab