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drc: update according to interpreter (2)
[pcsx_rearmed.git] / libpcsxcore / psxinterpreter.c
CommitLineData
ef79bbde
P		 1/***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
f9ae4f29 3 * Copyright (C) 2023 notaz *
ef79bbde
P		 4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
19 ***************************************************************************/
20
21/*
22 * PSX assembly interpreter.
23 */
24
25#include "psxcommon.h"
26#include "r3000a.h"
27#include "gte.h"
28#include "psxhle.h"
3968e69e 29#include "psxinterpreter.h"
4cc373dd 30#include <stddef.h>
32631e6a 31#include <assert.h>
905b7c25 32#include "../include/compiler_features.h"
33
34// these may cause issues: because of poor timing we may step
35// on instructions that real hardware would never reach
36#define DO_EXCEPTION_RESERVEDI
f9ae4f29 37#define HANDLE_LOAD_DELAY
ef79bbde 38
bc7c5acb 39static int branchSeen = 0;
ef79bbde 40
4cc373dd 41#ifdef __i386__
42#define INT_ATTR __attribute__((regparm(2)))
43#else
44#define INT_ATTR
45#endif
46#ifndef INVALID_PTR
47#define INVALID_PTR NULL
48#endif
49
ef79bbde 50// Subsets
4cc373dd 51static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code);
52static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code);
53
f9ae4f29 54// load delay
55static void doLoad(psxRegisters *regs, u32 r, u32 val)
56{
57#ifdef HANDLE_LOAD_DELAY
58 int sel = regs->dloadSel ^ 1;
59 assert(regs->dloadReg[sel] == 0);
60 regs->dloadReg[sel] = r;
61 regs->dloadVal[sel] = r ? val : 0;
62 if (regs->dloadReg[sel ^ 1] == r)
63 regs->dloadVal[sel ^ 1] = regs->dloadReg[sel ^ 1] = 0;
64#else
65 regs->GPR.r[r] = r ? val : 0;
66#endif
67}
68
69static void dloadRt(psxRegisters *regs, u32 r, u32 val)
70{
71#ifdef HANDLE_LOAD_DELAY
72 int sel = regs->dloadSel;
73 if (unlikely(regs->dloadReg[sel] == r))
74 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
75#endif
76 regs->GPR.r[r] = r ? val : 0;
77}
78
79static void dloadStep(psxRegisters *regs)
80{
81#ifdef HANDLE_LOAD_DELAY
82 int sel = regs->dloadSel;
83 regs->GPR.r[regs->dloadReg[sel]] = regs->dloadVal[sel];
84 regs->dloadVal[sel] = regs->dloadReg[sel] = 0;
85 regs->dloadSel ^= 1;
86 assert(regs->GPR.r[0] == 0);
87#endif
88}
89
90static void dloadFlush(psxRegisters *regs)
91{
92#ifdef HANDLE_LOAD_DELAY
93 regs->GPR.r[regs->dloadReg[0]] = regs->dloadVal[0];
94 regs->GPR.r[regs->dloadReg[1]] = regs->dloadVal[1];
95 regs->dloadVal[0] = regs->dloadVal[1] = 0;
96 regs->dloadReg[0] = regs->dloadReg[1] = 0;
97 assert(regs->GPR.r[0] == 0);
98#endif
99}
100
101static void dloadClear(psxRegisters *regs)
102{
103#ifdef HANDLE_LOAD_DELAY
104 regs->dloadVal[0] = regs->dloadVal[1] = 0;
105 regs->dloadReg[0] = regs->dloadReg[1] = 0;
106 regs->dloadSel = 0;
107#endif
108}
109
110static void intException(psxRegisters *regs, u32 pc, u32 cause)
111{
bc7c5acb 112 if (cause != 0x20) {
113 //FILE *f = fopen("/tmp/psx_ram.bin", "wb");
114 //fwrite(psxM, 1, 0x200000, f); fclose(f);
115 log_unhandled("exception %08x @%08x\n", cause, pc);
116 }
f9ae4f29 117 dloadFlush(regs);
118 regs->pc = pc;
bc7c5acb 119 psxException(cause, regs->branching, &regs->CP0);
120 regs->branching = R3000A_BRANCH_NONE_OR_EXCEPTION;
121}
122
123// exception caused by current instruction (excluding unkasking)
124static void intExceptionInsn(psxRegisters *regs, u32 cause)
125{
126 cause |= (regs->code & 0x0c000000) << 2;
127 intException(regs, regs->pc - 4, cause);
128}
129
130// 29 Enable for 80000000-ffffffff
131// 30 Enable for 00000000-7fffffff
132// 31 Enable exception
133#define DBR_ABIT(dc, a) ((dc) & (1u << (29+(((a)>>31)^1))))
134#define DBR_EN_EXEC(dc, a) (((dc) & 0x01800000) == 0x01800000 && DBR_ABIT(dc, a))
135#define DBR_EN_LD(dc, a) (((dc) & 0x06800000) == 0x06800000 && DBR_ABIT(dc, a))
136#define DBR_EN_ST(dc, a) (((dc) & 0x0a800000) == 0x0a800000 && DBR_ABIT(dc, a))
137static void intExceptionDebugBp(psxRegisters *regs, u32 pc)
138{
139 psxCP0Regs *cp0 = &regs->CP0;
140 dloadFlush(regs);
141 cp0->n.Cause &= 0x300;
142 cp0->n.Cause |= (regs->branching << 30) | (R3000E_Bp << 2);
143 cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
144 cp0->n.EPC = regs->branching ? pc - 4 : pc;
145 psxRegs.pc = 0x80000040;
146}
147
148static int execBreakCheck(psxRegisters *regs, u32 pc)
149{
150 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, pc) &&
151 ((pc ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
152 {
153 regs->CP0.n.DCIC |= 0x03;
154 if (regs->CP0.n.DCIC & (1u << 31)) {
155 intExceptionDebugBp(regs, pc);
156 return 1;
157 }
158 }
159 return 0;
f9ae4f29 160}
161
905b7c25 162// get an opcode without triggering exceptions or affecting cache
163u32 intFakeFetch(u32 pc)
164{
165 u8 *base = psxMemRLUT[pc >> 16];
166 u32 *code;
167 if (unlikely(base == INVALID_PTR))
168 return 0; // nop
169 code = (u32 *)(base + (pc & 0xfffc));
170 return SWAP32(*code);
171
172}
173
174static u32 INT_ATTR fetchNoCache(psxRegisters *regs, u8 **memRLUT, u32 pc)
61ad2a61 175{
4cc373dd 176 u8 *base = memRLUT[pc >> 16];
905b7c25 177 u32 *code;
178 if (unlikely(base == INVALID_PTR)) {
179 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
f9ae4f29 180 intException(regs, pc, R3000E_IBE << 2);
905b7c25 181 return 0; // execute as nop
182 }
183 code = (u32 *)(base + (pc & 0xfffc));
4cc373dd 184 return SWAP32(*code);
61ad2a61 185}
186
943a507a 187/*
188Formula One 2001 :
189Use old CPU cache code when the RAM location is updated with new code (affects in-game racing)
190*/
9f84fc93 191static struct cache_entry {
192 u32 tag;
193 u32 data[4];
194} ICache[256];
195
905b7c25 196static u32 INT_ATTR fetchICache(psxRegisters *regs, u8 **memRLUT, u32 pc)
943a507a 197{
9f84fc93 198 // cached?
199 if (pc < 0xa0000000)
943a507a 200 {
9f84fc93 201 // this is not how the hardware works but whatever
202 struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4];
203
204 if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
943a507a 205 {
4cc373dd 206 const u8 *base = memRLUT[pc >> 16];
207 const u32 *code;
905b7c25 208 if (unlikely(base == INVALID_PTR)) {
209 SysPrintf("game crash @%08x, ra=%08x\n", pc, regs->GPR.n.ra);
f9ae4f29 210 intException(regs, pc, R3000E_IBE << 2);
905b7c25 211 return 0; // execute as nop
212 }
4cc373dd 213 code = (u32 *)(base + (pc & 0xfff0));
9f84fc93 214
215 entry->tag = pc;
216 // treat as 4 words, although other configurations are said to be possible
217 switch (pc & 0x0c)
218 {
219 case 0x00: entry->data[0] = SWAP32(code[0]);
220 case 0x04: entry->data[1] = SWAP32(code[1]);
221 case 0x08: entry->data[2] = SWAP32(code[2]);
222 case 0x0c: entry->data[3] = SWAP32(code[3]);
223 }
943a507a 224 }
9f84fc93 225 return entry->data[(pc & 0x0f) >> 2];
943a507a 226 }
227
905b7c25 228 return fetchNoCache(regs, memRLUT, pc);
943a507a 229}
61ad2a61 230
905b7c25 231static u32 (INT_ATTR *fetch)(psxRegisters *regs_, u8 **memRLUT, u32 pc) = fetchNoCache;
943a507a 232
d5aeda23 233// Make the timing events trigger faster as we are currently assuming everything
234// takes one cycle, which is not the case on real hardware.
235// FIXME: count cache misses, memory latencies, stalls to get rid of this
bc7c5acb 236static inline void addCycle(psxRegisters *regs)
d5aeda23 237{
bc7c5acb 238 assert(regs->subCycleStep >= 0x10000);
239 regs->subCycle += regs->subCycleStep;
240 regs->cycle += regs->subCycle >> 16;
241 regs->subCycle &= 0xffff;
d5aeda23 242}
243
4cc373dd 244/**** R3000A Instruction Macros ****/
245#define _PC_ regs_->pc // The next PC to be executed
246
247#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
248#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
249#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
250#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
251#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
252#define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
253#define _fIm_(code) ((u16)code) // The immediate part of the instruction register
254#define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
255
256#define _fImm_(code) ((s16)code) // sign-extended immediate
257#define _fImmU_(code) (code&0xffff) // zero-extended immediate
258
259#define _Op_ _fOp_(code)
260#define _Funct_ _fFunct_(code)
261#define _Rd_ _fRd_(code)
262#define _Rt_ _fRt_(code)
263#define _Rs_ _fRs_(code)
264#define _Sa_ _fSa_(code)
265#define _Im_ _fIm_(code)
266#define _Target_ _fTarget_(code)
267
268#define _Imm_ _fImm_(code)
269#define _ImmU_ _fImmU_(code)
270
271#define _rRs_ regs_->GPR.r[_Rs_] // Rs register
272#define _rRt_ regs_->GPR.r[_Rt_] // Rt register
4cc373dd 273#define _rSa_ regs_->GPR.r[_Sa_] // Sa register
4cc373dd 274
275#define _rHi_ regs_->GPR.n.hi // The HI register
276#define _rLo_ regs_->GPR.n.lo // The LO register
277
278#define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
279#define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
280
f9ae4f29 281#define _SetLink(x) dloadRt(regs_, x, _PC_ + 4); // Sets the return address in the link register
4cc373dd 282
283#define OP(name) \
284 static inline INT_ATTR void name(psxRegisters *regs_, u32 code)
285
ef79bbde
P		 286// this defines shall be used with the tmp
287// of the next func (instead of _Funct_...)
288#define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register
289#define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register
290#define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register
291#define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register
292#define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register
293
4cc373dd 294#define _i32(x) (s32)(x)
295#define _u32(x) (u32)(x)
296
b9698f9d 297#define isBranch(c_) \
298 ((1 <= ((c_) >> 26) && ((c_) >> 26) <= 7) || ((c_) & 0xfc00003e) == 8)
299#define swap_(a_, b_) { u32 t_ = a_; a_ = b_; b_ = t_; }
990cb018 300
b9698f9d 301// tar1 is main branch target, 'code' is opcode in DS
302static u32 psxBranchNoDelay(psxRegisters *regs_, u32 tar1, u32 code, int *taken) {
303 u32 temp, rt;
304
305 assert(isBranch(code));
306 *taken = 1;
307 switch (code >> 26) {
990cb018 308 case 0x00: // SPECIAL
309 switch (_Funct_) {
310 case 0x08: // JR
311 return _u32(_rRs_);
312 case 0x09: // JALR
313 temp = _u32(_rRs_);
b9698f9d 314 if (_Rd_)
315 regs_->GPR.r[_Rd_] = tar1 + 4;
990cb018 316 return temp;
317 }
318 break;
319 case 0x01: // REGIMM
b9698f9d 320 rt = _Rt_;
321 switch (rt) {
322 case 0x10: // BLTZAL
323 regs_->GPR.n.ra = tar1 + 4;
990cb018 324 if (_i32(_rRs_) < 0)
b9698f9d 325 return tar1 + (s16)_Im_ * 4;
990cb018 326 break;
b9698f9d 327 case 0x11: // BGEZAL
328 regs_->GPR.n.ra = tar1 + 4;
990cb018 329 if (_i32(_rRs_) >= 0)
b9698f9d 330 return tar1 + (s16)_Im_ * 4;
990cb018 331 break;
b9698f9d 332 default:
333 if (rt & 1) { // BGEZ
334 if (_i32(_rRs_) >= 0)
335 return tar1 + (s16)_Im_ * 4;
990cb018 336 }
b9698f9d 337 else { // BLTZ
338 if (_i32(_rRs_) < 0)
339 return tar1 + (s16)_Im_ * 4;
990cb018 340 }
341 break;
342 }
343 break;
344 case 0x02: // J
b9698f9d 345 return (tar1 & 0xf0000000u) + _Target_ * 4;
990cb018 346 case 0x03: // JAL
b9698f9d 347 regs_->GPR.n.ra = tar1 + 4;
348 return (tar1 & 0xf0000000u) + _Target_ * 4;
990cb018 349 case 0x04: // BEQ
350 if (_i32(_rRs_) == _i32(_rRt_))
b9698f9d 351 return tar1 + (s16)_Im_ * 4;
990cb018 352 break;
353 case 0x05: // BNE
354 if (_i32(_rRs_) != _i32(_rRt_))
b9698f9d 355 return tar1 + (s16)_Im_ * 4;
990cb018 356 break;
357 case 0x06: // BLEZ
358 if (_i32(_rRs_) <= 0)
b9698f9d 359 return tar1 + (s16)_Im_ * 4;
990cb018 360 break;
361 case 0x07: // BGTZ
362 if (_i32(_rRs_) > 0)
b9698f9d 363 return tar1 + (s16)_Im_ * 4;
990cb018 364 break;
365 }
366
b9698f9d 367 *taken = 0;
368 return tar1;
990cb018 369}
370
b9698f9d 371static void psxDoDelayBranch(psxRegisters *regs, u32 tar1, u32 code1) {
372 u32 tar2, code;
373 int taken, lim;
990cb018 374
b9698f9d 375 tar2 = psxBranchNoDelay(regs, tar1, code1, &taken);
376 regs->pc = tar1;
377 if (!taken)
378 return;
990cb018 379
990cb018 380 /*
b9698f9d 381 * taken branch in delay slot:
990cb018 382 * - execute 1 instruction at tar1
383 * - jump to tar2 (target of branch in delay slot; this branch
384 * has no normal delay slot, instruction at tar1 was fetched instead)
385 */
b9698f9d 386 for (lim = 0; lim < 8; lim++) {
387 regs->code = code = fetch(regs, psxMemRLUT, tar1);
bc7c5acb 388 addCycle(regs);
b9698f9d 389 if (likely(!isBranch(code))) {
f9ae4f29 390 dloadStep(regs);
b9698f9d 391 psxBSC[code >> 26](regs, code);
392 regs->pc = tar2;
393 return;
394 }
395 tar1 = psxBranchNoDelay(regs, tar2, code, &taken);
396 regs->pc = tar2;
397 if (!taken)
398 return;
399 swap_(tar1, tar2);
990cb018 400 }
b9698f9d 401 SysPrintf("Evil chained DS branches @ %08x %08x %08x\n", regs->pc, tar1, tar2);
990cb018 402}
403
bc7c5acb 404static void doBranch(psxRegisters *regs, u32 tar, enum R3000Abdt taken) {
405 u32 code, pc, pc_final;
ef79bbde 406
bc7c5acb 407 branchSeen = regs->branching = taken;
408 pc_final = taken == R3000A_BRANCH_TAKEN ? tar : regs->pc + 4;
990cb018 409
b9698f9d 410 // fetch the delay slot
411 pc = regs->pc;
412 regs->pc = pc + 4;
413 regs->code = code = fetch(regs, psxMemRLUT, pc);
905b7c25 414
bc7c5acb 415 addCycle(regs);
ef79bbde 416
b9698f9d 417 // check for branch in delay slot
418 if (unlikely(isBranch(code))) {
bc7c5acb 419 regs->pc = pc;
420 if (taken == R3000A_BRANCH_TAKEN)
421 psxDoDelayBranch(regs, tar, code);
b9698f9d 422 log_unhandled("branch in DS: %08x->%08x\n", pc, regs->pc);
bc7c5acb 423 regs->branching = 0;
b9698f9d 424 psxBranchTest();
425 return;
426 }
427
f9ae4f29 428 dloadStep(regs);
b9698f9d 429 psxBSC[code >> 26](regs, code);
ef79bbde 430
bc7c5acb 431 if (likely(regs->branching != R3000A_BRANCH_NONE_OR_EXCEPTION))
432 regs->pc = pc_final;
433 else
434 regs->CP0.n.Target = pc_final;
435 regs->branching = 0;
ef79bbde
P		 436
437 psxBranchTest();
438}
439
b9698f9d 440static void doBranchReg(psxRegisters *regs, u32 tar) {
bc7c5acb 441 doBranch(regs, tar & ~3, R3000A_BRANCH_TAKEN);
442}
443
444static void doBranchRegE(psxRegisters *regs, u32 tar) {
445 if (unlikely(DBR_EN_EXEC(regs->CP0.n.DCIC, tar) &&
446 ((tar ^ regs->CP0.n.BPC) & regs->CP0.n.BPCM) == 0))
447 regs->CP0.n.DCIC |= 0x03;
905b7c25 448 if (unlikely(tar & 3)) {
f9ae4f29 449 SysPrintf("game crash @%08x, ra=%08x\n", tar, regs->GPR.n.ra);
bc7c5acb 450 regs->CP0.n.BadVAddr = tar;
f9ae4f29 451 intException(regs, tar, R3000E_AdEL << 2);
905b7c25 452 return;
453 }
bc7c5acb 454 doBranch(regs, tar, R3000A_BRANCH_TAKEN);
905b7c25 455}
456
905b7c25 457static void addExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
f9ae4f29 458 s32 val;
459 if (add_overflow(a1, a2, val)) {
460 //printf("ov %08x + %08x = %08x\n", a1, a2, val);
bc7c5acb 461 intExceptionInsn(regs, R3000E_Ov << 2);
905b7c25 462 return;
463 }
f9ae4f29 464 dloadRt(regs, rt, val);
905b7c25 465}
466
467static void subExc(psxRegisters *regs, u32 rt, s32 a1, s32 a2) {
f9ae4f29 468 s32 val;
469 if (sub_overflow(a1, a2, val)) {
bc7c5acb 470 intExceptionInsn(regs, R3000E_Ov << 2);
905b7c25 471 return;
472 }
f9ae4f29 473 dloadRt(regs, rt, val);
905b7c25 474}
475
ef79bbde
P		 476/*********************************************************
477* Arithmetic with immediate operand *
478* Format: OP rt, rs, immediate *
479*********************************************************/
f9ae4f29 480OP(psxADDI) { addExc (regs_, _Rt_, _i32(_rRs_), _Imm_); } // Rt = Rs + Im (Exception on Integer Overflow)
481OP(psxADDIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) + _Imm_ ); } // Rt = Rs + Im
482OP(psxANDI) { dloadRt(regs_, _Rt_, _u32(_rRs_) & _ImmU_); } // Rt = Rs And Im
483OP(psxORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) | _ImmU_); } // Rt = Rs Or Im
484OP(psxXORI) { dloadRt(regs_, _Rt_, _u32(_rRs_) ^ _ImmU_); } // Rt = Rs Xor Im
485OP(psxSLTI) { dloadRt(regs_, _Rt_, _i32(_rRs_) < _Imm_ ); } // Rt = Rs < Im (Signed)
486OP(psxSLTIU) { dloadRt(regs_, _Rt_, _u32(_rRs_) < ((u32)_Imm_)); } // Rt = Rs < Im (Unsigned)
ef79bbde
P		 487
488/*********************************************************
489* Register arithmetic *
490* Format: OP rd, rs, rt *
491*********************************************************/
f9ae4f29 492OP(psxADD) { addExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs + Rt (Exception on Integer Overflow)
493OP(psxSUB) { subExc (regs_, _Rd_, _i32(_rRs_), _i32(_rRt_)); } // Rd = Rs - Rt (Exception on Integer Overflow)
494OP(psxADDU) { dloadRt(regs_, _Rd_, _u32(_rRs_) + _u32(_rRt_)); } // Rd = Rs + Rt
495OP(psxSUBU) { dloadRt(regs_, _Rd_, _u32(_rRs_) - _u32(_rRt_)); } // Rd = Rs - Rt
496OP(psxAND) { dloadRt(regs_, _Rd_, _u32(_rRs_) & _u32(_rRt_)); } // Rd = Rs And Rt
497OP(psxOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) | _u32(_rRt_)); } // Rd = Rs Or Rt
498OP(psxXOR) { dloadRt(regs_, _Rd_, _u32(_rRs_) ^ _u32(_rRt_)); } // Rd = Rs Xor Rt
499OP(psxNOR) { dloadRt(regs_, _Rd_, ~_u32(_rRs_ | _u32(_rRt_))); } // Rd = Rs Nor Rt
500OP(psxSLT) { dloadRt(regs_, _Rd_, _i32(_rRs_) < _i32(_rRt_)); } // Rd = Rs < Rt (Signed)
501OP(psxSLTU) { dloadRt(regs_, _Rd_, _u32(_rRs_) < _u32(_rRt_)); } // Rd = Rs < Rt (Unsigned)
ef79bbde
P		 502
503/*********************************************************
504* Register mult/div & Register trap logic *
505* Format: OP rs, rt *
506*********************************************************/
4cc373dd 507OP(psxDIV) {
508 if (!_rRt_) {
509 _rHi_ = _rRs_;
510 if (_rRs_ & 0x80000000) {
511 _rLo_ = 1;
512 } else {
513 _rLo_ = 0xFFFFFFFF;
514 }
515 }
a4ae3997 516#if !defined(__arm__) && !defined(__aarch64__)
4cc373dd 517 else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) {
518 _rLo_ = 0x80000000;
519 _rHi_ = 0;
520 }
a4ae3997 521#endif
4cc373dd 522 else {
523 _rLo_ = _i32(_rRs_) / _i32(_rRt_);
524 _rHi_ = _i32(_rRs_) % _i32(_rRt_);
525 }
ef79bbde
P		 526}
527
4cc373dd 528OP(psxDIV_stall) {
529 regs_->muldivBusyCycle = regs_->cycle + 37;
530 psxDIV(regs_, code);
32631e6a 531}
532
4cc373dd 533OP(psxDIVU) {
ef79bbde
P		 534 if (_rRt_ != 0) {
535 _rLo_ = _rRs_ / _rRt_;
536 _rHi_ = _rRs_ % _rRt_;
537 }
c7a56f4f 538 else {
4cc373dd 539 _rLo_ = 0xffffffff;
540 _rHi_ = _rRs_;
c7a56f4f 541 }
ef79bbde
P		 542}
543
4cc373dd 544OP(psxDIVU_stall) {
545 regs_->muldivBusyCycle = regs_->cycle + 37;
546 psxDIVU(regs_, code);
32631e6a 547}
548
4cc373dd 549OP(psxMULT) {
550 u64 res = (s64)_i32(_rRs_) * _i32(_rRt_);
ef79bbde 551
4cc373dd 552 regs_->GPR.n.lo = (u32)res;
553 regs_->GPR.n.hi = (u32)(res >> 32);
ef79bbde
P		 554}
555
4cc373dd 556OP(psxMULT_stall) {
32631e6a 557 // approximate, but maybe good enough
558 u32 rs = _rRs_;
559 u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1));
560 u32 c = 7 + (2 - (lz / 11)) * 4;
4cc373dd 561 regs_->muldivBusyCycle = regs_->cycle + c;
562 psxMULT(regs_, code);
32631e6a 563}
564
4cc373dd 565OP(psxMULTU) {
566 u64 res = (u64)_u32(_rRs_) * _u32(_rRt_);
ef79bbde 567
4cc373dd 568 regs_->GPR.n.lo = (u32)(res & 0xffffffff);
569 regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
ef79bbde
P		 570}
571
4cc373dd 572OP(psxMULTU_stall) {
32631e6a 573 // approximate, but maybe good enough
574 u32 lz = __builtin_clz(_rRs_ | 1);
575 u32 c = 7 + (2 - (lz / 11)) * 4;
4cc373dd 576 regs_->muldivBusyCycle = regs_->cycle + c;
577 psxMULTU(regs_, code);
32631e6a 578}
579
ef79bbde
P		 580/*********************************************************
581* Register branch logic *
582* Format: OP rs, offset *
583*********************************************************/
bc7c5acb 584#define BrCond(c) (c) ? R3000A_BRANCH_TAKEN : R3000A_BRANCH_NOT_TAKEN
19fae7fc 585#define RepZBranchi32(op) \
bc7c5acb 586 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op 0));
19fae7fc 587#define RepZBranchLinki32(op) { \
588 s32 temp = _i32(_rRs_); \
bc7c5acb 589 dloadFlush(regs_); \
19fae7fc 590 _SetLink(31); \
bc7c5acb 591 doBranch(regs_, _BranchTarget_, BrCond(temp op 0)); \
19fae7fc 592}
ef79bbde 593
4cc373dd 594OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0
595OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
596OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0
597OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0
598OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0
599OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
ef79bbde
P		 600
601/*********************************************************
602* Shift arithmetic with constant shift *
603* Format: OP rd, rt, sa *
604*********************************************************/
f9ae4f29 605OP(psxSLL) { dloadRt(regs_, _Rd_, _u32(_rRt_) << _Sa_); } // Rd = Rt << sa
606OP(psxSRA) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (arithmetic)
607OP(psxSRL) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> _Sa_); } // Rd = Rt >> sa (logical)
ef79bbde
P		 608
609/*********************************************************
610* Shift arithmetic with variant register shift *
611* Format: OP rd, rt, rs *
612*********************************************************/
f9ae4f29 613OP(psxSLLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) << (_u32(_rRs_) & 0x1F)); } // Rd = Rt << rs
614OP(psxSRAV) { dloadRt(regs_, _Rd_, _i32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (arithmetic)
615OP(psxSRLV) { dloadRt(regs_, _Rd_, _u32(_rRt_) >> (_u32(_rRs_) & 0x1F)); } // Rd = Rt >> rs (logical)
ef79bbde
P		 616
617/*********************************************************
618* Load higher 16 bits of the first word in GPR with imm *
619* Format: OP rt, immediate *
620*********************************************************/
f9ae4f29 621OP(psxLUI) { dloadRt(regs_, _Rt_, code << 16); } // Upper halfword of Rt = Im
ef79bbde
P		 622
623/*********************************************************
624* Move from HI/LO to GPR *
625* Format: OP rd *
626*********************************************************/
f9ae4f29 627OP(psxMFHI) { dloadRt(regs_, _Rd_, _rHi_); } // Rd = Hi
628OP(psxMFLO) { dloadRt(regs_, _Rd_, _rLo_); } // Rd = Lo
ef79bbde 629
4cc373dd 630static void mflohiCheckStall(psxRegisters *regs_)
32631e6a 631{
4cc373dd 632 u32 left = regs_->muldivBusyCycle - regs_->cycle;
32631e6a 633 if (left <= 37) {
634 //printf("muldiv stall %u\n", left);
4cc373dd 635 regs_->cycle = regs_->muldivBusyCycle;
32631e6a 636 }
637}
638
4cc373dd 639OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); }
640OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); }
32631e6a 641
ef79bbde
P		 642/*********************************************************
643* Move to GPR to HI/LO & Register jump *
644* Format: OP rs *
645*********************************************************/
4cc373dd 646OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs
647OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs
ef79bbde
P		 648
649/*********************************************************
650* Special purpose instructions *
651* Format: OP *
652*********************************************************/
4cc373dd 653OP(psxBREAK) {
bc7c5acb 654 intExceptionInsn(regs_, R3000E_Bp << 2);
ef79bbde
P		 655}
656
4cc373dd 657OP(psxSYSCALL) {
bc7c5acb 658 intExceptionInsn(regs_, R3000E_Syscall << 2);
ef79bbde
P		 659}
660
905b7c25 661static inline void execI_(u8 **memRLUT, psxRegisters *regs_);
662
663static inline void psxTestSWInts(psxRegisters *regs_, int step) {
bc7c5acb 664 if ((regs_->CP0.n.Cause & regs_->CP0.n.SR & 0x0300) &&
665 (regs_->CP0.n.SR & 0x1)) {
905b7c25 666 if (step)
667 execI_(psxMemRLUT, regs_);
4cc373dd 668 regs_->CP0.n.Cause &= ~0x7c;
f9ae4f29 669 intException(regs_, regs_->pc, regs_->CP0.n.Cause);
4cc373dd 670 }
671}
672
673OP(psxRFE) {
bc7c5acb 674 regs_->CP0.n.SR = (regs_->CP0.n.SR & ~0x0f) | ((regs_->CP0.n.SR & 0x3c) >> 2);
905b7c25 675 psxTestSWInts(regs_, 0);
ef79bbde
P		 676}
677
678/*********************************************************
679* Register branch logic *
680* Format: OP rs, rt, offset *
681*********************************************************/
bc7c5acb 682#define RepBranchi32(op) \
683 doBranch(regs_, _BranchTarget_, BrCond(_i32(_rRs_) op _i32(_rRt_)));
ef79bbde 684
4cc373dd 685OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt
686OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt
ef79bbde
P		 687
688/*********************************************************
689* Jump to target *
690* Format: OP target *
691*********************************************************/
bc7c5acb 692OP(psxJ) { doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN); }
693OP(psxJAL) {
694 dloadFlush(regs_);
695 _SetLink(31);
696 doBranch(regs_, _JumpTarget_, R3000A_BRANCH_TAKEN);
697}
ef79bbde
P		 698
699/*********************************************************
700* Register jump *
701* Format: OP rs, rd *
702*********************************************************/
4cc373dd 703OP(psxJR) {
b9698f9d 704 doBranchReg(regs_, _rRs_);
ef79bbde
P		 705 psxJumpTest();
706}
707
bc7c5acb 708OP(psxJRe) {
709 doBranchRegE(regs_, _rRs_);
710 psxJumpTest();
711}
712
4cc373dd 713OP(psxJALR) {
ef79bbde 714 u32 temp = _u32(_rRs_);
bc7c5acb 715 dloadFlush(regs_);
ef79bbde 716 if (_Rd_) { _SetLink(_Rd_); }
b9698f9d 717 doBranchReg(regs_, temp);
ef79bbde
P		 718}
719
bc7c5acb 720OP(psxJALRe) {
721 u32 temp = _u32(_rRs_);
722 dloadFlush(regs_);
723 if (_Rd_) { _SetLink(_Rd_); }
724 doBranchRegE(regs_, temp);
725}
726
ef79bbde 727/*********************************************************
ef79bbde
P		 728*********************************************************/
729
bc7c5acb 730// revisit: incomplete
731#define BUS_LOCKED_ADDR(a) \
732 ((0x1fc80000u <= (a) && (a) < 0x80000000u) || \
733 (0xc0000000u <= (a) && (a) < 0xfffe0000u))
734
735// exception checking order is important
736static inline int checkLD(psxRegisters *regs, u32 addr, u32 m) {
737 int bpException = 0;
738 if (unlikely(DBR_EN_LD(regs->CP0.n.DCIC, addr) &&
739 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
740 regs->CP0.n.DCIC |= 0x0d;
741 bpException = regs->CP0.n.DCIC >> 31;
742 }
f9ae4f29 743 if (unlikely(addr & m)) {
bc7c5acb 744 regs->CP0.n.BadVAddr = addr;
745 intExceptionInsn(regs, R3000E_AdEL << 2);
746 return 0;
747 }
748 if (unlikely(bpException)) {
749 intExceptionDebugBp(regs, regs->pc - 4);
750 return 0;
751 }
752 if (unlikely(BUS_LOCKED_ADDR(addr))) {
753 intException(regs, regs->pc - 4, R3000E_DBE << 2);
f9ae4f29 754 return 0;
f9ae4f29 755 }
756 return 1;
757}
758
bc7c5acb 759static inline int checkST(psxRegisters *regs, u32 addr, u32 m) {
760 int bpException = 0;
761 if (unlikely(DBR_EN_ST(regs->CP0.n.DCIC, addr) &&
762 ((addr ^ regs->CP0.n.BDA) & regs->CP0.n.BDAM) == 0)) {
763 regs->CP0.n.DCIC |= 0x15;
764 bpException = regs->CP0.n.DCIC >> 31;
765 }
f9ae4f29 766 if (unlikely(addr & m)) {
bc7c5acb 767 regs->CP0.n.BadVAddr = addr;
768 intExceptionInsn(regs, R3000E_AdES << 2);
769 return 0;
770 }
771 if (unlikely(bpException)) {
772 intExceptionDebugBp(regs, regs->pc - 4);
773 return 0;
774 }
775 if (unlikely(BUS_LOCKED_ADDR(addr))) {
776 intException(regs, regs->pc - 4, R3000E_DBE << 2);
f9ae4f29 777 return 0;
f9ae4f29 778 }
779 return 1;
780}
781
782/*********************************************************
783* Load and store for GPR *
784* Format: OP rt, offset(base) *
785*********************************************************/
786
bc7c5acb 787/*********************************************************
788* Load and store for GPR *
789* Format: OP rt, offset(base) *
790*********************************************************/
791
4cc373dd 792#define _oB_ (regs_->GPR.r[_Rs_] + _Imm_)
ef79bbde 793
bc7c5acb 794OP(psxLB) { doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
795OP(psxLBU) { doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
796OP(psxLH) { doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_ & ~1)); }
797OP(psxLHU) { doLoad(regs_, _Rt_, psxMemRead16(_oB_ & ~1)); }
798OP(psxLW) { doLoad(regs_, _Rt_, psxMemRead32(_oB_ & ~3)); }
ef79bbde 799
bc7c5acb 800OP(psxLBe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, (s8)psxMemRead8(_oB_)); }
801OP(psxLBUe) { if (checkLD(regs_, _oB_, 0)) doLoad(regs_, _Rt_, psxMemRead8(_oB_)); }
802OP(psxLHe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, (s16)psxMemRead16(_oB_)); }
803OP(psxLHUe) { if (checkLD(regs_, _oB_, 1)) doLoad(regs_, _Rt_, psxMemRead16(_oB_)); }
804OP(psxLWe) { if (checkLD(regs_, _oB_, 3)) doLoad(regs_, _Rt_, psxMemRead32(_oB_)); }
805
806static void doLWL(psxRegisters *regs, u32 rt, u32 addr) {
4cc373dd 807 static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 };
808 static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 };
ef79bbde 809 u32 shift = addr & 3;
bc7c5acb 810 u32 val, mem;
811 u32 oldval = regs->GPR.r[rt];
ef79bbde 812
f9ae4f29 813#ifdef HANDLE_LOAD_DELAY
bc7c5acb 814 int sel = regs->dloadSel;
815 if (regs->dloadReg[sel] == rt)
816 oldval = regs->dloadVal[sel];
f9ae4f29 817#endif
bc7c5acb 818 mem = psxMemRead32(addr & ~3);
f9ae4f29 819 val = (oldval & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]);
bc7c5acb 820 doLoad(regs, rt, val);
ef79bbde
P		 821
822 /*
823 Mem = 1234. Reg = abcd
824
825 0 4bcd (mem << 24) | (reg & 0x00ffffff)
826 1 34cd (mem << 16) | (reg & 0x0000ffff)
827 2 234d (mem << 8) | (reg & 0x000000ff)
828 3 1234 (mem ) | (reg & 0x00000000)
829 */
830}
831
bc7c5acb 832static void doLWR(psxRegisters *regs, u32 rt, u32 addr) {
4cc373dd 833 static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
834 static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
ef79bbde 835 u32 shift = addr & 3;
bc7c5acb 836 u32 val, mem;
837 u32 oldval = regs->GPR.r[rt];
ef79bbde 838
f9ae4f29 839#ifdef HANDLE_LOAD_DELAY
bc7c5acb 840 int sel = regs->dloadSel;
841 if (regs->dloadReg[sel] == rt)
842 oldval = regs->dloadVal[sel];
f9ae4f29 843#endif
bc7c5acb 844 mem = psxMemRead32(addr & ~3);
f9ae4f29 845 val = (oldval & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]);
bc7c5acb 846 doLoad(regs, rt, val);
ef79bbde
P		 847
848 /*
849 Mem = 1234. Reg = abcd
850
851 0 1234 (mem ) | (reg & 0x00000000)
852 1 a123 (mem >> 8) | (reg & 0xff000000)
853 2 ab12 (mem >> 16) | (reg & 0xffff0000)
854 3 abc1 (mem >> 24) | (reg & 0xffffff00)
855 */
856}
857
bc7c5acb 858OP(psxLWL) { doLWL(regs_, _Rt_, _oB_); }
859OP(psxLWR) { doLWR(regs_, _Rt_, _oB_); }
ef79bbde 860
bc7c5acb 861OP(psxLWLe) { if (checkLD(regs_, _oB_ & ~3, 0)) doLWL(regs_, _Rt_, _oB_); }
862OP(psxLWRe) { if (checkLD(regs_, _oB_ , 0)) doLWR(regs_, _Rt_, _oB_); }
ef79bbde 863
bc7c5acb 864OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); }
865OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
866OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
867
868OP(psxSBe) { if (checkST(regs_, _oB_, 0)) psxMemWrite8 (_oB_, _rRt_ & 0xff); }
869OP(psxSHe) { if (checkST(regs_, _oB_, 1)) psxMemWrite16(_oB_, _rRt_ & 0xffff); }
870OP(psxSWe) { if (checkST(regs_, _oB_, 3)) psxMemWrite32(_oB_, _rRt_); }
871
872static void doSWL(psxRegisters *regs, u32 rt, u32 addr) {
873 u32 val = regs->GPR.r[rt];
874 switch (addr & 3) {
875 case 0: psxMemWrite8( addr , val >> 24); break;
876 case 1: psxMemWrite16(addr & ~3, val >> 16); break;
877 case 2: // revisit: should be a single 24bit write
878 psxMemWrite16(addr & ~3, (val >> 8) & 0xffff);
879 psxMemWrite8( addr , val >> 24); break;
880 case 3: psxMemWrite32(addr & ~3, val); break;
881 }
ef79bbde
P		 882 /*
883 Mem = 1234. Reg = abcd
884
885 0 123a (reg >> 24) | (mem & 0xffffff00)
886 1 12ab (reg >> 16) | (mem & 0xffff0000)
887 2 1abc (reg >> 8) | (mem & 0xff000000)
888 3 abcd (reg ) | (mem & 0x00000000)
889 */
890}
891
bc7c5acb 892static void doSWR(psxRegisters *regs, u32 rt, u32 addr) {
893 u32 val = regs->GPR.r[rt];
894 switch (addr & 3) {
895 case 0: psxMemWrite32(addr , val); break;
896 case 1: // revisit: should be a single 24bit write
897 psxMemWrite8 (addr , val & 0xff);
898 psxMemWrite16(addr + 1, (val >> 8) & 0xffff); break;
899 case 2: psxMemWrite16(addr , val & 0xffff); break;
900 case 3: psxMemWrite8 (addr , val & 0xff); break;
901 }
ef79bbde
P		 902
903 /*
904 Mem = 1234. Reg = abcd
905
906 0 abcd (reg ) | (mem & 0x00000000)
907 1 bcd4 (reg << 8) | (mem & 0x000000ff)
908 2 cd34 (reg << 16) | (mem & 0x0000ffff)
909 3 d234 (reg << 24) | (mem & 0x00ffffff)
910 */
911}
912
bc7c5acb 913OP(psxSWL) { doSWL(regs_, _Rt_, _oB_); }
914OP(psxSWR) { doSWR(regs_, _Rt_, _oB_); }
915
916OP(psxSWLe) { if (checkST(regs_, _oB_ & ~3, 0)) doSWL(regs_, _Rt_, _oB_); }
917OP(psxSWRe) { if (checkST(regs_, _oB_ , 0)) doSWR(regs_, _Rt_, _oB_); }
918
ef79bbde
P		 919/*********************************************************
920* Moves between GPR and COPx *
921* Format: OP rt, fs *
922*********************************************************/
905b7c25 923OP(psxMFC0) {
924 u32 r = _Rd_;
925#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 926 if (unlikely(0x00000417u & (1u << r)))
927 intExceptionInsn(regs_, R3000E_RI << 2);
905b7c25 928#endif
f9ae4f29 929 doLoad(regs_, _Rt_, regs_->CP0.r[r]);
905b7c25 930}
931
905b7c25 932static void setupCop(u32 sr);
933
4cc373dd 934void MTC0(psxRegisters *regs_, int reg, u32 val) {
ef79bbde
P		 935// SysPrintf("MTC0 %d: %x\n", reg, val);
936 switch (reg) {
bc7c5acb 937 case 12: // SR
938 if (unlikely((regs_->CP0.n.SR ^ val) & (1 << 16)))
679d5ee3 939 psxMemOnIsolate((val >> 16) & 1);
bc7c5acb 940 if (unlikely((regs_->CP0.n.SR ^ val) & (7 << 29)))
905b7c25 941 setupCop(val);
bc7c5acb 942 regs_->CP0.n.SR = val;
905b7c25 943 psxTestSWInts(regs_, 1);
ef79bbde
P		 944 break;
945
946 case 13: // Cause
4cc373dd 947 regs_->CP0.n.Cause &= ~0x0300;
948 regs_->CP0.n.Cause |= val & 0x0300;
905b7c25 949 psxTestSWInts(regs_, 0);
ef79bbde
P		 950 break;
951
bc7c5acb 952 case 7:
953 if ((regs_->CP0.n.DCIC ^ val) & 0xff800000)
954 log_unhandled("DCIC: %08x->%08x\n", regs_->CP0.n.DCIC, val);
955 // fallthrough
ef79bbde 956 default:
4cc373dd 957 regs_->CP0.r[reg] = val;
ef79bbde
P		 958 break;
959 }
960}
961
4cc373dd 962OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
ef79bbde 963
bc7c5acb 964// no exception
965static inline void psxNULLne(psxRegisters *regs) {
966 log_unhandled("unhandled op %08x @%08x\n", regs->code, regs->pc - 4);
967}
968
ef79bbde 969/*********************************************************
905b7c25 970* Unknown instruction (would generate an exception) *
ef79bbde
P		 971* Format: ? *
972*********************************************************/
905b7c25 973
974OP(psxNULL) {
bc7c5acb 975 psxNULLne(regs_);
905b7c25 976#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 977 intExceptionInsn(regs_, R3000E_RI << 2);
ef79bbde
P		 978#endif
979}
980
905b7c25 981void gteNULL(struct psxCP2Regs *regs) {
bc7c5acb 982 psxRegisters *regs_ = (psxRegisters *)((u8 *)regs - offsetof(psxRegisters, CP2));
983 psxNULLne(regs_);
905b7c25 984}
ef79bbde 985
4cc373dd 986OP(psxSPECIAL) {
987 psxSPC[_Funct_](regs_, code);
ef79bbde
P		 988}
989
4cc373dd 990OP(psxCOP0) {
3d1c03e7 991 u32 rs = _Rs_;
992 if (rs & 0x10) {
993 u32 op2 = code & 0x1f;
994 switch (op2) {
995 case 0x01:
996 case 0x02:
997 case 0x06:
998 case 0x08: psxNULL(regs_, code); break;
999 case 0x10: psxRFE(regs_, code); break;
1000 default: psxNULLne(regs_); break;
1001 }
1002 return;
1003 }
1004 switch (rs) {
4cc373dd 1005 case 0x00: psxMFC0(regs_, code); break;
4cc373dd 1006 case 0x04: psxMTC0(regs_, code); break;
3d1c03e7 1007 case 0x02: // CFC
1008 case 0x06: psxNULL(regs_, code); break; // CTC -> exception
1009 case 0x08:
1010 case 0x0c: log_unhandled("BC0 %08x @%08x\n", code, regs_->pc - 4);
bc7c5acb 1011 default: psxNULLne(regs_); break;
4cc373dd 1012 }
ef79bbde
P		 1013}
1014
905b7c25 1015OP(psxCOP1) {
1016 // ??? what actually happens here?
bc7c5acb 1017 log_unhandled("COP1 %08x @%08x\n", code, regs_->pc - 4);
905b7c25 1018}
1019
4cc373dd 1020OP(psxCOP2) {
3d1c03e7 1021 u32 rt = _Rt_, rd = _Rd_, rs = _Rs_;
1022 if (rs & 0x10) {
1023 psxCP2[_Funct_](&regs_->CP2);
1024 return;
1025 }
1026 switch (rs) {
1027 case 0x00: doLoad(regs_, rt, MFC2(&regs_->CP2, rd)); break; // MFC2
1028 case 0x02: doLoad(regs_, rt, regs_->CP2C.r[rd]); break; // CFC2
1029 case 0x04: MTC2(&regs_->CP2, regs_->GPR.r[rt], rd); break; // MTC2
1030 case 0x06: CTC2(&regs_->CP2, regs_->GPR.r[rt], rd); break; // CTC2
1031 case 0x08:
1032 case 0x0c: log_unhandled("BC2 %08x @%08x\n", code, regs_->pc - 4);
1033 default: psxNULLne(regs_); break;
1034 }
32631e6a 1035}
1036
4cc373dd 1037OP(psxCOP2_stall) {
81dbbf4c 1038 u32 f = _Funct_;
32631e6a 1039 gteCheckStall(f);
3d1c03e7 1040 psxCOP2(regs_, code);
4cc373dd 1041}
1042
1043OP(gteLWC2) {
1044 MTC2(&regs_->CP2, psxMemRead32(_oB_), _Rt_);
1045}
1046
4cc373dd 1047OP(gteLWC2_stall) {
1048 gteCheckStall(0);
1049 gteLWC2(regs_, code);
ef79bbde
P		 1050}
1051
bc7c5acb 1052OP(gteLWC2e_stall) {
1053 gteCheckStall(0);
1054 if (checkLD(regs_, _oB_, 3))
1055 MTC2(&regs_->CP2, psxMemRead32(_oB_), _Rt_);
1056}
1057
1058OP(gteSWC2) {
1059 psxMemWrite32(_oB_, MFC2(&regs_->CP2, _Rt_));
1060}
1061
4cc373dd 1062OP(gteSWC2_stall) {
1063 gteCheckStall(0);
1064 gteSWC2(regs_, code);
1065}
1066
bc7c5acb 1067OP(gteSWC2e_stall) {
1068 gteCheckStall(0);
1069 if (checkST(regs_, _oB_, 3))
1070 gteSWC2(regs_, code);
1071}
1072
905b7c25 1073OP(psxCOP3) {
1074 // ??? what actually happens here?
bc7c5acb 1075 log_unhandled("COP3 %08x @%08x\n", code, regs_->pc - 4);
905b7c25 1076}
1077
bc7c5acb 1078OP(psxCOPd) {
1079 log_unhandled("disabled cop%d @%08x\n", (code >> 26) & 3, regs_->pc - 4);
905b7c25 1080#ifdef DO_EXCEPTION_RESERVEDI
bc7c5acb 1081 intExceptionInsn(regs_, R3000E_CpU << 2);
905b7c25 1082#endif
1083}
1084
1085OP(psxLWCx) {
bc7c5acb 1086 log_unhandled("LWCx %08x @%08x\n", code, regs_->pc - 4);
1087 checkLD(regs_, _oB_, 3);
905b7c25 1088}
1089
1090OP(psxSWCx) {
1091 // does this write something to memory?
bc7c5acb 1092 log_unhandled("SWCx %08x @%08x\n", code, regs_->pc - 4);
1093 checkST(regs_, _oB_, 3);
905b7c25 1094}
1095
4cc373dd 1096OP(psxREGIMM) {
19fae7fc 1097 u32 rt = _Rt_;
1098 switch (rt) {
4cc373dd 1099 case 0x10: psxBLTZAL(regs_, code); break;
1100 case 0x11: psxBGEZAL(regs_, code); break;
19fae7fc 1101 default:
1102 if (rt & 1)
1103 psxBGEZ(regs_, code);
1104 else
1105 psxBLTZ(regs_, code);
4cc373dd 1106 }
ef79bbde
P		 1107}
1108
4cc373dd 1109OP(psxHLE) {
905b7c25 1110 u32 hleCode;
1111 if (unlikely(!Config.HLE)) {
1112 psxSWCx(regs_, code);
1113 return;
1114 }
1115 hleCode = code & 0x03ffffff;
1116 if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) {
1117 psxSWCx(regs_, code);
1118 return;
1119 }
1120 psxHLEt[hleCode]();
ef79bbde
P		 1121}
1122
4cc373dd 1123static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
ef79bbde
P		 1124 psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
1125 psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
bc7c5acb 1126 psxCOP0 , psxCOPd , psxCOP2, psxCOPd, psxNULL, psxNULL, psxNULL, psxNULL,
1127 psxNULL , psxNULL , psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL,
1128 psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL,
1129 psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL,
1130 psxLWCx , psxLWCx , gteLWC2, psxLWCx , psxNULL, psxNULL, psxNULL, psxNULL,
1131 psxSWCx , psxSWCx , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL,
ef79bbde
P		 1132};
1133
4cc373dd 1134static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = {
ef79bbde
P		 1135 psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV,
1136 psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
1137 psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL,
1138 psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL,
1139 psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR ,
1140 psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL,
1141 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL,
1142 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL
1143};
1144
6c0eefaf 1145void (*psxCP2[64])(struct psxCP2Regs *regs) = {
3d1c03e7 1146 gteNULL , gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00
4cc373dd 1147 gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08
1148 gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10
1149 gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18
1150 gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20
1151 gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28
1152 gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30
1153 gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38
ef79bbde
P		 1154};
1155
ef79bbde
P		 1156///////////////////////////////////////////
1157
1158static int intInit() {
1159 return 0;
1160}
1161
1162static void intReset() {
f9ae4f29 1163 dloadClear(&psxRegs);
3d1c03e7 1164 psxRegs.subCycle = 0;
ef79bbde
P		 1165}
1166
bc7c5acb 1167static inline void execI_(u8 **memRLUT, psxRegisters *regs) {
1168 u32 pc = regs->pc;
905b7c25 1169
bc7c5acb 1170 addCycle(regs);
1171 dloadStep(regs);
4cc373dd 1172
bc7c5acb 1173 regs->pc += 4;
1174 regs->code = fetch(regs, memRLUT, pc);
1175 psxBSC[regs->code >> 26](regs, regs->code);
1176}
1177
1178static inline void execIbp(u8 **memRLUT, psxRegisters *regs) {
1179 u32 pc = regs->pc;
1180
1181 addCycle(regs);
1182 dloadStep(regs);
1183
1184 if (execBreakCheck(regs, pc))
1185 return;
1186
1187 regs->pc += 4;
1188 regs->code = fetch(regs, memRLUT, pc);
1189 psxBSC[regs->code >> 26](regs, regs->code);
4cc373dd 1190}
1191
1192static void intExecute() {
1193 psxRegisters *regs_ = &psxRegs;
1194 u8 **memRLUT = psxMemRLUT;
796a91ef 1195 extern int stop;
4cc373dd 1196
1197 while (!stop)
1198 execI_(memRLUT, regs_);
ef79bbde
P		 1199}
1200
bc7c5acb 1201static void intExecuteBp() {
1202 psxRegisters *regs_ = &psxRegs;
1203 u8 **memRLUT = psxMemRLUT;
1204 extern int stop;
1205
1206 while (!stop)
1207 execIbp(memRLUT, regs_);
1208}
1209
da65071f 1210void intExecuteBlock(enum blockExecCaller caller) {
4cc373dd 1211 psxRegisters *regs_ = &psxRegs;
1212 u8 **memRLUT = psxMemRLUT;
1213
bc7c5acb 1214 branchSeen = 0;
1215 while (!branchSeen)
4cc373dd 1216 execI_(memRLUT, regs_);
ef79bbde
P		 1217}
1218
1219static void intClear(u32 Addr, u32 Size) {
1220}
1221
980f7a58 1222static void intNotify(enum R3000Anote note, void *data) {
1223 switch (note) {
f9ae4f29 1224 case R3000ACPU_NOTIFY_BEFORE_SAVE:
1225 dloadFlush(&psxRegs);
1226 break;
980f7a58 1227 case R3000ACPU_NOTIFY_AFTER_LOAD:
f9ae4f29 1228 dloadClear(&psxRegs);
3d1c03e7 1229 psxRegs.subCycle = 0;
bc7c5acb 1230 setupCop(psxRegs.CP0.n.SR);
905b7c25 1231 // fallthrough
1232 case R3000ACPU_NOTIFY_CACHE_ISOLATED: // Armored Core?
9f84fc93 1233 memset(&ICache, 0xff, sizeof(ICache));
980f7a58 1234 break;
1235 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
980f7a58 1236 break;
943a507a 1237 }
943a507a 1238}
1239
905b7c25 1240static void setupCop(u32 sr)
1241{
1242 if (sr & (1u << 29))
1243 psxBSC[17] = psxCOP1;
1244 else
bc7c5acb 1245 psxBSC[17] = psxCOPd;
905b7c25 1246 if (sr & (1u << 30))
1247 psxBSC[18] = Config.DisableStalls ? psxCOP2 : psxCOP2_stall;
1248 else
bc7c5acb 1249 psxBSC[18] = psxCOPd;
905b7c25 1250 if (sr & (1u << 31))
1251 psxBSC[19] = psxCOP3;
1252 else
bc7c5acb 1253 psxBSC[19] = psxCOPd;
905b7c25 1254}
1255
61ad2a61 1256void intApplyConfig() {
d5aeda23 1257 int cycle_mult;
1258
32631e6a 1259 assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall);
1260 assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall);
1261 assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall);
1262 assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall);
1263 assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall);
1264 assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall);
1265
1266 if (Config.DisableStalls) {
1267 psxBSC[18] = psxCOP2;
1268 psxBSC[50] = gteLWC2;
1269 psxBSC[58] = gteSWC2;
1270 psxSPC[16] = psxMFHI;
1271 psxSPC[18] = psxMFLO;
1272 psxSPC[24] = psxMULT;
1273 psxSPC[25] = psxMULTU;
1274 psxSPC[26] = psxDIV;
1275 psxSPC[27] = psxDIVU;
1276 } else {
1277 psxBSC[18] = psxCOP2_stall;
1278 psxBSC[50] = gteLWC2_stall;
1279 psxBSC[58] = gteSWC2_stall;
1280 psxSPC[16] = psxMFHI_stall;
1281 psxSPC[18] = psxMFLO_stall;
1282 psxSPC[24] = psxMULT_stall;
1283 psxSPC[25] = psxMULTU_stall;
1284 psxSPC[26] = psxDIV_stall;
1285 psxSPC[27] = psxDIVU_stall;
1286 }
bc7c5acb 1287 setupCop(psxRegs.CP0.n.SR);
1288
1289 if (Config.PreciseExceptions) {
1290 psxBSC[0x20] = psxLBe;
1291 psxBSC[0x21] = psxLHe;
1292 psxBSC[0x22] = psxLWLe;
1293 psxBSC[0x23] = psxLWe;
1294 psxBSC[0x24] = psxLBUe;
1295 psxBSC[0x25] = psxLHUe;
1296 psxBSC[0x26] = psxLWRe;
1297 psxBSC[0x28] = psxSBe;
1298 psxBSC[0x29] = psxSHe;
1299 psxBSC[0x2a] = psxSWLe;
1300 psxBSC[0x2b] = psxSWe;
1301 psxBSC[0x2e] = psxSWRe;
1302 psxBSC[0x32] = gteLWC2e_stall;
1303 psxBSC[0x3a] = gteSWC2e_stall;
1304 psxSPC[0x08] = psxJRe;
1305 psxSPC[0x09] = psxJALRe;
1306 psxInt.Execute = intExecuteBp;
1307 } else {
1308 psxBSC[0x20] = psxLB;
1309 psxBSC[0x21] = psxLH;
1310 psxBSC[0x22] = psxLWL;
1311 psxBSC[0x23] = psxLW;
1312 psxBSC[0x24] = psxLBU;
1313 psxBSC[0x25] = psxLHU;
1314 psxBSC[0x26] = psxLWR;
1315 psxBSC[0x28] = psxSB;
1316 psxBSC[0x29] = psxSH;
1317 psxBSC[0x2a] = psxSWL;
1318 psxBSC[0x2b] = psxSW;
1319 psxBSC[0x2e] = psxSWR;
1320 // LWC2, SWC2 handled by Config.DisableStalls
1321 psxSPC[0x08] = psxJR;
1322 psxSPC[0x09] = psxJALR;
1323 psxInt.Execute = intExecute;
1324 }
61ad2a61 1325
bc7c5acb 1326 // the dynarec may occasionally call the interpreter, in such a case the
61ad2a61 1327 // cache won't work (cache only works right if all fetches go through it)
1328 if (!Config.icache_emulation || psxCpu != &psxInt)
1329 fetch = fetchNoCache;
1330 else
1331 fetch = fetchICache;
d5aeda23 1332
1333 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
1334 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
1335 psxRegs.subCycleStep = 0x10000 * cycle_mult / 100;
32631e6a 1336}
1337
ef79bbde 1338static void intShutdown() {
a5cd72d0 1339 dloadClear(&psxRegs);
ef79bbde
P		 1340}
1341
a5cd72d0 1342// single step (may do several ops in case of a branch or load delay)
bc7c5acb 1343void execI(psxRegisters *regs) {
a5cd72d0 1344 do {
1345 execIbp(psxMemRLUT, regs);
1346 } while (regs->dloadReg[0] || regs->dloadReg[1]);
ef79bbde
P		 1347}
1348
1349R3000Acpu psxInt = {
1350 intInit,
1351 intReset,
1352 intExecute,
1353 intExecuteBlock,
1354 intClear,
943a507a 1355 intNotify,
61ad2a61 1356 intApplyConfig,
ef79bbde
P		 1357 intShutdown
1358};
ARM optimized PCSX fork