[pcsx_rearmed.git] / libpcsxcore / r3000a.h

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

#ifndef __R3000A_H__
#define __R3000A_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "psxcommon.h"
#include "psxmem.h"
#include "psxcounters.h"
#include "psxbios.h"

typedef struct {
	int  (*Init)();
	void (*Reset)();
	void (*Execute)();		/* executes up to a break */
	void (*ExecuteBlock)();	/* executes up to a jump */
	void (*Clear)(u32 Addr, u32 Size);
	void (*Shutdown)();
} R3000Acpu;

extern R3000Acpu *psxCpu;
extern R3000Acpu psxInt;
extern R3000Acpu psxRec;

typedef union {
#if defined(__BIGENDIAN__)
	struct { u8 h3, h2, h, l; } b;
	struct { s8 h3, h2, h, l; } sb;
	struct { u16 h, l; } w;
	struct { s16 h, l; } sw;
#else
	struct { u8 l, h, h2, h3; } b;
	struct { u16 l, h; } w;
	struct { s8 l, h, h2, h3; } sb;
	struct { s16 l, h; } sw;
#endif
} PAIR;

typedef union {
	struct {
		u32   r0, at, v0, v1, a0, a1, a2, a3,
						t0, t1, t2, t3, t4, t5, t6, t7,
						s0, s1, s2, s3, s4, s5, s6, s7,
						t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	} n;
	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	PAIR p[34];
} psxGPRRegs;

typedef union {
	struct {
		u32	Index,     Random,    EntryLo0,  EntryLo1,
						Context,   PageMask,  Wired,     Reserved0,
						BadVAddr,  Count,     EntryHi,   Compare,
						Status,    Cause,     EPC,       PRid,
						Config,    LLAddr,    WatchLO,   WatchHI,
						XContext,  Reserved1, Reserved2, Reserved3,
						Reserved4, Reserved5, ECC,       CacheErr,
						TagLo,     TagHi,     ErrorEPC,  Reserved6;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP0Regs;

typedef struct {
	short x, y;
} SVector2D;

typedef struct {
	short z, pad;
} SVector2Dz;

typedef struct {
	short x, y, z, pad;
} SVector3D;

typedef struct {
	short x, y, z, pad;
} LVector3D;

typedef struct {
	unsigned char r, g, b, c;
} CBGR;

typedef struct {
	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
} SMatrix3D;

typedef union {
	struct {
		SVector3D     v0, v1, v2;
		CBGR          rgb;
		s32          otz;
		s32          ir0, ir1, ir2, ir3;
		SVector2D     sxy0, sxy1, sxy2, sxyp;
		SVector2Dz    sz0, sz1, sz2, sz3;
		CBGR          rgb0, rgb1, rgb2;
		s32          reserved;
		s32          mac0, mac1, mac2, mac3;
		u32 irgb, orgb;
		s32          lzcs, lzcr;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Data;

typedef union {
	struct {
		SMatrix3D rMatrix;
		s32      trX, trY, trZ;
		SMatrix3D lMatrix;
		s32      rbk, gbk, bbk;
		SMatrix3D cMatrix;
		s32      rfc, gfc, bfc;
		s32      ofx, ofy;
		s32      h;
		s32      dqa, dqb;
		s32      zsf3, zsf4;
		s32      flag;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Ctrl;

enum {
	PSXINT_SIO = 0,
	PSXINT_CDR,
	PSXINT_CDREAD,
	PSXINT_GPUDMA,
	PSXINT_MDECOUTDMA,
	PSXINT_SPUDMA,
	PSXINT_GPUBUSY,
	PSXINT_MDECINDMA,
	PSXINT_GPUOTCDMA,
	PSXINT_CDRDMA,
	PSXINT_NEWDRC_CHECK,
	PSXINT_RCNT,
	PSXINT_CDRLID,
	PSXINT_CDRPLAY,
	PSXINT_SPU_UPDATE,
	PSXINT_COUNT
};

typedef struct psxCP2Regs {
	psxCP2Data CP2D; 	/* Cop2 data registers */
	psxCP2Ctrl CP2C; 	/* Cop2 control registers */
} psxCP2Regs;

typedef struct {
	psxGPRRegs GPR;		/* General Purpose Registers */
	psxCP0Regs CP0;		/* Coprocessor0 Registers */
	union {
		struct {
			psxCP2Data CP2D; 	/* Cop2 data registers */
			psxCP2Ctrl CP2C; 	/* Cop2 control registers */
		};
		psxCP2Regs CP2;
	};
    u32 pc;				/* Program counter */
    u32 code;			/* The instruction */
	u32 cycle;
	u32 interrupt;
	struct { u32 sCycle, cycle; } intCycle[32];
} psxRegisters;

extern psxRegisters psxRegs;

/* new_dynarec stuff */
extern u32 event_cycles[PSXINT_COUNT];
extern u32 next_interupt;

void new_dyna_before_save(void);
void new_dyna_after_save(void);
void new_dyna_freeze(void *f, int mode);

#define new_dyna_set_event(e, c) { \
	s32 c_ = c; \
	u32 abs_ = psxRegs.cycle + c_; \
	s32 odi_ = next_interupt - psxRegs.cycle; \
	event_cycles[e] = abs_; \
	if (c_ < odi_) { \
		/*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
		next_interupt = abs_; \
	} \
}

#if defined(__BIGENDIAN__)

#define _i32(x) *(s32 *)&x
#define _u32(x) x

#define _i16(x) (((short *)&x)[1])
#define _u16(x) (((unsigned short *)&x)[1])

#define _i8(x) (((char *)&x)[3])
#define _u8(x) (((unsigned char *)&x)[3])

#else

#define _i32(x) *(s32 *)&x
#define _u32(x) x

#define _i16(x) *(short *)&x
#define _u16(x) *(unsigned short *)&x

#define _i8(x) *(char *)&x
#define _u8(x) *(unsigned char *)&x

#endif

/**** R3000A Instruction Macros ****/
#define _PC_       psxRegs.pc       // The next PC to be executed

#define _fOp_(code)		((code >> 26)       )  // The opcode part of the instruction register 
#define _fFunct_(code)	((code      ) & 0x3F)  // The funct part of the instruction register 
#define _fRd_(code)		((code >> 11) & 0x1F)  // The rd part of the instruction register 
#define _fRt_(code)		((code >> 16) & 0x1F)  // The rt part of the instruction register 
#define _fRs_(code)		((code >> 21) & 0x1F)  // The rs part of the instruction register 
#define _fSa_(code)		((code >>  6) & 0x1F)  // The sa part of the instruction register
#define _fIm_(code)		((u16)code)            // The immediate part of the instruction register
#define _fTarget_(code)	(code & 0x03ffffff)    // The target part of the instruction register

#define _fImm_(code)	((s16)code)            // sign-extended immediate
#define _fImmU_(code)	(code&0xffff)          // zero-extended immediate

#define _Op_     _fOp_(psxRegs.code)
#define _Funct_  _fFunct_(psxRegs.code)
#define _Rd_     _fRd_(psxRegs.code)
#define _Rt_     _fRt_(psxRegs.code)
#define _Rs_     _fRs_(psxRegs.code)
#define _Sa_     _fSa_(psxRegs.code)
#define _Im_     _fIm_(psxRegs.code)
#define _Target_ _fTarget_(psxRegs.code)

#define _Imm_	 _fImm_(psxRegs.code)
#define _ImmU_	 _fImmU_(psxRegs.code)

#define _rRs_   psxRegs.GPR.r[_Rs_]   // Rs register
#define _rRt_   psxRegs.GPR.r[_Rt_]   // Rt register
#define _rRd_   psxRegs.GPR.r[_Rd_]   // Rd register
#define _rSa_   psxRegs.GPR.r[_Sa_]   // Sa register
#define _rFs_   psxRegs.CP0.r[_Rd_]   // Fs register

#define _c2dRs_ psxRegs.CP2D.r[_Rs_]  // Rs cop2 data register
#define _c2dRt_ psxRegs.CP2D.r[_Rt_]  // Rt cop2 data register
#define _c2dRd_ psxRegs.CP2D.r[_Rd_]  // Rd cop2 data register
#define _c2dSa_ psxRegs.CP2D.r[_Sa_]  // Sa cop2 data register

#define _rHi_   psxRegs.GPR.n.hi   // The HI register
#define _rLo_   psxRegs.GPR.n.lo   // The LO register

#define _JumpTarget_    ((_Target_ * 4) + (_PC_ & 0xf0000000))   // Calculates the target during a jump instruction
#define _BranchTarget_  ((s16)_Im_ * 4 + _PC_)                 // Calculates the target during a branch instruction

#define _SetLink(x)     psxRegs.GPR.r[x] = _PC_ + 4;       // Sets the return address in the link register

int  psxInit();
void psxReset();
void psxShutdown();
void psxException(u32 code, u32 bd);
void psxBranchTest();
void psxExecuteBios();
int  psxTestLoadDelay(int reg, u32 tmp);
void psxDelayTest(int reg, u32 bpc);
void psxTestSWInts();
void psxJumpTest();

#ifdef __cplusplus
}
#endif
#endif
Commit	Line	Data
ef79bbde P	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	#ifndef __R3000A_H__
	21	#define __R3000A_H__
	22
	23	#ifdef __cplusplus
	24	extern "C" {
	25	#endif
	26
	27	#include "psxcommon.h"
	28	#include "psxmem.h"
	29	#include "psxcounters.h"
	30	#include "psxbios.h"
	31
	32	typedef struct {
	33	int (*Init)();
	34	void (*Reset)();
	35	void (Execute)(); / executes up to a break */
	36	void (ExecuteBlock)(); / executes up to a jump */
	37	void (*Clear)(u32 Addr, u32 Size);
	38	void (*Shutdown)();
	39	} R3000Acpu;
	40
	41	extern R3000Acpu *psxCpu;
	42	extern R3000Acpu psxInt;
ef79bbde	43	extern R3000Acpu psxRec;
ef79bbde P	44
	45	typedef union {
	46	#if defined(__BIGENDIAN__)
	47	struct { u8 h3, h2, h, l; } b;
	48	struct { s8 h3, h2, h, l; } sb;
	49	struct { u16 h, l; } w;
	50	struct { s16 h, l; } sw;
	51	#else
	52	struct { u8 l, h, h2, h3; } b;
	53	struct { u16 l, h; } w;
	54	struct { s8 l, h, h2, h3; } sb;
	55	struct { s16 l, h; } sw;
	56	#endif
	57	} PAIR;
	58
	59	typedef union {
	60	struct {
	61	u32 r0, at, v0, v1, a0, a1, a2, a3,
	62	t0, t1, t2, t3, t4, t5, t6, t7,
	63	s0, s1, s2, s3, s4, s5, s6, s7,
	64	t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	65	} n;
	66	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	67	PAIR p[34];
	68	} psxGPRRegs;
	69
	70	typedef union {
	71	struct {
	72	u32 Index, Random, EntryLo0, EntryLo1,
	73	Context, PageMask, Wired, Reserved0,
	74	BadVAddr, Count, EntryHi, Compare,
	75	Status, Cause, EPC, PRid,
	76	Config, LLAddr, WatchLO, WatchHI,
	77	XContext, Reserved1, Reserved2, Reserved3,
	78	Reserved4, Reserved5, ECC, CacheErr,
	79	TagLo, TagHi, ErrorEPC, Reserved6;
	80	} n;
	81	u32 r[32];
	82	PAIR p[32];
	83	} psxCP0Regs;
	84
	85	typedef struct {
	86	short x, y;
	87	} SVector2D;
	88
	89	typedef struct {
	90	short z, pad;
	91	} SVector2Dz;
	92
	93	typedef struct {
	94	short x, y, z, pad;
	95	} SVector3D;
	96
	97	typedef struct {
	98	short x, y, z, pad;
	99	} LVector3D;
	100
	101	typedef struct {
	102	unsigned char r, g, b, c;
	103	} CBGR;
	104
	105	typedef struct {
	106	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
	107	} SMatrix3D;
108
109	typedef union {
110	struct {
111	SVector3D v0, v1, v2;
112	CBGR rgb;
113	s32 otz;
114	s32 ir0, ir1, ir2, ir3;
115	SVector2D sxy0, sxy1, sxy2, sxyp;
116	SVector2Dz sz0, sz1, sz2, sz3;
117	CBGR rgb0, rgb1, rgb2;
118	s32 reserved;
119	s32 mac0, mac1, mac2, mac3;
120	u32 irgb, orgb;
121	s32 lzcs, lzcr;
122	} n;
123	u32 r[32];
124	PAIR p[32];
125	} psxCP2Data;
126
127	typedef union {
128	struct {
129	SMatrix3D rMatrix;
130	s32 trX, trY, trZ;
131	SMatrix3D lMatrix;
132	s32 rbk, gbk, bbk;
133	SMatrix3D cMatrix;
134	s32 rfc, gfc, bfc;
135	s32 ofx, ofy;
136	s32 h;
137	s32 dqa, dqb;
138	s32 zsf3, zsf4;
139	s32 flag;
140	} n;
141	u32 r[32];
142	PAIR p[32];
143	} psxCP2Ctrl;
144
d28b54b1	145	enum {
	146	PSXINT_SIO = 0,
	147	PSXINT_CDR,
	148	PSXINT_CDREAD,
	149	PSXINT_GPUDMA,
	150	PSXINT_MDECOUTDMA,
	151	PSXINT_SPUDMA,
528ad661	152	PSXINT_GPUBUSY,
528ad661	153	PSXINT_MDECINDMA,
57a757ce	154	PSXINT_GPUOTCDMA,
9f8b032d	155	PSXINT_CDRDMA,
d28b54b1	156	PSXINT_NEWDRC_CHECK,
5b8c000f	157	PSXINT_RCNT,
9f8b032d	158	PSXINT_CDRLID,
7f457614	159	PSXINT_CDRPLAY,
2b30c129	160	PSXINT_SPU_UPDATE,
d28b54b1	161	PSXINT_COUNT
	162	};
	163
eac38522	164	typedef struct psxCP2Regs {
	165	psxCP2Data CP2D; /* Cop2 data registers */
	166	psxCP2Ctrl CP2C; /* Cop2 control registers */
	167	} psxCP2Regs;
	168
ef79bbde P	169	typedef struct {
	170	psxGPRRegs GPR; /* General Purpose Registers */
	171	psxCP0Regs CP0; /* Coprocessor0 Registers */
eac38522	172	union {
	173	struct {
	174	psxCP2Data CP2D; /* Cop2 data registers */
	175	psxCP2Ctrl CP2C; /* Cop2 control registers */
	176	};
	177	psxCP2Regs CP2;
	178	};
ef79bbde P	179	u32 pc; /* Program counter */
	180	u32 code; /* The instruction */
	181	u32 cycle;
	182	u32 interrupt;
d28b54b1	183	struct { u32 sCycle, cycle; } intCycle[32];
ef79bbde P	184	} psxRegisters;
	185
	186	extern psxRegisters psxRegs;
	187
d28b54b1	188	/* new_dynarec stuff */
	189	extern u32 event_cycles[PSXINT_COUNT];
	190	extern u32 next_interupt;
	191
03f55e6b	192	void new_dyna_before_save(void);
5b8c000f	193	void new_dyna_after_save(void);
03f55e6b	194	void new_dyna_freeze(void *f, int mode);
52082bc1	195
d28b54b1	196	#define new_dyna_set_event(e, c) { \
	197	s32 c_ = c; \
	198	u32 abs_ = psxRegs.cycle + c_; \
	199	s32 odi_ = next_interupt - psxRegs.cycle; \
	200	event_cycles[e] = abs_; \
	201	if (c_ < odi_) { \
	202	/printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);/ \
	203	next_interupt = abs_; \
	204	} \
	205	}
	206
ef79bbde P	207	#if defined(__BIGENDIAN__)
	208
	209	#define _i32(x) (s32 )&x
	210	#define _u32(x) x
	211
	212	#define _i16(x) (((short *)&x)[1])
	213	#define _u16(x) (((unsigned short *)&x)[1])
	214
	215	#define _i8(x) (((char *)&x)[3])
	216	#define _u8(x) (((unsigned char *)&x)[3])
	217
	218	#else
	219
	220	#define _i32(x) (s32 )&x
	221	#define _u32(x) x
	222
	223	#define _i16(x) (short )&x
	224	#define _u16(x) (unsigned short )&x
	225
	226	#define _i8(x) (char )&x
	227	#define _u8(x) (unsigned char )&x
	228
	229	#endif
	230
	231	/** R3000A Instruction Macros **/
	232	#define _PC_ psxRegs.pc // The next PC to be executed
	233
	234	#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
	235	#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
	236	#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
	237	#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
	238	#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
	239	#define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
	240	#define _fIm_(code) ((u16)code) // The immediate part of the instruction register
	241	#define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
	242
	243	#define _fImm_(code) ((s16)code) // sign-extended immediate
	244	#define _fImmU_(code) (code&0xffff) // zero-extended immediate
	245
	246	#define _Op_ _fOp_(psxRegs.code)
	247	#define _Funct_ _fFunct_(psxRegs.code)
	248	#define _Rd_ _fRd_(psxRegs.code)
	249	#define _Rt_ _fRt_(psxRegs.code)
	250	#define _Rs_ _fRs_(psxRegs.code)
	251	#define _Sa_ _fSa_(psxRegs.code)
	252	#define _Im_ _fIm_(psxRegs.code)
	253	#define _Target_ _fTarget_(psxRegs.code)
	254
	255	#define _Imm_ _fImm_(psxRegs.code)
	256	#define _ImmU_ _fImmU_(psxRegs.code)
	257
	258	#define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register
	259	#define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register
	260	#define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register
	261	#define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register
	262	#define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register
	263
	264	#define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register
	265	#define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register
	266	#define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register
	267	#define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register
	268
	269	#define _rHi_ psxRegs.GPR.n.hi // The HI register
	270	#define _rLo_ psxRegs.GPR.n.lo // The LO register
271
272	#define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
273	#define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
274
275	#define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
276
277	int psxInit();
278	void psxReset();
279	void psxShutdown();
280	void psxException(u32 code, u32 bd);
281	void psxBranchTest();
282	void psxExecuteBios();
283	int psxTestLoadDelay(int reg, u32 tmp);
284	void psxDelayTest(int reg, u32 bpc);
285	void psxTestSWInts();
286	void psxJumpTest();
287
288	#ifdef __cplusplus
289	}
290	#endif
291	#endif