psx_gpu: implement setup_sprite_untextured in asm
[pcsx_rearmed.git] / plugins / gpu_neon / psx_gpu / psx_gpu_arm_neon.S
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1/*
2 * Copyright (C) 2011 Gilead Kutnick "Exophase" <exophase@gmail.com>
59d15d23 3 * Copyright (C) 2012 GraÅžvydas Ignotas "notaz" <notasas@gmail.com>
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4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15
16#define MAX_SPANS 512
17#define MAX_BLOCKS 64
18#define MAX_BLOCKS_PER_ROW 128
19
f0931e56 20#define RENDER_STATE_MASK_EVALUATE 0x20
21#define RENDER_FLAGS_MODULATE_TEXELS 0x1
22#define RENDER_FLAGS_BLEND 0x2
23
cb88320b 24#include "psx_gpu_offsets.h"
75e28f62 25
cb88320b 26#define psx_gpu_b_dx_offset (psx_gpu_b_block_span_offset + 4)
75e28f62 27
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28#define edge_data_left_x_offset 0
29#define edge_data_num_blocks_offset 2
30#define edge_data_right_mask_offset 4
31#define edge_data_y_offset 6
32
33
34#define psx_gpu r0
35#define v_a r1
36#define v_b r2
37#define v_c r3
38
39#define x0 r4
40#define x1 r5
41#define x2 r6
42#define x0_x1 r5
43#define x1_x2 r6
44#define y0 r7
45#define y1 r8
46#define y2 r9
47#define y0_y1 r7
48#define y1_y2 r8
49#define b0 r9
50#define b1 r10
51#define b2 r11
52#define b0_b1 r10
53#define b1_b2 r11
54
55
56#define area_r_s r5
57
58#define g_bx0 r2
59#define g_bx r3
60#define g_bx2 r4
61#define g_bx3 r5
62#define b_base r6
63#define g_by r8
64
65#define gs_bx r7
66#define gs_by r10
67
68#define ga_bx g_bx
69#define ga_by g_by
70
71#define gw_bx_h g_bx
72#define gw_by_h g_by
73
74#define gw_bx_l r11
75#define gw_by_l gw_bx_l
76
77#define store_a r0
78#define store_b r1
79#define store_inc r5
80
81
82#define v0 q0
83#define uvrgb0 d0
84#define x0_y0 d1
85
86#define v1 q1
87#define uvrgb1 d2
88#define x1_y1 d3
89
90#define v2 q2
91#define uvrgb2 d4
92#define x2_y2 d5
93
94#define x0_ab q3
95#define uvrg_xxxx0 q3
96#define uvrg0 d6
97#define xxxx0 d7
98
99#define x1_ab q4
100#define uvrg_xxxx1 q4
101#define uvrg1 d8
102#define xxxx1 d9
103
104#define x2_ab q5
105#define uvrg_xxxx2 q5
106#define uvrg2 d10
107#define xxxx2 d11
108
109#define y0_ab q6
110#define yyyy_uvrg0 q6
111#define yyyy0 d12
112#define uvrg0b d13
113
114#define y1_ab q7
115#define yyyy_uvrg1 q7
116#define yyyy1 d14
117#define uvrg1b d15
118
119#define y2_ab q8
120#define yyyy_uvrg2 q8
121#define yyyy2 d16
122#define uvrg2b d17
123
124#define d0_ab q9
125#define d0_a d18
126#define d0_b d19
127
128#define d1_ab q10
129#define d1_a d20
130#define d1_b d21
131
132#define d2_ab q11
133#define d2_a d22
134#define d2_b d23
135
136#define d3_ab q12
137#define d3_a d24
138#define d3_b d25
139
140#define ga_uvrg_x q1
141#define ga_uvrg_y q4
142
143#define dx x0_x1
144#define dy y0_y1
145#define db b0_b1
146
147#define uvrg_base q11
148
149#define gs_uvrg_x q5
150#define gs_uvrg_y q6
151
152#define g_uvrg_x q1
153#define ga_uv_x d2
154#define g_uv_x d2
155#define ga_rg_x d3
156#define g_rg_x d3
157
158#define g_uvrg_y q4
159#define ga_uv_y d8
160#define g_uv_y d8
161#define ga_rg_y d9
162#define g_rg_y d9
163
164#define gw_uv_x q1
165#define gw_rg_x q2
166#define gw_uv_y q4
167#define gw_rg_y q3
168
169#define w_mask q9
170#define w_mask_l d18
171
172#define r_shift q10
173
174#define uvrg_dx0 q0
175#define uvrg_dx0l d0
176#define uvrg_dx0h d1
177
178#define uvrg_dx1 q1
179#define uvrg_dx1l d2
180#define uvrg_dx1h d3
181
182#define uvrg_dx2 q2
183#define uvrg_dx2l d4
184#define uvrg_dx2h d5
185
186#define uvrg_dx3 q3
187#define uvrg_dx3l d6
188#define uvrg_dx3h d7
189
c6063f89 190#define uvrgb_phase q13
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191
192.align 4
193
5d834c08 194/* FIXME: users of this should be in psx_gpu instead */
195#ifndef __PIC__
196#define load_pointer(register, pointer) \
197 movw register, :lower16:pointer; \
198 movt register, :upper16:pointer; \
199
200#else
201#define load_pointer(register, pointer) \
202 ldr register, =pointer \
203
204#endif
205
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206#define function(name) \
207 .global name; \
208 name: \
209
210@ r0: psx_gpu
211@ r1: v_a
212@ r2: v_b
213@ r3: v_c
214
215function(compute_all_gradients)
216 // First compute the triangle area reciprocal and shift. The division will
217 // happen concurrently with much of the work which follows.
218 @ r12 = psx_gpu->triangle_area
219 ldr r12, [ psx_gpu, #psx_gpu_triangle_area_offset ]
220 stmdb sp!, { r4 - r11, lr }
221
222 @ load exponent of 62 into upper half of double
223 movw r4, #0
224 clz r14, r12 @ r14 = shift
225
226 movt r4, #((62 + 1023) << 4)
227 mov r12, r12, lsl r14 @ r12 = triangle_area_normalized
228
229 @ load area normalized into lower half of double
230 mov r5, r12, lsr #10
231 vmov.f64 d30, r5, r4 @ d30 = (1 << 62) + ta_n
232
233 movt r4, #((1022 + 31) << 4)
234 mov r5, r12, lsl #20
235
236 add r4, r4, r12, lsr #11
237 vmov.f64 d31, r5, r4
238
239 vdiv.f64 d30, d30, d31 @ d30 = ((1 << 62) + ta_n) / ta_n
240
241 // ((x1 - x0) * (y2 - y1)) - ((x2 - x1) * (y1 - y0)) =
242 // ( d0 * d1 ) - ( d2 * d3 ) =
243 // ( m0 ) - ( m1 ) = gradient
244
245 // This is split to do 12 elements at a time over three sets: a, b, and c.
246 // Technically we only need to do 10 elements (uvrgb_x and uvrgb_y), so
247 // two of the slots are unused.
248
249 // Inputs are all 16-bit signed. The m0/m1 results are 32-bit signed, as
250 // is g.
251
252 // First type is: uvrg bxxx xxxx
253 // Second type is: yyyy ybyy uvrg
254 // Since x_a and y_c are the same the same variable is used for both.
255
256 vld1.u32 { v0 }, [ v_a, : 128 ] @ v0 = { uvrg0, b0, x0, y0 }
257 ldrsh x0, [ v_a, #8 ] @ load x0
258
259 vld1.u32 { v1 }, [ v_b, : 128 ] @ v1 = { uvrg1, b1, x1, y1}
260 ldrh x1, [ v_b, #8 ] @ load x1
261
262 vld1.u32 { v2 }, [ v_c, : 128 ] @ v2 = { uvrg2, b2, x2, y2 }
263 ldrh x2, [ v_c, #8 ] @ load x2
264
265 vmovl.u8 uvrg_xxxx0, uvrgb0 @ uvrg_xxxx0 = { uv0, rg0, b0-, -- }
266 ldrh y0, [ v_a, #10 ] @ load y0
267
268 vmovl.u8 uvrg_xxxx1, uvrgb1 @ uvrg_xxxx1 = { uv1, rg1, b1-, -- }
269 ldrh y1, [ v_b, #10 ] @ load y1
270
271 vmovl.u8 uvrg_xxxx2, uvrgb2 @ uvrg_xxxx2 = { uv2, rg2, b2-, -- }
272 ldrh y2, [ v_c, #10 ] @ load y2
273
274 vmov.u8 uvrg0b, uvrg0 @ uvrg0b = { uv0, rg0 }
275 vdup.u16 xxxx0, x0_y0[0] @ xxxx0 = { xx0, xx0 }
276
277 orr x1_x2, x1, x2, lsl #16 @ x1_x2 = { x1, x2 }
278 pkhbt x0_x1, x0, x1, lsl #16 @ x0_x1 = { x0, x1 }
279
280 vmov.u8 uvrg1b, uvrg1 @ uvrg1b = { uv1, rg1 }
281 vdup.u16 xxxx1, x1_y1[0] @ xxxx1 = { xx1, xx1 }
282
283 vmov.u8 uvrg2b, uvrg2 @ uvrg2b = { uv2, rg2 }
284 vdup.u16 xxxx2, x2_y2[0] @ xxxx2 = { xx2, xx2 }
285
286 ldrb b2, [ v_c, #4 ] @ load b2
287 orr y0_y1, y0, y1, lsl #16 @ y0_y1 = { y0, y1 }
288
289 ldrb b1, [ v_b, #4 ] @ load b1
290 orr y1_y2, y1, y2, lsl #16 @ y1_y2 = { y1, y2 }
291
292 vdup.u16 yyyy0, x0_y0[1] @ yyyy0 = { yy0, yy0 }
293 vsub.s16 d0_ab, x1_ab, x0_ab
294
295 ldrb b0, [ v_a, #4 ] @ load b0
296 orr b1_b2, b1, b2, lsl #16 @ b1_b2 = { b1, b2 }
297
298 vdup.u16 yyyy1, x1_y1[1] @ yyyy1 = { yy1, yy1 }
299 vsub.s16 d2_ab, x2_ab, x1_ab
300
301 vdup.u16 yyyy2, x2_y2[1] @ yyyy2 = { yy2, yy2 }
302 vsub.s16 d1_ab, y2_ab, y1_ab
303
304 orr b0_b1, b0, b1, lsl #16 @ b1_b2 = { b1, b2 }
305 ssub16 dx, x1_x2, x0_x1 @ dx = { x1 - x0, x2 - x1 }
306
307 ssub16 dy, y1_y2, y0_y1 @ dy = { y1 - y0, y2 - y1 }
308 ssub16 db, b1_b2, b0_b1 @ db = { b1 - b0, b2 - b1 }
309
310 vsub.s16 d3_ab, y1_ab, y0_ab
311 smusdx ga_by, dx, db @ ga_by = ((x1 - x0) * (b2 - b1)) -
312 @ ((x2 - X1) * (b1 - b0))
313 vmull.s16 ga_uvrg_x, d0_a, d1_a
314 smusdx ga_bx, db, dy @ ga_bx = ((b1 - b0) * (y2 - y1)) -
315 @ ((b2 - b1) * (y1 - y0))
316 vmlsl.s16 ga_uvrg_x, d2_a, d3_a
317 movs gs_bx, ga_bx, asr #31
318
319 vmull.s16 ga_uvrg_y, d0_b, d1_b
320 rsbmi ga_bx, ga_bx, #0
321
c6063f89 322 @ r12 = psx_gpu->uvrgb_phase
323 ldr r12, [ psx_gpu, #psx_gpu_uvrgb_phase_offset ]
324
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325 vmlsl.s16 ga_uvrg_y, d2_b, d3_b
326 movs gs_by, ga_by, asr #31
327
328 vshr.u64 d0, d30, #22
c6063f89 329 add b_base, r12, b0, lsl #16
330
331 vdup.u32 uvrgb_phase, r12
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332
333 rsbmi ga_by, ga_by, #0
334 vclt.s32 gs_uvrg_x, ga_uvrg_x, #0 @ gs_uvrg_x = ga_uvrg_x < 0
335
336 @ r12 = psx_gpu->triangle_winding_offset
337 ldrb r12, [ psx_gpu, #psx_gpu_triangle_winding_offset ]
338 vclt.s32 gs_uvrg_y, ga_uvrg_y, #0 @ gs_uvrg_y = ga_uvrg_y < 0
339
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340 rsb r12, r12, #0 @ r12 = -(triangle->winding)
341
342 vdup.u32 w_mask, r12 @ w_mask = { -w, -w, -w, -w }
343 sub r14, r14, #(62 - 12) @ r14 = shift - (62 - FIXED_BITS)
344
345 vshll.u16 uvrg_base, uvrg0, #16 @ uvrg_base = uvrg0 << 16
346 vdup.u32 r_shift, r14 @ r_shift = { shift, shift, shift, shift }
347
c6063f89 348 vadd.u32 uvrg_base, uvrgb_phase
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349 vabs.s32 ga_uvrg_x, ga_uvrg_x @ ga_uvrg_x = abs(ga_uvrg_x)
350
351 vmov area_r_s, s0 @ area_r_s = triangle_reciprocal
352 vabs.s32 ga_uvrg_y, ga_uvrg_y @ ga_uvrg_y = abs(ga_uvrg_y)
353
354 vmull.u32 gw_rg_x, ga_rg_x, d0[0]
355 vmull.u32 gw_uv_x, ga_uv_x, d0[0]
356 vmull.u32 gw_rg_y, ga_rg_y, d0[0]
357 vmull.u32 gw_uv_y, ga_uv_y, d0[0]
358
359 vshl.u64 gw_rg_x, gw_rg_x, r_shift
360 vshl.u64 gw_uv_x, gw_uv_x, r_shift
361 vshl.u64 gw_rg_y, gw_rg_y, r_shift
362 vshl.u64 gw_uv_y, gw_uv_y, r_shift
363
364 veor.u32 gs_uvrg_x, gs_uvrg_x, w_mask
365 vmovn.u64 g_uv_x, gw_uv_x
366
367 veor.u32 gs_uvrg_y, gs_uvrg_y, w_mask
368 vmovn.u64 g_rg_x, gw_rg_x
369
370 veor.u32 g_uvrg_x, g_uvrg_x, gs_uvrg_x
371 vmovn.u64 g_uv_y, gw_uv_y
372
373 vsub.u32 g_uvrg_x, g_uvrg_x, gs_uvrg_x
374 vmovn.u64 g_rg_y, gw_rg_y
375
376 veor.u32 g_uvrg_y, g_uvrg_y, gs_uvrg_y
377 mov ga_bx, ga_bx, lsl #13
378
379 vsub.u32 g_uvrg_y, g_uvrg_y, gs_uvrg_y
380 mov ga_by, ga_by, lsl #13
381
382 vdup.u32 x0_y0, x0
383 umull gw_bx_l, gw_bx_h, ga_bx, area_r_s
384
385 vshl.u32 g_uvrg_x, g_uvrg_x, #4
386 vshl.u32 g_uvrg_y, g_uvrg_y, #4
387
388 umull gw_by_l, gw_by_h, ga_by, area_r_s
389 vmls.s32 uvrg_base, ga_uvrg_x, x0_y0[0]
390
391 eor gs_bx, gs_bx, r12
392 vadd.u32 uvrg_dx2, uvrg_dx1, uvrg_dx1
393
394 veor.u32 uvrg_dx0, uvrg_dx0, uvrg_dx0
395 eor gs_by, gs_by, r12
396
397 rsb r11, r14, #0 @ r11 = negative shift for scalar lsr
398 add store_a, psx_gpu, #psx_gpu_uvrg_offset
399
400 sub r11, r11, #(32 - 13)
401
402 add store_b, store_a, #16
403 mov store_inc, #32
404
405 vadd.u32 uvrg_dx3, uvrg_dx2, uvrg_dx1
406 vst1.u32 { uvrg_base }, [ store_a, : 128 ], store_inc
407
408 vst1.u32 { uvrg_dx1 }, [ store_b, : 128 ], store_inc
409 mov g_bx, gw_bx_h, lsr r11
410
411 vst1.u32 { g_uvrg_y }, [ store_a, : 128 ], store_inc
412 mov g_by, gw_by_h, lsr r11
413
414 vst4.u32 { uvrg_dx0l, uvrg_dx1l, uvrg_dx2l, uvrg_dx3l }, \
415 [ store_b, : 128 ], store_inc
416 eor g_bx, g_bx, gs_bx
417
418 vst4.u32 { uvrg_dx0h, uvrg_dx1h, uvrg_dx2h, uvrg_dx3h }, \
419 [ store_b, : 128 ], store_inc
420 sub g_bx, g_bx, gs_bx
421
422 lsl g_bx, g_bx, #4
423 eor g_by, g_by, gs_by
424
425 mls b_base, g_bx, x0, b_base
426 sub g_by, g_by, gs_by
427
428 lsl g_by, g_by, #4
429 mov g_bx0, #0
430
431 add g_bx2, g_bx, g_bx
432 add g_bx3, g_bx, g_bx2
433
434 stmia store_b, { g_bx0, g_bx, g_bx2, g_bx3, b_base, g_by }
435
436 ldmia sp!, { r4 - r11, pc }
437
438
439#define psx_gpu r0
440#define v_a r1
441#define v_b r2
442#define v_c r3
443
444#define temp r14
445
446#define x_a r4
447#define x_b r5
448#define x_c r6
449#define y_a r1
450#define y_b r2
451#define y_c r3
452
453#define height_minor_a r7
454#define height_minor_b r8
455#define height_major r9
456#define height r9
457
458#define reciprocal_table_ptr r10
459
460#define edge_alt_low r4
461#define edge_alt_high r5
462#define edge_dx_dy_alt r6
463#define edge_shift_alt r10
464
465#define edge_dx_dy_alt_low r4
466#define edge_dx_dy_alt_high r5
467
468#define span_edge_data r4
469#define span_uvrg_offset r5
470#define span_b_offset r6
471
472#define clip r14
473
474#define b r11
475#define b_dy r12
476
477
478#define alternate_x q0
479#define alternate_dx_dy q1
480#define alternate_x_32 q2
481
482#define alternate_x_low d0
483#define alternate_x_high d1
484#define alternate_dx_dy_low d2
485#define alternate_dx_dy_high d3
486#define alternate_x_32_low d4
487#define alternate_x_32_high d5
488
489#define left_x q3
490#define right_x q4
491#define left_dx_dy q5
492#define right_dx_dy q6
493#define left_edge q7
494#define right_edge q8
495
496#define left_x_low d6
497#define left_x_high d7
498#define right_x_low d8
499#define right_x_high d9
500#define left_dx_dy_low d10
501#define left_dx_dy_high d11
502#define right_dx_dy_low d12
503#define right_dx_dy_high d13
504#define left_edge_low d14
505#define left_edge_high d15
506#define right_edge_low d16
507#define right_edge_high d17
508
509#define y_mid_point d18
510#define c_0x0004 d19
511
512#define left_right_x_16 q11
513#define span_shifts_y q12
514#define c_0x0001 q13
515
516#define span_shifts d24
517#define y_x4 d25
518#define c_0xFFFE d26
519#define c_0x0007 d27
520
521#define left_right_x_16_low d22
522#define left_right_x_16_high d23
523
524#define uvrg q14
525#define uvrg_dy q15
526
527#define alternate_x_16 d4
528
529#define v_clip q3
530#define v_clip_low d6
531
532#define right_x_32 q10
533#define left_x_32 q11
534#define alternate_select d24
535
536#define right_x_32_low d20
537#define right_x_32_high d21
538#define left_x_32_low d22
539#define left_x_32_high d23
540
541#define edges_xy q0
542#define edges_dx_dy d2
543#define edge_shifts d3
544#define edge_shifts_64 q2
545
546#define edges_xy_left d0
547#define edges_xy_right d1
548
549#define height_reciprocals d6
550#define heights d7
551
552#define widths d8
553#define c_0x01 d9
554#define x_starts d10
555#define x_ends d11
556
557#define heights_b d12
558#define edges_dx_dy_64 q10
559
560#define edges_dx_dy_64_left d20
561#define edges_dx_dy_64_right d21
562
563
564#define setup_spans_prologue() \
565 stmdb sp!, { r4 - r11, lr }; \
566 \
567 ldrsh x_a, [ v_a, #8 ]; \
568 ldrsh x_b, [ v_b, #8 ]; \
569 ldrsh x_c, [ v_c, #8 ]; \
570 ldrsh y_a, [ v_a, #10 ]; \
571 ldrsh y_b, [ v_b, #10 ]; \
572 ldrsh y_c, [ v_c, #10 ]; \
573 \
574 add temp, psx_gpu, #psx_gpu_uvrg_offset; \
575 vld1.32 { uvrg }, [ temp ]; \
576 add temp, psx_gpu, #psx_gpu_uvrg_dy_offset; \
577 vld1.32 { uvrg_dy }, [ temp ]; \
5d834c08 578 load_pointer(reciprocal_table_ptr, reciprocal_table); \
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579 \
580 vmov.u32 c_0x01, #0x01 \
581
582#define setup_spans_load_b() \
583 ldr b, [ psx_gpu, #psx_gpu_b_offset ]; \
584 ldr b_dy, [ psx_gpu, #psx_gpu_b_dy_offset ] \
585
586#define setup_spans_prologue_b() \
587 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
588 add temp, psx_gpu, #psx_gpu_viewport_start_x_offset; \
589 \
590 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
591 vmov.u16 c_0x0004, #0x0004; \
592 \
593 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
594 vmov.u16 c_0x0001, #0x0001; \
595 \
596 vld1.u16 { left_edge_low[], left_edge_high[] }, [ temp ]; \
597 add temp, psx_gpu, #psx_gpu_viewport_end_x_offset; \
598 \
599 vld1.u16 { right_edge_low[], right_edge_high[] }, [ temp ]; \
600 vadd.u16 right_edge, right_edge, c_0x0001; \
601 \
602 vmov.u16 c_0x0007, #0x0007; \
603 vmvn.u16 c_0xFFFE, #0x0001 \
604
605
606#define compute_edge_delta_x2() \
607 ldr temp, [ reciprocal_table_ptr, height, lsl #2 ]; \
608 \
609 vdup.u32 heights, height; \
610 vsub.u32 widths, x_ends, x_starts; \
611 \
612 vdup.u32 edge_shifts, temp; \
613 vsub.u32 heights_b, heights, c_0x01; \
7d5140f5 614 vshr.u32 height_reciprocals, edge_shifts, #10; \
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615 \
616 vmla.s32 heights_b, x_starts, heights; \
617 vbic.u16 edge_shifts, #0xE0; \
618 vmul.s32 edges_dx_dy, widths, height_reciprocals; \
619 vmull.s32 edges_xy, heights_b, height_reciprocals \
620
621#define width_alt r6
622#define height_reciprocal_alt r11
623#define height_b_alt r12
624
625#define compute_edge_delta_x3(start_c, height_a, height_b) \
626 vmov.u32 heights, height_a, height_b; \
627 ldr temp, [ reciprocal_table_ptr, height_a, lsl #2 ]; \
628 vmov.u32 edge_shifts[0], temp; \
629 ldr temp, [ reciprocal_table_ptr, height_b, lsl #2 ]; \
630 vmov.u32 edge_shifts[1], temp; \
631 ldr edge_shift_alt, [ reciprocal_table_ptr, height_minor_b, lsl #2 ]; \
632 \
633 vsub.u32 widths, x_ends, x_starts; \
634 sub width_alt, x_c, start_c; \
635 \
636 vsub.u32 heights_b, heights, c_0x01; \
637 sub height_b_alt, height_minor_b, #1; \
638 \
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639 vshr.u32 height_reciprocals, edge_shifts, #10; \
640 lsr height_reciprocal_alt, edge_shift_alt, #10; \
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641 \
642 vmla.s32 heights_b, x_starts, heights; \
643 mla height_b_alt, height_minor_b, start_c, height_b_alt; \
644 \
645 vbic.u16 edge_shifts, #0xE0; \
646 and edge_shift_alt, edge_shift_alt, #0x1F; \
647 \
648 vmul.s32 edges_dx_dy, widths, height_reciprocals; \
649 mul edge_dx_dy_alt, width_alt, height_reciprocal_alt; \
650 \
651 vmull.s32 edges_xy, heights_b, height_reciprocals; \
652 smull edge_alt_low, edge_alt_high, height_b_alt, height_reciprocal_alt \
653
654
655#define setup_spans_adjust_y_up() \
656 vsub.u32 y_x4, y_x4, c_0x0004 \
657
658#define setup_spans_adjust_y_down() \
659 vadd.u32 y_x4, y_x4, c_0x0004 \
660
661#define setup_spans_adjust_interpolants_up() \
662 vsub.u32 uvrg, uvrg, uvrg_dy; \
663 sub b, b, b_dy \
664
665#define setup_spans_adjust_interpolants_down() \
666 vadd.u32 uvrg, uvrg, uvrg_dy; \
667 add b, b, b_dy \
668
669
670#define setup_spans_clip_interpolants_increment() \
671 mla b, b_dy, clip, b; \
672 vmla.s32 uvrg, uvrg_dy, v_clip \
673
674#define setup_spans_clip_interpolants_decrement() \
675 mls b, b_dy, clip, b; \
676 vmls.s32 uvrg, uvrg_dy, v_clip \
677
678#define setup_spans_clip_alternate_yes() \
679 smlal edge_alt_low, edge_alt_high, edge_dx_dy_alt, clip \
680
681#define setup_spans_clip_alternate_no() \
682
683#define setup_spans_clip(direction, alternate_active) \
684 vdup.u32 v_clip, clip; \
685 setup_spans_clip_alternate_##alternate_active(); \
686 setup_spans_clip_interpolants_##direction(); \
687 vmlal.s32 edges_xy, edges_dx_dy, v_clip_low \
688
689
690#define setup_spans_adjust_edges_alternate_no(left_index, right_index) \
691 vmovl.s32 edge_shifts_64, edge_shifts; \
692 vmovl.s32 edges_dx_dy_64, edges_dx_dy; \
693 \
694 vshl.s64 edges_xy, edges_xy, edge_shifts_64; \
695 vshl.s64 edges_dx_dy_64, edges_dx_dy_64, edge_shifts_64; \
696 \
697 vmov left_x_low, edges_xy_##left_index; \
698 vmov right_x_low, edges_xy_##right_index; \
699 \
700 vmov left_dx_dy_low, edges_dx_dy_64_##left_index; \
701 vmov left_dx_dy_high, edges_dx_dy_64_##left_index; \
702 vmov right_dx_dy_low, edges_dx_dy_64_##right_index; \
703 vmov right_dx_dy_high, edges_dx_dy_64_##right_index; \
704 \
705 vadd.u64 left_x_high, left_x_low, left_dx_dy_low; \
706 vadd.u64 right_x_high, right_x_low, right_dx_dy_low; \
707 \
708 vadd.u64 left_dx_dy, left_dx_dy, left_dx_dy; \
709 vadd.u64 right_dx_dy, right_dx_dy, right_dx_dy \
710
711
712#define setup_spans_adjust_edges_alternate_yes(left_index, right_index) \
713 setup_spans_adjust_edges_alternate_no(left_index, right_index); \
714 \
715 vdup.u16 y_mid_point, y_b; \
716 rsb temp, edge_shift_alt, #32; \
717 \
718 lsl edge_alt_high, edge_alt_high, edge_shift_alt; \
719 orr edge_alt_high, edge_alt_high, edge_alt_low, lsr temp; \
720 lsl edge_alt_low, edge_alt_low, edge_shift_alt; \
721 vmov alternate_x_low, edge_alt_low, edge_alt_high; \
722 \
723 asr edge_dx_dy_alt_high, edge_dx_dy_alt, temp; \
724 lsl edge_dx_dy_alt_low, edge_dx_dy_alt, edge_shift_alt; \
725 vmov alternate_dx_dy_low, edge_dx_dy_alt_low, edge_dx_dy_alt_high; \
726 vmov alternate_dx_dy_high, alternate_dx_dy_low; \
727 \
728 vadd.u64 alternate_x_high, alternate_x_low, alternate_dx_dy_low; \
729 vadd.u64 alternate_dx_dy, alternate_dx_dy, alternate_dx_dy \
730
731
732#define setup_spans_y_select_up() \
733 vclt.s16 alternate_select, y_x4, y_mid_point \
734
735#define setup_spans_y_select_down() \
736 vcgt.s16 alternate_select, y_x4, y_mid_point \
737
738
739#define setup_spans_alternate_select_left() \
740 vbit.u16 left_right_x_16_low, alternate_x_16, alternate_select \
741
742#define setup_spans_alternate_select_right() \
743 vbit.u16 left_right_x_16_high, alternate_x_16, alternate_select \
744
745
746#define setup_spans_set_x4_alternate_yes(alternate, direction) \
747 vshrn.s64 alternate_x_32_low, alternate_x, #32; \
748 vshrn.s64 left_x_32_low, left_x, #32; \
749 vshrn.s64 right_x_32_low, right_x, #32; \
750 \
751 vadd.u64 alternate_x, alternate_x, alternate_dx_dy; \
752 vadd.u64 left_x, left_x, left_dx_dy; \
753 vadd.u64 right_x, right_x, right_dx_dy; \
754 \
755 vshrn.s64 alternate_x_32_high, alternate_x, #32; \
756 vshrn.s64 left_x_32_high, left_x, #32; \
757 vshrn.s64 right_x_32_high, right_x, #32; \
758 \
759 vadd.u64 alternate_x, alternate_x, alternate_dx_dy; \
760 vadd.u64 left_x, left_x, left_dx_dy; \
761 vadd.u64 right_x, right_x, right_dx_dy; \
762 \
763 vmovn.u32 alternate_x_16, alternate_x_32; \
764 setup_spans_y_select_##direction(); \
765 vmovn.u32 left_right_x_16_low, left_x_32; \
766 \
767 vmovn.u32 left_right_x_16_high, right_x_32; \
768 setup_spans_alternate_select_##alternate(); \
769 \
770 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
771 str b, [ span_b_offset ], #4; \
772 setup_spans_adjust_interpolants_##direction(); \
773 \
774 vmax.s16 left_right_x_16, left_right_x_16, left_edge; \
775 \
776 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
777 str b, [ span_b_offset ], #4; \
778 setup_spans_adjust_interpolants_##direction(); \
779 \
780 vmin.s16 left_right_x_16, left_right_x_16, right_edge; \
781 \
782 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
783 str b, [ span_b_offset ], #4; \
784 setup_spans_adjust_interpolants_##direction(); \
785 \
786 vsub.u16 left_right_x_16_high, left_right_x_16_high, left_right_x_16_low; \
787 vadd.u16 left_right_x_16_high, left_right_x_16_high, c_0x0007; \
788 vand.u16 span_shifts, left_right_x_16_high, c_0x0007; \
789 \
790 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
791 str b, [ span_b_offset ], #4; \
792 setup_spans_adjust_interpolants_##direction(); \
793 \
794 vshr.u16 left_right_x_16_high, left_right_x_16_high, #3; \
795 vshl.u16 span_shifts, c_0xFFFE, span_shifts; \
796 \
797 vst4.u16 { left_right_x_16, span_shifts_y }, [ span_edge_data ]!; \
798 \
799 setup_spans_adjust_y_##direction() \
800
801
802#define setup_spans_set_x4_alternate_no(alternate, direction) \
803 vshrn.s64 left_x_32_low, left_x, #32; \
804 vshrn.s64 right_x_32_low, right_x, #32; \
805 \
806 vadd.u64 left_x, left_x, left_dx_dy; \
807 vadd.u64 right_x, right_x, right_dx_dy; \
808 \
809 vshrn.s64 left_x_32_high, left_x, #32; \
810 vshrn.s64 right_x_32_high, right_x, #32; \
811 \
812 vadd.u64 left_x, left_x, left_dx_dy; \
813 vadd.u64 right_x, right_x, right_dx_dy; \
814 \
815 vmovn.u32 left_right_x_16_low, left_x_32; \
816 vmovn.u32 left_right_x_16_high, right_x_32; \
817 \
818 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
819 str b, [ span_b_offset ], #4; \
820 setup_spans_adjust_interpolants_##direction(); \
821 \
822 vmax.s16 left_right_x_16, left_right_x_16, left_edge; \
823 \
824 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
825 str b, [ span_b_offset ], #4; \
826 setup_spans_adjust_interpolants_##direction(); \
827 \
828 vmin.s16 left_right_x_16, left_right_x_16, right_edge; \
829 \
830 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
831 str b, [ span_b_offset ], #4; \
832 setup_spans_adjust_interpolants_##direction(); \
833 \
834 vsub.u16 left_right_x_16_high, left_right_x_16_high, left_right_x_16_low; \
835 vadd.u16 left_right_x_16_high, left_right_x_16_high, c_0x0007; \
836 vand.u16 span_shifts, left_right_x_16_high, c_0x0007; \
837 \
838 vst1.u32 { uvrg }, [ span_uvrg_offset, :128 ]!; \
839 str b, [ span_b_offset ], #4; \
840 setup_spans_adjust_interpolants_##direction(); \
841 \
842 vshl.u16 span_shifts, c_0xFFFE, span_shifts; \
843 vshr.u16 left_right_x_16_high, left_right_x_16_high, #3; \
844 \
845 vst4.u16 { left_right_x_16, span_shifts_y }, [ span_edge_data ]!; \
846 \
847 setup_spans_adjust_y_##direction() \
848
849
850#define edge_adjust_low r11
851#define edge_adjust_high r12
852
853#define setup_spans_alternate_adjust_yes() \
854 smull edge_adjust_low, edge_adjust_high, edge_dx_dy_alt, height_minor_a; \
855 subs edge_alt_low, edge_alt_low, edge_adjust_low; \
856 sbc edge_alt_high, edge_alt_high, edge_adjust_high \
857
858#define setup_spans_alternate_adjust_no() \
859
860
861#define setup_spans_down(left_index, right_index, alternate, alternate_active) \
862 setup_spans_alternate_adjust_##alternate_active(); \
863 setup_spans_load_b(); \
864 \
865 ldrsh temp, [ psx_gpu, #psx_gpu_viewport_end_y_offset ]; \
866 subs y_c, y_c, temp; \
867 subgt height, height, y_c; \
868 addgt height, height, #1; \
869 \
870 ldrsh temp, [ psx_gpu, #psx_gpu_viewport_start_y_offset ]; \
871 subs clip, temp, y_a; \
872 ble 0f; \
873 \
874 sub height, height, clip; \
875 add y_a, y_a, clip; \
876 setup_spans_clip(increment, alternate_active); \
877 \
878 0: \
879 cmp height, #0; \
880 ble 1f; \
881 \
882 orr temp, y_a, y_a, lsl #16; \
883 add temp, temp, #(1 << 16); \
884 add y_a, temp, #2; \
885 add y_a, y_a, #(2 << 16); \
886 vmov.u32 y_x4, temp, y_a; \
887 \
888 setup_spans_adjust_edges_alternate_##alternate_active(left_index, \
889 right_index); \
890 setup_spans_prologue_b(); \
891 \
892 strh height, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
893 \
894 2: \
895 setup_spans_set_x4_alternate_##alternate_active(alternate, down); \
896 subs height, height, #4; \
897 bhi 2b; \
898 \
899 1: \
900
901
902#define setup_spans_alternate_pre_increment_yes() \
903 adds edge_alt_low, edge_alt_low, edge_dx_dy_alt; \
904 adc edge_alt_high, edge_alt_high, edge_dx_dy_alt, asr #31 \
905
906#define setup_spans_alternate_pre_increment_no() \
907
908
909#define setup_spans_up_decrement_yes() \
910 suble height, height, #1 \
911
912#define setup_spans_up_decrement_no() \
913
914
915#define setup_spans_up(left_index, right_index, alternate, alternate_active) \
916 setup_spans_alternate_adjust_##alternate_active(); \
917 setup_spans_load_b(); \
918 sub y_a, y_a, #1; \
919 \
920 ldrh temp, [ psx_gpu, #psx_gpu_viewport_start_y_offset ]; \
921 subs temp, temp, y_c; \
922 subgt height, height, temp; \
923 setup_spans_up_decrement_##alternate_active(); \
924 \
925 ldrh temp, [ psx_gpu, #psx_gpu_viewport_end_y_offset ]; \
926 subs clip, y_a, temp; \
927 ble 0f; \
928 \
929 sub height, height, clip; \
930 sub y_a, y_a, clip; \
931 setup_spans_clip(decrement, alternate_active); \
932 \
933 0: \
934 cmp height, #0; \
935 ble 1f; \
936 \
937 orr temp, y_a, y_a, lsl #16; \
938 sub temp, temp, #(1 << 16); \
939 sub y_a, temp, #2; \
940 sub y_a, y_a, #(2 << 16); \
941 vmov.u32 y_x4, temp, y_a; \
942 \
943 vaddw.s32 edges_xy, edges_xy, edges_dx_dy; \
944 \
945 setup_spans_alternate_pre_increment_##alternate_active(); \
946 setup_spans_adjust_edges_alternate_##alternate_active(left_index, \
947 right_index); \
948 setup_spans_adjust_interpolants_up(); \
949 setup_spans_prologue_b(); \
950 \
951 strh height, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
952 \
953 2: \
954 setup_spans_set_x4_alternate_##alternate_active(alternate, up); \
955 subs height, height, #4; \
956 bhi 2b; \
957 \
958 1: \
959
960
961#define setup_spans_epilogue() \
962 ldmia sp!, { r4 - r11, pc } \
963
964
965#define setup_spans_up_up(minor, major) \
966 setup_spans_prologue(); \
967 sub height_minor_a, y_a, y_b; \
968 sub height_minor_b, y_b, y_c; \
969 sub height, y_a, y_c; \
970 \
971 vdup.u32 x_starts, x_a; \
972 vmov.u32 x_ends, x_c, x_b; \
973 \
974 compute_edge_delta_x3(x_b, height_major, height_minor_a); \
975 setup_spans_up(major, minor, minor, yes); \
976 setup_spans_epilogue() \
977
978function(setup_spans_up_left)
979 setup_spans_up_up(left, right)
980
981function(setup_spans_up_right)
982 setup_spans_up_up(right, left)
983
5d834c08 984.pool
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985
986#define setup_spans_down_down(minor, major) \
987 setup_spans_prologue(); \
988 sub height_minor_a, y_b, y_a; \
989 sub height_minor_b, y_c, y_b; \
990 sub height, y_c, y_a; \
991 \
992 vdup.u32 x_starts, x_a; \
993 vmov.u32 x_ends, x_c, x_b; \
994 \
995 compute_edge_delta_x3(x_b, height_major, height_minor_a); \
996 setup_spans_down(major, minor, minor, yes); \
997 setup_spans_epilogue() \
998
999function(setup_spans_down_left)
1000 setup_spans_down_down(left, right)
1001
1002function(setup_spans_down_right)
1003 setup_spans_down_down(right, left)
1004
1005
1006#define setup_spans_up_flat() \
1007 sub height, y_a, y_c; \
1008 \
1009 compute_edge_delta_x2(); \
1010 setup_spans_up(left, right, none, no); \
1011 setup_spans_epilogue() \
1012
1013function(setup_spans_up_a)
1014 setup_spans_prologue()
1015
1016 vmov.u32 x_starts, x_a, x_b
1017 vdup.u32 x_ends, x_c
1018
1019 setup_spans_up_flat()
1020
1021function(setup_spans_up_b)
1022 setup_spans_prologue()
1023
1024 vdup.u32 x_starts, x_a
1025 vmov.u32 x_ends, x_b, x_c
1026
1027 setup_spans_up_flat()
1028
1029#define setup_spans_down_flat() \
1030 sub height, y_c, y_a; \
1031 \
1032 compute_edge_delta_x2(); \
1033 setup_spans_down(left, right, none, no); \
1034 setup_spans_epilogue() \
1035
1036function(setup_spans_down_a)
1037 setup_spans_prologue()
1038
1039 vmov.u32 x_starts, x_a, x_b
1040 vdup.u32 x_ends, x_c
1041
1042 setup_spans_down_flat()
1043
1044function(setup_spans_down_b)
1045 setup_spans_prologue()
1046
1047 vdup.u32 x_starts, x_a
1048 vmov.u32 x_ends, x_b, x_c
1049
1050 setup_spans_down_flat()
1051
1052
1053#define middle_y r9
1054
1055#define edges_xy_b q11
1056#define edges_dx_dy_b d26
1057#define edge_shifts_b d27
1058#define edges_dx_dy_and_shifts_b q13
1059#define height_increment d20
1060
1061#define edges_dx_dy_and_shifts q1
1062
1063#define edges_xy_b_left d22
1064#define edges_xy_b_right d23
1065
1066#define setup_spans_up_down_load_edge_set_b() \
1067 vmov edges_xy, edges_xy_b; \
1068 vmov edges_dx_dy_and_shifts, edges_dx_dy_and_shifts_b \
1069
1070
1071function(setup_spans_up_down)
1072 setup_spans_prologue()
1073
1074 // s32 middle_y = y_a;
1075 sub height_minor_a, y_a, y_b
1076 sub height_minor_b, y_c, y_a
1077 sub height_major, y_c, y_b
1078
1079 vmov.u32 x_starts, x_a, x_c
1080 vdup.u32 x_ends, x_b
1081
1082 compute_edge_delta_x3(x_a, height_minor_a, height_major)
1083
1084 mov temp, #0
1085 vmov.u32 height_increment, temp, height_minor_b
1086 vmlal.s32 edges_xy, edges_dx_dy, height_increment
1087
1088 vmov edges_xy_b_left, edge_alt_low, edge_alt_high
1089 vmov edges_xy_b_right, edges_xy_right
1090
1091 vmov edge_shifts_b, edge_shifts
1092 vmov.u32 edge_shifts_b[0], edge_shift_alt
1093
1094 vneg.s32 edges_dx_dy_b, edges_dx_dy
1095 vmov.u32 edges_dx_dy_b[0], edge_dx_dy_alt
1096
1097 mov middle_y, y_a
1098
1099 setup_spans_load_b()
1100 sub y_a, y_a, #1
1101
1102 ldrh temp, [ psx_gpu, #psx_gpu_viewport_start_y_offset ]
1103 subs temp, temp, y_b
1104 subgt height_minor_a, height_minor_a, temp
1105
1106 ldrh temp, [ psx_gpu, #psx_gpu_viewport_end_y_offset ]
1107 subs clip, y_a, temp
1108 ble 0f
1109
1110 sub height_minor_a, height_minor_a, clip
1111 sub y_a, y_a, clip
1112 setup_spans_clip(decrement, no)
1113
1114 0:
1115 cmp height_minor_a, #0
1116 ble 3f
1117
1118 orr temp, y_a, y_a, lsl #16
1119 sub temp, temp, #(1 << 16)
1120 sub y_a, temp, #2
1121 sub y_a, y_a, #(2 << 16)
1122 vmov.u32 y_x4, temp, y_a
1123
1124 vaddw.s32 edges_xy, edges_xy, edges_dx_dy
1125
1126 strh height_minor_a, [ psx_gpu, #psx_gpu_num_spans_offset ]
1127
1128 setup_spans_adjust_edges_alternate_no(left, right);
1129 setup_spans_adjust_interpolants_up()
1130 setup_spans_up_down_load_edge_set_b()
1131
1132 setup_spans_prologue_b()
1133
1134
1135 2:
1136 setup_spans_set_x4_alternate_no(none, up)
1137 subs height_minor_a, height_minor_a, #4
1138 bhi 2b
1139
1140 add span_edge_data, span_edge_data, height_minor_a, lsl #3
1141 add span_uvrg_offset, span_uvrg_offset, height_minor_a, lsl #4
1142 add span_b_offset, span_b_offset, height_minor_a, lsl #2
1143
1144 4:
1145 add temp, psx_gpu, #psx_gpu_uvrg_offset
1146 vld1.32 { uvrg }, [ temp ]
1147 mov y_a, middle_y
1148
1149 setup_spans_load_b()
1150
1151 ldrh temp, [ psx_gpu, #psx_gpu_viewport_end_y_offset ]
1152 subs y_c, y_c, temp
1153 subgt height_minor_b, height_minor_b, y_c
1154 addgt height_minor_b, height_minor_b, #1
1155
1156 ldrh temp, [ psx_gpu, #psx_gpu_viewport_start_y_offset ]
1157 subs clip, temp, y_a
1158 ble 0f
1159
1160 sub height_minor_b, height_minor_b, clip
1161 add y_a, y_a, clip
1162 setup_spans_clip(increment, no)
1163
1164 0:
1165 cmp height_minor_b, #0
1166 ble 1f
1167
1168 orr temp, y_a, y_a, lsl #16
1169 add temp, temp, #(1 << 16)
1170 add y_a, temp, #2
1171 add y_a, y_a, #(2 << 16)
1172 vmov.u32 y_x4, temp, y_a
1173
1174 setup_spans_adjust_edges_alternate_no(left, right)
1175
1176 ldrh temp, [ psx_gpu, #psx_gpu_num_spans_offset ]
1177 add temp, temp, height_minor_b
1178 strh temp, [ psx_gpu, #psx_gpu_num_spans_offset ]
1179
1180 2:
1181 setup_spans_set_x4_alternate_no(none, down)
1182 subs height_minor_b, height_minor_b, #4
1183 bhi 2b
1184
1185 1:
1186 setup_spans_epilogue()
1187
1188 3:
1189 setup_spans_up_down_load_edge_set_b()
1190 setup_spans_prologue_b()
1191 bal 4b
1192
5d834c08 1193.pool
75e28f62
E
1194
1195#undef span_uvrg_offset
1196#undef span_edge_data
1197#undef span_b_offset
1198#undef left_x
1199#undef b
1200
1201#define psx_gpu r0
1202#define num_spans r1
1203#define span_uvrg_offset r2
1204#define span_edge_data r3
1205#define span_b_offset r4
1206#define b_dx r5
1207#define span_num_blocks r6
1208#define y r7
1209#define left_x r8
1210#define b r9
1211#define dither_offset_ptr r10
1212#define block_ptr_a r11
1213#define fb_ptr r12
1214#define num_blocks r14
1215
1216#define uvrg_dx_ptr r2
1217#define texture_mask_ptr r3
1218#define dither_shift r8
1219#define dither_row r10
1220
1221#define c_32 r7
1222#define b_dx4 r8
1223#define b_dx8 r9
1224#define block_ptr_b r10
1225
1226#define block_span_ptr r10
1227#define right_mask r8
1228
1229#define color r2
1230#define color_r r3
1231#define color_g r4
1232#define color_b r5
1233
1234#undef uvrg
1235
1236#define u_block q0
1237#define v_block q1
1238#define r_block q2
1239#define g_block q3
1240#define b_block q4
1241
1242#define uv_dx4 d10
1243#define rg_dx4 d11
1244#define uv_dx8 d12
1245#define rg_dx8 d13
1246#define b_whole_8 d14
1247#define fb_mask_ptrs d15
1248
1249#define uvrg_dx4 q5
1250#define uvrg_dx8 q6
1251#define uv_dx8 d12
1252#define rg_dx8 d13
1253
1254#define u_whole q8
1255#define v_whole q9
1256#define r_whole q10
1257#define g_whole q11
1258#define b_whole q12
1259
1260#define u_whole_low d16
1261#define u_whole_high d17
1262#define v_whole_low d18
1263#define v_whole_high d19
1264#define r_whole_low d20
1265#define r_whole_high d21
1266#define g_whole_low d22
1267#define g_whole_high d23
1268#define b_whole_low d24
1269#define b_whole_high d25
1270
1271#define dx4 q13
1272#define dx8 q13
1273
1274#define u_whole_8 d26
1275#define v_whole_8 d27
1276#define u_whole_8b d24
1277#define r_whole_8 d24
1278#define g_whole_8 d25
1279
1280#define uv_whole_8 q13
1281#define uv_whole_8b q14
1282
1283#define dither_offsets q14
1284#define texture_mask q15
1285#define texture_mask_u d30
1286#define texture_mask_v d31
1287
1288#define dither_offsets_short d28
1289
1290#define v_left_x q8
1291#define uvrg q9
1292#define block_span q10
1293
1294#define uv d18
1295#define rg d19
1296
1297#define draw_mask q1
1298#define draw_mask_edge q13
1299#define test_mask q0
1300
1301#define uvrg_dx q3
1302
1303#define colors q2
1304
1305#define setup_blocks_texture_swizzled() \
1306 vand.u8 u_whole_8b, u_whole_8, texture_mask_u; \
1307 vsli.u8 u_whole_8, v_whole_8, #4; \
1308 vsri.u8 v_whole_8, u_whole_8b, #4 \
1309
1310#define setup_blocks_texture_unswizzled() \
1311
1312
1313#define setup_blocks_shaded_textured_builder(swizzling) \
1314.align 3; \
1315 \
1316function(setup_blocks_shaded_textured_dithered_##swizzling##_indirect) \
1317 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
1318 add uvrg_dx_ptr, psx_gpu, #psx_gpu_uvrg_dx_offset; \
1319 \
1320 vld1.u32 { uvrg_dx }, [ uvrg_dx_ptr, :128 ]; \
1321 add texture_mask_ptr, psx_gpu, #psx_gpu_texture_mask_width_offset; \
1322 \
1323 cmp num_spans, #0; \
1324 bxeq lr; \
1325 \
1326 stmdb sp!, { r4 - r11, r14 }; \
1327 vshl.u32 uvrg_dx4, uvrg_dx, #2; \
1328 \
1329 ldr b_dx, [ psx_gpu, #psx_gpu_b_dx_offset ]; \
1330 vshl.u32 uvrg_dx8, uvrg_dx, #3; \
1331 \
1332 vld2.u8 { texture_mask_u[], texture_mask_v[] }, [ texture_mask_ptr, :16 ]; \
1333 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
1334 \
1335 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
1336 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
1337 \
1338 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
1339 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1340 \
1341 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
1342 \
1343 0: \
1344 vmov.u8 fb_mask_ptrs, #0; \
1345 \
1346 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]; \
1347 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
1348 \
1349 ldrh y, [ span_edge_data, #edge_data_y_offset ]; \
c1817bd9 1350 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]; \
75e28f62
E
1351 \
1352 cmp span_num_blocks, #0; \
1353 beq 1f; \
1354 \
1355 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]; \
1356 add num_blocks, span_num_blocks, num_blocks; \
1357 \
1358 cmp num_blocks, #MAX_BLOCKS; \
1359 bgt 2f; \
1360 \
1361 3: \
1362 ldr b, [ span_b_offset ]; \
1363 add fb_ptr, fb_ptr, y, lsl #11; \
1364 \
1365 vdup.u32 v_left_x, left_x; \
1366 and y, y, #0x3; \
1367 \
1368 ldr dither_row, [ dither_offset_ptr, y, lsl #2 ]; \
1369 add fb_ptr, fb_ptr, left_x, lsl #1; \
1370 \
1371 mla b, b_dx, left_x, b; \
1372 and dither_shift, left_x, #0x03; \
1373 \
1374 vld1.u32 { uvrg }, [ span_uvrg_offset, :128 ]; \
1375 vshr.u32 uvrg_dx, uvrg_dx4, #2; \
1376 \
1377 mov dither_shift, dither_shift, lsl #3; \
1378 vmla.u32 uvrg, uvrg_dx, v_left_x; \
1379 \
1380 mov c_32, #32; \
1381 subs span_num_blocks, span_num_blocks, #1; \
1382 \
1383 mov dither_row, dither_row, ror dither_shift; \
1384 mov b_dx4, b_dx, lsl #2; \
1385 \
1386 vdup.u32 dither_offsets_short, dither_row; \
1387 add block_span_ptr, psx_gpu, #psx_gpu_u_block_span_offset; \
1388 \
1389 vdup.u32 b_block, b; \
1390 vshll.s8 dither_offsets, dither_offsets_short, #4; \
1391 \
1392 vdup.u32 u_block, uv[0]; \
1393 mov b_dx8, b_dx, lsl #3; \
1394 \
1395 vdup.u32 v_block, uv[1]; \
1396 vdup.u32 r_block, rg[0]; \
1397 vdup.u32 g_block, rg[1]; \
1398 \
1399 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1400 \
1401 vadd.u32 u_block, u_block, block_span; \
1402 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1403 \
1404 vadd.u32 v_block, v_block, block_span; \
1405 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1406 \
1407 vadd.u32 r_block, r_block, block_span; \
1408 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1409 \
1410 vadd.u32 g_block, g_block, block_span; \
1411 vld1.u32 { block_span }, [ block_span_ptr, :128 ]; \
1412 \
1413 vadd.u32 b_block, b_block, block_span; \
1414 add block_ptr_b, block_ptr_a, #16; \
1415 \
1416 vshrn.u32 u_whole_low, u_block, #16; \
1417 vshrn.u32 v_whole_low, v_block, #16; \
1418 vshrn.u32 r_whole_low, r_block, #16; \
1419 vshrn.u32 g_whole_low, g_block, #16; \
1420 \
1421 vdup.u32 dx4, uv_dx4[0]; \
1422 vshrn.u32 b_whole_low, b_block, #16; \
1423 \
1424 vaddhn.u32 u_whole_high, u_block, dx4; \
1425 vdup.u32 dx4, uv_dx4[1]; \
1426 \
1427 vaddhn.u32 v_whole_high, v_block, dx4; \
1428 vdup.u32 dx4, rg_dx4[0]; \
1429 \
1430 vaddhn.u32 r_whole_high, r_block, dx4; \
1431 vdup.u32 dx4, rg_dx4[1]; \
1432 \
1433 vaddhn.u32 g_whole_high, g_block, dx4; \
1434 vdup.u32 dx4, b_dx4; \
1435 \
1436 vaddhn.u32 b_whole_high, b_block, dx4; \
1437 vdup.u32 dx8, uv_dx8[0]; \
1438 \
1439 vadd.u32 u_block, u_block, dx8; \
1440 vdup.u32 dx8, uv_dx8[1]; \
1441 \
1442 vadd.u32 v_block, v_block, dx8; \
1443 vdup.u32 dx8, rg_dx8[0]; \
1444 \
1445 vadd.u32 r_block, r_block, dx8; \
1446 vdup.u32 dx8, rg_dx8[1]; \
1447 \
1448 vadd.u32 g_block, g_block, dx8; \
1449 vdup.u32 dx8, b_dx8; \
1450 \
1451 vadd.u32 b_block, b_block, dx8; \
1452 vmovn.u16 u_whole_8, u_whole; \
1453 \
1454 vmovn.u16 v_whole_8, v_whole; \
1455 \
1456 vmovn.u16 b_whole_8, b_whole; \
1457 pld [ fb_ptr ]; \
1458 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1459 \
1460 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1461 setup_blocks_texture_##swizzling(); \
1462 \
1463 vmovn.u16 r_whole_8, r_whole; \
1464 beq 5f; \
1465 \
1466 4: \
1467 vmovn.u16 g_whole_8, g_whole; \
1468 vshrn.u32 u_whole_low, u_block, #16; \
1469 \
1470 vst2.u8 { u_whole_8, v_whole_8 }, [ block_ptr_a, :128 ], c_32; \
1471 vshrn.u32 v_whole_low, v_block, #16; \
1472 \
1473 vst1.u32 { r_whole_8, g_whole_8 }, [ block_ptr_b, :128 ], c_32; \
1474 vshrn.u32 r_whole_low, r_block, #16; \
1475 \
1476 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32; \
1477 vshrn.u32 g_whole_low, g_block, #16; \
1478 \
1479 vdup.u32 dx4, uv_dx4[0]; \
1480 vshrn.u32 b_whole_low, b_block, #16; \
1481 \
1482 vaddhn.u32 u_whole_high, u_block, dx4; \
1483 vdup.u32 dx4, uv_dx4[1]; \
1484 \
1485 vaddhn.u32 v_whole_high, v_block, dx4; \
1486 vdup.u32 dx4, rg_dx4[0]; \
1487 \
1488 vaddhn.u32 r_whole_high, r_block, dx4; \
1489 vdup.u32 dx4, rg_dx4[1]; \
1490 \
1491 vaddhn.u32 g_whole_high, g_block, dx4; \
1492 vdup.u32 dx4, b_dx4; \
1493 \
1494 vaddhn.u32 b_whole_high, b_block, dx4; \
1495 vdup.u32 dx8, uv_dx8[0]; \
1496 \
1497 vadd.u32 u_block, u_block, dx8; \
1498 vdup.u32 dx8, uv_dx8[1]; \
1499 \
1500 vadd.u32 v_block, v_block, dx8; \
1501 vdup.u32 dx8, rg_dx8[0]; \
1502 \
1503 vadd.u32 r_block, r_block, dx8; \
1504 vdup.u32 dx8, rg_dx8[1]; \
1505 \
1506 vadd.u32 g_block, g_block, dx8; \
1507 vdup.u32 dx8, b_dx8; \
1508 \
1509 vadd.u32 b_block, b_block, dx8; \
1510 vmovn.u16 u_whole_8, u_whole; \
1511 \
1512 add fb_ptr, fb_ptr, #16; \
1513 vmovn.u16 v_whole_8, v_whole; \
1514 \
1515 vst1.u32 { dither_offsets }, [ block_ptr_b, :128 ], c_32; \
1516 vmovn.u16 b_whole_8, b_whole; \
1517 \
1518 pld [ fb_ptr ]; \
1519 \
1520 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1521 subs span_num_blocks, span_num_blocks, #1; \
1522 \
1523 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1524 setup_blocks_texture_##swizzling(); \
1525 \
1526 vmovn.u16 r_whole_8, r_whole; \
1527 bne 4b; \
1528 \
1529 5: \
1530 vmovn.u16 g_whole_8, g_whole; \
1531 ldrh right_mask, [ span_edge_data, #edge_data_right_mask_offset ]; \
1532 \
1533 vld1.u32 { test_mask }, [ psx_gpu, :128 ]; \
1534 vdup.u8 draw_mask, right_mask; \
1535 \
1536 vmov.u32 fb_mask_ptrs[0], right_mask; \
1537 vtst.u16 draw_mask, draw_mask, test_mask; \
1538 vzip.u8 u_whole_8, v_whole_8; \
1539 \
1540 vbic.u16 uv_whole_8, uv_whole_8, draw_mask; \
1541 vst1.u32 { r_whole_8, g_whole_8 }, [ block_ptr_b, :128 ], c_32; \
1542 vst1.u32 { uv_whole_8 }, [ block_ptr_a, :128 ], c_32; \
1543 vst1.u32 { dither_offsets }, [ block_ptr_b, :128 ], c_32; \
1544 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32; \
1545 \
1546 1: \
1547 add span_uvrg_offset, span_uvrg_offset, #16; \
1548 add span_b_offset, span_b_offset, #4; \
1549 \
1550 add span_edge_data, span_edge_data, #8; \
1551 subs num_spans, num_spans, #1; \
1552 \
1553 strh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
1554 bne 0b; \
1555 \
1556 ldmia sp!, { r4 - r11, pc }; \
1557 \
1558 2: \
1559 /* TODO: Load from psx_gpu instead of saving/restoring these */\
1560 vpush { texture_mask }; \
1561 vpush { uvrg_dx4 }; \
1562 \
1563 stmdb sp!, { r0 - r3, r12, r14 }; \
1564 bl flush_render_block_buffer; \
1565 ldmia sp!, { r0 - r3, r12, r14 }; \
1566 \
1567 vpop { uvrg_dx4 }; \
1568 vpop { texture_mask }; \
1569 \
1570 vadd.u32 uvrg_dx8, uvrg_dx4, uvrg_dx4; \
1571 vmov.u8 fb_mask_ptrs, #0; \
1572 \
1573 mov num_blocks, span_num_blocks; \
1574 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1575 bal 3b \
1576
1577
1578setup_blocks_shaded_textured_builder(swizzled)
1579setup_blocks_shaded_textured_builder(unswizzled)
1580
1581
1582#define setup_blocks_unshaded_textured_builder(swizzling) \
1583.align 3; \
1584 \
1585function(setup_blocks_unshaded_textured_dithered_##swizzling##_indirect) \
1586 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
1587 add uvrg_dx_ptr, psx_gpu, #psx_gpu_uvrg_dx_offset; \
1588 \
1589 vld1.u32 { uvrg_dx }, [ uvrg_dx_ptr, :128 ]; \
1590 add texture_mask_ptr, psx_gpu, #psx_gpu_texture_mask_width_offset; \
1591 \
1592 cmp num_spans, #0; \
1593 bxeq lr; \
1594 \
1595 stmdb sp!, { r4 - r11, r14 }; \
1596 vshl.u32 uvrg_dx4, uvrg_dx, #2; \
1597 \
1598 vshl.u32 uvrg_dx8, uvrg_dx, #3; \
1599 \
1600 vld2.u8 { texture_mask_u[], texture_mask_v[] }, [ texture_mask_ptr, :16 ]; \
1601 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
1602 \
1603 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
1604 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
1605 \
1606 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1607 \
1608 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
1609 \
1610 0: \
1611 vmov.u8 fb_mask_ptrs, #0; \
1612 \
1613 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]; \
1614 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
1615 \
1616 ldrh y, [ span_edge_data, #edge_data_y_offset ]; \
c1817bd9 1617 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]; \
75e28f62
E
1618 \
1619 cmp span_num_blocks, #0; \
1620 beq 1f; \
1621 \
1622 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]; \
1623 add num_blocks, span_num_blocks, num_blocks; \
1624 \
1625 cmp num_blocks, #MAX_BLOCKS; \
1626 bgt 2f; \
1627 \
1628 3: \
1629 add fb_ptr, fb_ptr, y, lsl #11; \
1630 \
1631 vdup.u32 v_left_x, left_x; \
1632 and y, y, #0x3; \
1633 \
1634 ldr dither_row, [ dither_offset_ptr, y, lsl #2 ]; \
1635 add fb_ptr, fb_ptr, left_x, lsl #1; \
1636 \
1637 and dither_shift, left_x, #0x03; \
1638 \
1639 vld1.u32 { uvrg }, [ span_uvrg_offset, :128 ]; \
1640 vshr.u32 uvrg_dx, uvrg_dx4, #2; \
1641 \
1642 mov dither_shift, dither_shift, lsl #3; \
1643 vmla.u32 uvrg, uvrg_dx, v_left_x; \
1644 \
1645 mov c_32, #32; \
1646 subs span_num_blocks, span_num_blocks, #1; \
1647 \
1648 mov dither_row, dither_row, ror dither_shift; \
1649 \
1650 vdup.u32 dither_offsets_short, dither_row; \
1651 add block_span_ptr, psx_gpu, #psx_gpu_u_block_span_offset; \
1652 \
1653 vshll.s8 dither_offsets, dither_offsets_short, #4; \
1654 \
1655 vdup.u32 u_block, uv[0]; \
1656 \
1657 vdup.u32 v_block, uv[1]; \
1658 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1659 \
1660 vadd.u32 u_block, u_block, block_span; \
1661 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
1662 \
1663 vadd.u32 v_block, v_block, block_span; \
1664 add block_ptr_b, block_ptr_a, #16; \
1665 \
1666 vshrn.u32 u_whole_low, u_block, #16; \
1667 vshrn.u32 v_whole_low, v_block, #16; \
1668 \
1669 vdup.u32 dx4, uv_dx4[0]; \
1670 \
1671 vaddhn.u32 u_whole_high, u_block, dx4; \
1672 vdup.u32 dx4, uv_dx4[1]; \
1673 \
1674 vaddhn.u32 v_whole_high, v_block, dx4; \
1675 vdup.u32 dx8, uv_dx8[0]; \
1676 \
1677 vadd.u32 u_block, u_block, dx8; \
1678 vdup.u32 dx8, uv_dx8[1]; \
1679 \
1680 vadd.u32 v_block, v_block, dx8; \
1681 vmovn.u16 u_whole_8, u_whole; \
1682 \
1683 vmovn.u16 v_whole_8, v_whole; \
1684 \
1685 pld [ fb_ptr ]; \
1686 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1687 \
1688 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1689 setup_blocks_texture_##swizzling(); \
1690 \
1691 beq 5f; \
1692 \
1693 4: \
1694 vshrn.u32 u_whole_low, u_block, #16; \
1695 \
1696 vst2.u8 { u_whole_8, v_whole_8 }, [ block_ptr_a, :128 ], c_32; \
1697 vshrn.u32 v_whole_low, v_block, #16; \
1698 \
1699 add block_ptr_b, block_ptr_b, #32; \
1700 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32; \
1701 \
1702 vdup.u32 dx4, uv_dx4[0]; \
1703 vaddhn.u32 u_whole_high, u_block, dx4; \
1704 vdup.u32 dx4, uv_dx4[1]; \
1705 \
1706 vaddhn.u32 v_whole_high, v_block, dx4; \
1707 vdup.u32 dx8, uv_dx8[0]; \
1708 \
1709 vadd.u32 u_block, u_block, dx8; \
1710 vdup.u32 dx8, uv_dx8[1]; \
1711 \
1712 vadd.u32 v_block, v_block, dx8; \
1713 vmovn.u16 u_whole_8, u_whole; \
1714 \
1715 add fb_ptr, fb_ptr, #16; \
1716 vmovn.u16 v_whole_8, v_whole; \
1717 \
1718 vst1.u32 { dither_offsets }, [ block_ptr_b, :128 ], c_32; \
1719 pld [ fb_ptr ]; \
1720 \
1721 vmov.u32 fb_mask_ptrs[1], fb_ptr; \
1722 subs span_num_blocks, span_num_blocks, #1; \
1723 \
1724 vand.u8 uv_whole_8, uv_whole_8, texture_mask; \
1725 setup_blocks_texture_##swizzling(); \
1726 \
1727 bne 4b; \
1728 \
1729 5: \
1730 ldrh right_mask, [ span_edge_data, #edge_data_right_mask_offset ]; \
1731 \
1732 vld1.u32 { test_mask }, [ psx_gpu, :128 ]; \
1733 vdup.u8 draw_mask, right_mask; \
1734 \
1735 vmov.u32 fb_mask_ptrs[0], right_mask; \
1736 vtst.u16 draw_mask, draw_mask, test_mask; \
1737 vzip.u8 u_whole_8, v_whole_8; \
1738 \
1739 vbic.u16 uv_whole_8, uv_whole_8, draw_mask; \
1740 add block_ptr_b, block_ptr_b, #32; \
1741 vst1.u32 { uv_whole_8 }, [ block_ptr_a, :128 ], c_32; \
1742 vst1.u32 { dither_offsets }, [ block_ptr_b, :128 ], c_32; \
1743 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32; \
1744 \
1745 1: \
1746 add span_uvrg_offset, span_uvrg_offset, #16; \
1747 add span_edge_data, span_edge_data, #8; \
1748 subs num_spans, num_spans, #1; \
1749 \
1750 strh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
1751 bne 0b; \
1752 \
1753 ldmia sp!, { r4 - r11, pc }; \
1754 \
1755 2: \
1756 /* TODO: Load from psx_gpu instead of saving/restoring these */\
1757 vpush { texture_mask }; \
1758 vpush { uvrg_dx4 }; \
1759 \
1760 stmdb sp!, { r0 - r3, r12, r14 }; \
1761 bl flush_render_block_buffer; \
1762 ldmia sp!, { r0 - r3, r12, r14 }; \
1763 \
1764 vpop { uvrg_dx4 }; \
1765 vpop { texture_mask }; \
1766 \
1767 vadd.u32 uvrg_dx8, uvrg_dx4, uvrg_dx4; \
1768 vmov.u8 fb_mask_ptrs, #0; \
1769 \
1770 mov num_blocks, span_num_blocks; \
1771 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
1772 bal 3b \
1773
1774
1775setup_blocks_unshaded_textured_builder(swizzled)
1776setup_blocks_unshaded_textured_builder(unswizzled)
1777
1778
1779.align 3
1780
1781function(setup_blocks_unshaded_untextured_undithered_unswizzled_indirect)
1782 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]
1783 veor.u32 draw_mask, draw_mask, draw_mask
1784
1785 cmp num_spans, #0
1786 bxeq lr
1787
1788 stmdb sp!, { r4 - r11, r14 }
1789 vld1.u32 { test_mask }, [ psx_gpu, :128 ]
1790
1791 ldr color, [ psx_gpu, #psx_gpu_triangle_color_offset ]
1792
1793 ubfx color_r, color, #3, #5
1794 ubfx color_g, color, #11, #5
1795 ubfx color_b, color, #19, #5
1796
1797 orr color, color_r, color_b, lsl #10
1798 orr color, color, color_g, lsl #5
1799
1800 vdup.u16 colors, color
1801
1802 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]
1803 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset
1804
1805 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset
1806 add block_ptr_a, block_ptr_a, num_blocks, lsl #6
1807
1808 0:
1809 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]
1810 ldrh y, [ span_edge_data, #edge_data_y_offset ]
1811
c1817bd9 1812 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]
75e28f62
E
1813
1814 cmp span_num_blocks, #0
1815 beq 1f
1816
1817 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]
1818 add num_blocks, span_num_blocks, num_blocks
1819
1820 cmp num_blocks, #MAX_BLOCKS
1821 bgt 2f
1822
1823 3:
1824 add fb_ptr, fb_ptr, y, lsl #11
1825 and y, y, #0x3
1826
1827 add fb_ptr, fb_ptr, left_x, lsl #1
1828 mov c_32, #32
1829
1830 subs span_num_blocks, span_num_blocks, #1
1831
1832 add block_ptr_b, block_ptr_a, #16
1833 pld [ fb_ptr ]
1834
1835 vmov.u32 fb_mask_ptrs[1], fb_ptr
1836 beq 5f
1837
1838 4:
1839 vst1.u32 { draw_mask }, [ block_ptr_a, :128 ], c_32
1840 vst1.u32 { colors }, [ block_ptr_b, :128 ], c_32
1841 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32
1842
1843 add fb_ptr, fb_ptr, #16
1844 add block_ptr_b, block_ptr_b, #32
1845
1846 pld [ fb_ptr ]
1847
1848 vmov.u32 fb_mask_ptrs[1], fb_ptr
1849 subs span_num_blocks, span_num_blocks, #1
1850
1851 bne 4b
1852
1853 5:
1854 ldrh right_mask, [ span_edge_data, #edge_data_right_mask_offset ]
1855
1856 vdup.u8 draw_mask_edge, right_mask
1857 vtst.u16 draw_mask_edge, draw_mask_edge, test_mask
1858
1859 vst1.u32 { colors }, [ block_ptr_b, :128 ], c_32
1860 vst1.u32 { draw_mask_edge }, [ block_ptr_a, :128 ], c_32
1861 add block_ptr_b, block_ptr_b, #32
1862 vst1.u32 { b_whole_8, fb_mask_ptrs }, [ block_ptr_a, :128 ], c_32
1863
1864 1:
1865 add span_edge_data, span_edge_data, #8
1866 subs num_spans, num_spans, #1
1867
1868 strh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]
1869 bne 0b
1870
1871 ldmia sp!, { r4 - r11, pc }
1872
1873 2:
1874 vpush { colors }
1875
1876 stmdb sp!, { r0 - r3, r12, r14 }
1877 bl flush_render_block_buffer
1878 ldmia sp!, { r0 - r3, r12, r14 }
1879
1880 vpop { colors }
1881
1882 vld1.u32 { test_mask }, [ psx_gpu, :128 ]
1883 veor.u32 draw_mask, draw_mask, draw_mask
1884
1885 mov num_blocks, span_num_blocks
1886 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset
1887 bal 3b
1888
1889
1890#define mask_msb_scalar r14
1891
1892#define msb_mask q15
1893
1894#define pixels_low d16
1895
1896#define msb_mask_low d30
1897#define msb_mask_high d31
1898
1899
1900.align 3
1901
1902function(setup_blocks_unshaded_untextured_undithered_unswizzled_direct)
1903 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]
1904
1905 cmp num_spans, #0
1906 bxeq lr
1907
1908 stmdb sp!, { r4 - r11, r14 }
1909
1910 ldr color, [ psx_gpu, #psx_gpu_triangle_color_offset ]
1911
1912 ubfx color_r, color, #3, #5
1913 ubfx color_g, color, #11, #5
1914
1915 ldrh mask_msb_scalar, [ psx_gpu, #psx_gpu_mask_msb_offset ]
1916 ubfx color_b, color, #19, #5
1917
1918 orr color, color_r, color_b, lsl #10
1919 orr color, color, color_g, lsl #5
1920 orr color, color, mask_msb_scalar
1921
1922 vdup.u16 colors, color
1923
1924 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset
3867c6ef
E
1925 orr color, color, lsl #16
1926
75e28f62
E
1927
1928 0:
1929 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]
1930 ldrh y, [ span_edge_data, #edge_data_y_offset ]
1931
c1817bd9 1932 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]
75e28f62
E
1933
1934 cmp span_num_blocks, #0
1935 beq 1f
1936
1937 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]
1938
1939 add fb_ptr, fb_ptr, y, lsl #11
1940 subs span_num_blocks, span_num_blocks, #1
1941
1942 add fb_ptr, fb_ptr, left_x, lsl #1
1943 beq 3f
1944
1945 2:
1946 vst1.u32 { colors }, [ fb_ptr ]!
1947 subs span_num_blocks, span_num_blocks, #1
1948
1949 bne 2b
1950
1951 3:
1952 ldrb right_mask, [ span_edge_data, #edge_data_right_mask_offset ]
75e28f62 1953
3867c6ef
E
1954 cmp right_mask, #0x0
1955 beq 5f
1956
1957 tst right_mask, #0xF
1958 streq color, [ fb_ptr ], #4
1959 moveq right_mask, right_mask, lsr #4
1960 streq color, [ fb_ptr ], #4
1961
1962 tst right_mask, #0x3
1963 streq color, [ fb_ptr ], #4
1964 moveq right_mask, right_mask, lsr #2
1965
1966 tst right_mask, #0x1
1967 streqh color, [ fb_ptr ]
75e28f62
E
1968
1969 1:
1970 add span_edge_data, span_edge_data, #8
1971 subs num_spans, num_spans, #1
75e28f62
E
1972 bne 0b
1973
1974 ldmia sp!, { r4 - r11, pc }
1975
3867c6ef
E
1976 5:
1977 vst1.u32 { colors }, [ fb_ptr ]
1978 bal 1b
75e28f62
E
1979
1980
1981#undef c_64
1982
1983#define c_64 r7
1984#define rg_dx_ptr r2
1985
1986
1987#undef r_block
1988#undef g_block
1989#undef b_block
1990#undef r_whole
1991#undef g_whole
1992#undef b_whole
1993#undef r_whole_low
1994#undef r_whole_high
1995#undef g_whole_low
1996#undef g_whole_high
1997#undef b_whole_low
1998#undef b_whole_high
1999#undef r_whole_8
2000#undef g_whole_8
2001#undef b_whole_8
2002#undef dither_offsets
2003#undef rg_dx4
2004#undef rg_dx8
2005#undef dx4
2006#undef dx8
2007#undef v_left_x
2008#undef uvrg
2009#undef block_span
2010#undef rg
2011#undef draw_mask
2012#undef test_mask
2013
2014#define r_block q0
2015#define g_block q1
2016#define b_block q2
2017
2018#define r_whole q3
2019#define g_whole q4
2020#define b_whole q5
2021
2022#define r_whole_low d6
2023#define r_whole_high d7
2024#define g_whole_low d8
2025#define g_whole_high d9
2026#define b_whole_low d10
2027#define b_whole_high d11
2028
2029#define gb_whole_8 q6
2030
2031#define g_whole_8 d12
2032#define b_whole_8 d13
2033
2034#define r_whole_8 d14
2035
2036#define pixels q8
2037
2038#define rg_dx4 d18
2039#define rg_dx8 d19
2040
2041#define dx4 q10
2042#define dx8 q10
2043
2044#define v_left_x d6
2045#define uvrg q4
2046#define block_span q5
2047
2048#define rg d9
2049
2050#define d64_1 d22
2051#define d64_128 d23
2052
2053#define d128_4 q12
2054#define d128_0x7 q13
2055
2056#define d64_4 d24
2057
2058#define dither_offsets q14
2059#define draw_mask q15
2060
2061#define dither_offsets_low d28
2062
2063#define rg_dx d0
2064#define test_mask q10
2065
2066
2067#define setup_blocks_shaded_untextured_dither_a_dithered() \
2068 vqadd.u8 r_whole_8, r_whole_8, dither_offsets_low; \
2069 vqadd.u8 gb_whole_8, gb_whole_8, dither_offsets; \
2070
2071#define setup_blocks_shaded_untextured_dither_b_dithered() \
2072 vqsub.u8 r_whole_8, r_whole_8, d64_4; \
2073 vqsub.u8 gb_whole_8, gb_whole_8, d128_4 \
2074
2075#define setup_blocks_shaded_untextured_dither_a_undithered() \
2076
2077#define setup_blocks_shaded_untextured_dither_b_undithered() \
2078
2079
2080#define setup_blocks_shaded_untextured_indirect_builder(dithering) \
2081.align 3; \
2082 \
2083function(setup_blocks_shaded_untextured_##dithering##_unswizzled_indirect) \
2084 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
2085 add rg_dx_ptr, psx_gpu, #(psx_gpu_uvrg_dx_offset + 8); \
2086 \
2087 vld1.u32 { rg_dx }, [ rg_dx_ptr, :64 ]; \
2088 \
2089 cmp num_spans, #0; \
2090 bxeq lr; \
2091 \
2092 stmdb sp!, { r4 - r11, r14 }; \
2093 vshl.u32 rg_dx4, rg_dx, #2; \
2094 \
2095 ldr b_dx, [ psx_gpu, #psx_gpu_b_dx_offset ]; \
2096 vshl.u32 rg_dx8, rg_dx, #3; \
2097 \
2098 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
2099 \
2100 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
2101 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
2102 \
2103 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
2104 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
2105 \
2106 add block_ptr_a, block_ptr_a, num_blocks, lsl #6; \
2107 vmov.u8 d64_1, #1; \
2108 \
2109 vmov.u8 d128_4, #4; \
2110 vmov.u8 d64_128, #128; \
2111 \
2112 vmov.u8 d128_0x7, #0x7; \
2113 \
2114 0: \
2115 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]; \
2116 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
2117 \
2118 ldrh y, [ span_edge_data, #edge_data_y_offset ]; \
c1817bd9 2119 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]; \
75e28f62
E
2120 \
2121 cmp span_num_blocks, #0; \
2122 beq 1f; \
2123 \
2124 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]; \
2125 add num_blocks, span_num_blocks, num_blocks; \
2126 \
2127 cmp num_blocks, #MAX_BLOCKS; \
2128 bgt 2f; \
2129 \
2130 3: \
2131 ldr b, [ span_b_offset ]; \
2132 add fb_ptr, fb_ptr, y, lsl #11; \
2133 \
2134 vdup.u32 v_left_x, left_x; \
2135 and y, y, #0x3; \
2136 \
2137 ldr dither_row, [ dither_offset_ptr, y, lsl #2 ]; \
2138 add fb_ptr, fb_ptr, left_x, lsl #1; \
2139 \
2140 mla b, b_dx, left_x, b; \
2141 and dither_shift, left_x, #0x03; \
2142 \
2143 vld1.u32 { uvrg }, [ span_uvrg_offset, :128 ]; \
2144 vshr.u32 rg_dx, rg_dx4, #2; \
2145 \
2146 mov dither_shift, dither_shift, lsl #3; \
2147 vmla.u32 rg, rg_dx, v_left_x; \
2148 \
2149 mov c_64, #64; \
2150 subs span_num_blocks, span_num_blocks, #1; \
2151 \
2152 mov dither_row, dither_row, ror dither_shift; \
2153 mov b_dx4, b_dx, lsl #2; \
2154 \
2155 vdup.u32 dither_offsets, dither_row; \
2156 add block_span_ptr, psx_gpu, #psx_gpu_r_block_span_offset; \
2157 \
2158 vdup.u32 b_block, b; \
2159 vadd.u8 dither_offsets, dither_offsets, d128_4; \
2160 \
2161 mov b_dx8, b_dx, lsl #3; \
2162 vdup.u32 r_block, rg[0]; \
2163 vdup.u32 g_block, rg[1]; \
2164 \
2165 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
2166 \
2167 vadd.u32 r_block, r_block, block_span; \
2168 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
2169 \
2170 vadd.u32 g_block, g_block, block_span; \
2171 vld1.u32 { block_span }, [ block_span_ptr, :128 ]; \
2172 \
2173 vadd.u32 b_block, b_block, block_span; \
2174 add block_ptr_b, block_ptr_a, #16; \
2175 \
2176 vshrn.u32 r_whole_low, r_block, #16; \
2177 vshrn.u32 g_whole_low, g_block, #16; \
2178 vshrn.u32 b_whole_low, b_block, #16; \
2179 vdup.u32 dx4, rg_dx4[0]; \
2180 \
2181 vaddhn.u32 r_whole_high, r_block, dx4; \
2182 vdup.u32 dx4, rg_dx4[1]; \
2183 \
2184 vaddhn.u32 g_whole_high, g_block, dx4; \
2185 vdup.u32 dx4, b_dx4; \
2186 \
2187 vaddhn.u32 b_whole_high, b_block, dx4; \
2188 vdup.u32 dx8, rg_dx8[0]; \
2189 \
2190 vadd.u32 r_block, r_block, dx8; \
2191 vdup.u32 dx8, rg_dx8[1]; \
2192 \
2193 vadd.u32 g_block, g_block, dx8; \
2194 vdup.u32 dx8, b_dx8; \
2195 \
2196 vadd.u32 b_block, b_block, dx8; \
2197 \
2198 vmovn.u16 r_whole_8, r_whole; \
2199 vmovn.u16 g_whole_8, g_whole; \
2200 vmovn.u16 b_whole_8, b_whole; \
2201 \
2202 beq 5f; \
2203 veor.u32 draw_mask, draw_mask, draw_mask; \
2204 \
2205 4: \
2206 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2207 vshrn.u32 r_whole_low, r_block, #16; \
2208 \
2209 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2210 vshrn.u32 g_whole_low, g_block, #16; \
2211 \
2212 vshrn.u32 b_whole_low, b_block, #16; \
2213 str fb_ptr, [ block_ptr_a, #44 ]; \
2214 \
2215 vdup.u32 dx4, rg_dx4[0]; \
2216 vshr.u8 r_whole_8, r_whole_8, #3; \
2217 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
2218 \
2219 vaddhn.u32 r_whole_high, r_block, dx4; \
2220 vdup.u32 dx4, rg_dx4[1]; \
2221 \
2222 vaddhn.u32 g_whole_high, g_block, dx4; \
2223 vdup.u32 dx4, b_dx4; \
2224 \
2225 vaddhn.u32 b_whole_high, b_block, dx4; \
2226 vdup.u32 dx8, rg_dx8[0]; \
2227 \
2228 vmull.u8 pixels, r_whole_8, d64_1; \
2229 vmlal.u8 pixels, g_whole_8, d64_4; \
2230 vmlal.u8 pixels, b_whole_8, d64_128; \
2231 \
2232 vadd.u32 r_block, r_block, dx8; \
2233 vdup.u32 dx8, rg_dx8[1]; \
2234 \
2235 vadd.u32 g_block, g_block, dx8; \
2236 vdup.u32 dx8, b_dx8; \
2237 \
2238 vadd.u32 b_block, b_block, dx8; \
2239 add fb_ptr, fb_ptr, #16; \
2240 \
2241 vmovn.u16 r_whole_8, r_whole; \
2242 vmovn.u16 g_whole_8, g_whole; \
2243 vmovn.u16 b_whole_8, b_whole; \
2244 \
2245 vst1.u32 { draw_mask }, [ block_ptr_a, :128 ], c_64; \
2246 vst1.u32 { pixels }, [ block_ptr_b, :128 ], c_64; \
2247 \
2248 pld [ fb_ptr ]; \
2249 \
2250 subs span_num_blocks, span_num_blocks, #1; \
2251 bne 4b; \
2252 \
2253 5: \
2254 str fb_ptr, [ block_ptr_a, #44 ]; \
2255 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2256 \
2257 ldrh right_mask, [ span_edge_data, #edge_data_right_mask_offset ]; \
2258 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2259 \
2260 vshr.u8 r_whole_8, r_whole_8, #3; \
2261 vdup.u8 draw_mask, right_mask; \
2262 \
2263 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
2264 vld1.u32 { test_mask }, [ psx_gpu, :128 ]; \
2265 \
2266 vtst.u16 draw_mask, draw_mask, test_mask; \
2267 \
2268 vmull.u8 pixels, r_whole_8, d64_1; \
2269 vmlal.u8 pixels, g_whole_8, d64_4; \
2270 vmlal.u8 pixels, b_whole_8, d64_128; \
2271 \
2272 vst1.u32 { draw_mask }, [ block_ptr_a, :128 ], c_64; \
2273 vst1.u32 { pixels }, [ block_ptr_b, :128 ], c_64; \
2274 \
2275 1: \
2276 add span_uvrg_offset, span_uvrg_offset, #16; \
2277 add span_b_offset, span_b_offset, #4; \
2278 \
2279 add span_edge_data, span_edge_data, #8; \
2280 subs num_spans, num_spans, #1; \
2281 \
2282 strh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
2283 bne 0b; \
2284 \
2285 ldmia sp!, { r4 - r11, pc }; \
2286 \
2287 2: \
2288 /* TODO: Load from psx_gpu instead of saving/restoring these */\
2289 vpush { rg_dx4 }; \
2290 \
2291 stmdb sp!, { r0 - r3, r12, r14 }; \
2292 bl flush_render_block_buffer; \
2293 ldmia sp!, { r0 - r3, r12, r14 }; \
2294 \
2295 vpop { rg_dx4 }; \
2296 \
2297 vmov.u8 d64_1, #1; \
2298 vmov.u8 d128_4, #4; \
2299 vmov.u8 d64_128, #128; \
2300 vmov.u8 d128_0x7, #0x7; \
2301 \
2302 vadd.u32 rg_dx8, rg_dx4, rg_dx4; \
2303 \
2304 mov num_blocks, span_num_blocks; \
2305 add block_ptr_a, psx_gpu, #psx_gpu_blocks_offset; \
2306 bal 3b \
2307
2308
2309setup_blocks_shaded_untextured_indirect_builder(undithered)
2310setup_blocks_shaded_untextured_indirect_builder(dithered)
2311
2312
2313#undef draw_mask
2314
2315#define mask_msb_ptr r14
2316
2317#define draw_mask q0
2318#define pixels_low d16
3867c6ef 2319#define pixels_high d17
75e28f62
E
2320
2321
2322
2323#define setup_blocks_shaded_untextured_direct_builder(dithering) \
2324.align 3; \
2325 \
2326function(setup_blocks_shaded_untextured_##dithering##_unswizzled_direct) \
2327 ldrh num_spans, [ psx_gpu, #psx_gpu_num_spans_offset ]; \
2328 add rg_dx_ptr, psx_gpu, #(psx_gpu_uvrg_dx_offset + 8); \
2329 \
2330 vld1.u32 { rg_dx }, [ rg_dx_ptr, :64 ]; \
2331 \
2332 cmp num_spans, #0; \
2333 bxeq lr; \
2334 \
2335 stmdb sp!, { r4 - r11, r14 }; \
2336 vshl.u32 rg_dx4, rg_dx, #2; \
2337 \
2338 ldr b_dx, [ psx_gpu, #psx_gpu_b_dx_offset ]; \
2339 vshl.u32 rg_dx8, rg_dx, #3; \
2340 \
2341 add span_uvrg_offset, psx_gpu, #psx_gpu_span_uvrg_offset_offset; \
2342 add span_edge_data, psx_gpu, #psx_gpu_span_edge_data_offset; \
2343 \
2344 add span_b_offset, psx_gpu, #psx_gpu_span_b_offset_offset; \
2345 vmov.u8 d64_1, #1; \
2346 \
2347 vmov.u8 d128_4, #4; \
2348 vmov.u8 d64_128, #128; \
2349 \
2350 vmov.u8 d128_0x7, #0x7; \
2351 add mask_msb_ptr, psx_gpu, #psx_gpu_mask_msb_offset; \
2352 vld1.u16 { msb_mask_low[], msb_mask_high[] }, [ mask_msb_ptr, :16 ]; \
2353 \
2354 0: \
2355 ldrh span_num_blocks, [ span_edge_data, #edge_data_num_blocks_offset ]; \
2356 add dither_offset_ptr, psx_gpu, #psx_gpu_dither_table_offset; \
2357 \
2358 ldrh y, [ span_edge_data, #edge_data_y_offset ]; \
c1817bd9 2359 ldr fb_ptr, [ psx_gpu, #psx_gpu_vram_out_ptr_offset ]; \
75e28f62
E
2360 \
2361 cmp span_num_blocks, #0; \
2362 beq 1f; \
2363 \
2364 ldrh left_x, [ span_edge_data, #edge_data_left_x_offset ]; \
2365 add fb_ptr, fb_ptr, y, lsl #11; \
2366 \
2367 ldr b, [ span_b_offset ]; \
2368 vdup.u32 v_left_x, left_x; \
2369 and y, y, #0x3; \
2370 \
2371 ldr dither_row, [ dither_offset_ptr, y, lsl #2 ]; \
2372 add fb_ptr, fb_ptr, left_x, lsl #1; \
2373 \
2374 mla b, b_dx, left_x, b; \
2375 and dither_shift, left_x, #0x03; \
2376 \
2377 vld1.u32 { uvrg }, [ span_uvrg_offset, :128 ]; \
2378 vshr.u32 rg_dx, rg_dx4, #2; \
2379 \
2380 mov dither_shift, dither_shift, lsl #3; \
2381 vmla.u32 rg, rg_dx, v_left_x; \
2382 \
2383 subs span_num_blocks, span_num_blocks, #1; \
2384 \
2385 mov dither_row, dither_row, ror dither_shift; \
2386 mov b_dx4, b_dx, lsl #2; \
2387 \
2388 vdup.u32 dither_offsets, dither_row; \
2389 add block_span_ptr, psx_gpu, #psx_gpu_r_block_span_offset; \
2390 \
2391 vdup.u32 b_block, b; \
2392 vadd.u8 dither_offsets, dither_offsets, d128_4; \
2393 \
2394 mov b_dx8, b_dx, lsl #3; \
2395 vdup.u32 r_block, rg[0]; \
2396 vdup.u32 g_block, rg[1]; \
2397 \
2398 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
2399 \
2400 vadd.u32 r_block, r_block, block_span; \
2401 vld1.u32 { block_span }, [ block_span_ptr, :128 ]!; \
2402 \
2403 vadd.u32 g_block, g_block, block_span; \
2404 vld1.u32 { block_span }, [ block_span_ptr, :128 ]; \
2405 \
2406 vadd.u32 b_block, b_block, block_span; \
2407 add block_ptr_b, block_ptr_a, #16; \
2408 \
2409 vshrn.u32 r_whole_low, r_block, #16; \
2410 vshrn.u32 g_whole_low, g_block, #16; \
2411 vshrn.u32 b_whole_low, b_block, #16; \
2412 vdup.u32 dx4, rg_dx4[0]; \
2413 \
2414 vaddhn.u32 r_whole_high, r_block, dx4; \
2415 vdup.u32 dx4, rg_dx4[1]; \
2416 \
2417 vaddhn.u32 g_whole_high, g_block, dx4; \
2418 vdup.u32 dx4, b_dx4; \
2419 \
2420 vaddhn.u32 b_whole_high, b_block, dx4; \
2421 vdup.u32 dx8, rg_dx8[0]; \
2422 \
2423 vadd.u32 r_block, r_block, dx8; \
2424 vdup.u32 dx8, rg_dx8[1]; \
2425 \
2426 vadd.u32 g_block, g_block, dx8; \
2427 vdup.u32 dx8, b_dx8; \
2428 \
2429 vadd.u32 b_block, b_block, dx8; \
2430 \
2431 vmovn.u16 r_whole_8, r_whole; \
2432 vmovn.u16 g_whole_8, g_whole; \
2433 vmovn.u16 b_whole_8, b_whole; \
2434 \
2435 beq 3f; \
2436 \
2437 2: \
2438 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2439 vshrn.u32 r_whole_low, r_block, #16; \
2440 \
2441 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2442 vshrn.u32 g_whole_low, g_block, #16; \
2443 \
2444 vshrn.u32 b_whole_low, b_block, #16; \
2445 \
2446 vdup.u32 dx4, rg_dx4[0]; \
2447 vshr.u8 r_whole_8, r_whole_8, #3; \
2448 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
2449 \
2450 vaddhn.u32 r_whole_high, r_block, dx4; \
2451 vdup.u32 dx4, rg_dx4[1]; \
2452 \
2453 vmov pixels, msb_mask; \
2454 vaddhn.u32 g_whole_high, g_block, dx4; \
2455 vdup.u32 dx4, b_dx4; \
2456 \
2457 vaddhn.u32 b_whole_high, b_block, dx4; \
2458 vdup.u32 dx8, rg_dx8[0]; \
2459 \
2460 vmlal.u8 pixels, r_whole_8, d64_1; \
2461 vmlal.u8 pixels, g_whole_8, d64_4; \
2462 vmlal.u8 pixels, b_whole_8, d64_128; \
2463 \
2464 vadd.u32 r_block, r_block, dx8; \
2465 vdup.u32 dx8, rg_dx8[1]; \
2466 \
2467 vadd.u32 g_block, g_block, dx8; \
2468 vdup.u32 dx8, b_dx8; \
2469 \
2470 vadd.u32 b_block, b_block, dx8; \
2471 \
2472 vmovn.u16 r_whole_8, r_whole; \
2473 vmovn.u16 g_whole_8, g_whole; \
2474 vmovn.u16 b_whole_8, b_whole; \
2475 \
2476 vst1.u32 { pixels }, [ fb_ptr ]!; \
2477 subs span_num_blocks, span_num_blocks, #1; \
2478 bne 2b; \
2479 \
2480 3: \
2481 setup_blocks_shaded_untextured_dither_a_##dithering(); \
2482 \
3867c6ef 2483 ldrh right_mask, [ span_edge_data, #edge_data_right_mask_offset ]; \
75e28f62
E
2484 setup_blocks_shaded_untextured_dither_b_##dithering(); \
2485 \
2486 vshr.u8 r_whole_8, r_whole_8, #3; \
3867c6ef 2487 rbit right_mask, right_mask; \
75e28f62
E
2488 vmov pixels, msb_mask; \
2489 vbic.u8 gb_whole_8, gb_whole_8, d128_0x7; \
3867c6ef 2490 clz right_mask, right_mask; \
75e28f62
E
2491 \
2492 vmlal.u8 pixels, r_whole_8, d64_1; \
2493 vmlal.u8 pixels, g_whole_8, d64_4; \
2494 vmlal.u8 pixels, b_whole_8, d64_128; \
2495 \
3867c6ef
E
2496 ldr pc, [ pc, right_mask, lsl #2 ]; \
2497 nop; \
2498 nop; \
2499 .word 4f; \
2500 .word 5f; \
2501 .word 6f; \
2502 .word 7f; \
2503 .word 8f; \
2504 .word 9f; \
2505 .word 10f; \
2506 .word 11f; \
2507 \
75e28f62 2508 4: \
3867c6ef
E
2509 vst1.u16 { pixels_low[0] }, [ fb_ptr ]; \
2510 bal 1f; \
2511 \
2512 5: \
2513 vst1.u32 { pixels_low[0] }, [ fb_ptr ]; \
2514 bal 1f; \
2515 \
2516 6: \
2517 vst1.u32 { pixels_low[0] }, [ fb_ptr ]!; \
2518 vst1.u16 { pixels_low[2] }, [ fb_ptr ]; \
2519 bal 1f; \
2520 \
2521 7: \
2522 vst1.u32 { pixels_low }, [ fb_ptr ]; \
2523 bal 1f; \
2524 \
2525 8: \
2526 vst1.u32 { pixels_low }, [ fb_ptr ]!; \
2527 vst1.u16 { pixels_high[0] }, [ fb_ptr ]; \
2528 bal 1f; \
2529 \
2530 9: \
2531 vst1.u32 { pixels_low }, [ fb_ptr ]!; \
2532 vst1.u32 { pixels_high[0] }, [ fb_ptr ]!; \
2533 bal 1f; \
2534 \
2535 10: \
2536 vst1.u32 { pixels_low }, [ fb_ptr ]!; \
2537 vst1.u32 { pixels_high[0] }, [ fb_ptr ]!; \
2538 vst1.u16 { pixels_high[2] }, [ fb_ptr ]; \
2539 bal 1f; \
2540 \
2541 11: \
2542 vst1.u32 { pixels }, [ fb_ptr ]; \
2543 bal 1f; \
75e28f62
E
2544 \
2545 1: \
2546 add span_uvrg_offset, span_uvrg_offset, #16; \
2547 add span_b_offset, span_b_offset, #4; \
2548 \
2549 add span_edge_data, span_edge_data, #8; \
2550 subs num_spans, num_spans, #1; \
2551 \
2552 bne 0b; \
2553 \
2554 ldmia sp!, { r4 - r11, pc } \
2555
2556setup_blocks_shaded_untextured_direct_builder(undithered)
2557setup_blocks_shaded_untextured_direct_builder(dithered)
2558
2559
2560#undef psx_gpu
2561#undef num_blocks
2562#undef triangle
2563#undef c_64
2564
2565#define psx_gpu r0
2566#define block_ptr r1
2567#define num_blocks r2
2568#define uv_01 r3
2569#define uv_23 r4
2570#define uv_45 r5
2571#define uv_67 r6
2572#define uv_0 r7
2573#define uv_1 r3
2574#define uv_2 r8
2575#define uv_3 r4
2576#define uv_4 r9
2577#define uv_5 r5
2578#define uv_6 r10
2579#define uv_7 r6
2580#define texture_ptr r11
2581
2582#define pixel_0 r7
2583#define pixel_1 r3
2584#define pixel_2 r8
2585#define pixel_3 r4
2586#define pixel_4 r9
2587#define pixel_5 r5
2588#define pixel_6 r10
2589#define pixel_7 r6
2590
2591#define pixels_a r7
2592#define pixels_b r9
2593#define pixels_c r8
2594#define pixels_d r10
2595
2596#define c_64 r0
2597
2598#define clut_ptr r12
2599#define current_texture_mask r5
2600#define dirty_textures_mask r6
2601
2602#define texels d0
2603
2604#define clut_low_a d2
2605#define clut_low_b d3
2606#define clut_high_a d4
2607#define clut_high_b d5
2608
2609#define clut_a q1
2610#define clut_b q2
2611
2612#define texels_low d6
2613#define texels_high d7
2614
2615.align 3
2616
2617function(texture_blocks_untextured)
2618 bx lr
2619
2620
2621.align 3
2622
2623function(texture_blocks_4bpp)
2624 stmdb sp!, { r3 - r11, r14 }
2625 add block_ptr, psx_gpu, #psx_gpu_blocks_offset
2626
2627 ldr texture_ptr, [ psx_gpu, #psx_gpu_texture_page_ptr_offset ]
2628 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]
2629
2630 ldr clut_ptr, [ psx_gpu, #psx_gpu_clut_ptr_offset ]
2631 vld1.u32 { clut_a, clut_b }, [ clut_ptr, :128 ]
2632
2633 ldr current_texture_mask, [ psx_gpu, #psx_gpu_current_texture_mask_offset ]
2634 vuzp.u8 clut_a, clut_b
2635
2636 ldr dirty_textures_mask, [ psx_gpu, #psx_gpu_dirty_textures_4bpp_mask_offset ]
2637 tst dirty_textures_mask, current_texture_mask
2638
2639 bne 1f
2640 mov c_64, #64
2641
26420:
2643 ldm block_ptr, { uv_01, uv_23, uv_45, uv_67 }
2644
2645 uxtah uv_0, texture_ptr, uv_01
2646 uxtah uv_1, texture_ptr, uv_01, ror #16
2647
2648 uxtah uv_2, texture_ptr, uv_23
2649 uxtah uv_3, texture_ptr, uv_23, ror #16
2650
2651 uxtah uv_4, texture_ptr, uv_45
2652 ldrb pixel_0, [ uv_0 ]
2653
2654 uxtah uv_5, texture_ptr, uv_45, ror #16
2655 ldrb pixel_1, [ uv_1 ]
2656
2657 uxtah uv_6, texture_ptr, uv_67
2658 ldrb pixel_2, [ uv_2 ]
2659
2660 uxtah uv_7, texture_ptr, uv_67, ror #16
2661 ldrb pixel_3, [ uv_3 ]
2662
2663 ldrb pixel_4, [ uv_4 ]
2664 subs num_blocks, num_blocks, #1
2665
2666 ldrb pixel_5, [ uv_5 ]
2667 orr pixels_a, pixel_0, pixel_1, lsl #8
2668
2669 ldrb pixel_6, [ uv_6 ]
2670 orr pixels_b, pixel_4, pixel_5, lsl #8
2671
2672 ldrb pixel_7, [ uv_7 ]
2673 orr pixels_a, pixels_a, pixel_2, lsl #16
2674
2675 orr pixels_b, pixels_b, pixel_6, lsl #16
2676 orr pixels_a, pixels_a, pixel_3, lsl #24
2677
2678 orr pixels_b, pixels_b, pixel_7, lsl #24
2679 vmov.u32 texels, pixels_a, pixels_b
2680
2681 vtbl.8 texels_low, { clut_low_a, clut_low_b }, texels
2682 vtbl.8 texels_high, { clut_high_a, clut_high_b }, texels
2683
2684 vst2.u8 { texels_low, texels_high }, [ block_ptr, :128 ], c_64
2685 bne 0b
2686
2687 ldmia sp!, { r3 - r11, pc }
2688
26891:
2690 stmdb sp!, { r1 - r2 }
2691 bl update_texture_4bpp_cache
2692
2693 mov c_64, #64
2694 ldmia sp!, { r1 - r2 }
2695 bal 0b
2696
2697
2698.align 3
2699
2700function(texture_blocks_8bpp)
2701 stmdb sp!, { r3 - r11, r14 }
2702 add block_ptr, psx_gpu, #psx_gpu_blocks_offset
2703
2704 ldr texture_ptr, [ psx_gpu, #psx_gpu_texture_page_ptr_offset ]
2705 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]
2706
2707 ldr clut_ptr, [ psx_gpu, #psx_gpu_clut_ptr_offset ]
2708 ldr current_texture_mask, [ psx_gpu, #psx_gpu_current_texture_mask_offset ]
2709
2710 ldr dirty_textures_mask, [ psx_gpu, #psx_gpu_dirty_textures_8bpp_mask_offset ]
2711 tst dirty_textures_mask, current_texture_mask
2712
2713 bne 1f
2714 nop
2715
27160:
2717 ldm block_ptr, { uv_01, uv_23, uv_45, uv_67 }
2718
2719 uxtah uv_0, texture_ptr, uv_01
2720 uxtah uv_1, texture_ptr, uv_01, ror #16
2721
2722 uxtah uv_2, texture_ptr, uv_23
2723 uxtah uv_3, texture_ptr, uv_23, ror #16
2724
2725 uxtah uv_4, texture_ptr, uv_45
2726 ldrb pixel_0, [ uv_0 ]
2727
2728 uxtah uv_5, texture_ptr, uv_45, ror #16
2729 ldrb pixel_1, [ uv_1 ]
2730
2731 uxtah uv_6, texture_ptr, uv_67
2732 ldrb pixel_2, [ uv_2 ]
2733
2734 uxtah uv_7, texture_ptr, uv_67, ror #16
2735 ldrb pixel_3, [ uv_3 ]
2736
2737 ldrb pixel_4, [ uv_4 ]
2738 add pixel_0, pixel_0, pixel_0
2739
2740 ldrb pixel_5, [ uv_5 ]
2741 add pixel_1, pixel_1, pixel_1
2742
2743 ldrb pixel_6, [ uv_6 ]
2744 add pixel_2, pixel_2, pixel_2
2745
2746 ldrb pixel_7, [ uv_7 ]
2747 add pixel_3, pixel_3, pixel_3
2748
2749 ldrh pixel_0, [ clut_ptr, pixel_0 ]
2750 add pixel_4, pixel_4, pixel_4
2751
2752 ldrh pixel_1, [ clut_ptr, pixel_1 ]
2753 add pixel_5, pixel_5, pixel_5
2754
2755 ldrh pixel_2, [ clut_ptr, pixel_2 ]
2756 add pixel_6, pixel_6, pixel_6
2757
2758 ldrh pixel_3, [ clut_ptr, pixel_3 ]
2759 add pixel_7, pixel_7, pixel_7
2760
2761 ldrh pixel_4, [ clut_ptr, pixel_4 ]
2762 orr pixels_a, pixel_0, pixel_1, lsl #16
2763
2764 ldrh pixel_5, [ clut_ptr, pixel_5 ]
2765 orr pixels_c, pixel_2, pixel_3, lsl #16
2766
2767 ldrh pixel_6, [ clut_ptr, pixel_6 ]
2768 subs num_blocks, num_blocks, #1
2769
2770 ldrh pixel_7, [ clut_ptr, pixel_7 ]
2771 orr pixels_b, pixel_4, pixel_5, lsl #16
2772
2773 orr pixels_d, pixel_6, pixel_7, lsl #16
2774 stm block_ptr, { pixels_a, pixels_c, pixels_b, pixels_d }
2775
2776 add block_ptr, block_ptr, #64
2777 bne 0b
2778
2779 ldmia sp!, { r3 - r11, pc }
2780
27811:
2782 stmdb sp!, { r1 - r2, r12 }
2783
2784 bl update_texture_8bpp_cache
2785
2786 ldmia sp!, { r1 - r2, r12 }
2787 bal 0b
2788
2789
2790#undef uv_0
2791#undef uv_1
2792#undef uv_2
2793#undef uv_3
2794#undef uv_4
2795#undef uv_5
2796#undef uv_6
2797#undef uv_7
2798
2799#undef pixel_0
2800#undef pixel_1
2801#undef pixel_2
2802#undef pixel_3
2803#undef pixel_4
2804#undef pixel_5
2805#undef pixel_6
2806#undef pixel_7
2807
2808#undef texture_ptr
2809
2810#undef pixels_a
2811#undef pixels_b
2812#undef pixels_c
2813#undef pixels_d
2814
2815#define psx_gpu r0
2816#define block_ptr r1
2817#define num_blocks r2
2818
2819#define uv_0 r3
2820#define uv_1 r4
2821#define u_0 r3
2822#define u_1 r4
2823#define v_0 r5
2824#define v_1 r6
2825
2826#define uv_2 r5
2827#define uv_3 r6
2828#define u_2 r5
2829#define u_3 r6
2830#define v_2 r7
2831#define v_3 r8
2832
2833#define uv_4 r7
2834#define uv_5 r8
2835#define u_4 r7
2836#define u_5 r8
2837#define v_4 r9
2838#define v_5 r10
2839
2840#define uv_6 r9
2841#define uv_7 r10
2842#define u_6 r9
2843#define u_7 r10
2844#define v_6 r11
2845#define v_7 r0
2846
2847#define pixel_0 r3
2848#define pixel_1 r4
2849#define pixel_2 r5
2850#define pixel_3 r6
2851#define pixel_4 r7
2852#define pixel_5 r8
2853#define pixel_6 r9
2854#define pixel_7 r10
2855
2856#define pixels_a r3
2857#define pixels_b r5
2858#define pixels_c r7
2859#define pixels_d r9
2860
2861#define texture_ptr r12
2862
2863
2864.align 3
2865
2866function(texture_blocks_16bpp)
2867 stmdb sp!, { r3 - r11, r14 }
2868 add block_ptr, psx_gpu, #psx_gpu_blocks_offset
2869
2870 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]
2871 ldr texture_ptr, [ psx_gpu, #psx_gpu_texture_page_ptr_offset ]
2872
28730:
2874 ldrh uv_0, [ block_ptr ]
2875 subs num_blocks, num_blocks, #1
2876
2877 ldrh uv_1, [ block_ptr, #2 ]
2878
2879 and v_0, uv_0, #0xFF00
2880 and v_1, uv_1, #0xFF00
2881
2882 and u_0, uv_0, #0xFF
2883 and u_1, uv_1, #0xFF
2884
2885 add uv_0, u_0, v_0, lsl #2
2886 ldrh uv_2, [ block_ptr, #4 ]
2887
2888 add uv_1, u_1, v_1, lsl #2
2889 ldrh uv_3, [ block_ptr, #6 ]
2890
2891 add uv_0, uv_0, uv_0
2892 add uv_1, uv_1, uv_1
2893
2894 and v_2, uv_2, #0xFF00
2895 and v_3, uv_3, #0xFF00
2896
2897 and u_2, uv_2, #0xFF
2898 and u_3, uv_3, #0xFF
2899
2900 add uv_2, u_2, v_2, lsl #2
2901 ldrh uv_4, [ block_ptr, #8 ]
2902
2903 add uv_3, u_3, v_3, lsl #2
2904 ldrh uv_5, [ block_ptr, #10 ]
2905
2906 add uv_2, uv_2, uv_2
2907 add uv_3, uv_3, uv_3
2908
2909 and v_4, uv_4, #0xFF00
2910 and v_5, uv_5, #0xFF00
2911
2912 and u_4, uv_4, #0xFF
2913 and u_5, uv_5, #0xFF
2914
2915 add uv_4, u_4, v_4, lsl #2
2916 ldrh uv_6, [ block_ptr, #12 ]
2917
2918 add uv_5, u_5, v_5, lsl #2
2919 ldrh uv_7, [ block_ptr, #14 ]
2920
2921 add uv_4, uv_4, uv_4
2922 ldrh pixel_0, [ texture_ptr, uv_0 ]
2923
2924 add uv_5, uv_5, uv_5
2925 ldrh pixel_1, [ texture_ptr, uv_1 ]
2926
2927 and v_6, uv_6, #0xFF00
2928 ldrh pixel_2, [ texture_ptr, uv_2 ]
2929
2930 and v_7, uv_7, #0xFF00
2931 ldrh pixel_3, [ texture_ptr, uv_3 ]
2932
2933 and u_6, uv_6, #0xFF
2934 ldrh pixel_4, [ texture_ptr, uv_4 ]
2935
2936 and u_7, uv_7, #0xFF
2937 ldrh pixel_5, [ texture_ptr, uv_5 ]
2938
2939 add uv_6, u_6, v_6, lsl #2
2940 add uv_7, u_7, v_7, lsl #2
2941
2942 add uv_6, uv_6, uv_6
2943 add uv_7, uv_7, uv_7
2944
2945 orr pixels_a, pixel_0, pixel_1, lsl #16
2946 orr pixels_b, pixel_2, pixel_3, lsl #16
2947
2948 ldrh pixel_6, [ texture_ptr, uv_6 ]
2949 orr pixels_c, pixel_4, pixel_5, lsl #16
2950
2951 ldrh pixel_7, [ texture_ptr, uv_7 ]
2952 orr pixels_d, pixel_6, pixel_7, lsl #16
2953
2954 stm block_ptr, { pixels_a, pixels_b, pixels_c, pixels_d }
2955 add block_ptr, block_ptr, #64
2956
2957 bne 0b
2958
2959 ldmia sp!, { r3 - r11, pc }
2960
2961
2962#undef num_blocks
2963
2964#undef test_mask
2965#undef texels
2966#undef pixels_b
2967#undef pixels
2968#undef d64_1
2969#undef d64_4
2970#undef d64_128
2971#undef draw_mask
2972#undef msb_mask
2973#undef msb_mask_low
2974#undef msb_mask_high
2975#undef fb_pixels
2976
2977#undef c_32
2978#undef fb_ptr
2979#undef mask_msb_ptr
2980
2981#define psx_gpu r0
2982#define num_blocks r1
2983#define color_ptr r2
3867c6ef
E
2984#define colors_scalar r2
2985#define colors_scalar_compare r3
75e28f62
E
2986#define mask_msb_ptr r2
2987
2988#define block_ptr_load_a r0
2989#define block_ptr_store r3
2990#define block_ptr_load_b r12
2991#define c_32 r2
2992
2993#define c_48 r4
2994#define fb_ptr r14
2995#define draw_mask_bits_scalar r5
2996
2997#define d128_0x07 q0
2998#define d128_0x1F q1
2999#define d128_0x8000 q2
3000#define test_mask q3
3001#define texels q4
3002#define colors_rg q5
3003#define colors_b_dm_bits q6
3004#define texels_rg q7
3005#define pixels_r q8
3006#define pixels_g q9
3007#define pixels_b q10
3008#define pixels q11
3009#define zero_mask q4
3010#define draw_mask q12
3011#define msb_mask q13
3012
3013#define fb_pixels q8
3014
3015#define pixels_gb_low q9
3016
3017#define colors_r d10
3018#define colors_g d11
3019#define colors_b d12
3020#define draw_mask_bits d13
3021#define texels_r d14
3022#define texels_g d15
3023#define pixels_r_low d16
3024#define pixels_g_low d18
3025#define pixels_b_low d19
3026#define msb_mask_low d26
3027#define msb_mask_high d27
3028
3029#define d64_1 d28
3030#define d64_4 d29
3031#define d64_128 d30
3032#define texels_b d31
3033
3034#define shade_blocks_textured_modulated_prologue_indirect() \
3035 mov c_48, #48; \
3036 add block_ptr_store, psx_gpu, #psx_gpu_blocks_offset \
3037
3038#define shade_blocks_textured_modulated_prologue_direct() \
3039 add mask_msb_ptr, psx_gpu, #psx_gpu_mask_msb_offset; \
3040 vld1.u16 { msb_mask_low[], msb_mask_high[] }, [ mask_msb_ptr, :16 ] \
3041
75e28f62 3042
3867c6ef
E
3043#define shade_blocks_textured_modulated_prologue_shaded(dithering, target) \
3044
3045#define shade_blocks_textured_false_modulation_check_undithered(target) \
3046 ldr colors_scalar, [ psx_gpu, #psx_gpu_triangle_color_offset ]; \
3047 movw colors_scalar_compare, #0x8080; \
3048 \
3049 movt colors_scalar_compare, #0x80; \
3050 cmp colors_scalar, colors_scalar_compare; \
3051 beq shade_blocks_textured_unmodulated_##target \
3052
3053#define shade_blocks_textured_false_modulation_check_dithered(target) \
3054
3055#define shade_blocks_textured_modulated_prologue_unshaded(dithering, target) \
3056 shade_blocks_textured_false_modulation_check_##dithering(target); \
75e28f62
E
3057 add color_ptr, psx_gpu, #psx_gpu_triangle_color_offset; \
3058 vld1.u32 { colors_r[] }, [ color_ptr, :32 ]; \
3059 vdup.u8 colors_g, colors_r[1]; \
3060 vdup.u8 colors_b, colors_r[2]; \
3061 vdup.u8 colors_r, colors_r[0] \
3062
3063
3064#define shade_blocks_textured_modulated_load_dithered(target) \
3065 vld1.u32 { target }, [ block_ptr_load_b, :128 ] \
3066
3067#define shade_blocks_textured_modulated_load_last_dithered(target) \
3068 vld1.u32 { target }, [ block_ptr_load_b, :128 ], c_32 \
3069
3070#define shade_blocks_textured_modulated_load_undithered(target) \
3071
3072#define shade_blocks_textured_modulated_load_last_undithered(target) \
3073 add block_ptr_load_b, block_ptr_load_b, #32 \
3074
3075#define shade_blocks_textured_modulate_dithered(channel) \
3076 vmlal.u8 pixels_##channel, texels_##channel, colors_##channel \
3077
3078#define shade_blocks_textured_modulate_undithered(channel) \
3079 vmull.u8 pixels_##channel, texels_##channel, colors_##channel \
3080
3081
3082#define shade_blocks_textured_modulated_store_draw_mask_indirect(offset) \
3083 vst1.u32 { draw_mask }, [ block_ptr_store, :128 ]! \
3084
3085#define shade_blocks_textured_modulated_store_draw_mask_direct(offset) \
3086 ldr fb_ptr, [ block_ptr_load_b, #(offset - 64) ]; \
3087 vld1.u32 { fb_pixels }, [ fb_ptr ]; \
3088 vbit.u16 pixels, fb_pixels, draw_mask \
3089
3090#define shade_blocks_textured_modulated_store_pixels_indirect() \
3091 vst1.u32 { pixels }, [ block_ptr_store, :128 ], c_48 \
3092
3093#define shade_blocks_textured_modulated_store_pixels_direct() \
3094 vst1.u32 { pixels }, [ fb_ptr ] \
3095
3096
3097#define shade_blocks_textured_modulated_load_rg_shaded() \
3098 vld1.u32 { colors_r, colors_g }, [ block_ptr_load_b, :128 ], c_32 \
3099
3100#define shade_blocks_textured_modulated_load_rg_unshaded() \
3101 add block_ptr_load_b, block_ptr_load_b, #32 \
3102
3103#define shade_blocks_textured_modulated_load_bdm_shaded() \
3104 vld1.u32 { colors_b, draw_mask_bits }, [ block_ptr_load_a, :128 ], c_32 \
3105
3106#define shade_blocks_textured_modulated_load_bdm_unshaded() \
3107 ldr draw_mask_bits_scalar, [ block_ptr_load_a, #8 ]; \
3108 add block_ptr_load_a, block_ptr_load_a, #32 \
3109
3110#define shade_blocks_textured_modulated_expand_draw_mask_shaded() \
3111 vdup.u16 draw_mask, draw_mask_bits[0] \
3112
3113#define shade_blocks_textured_modulated_expand_draw_mask_unshaded() \
3114 vdup.u16 draw_mask, draw_mask_bits_scalar \
3115
3116
3117#define shade_blocks_textured_modulated_apply_msb_mask_indirect() \
3118
3119#define shade_blocks_textured_modulated_apply_msb_mask_direct() \
3120 vorr.u16 pixels, pixels, msb_mask \
3121
3122
3123#define shade_blocks_textured_modulated_builder(shading, dithering, target) \
3124.align 3; \
3125 \
3126function(shade_blocks_##shading##_textured_modulated_##dithering##_##target) \
3867c6ef 3127 shade_blocks_textured_modulated_prologue_##shading(dithering, target); \
75e28f62
E
3128 stmdb sp!, { r4 - r5, lr }; \
3129 ldrh num_blocks, [ psx_gpu, #psx_gpu_num_blocks_offset ]; \
3130 \
3131 vld1.u32 { test_mask }, [ psx_gpu, :128 ]; \
3132 \
3133 shade_blocks_textured_modulated_prologue_##target(); \
75e28f62
E
3134 \
3135 add block_ptr_load_a, psx_gpu, #psx_gpu_blocks_offset; \
3136 mov c_32, #32; \
3137 \
3138 add block_ptr_load_b, block_ptr_load_a, #16; \
3139 vmov.u8 d64_1, #1; \
3140 vmov.u8 d64_4, #4; \
3141 vmov.u8 d64_128, #128; \
3142 \
3143 vld1.u32 { texels }, [ block_ptr_load_a, :128 ], c_32; \
3144 vmov.u8 d128_0x07, #0x07; \
3145 \
3146 shade_blocks_textured_modulated_load_rg_##shading(); \
3147 vmov.u8 d128_0x1F, #0x1F; \
3148 \
3149 shade_blocks_textured_modulated_load_bdm_##shading(); \
3150 vmov.u16 d128_0x8000, #0x8000; \
3151 \
3152 vmovn.u16 texels_r, texels; \
3153 vshrn.u16 texels_g, texels, #5; \
3154 \
3155 vshrn.u16 texels_b, texels, #7; \
3156 shade_blocks_textured_modulated_expand_draw_mask_##shading(); \
3157 \
3158 shade_blocks_textured_modulated_load_##dithering(pixels_r); \
3159 vtst.u16 draw_mask, draw_mask, test_mask; \
3160 \
3161 shade_blocks_textured_modulated_load_##dithering(pixels_g); \
3162 vand.u8 texels_rg, texels_rg, d128_0x1F; \
3163 \
3164 shade_blocks_textured_modulated_load_last_##dithering(pixels_b); \
3165 vshr.u8 texels_b, texels_b, #3; \
3166 \
3167 shade_blocks_textured_modulate_##dithering(r); \
3168 shade_blocks_textured_modulate_##dithering(g); \
3169 shade_blocks_textured_modulate_##dithering(b); \
3170 \
3171 vand.u16 pixels, texels, d128_0x8000; \
3172 vceq.u16 zero_mask, texels, #0; \
3173 \
3174 vqshrun.s16 pixels_r_low, pixels_r, #4; \
3175 vqshrun.s16 pixels_g_low, pixels_g, #4; \
3176 vqshrun.s16 pixels_b_low, pixels_b, #4; \
3177 \
3178 shade_blocks_textured_modulated_apply_msb_mask_##target(); \
3179 vorr.u16 draw_mask, draw_mask, zero_mask; \
3180 vshr.u8 pixels_r_low, pixels_r_low, #3; \
3181 vbic.u8 pixels_gb_low, pixels_gb_low, d128_0x07; \
3182 \
3183 subs num_blocks, num_blocks, #1; \
3184 beq 1f; \
3185 \
3186 .align 3; \
3187 \
3188 0: \
3189 vld1.u32 { texels }, [ block_ptr_load_a, :128 ], c_32; \
3190 shade_blocks_textured_modulated_load_rg_##shading(); \
3191 vshrn.u16 texels_g, texels, #5; \
3192 \
3193 shade_blocks_textured_modulated_load_bdm_##shading(); \
3194 vshrn.u16 texels_b, texels, #7; \
3195 \
59d15d23 3196 pld [ block_ptr_load_a ]; \
75e28f62
E
3197 vmovn.u16 texels_r, texels; \
3198 vmlal.u8 pixels, pixels_r_low, d64_1; \
3199 \
3200 vmlal.u8 pixels, pixels_g_low, d64_4; \
3201 vmlal.u8 pixels, pixels_b_low, d64_128; \
3202 shade_blocks_textured_modulated_store_draw_mask_##target(-4); \