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spu: rework synchronization
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h
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CommitLineData
1#include "new_dynarec.h"
2#include "../r3000a.h"
3
4extern char invalid_code[0x100000];
5
6/* weird stuff */
7#define EAX 0
8#define ECX 1
9
10/* same as psxRegs */
11extern int reg[];
12
13/* same as psxRegs.GPR.n.* */
14extern int hi, lo;
15
16/* same as psxRegs.CP0.n.* */
17extern int reg_cop0[];
18#define Status psxRegs.CP0.n.Status
19#define Cause psxRegs.CP0.n.Cause
20#define EPC psxRegs.CP0.n.EPC
21#define BadVAddr psxRegs.CP0.n.BadVAddr
22#define Context psxRegs.CP0.n.Context
23#define EntryHi psxRegs.CP0.n.EntryHi
24#define Count psxRegs.cycle // psxRegs.CP0.n.Count
25
26/* COP2/GTE */
27enum gte_opcodes {
28 GTE_RTPS = 0x01,
29 GTE_NCLIP = 0x06,
30 GTE_OP = 0x0c,
31 GTE_DPCS = 0x10,
32 GTE_INTPL = 0x11,
33 GTE_MVMVA = 0x12,
34 GTE_NCDS = 0x13,
35 GTE_CDP = 0x14,
36 GTE_NCDT = 0x16,
37 GTE_NCCS = 0x1b,
38 GTE_CC = 0x1c,
39 GTE_NCS = 0x1e,
40 GTE_NCT = 0x20,
41 GTE_SQR = 0x28,
42 GTE_DCPL = 0x29,
43 GTE_DPCT = 0x2a,
44 GTE_AVSZ3 = 0x2d,
45 GTE_AVSZ4 = 0x2e,
46 GTE_RTPT = 0x30,
47 GTE_GPF = 0x3d,
48 GTE_GPL = 0x3e,
49 GTE_NCCT = 0x3f,
50};
51
52extern int reg_cop2d[], reg_cop2c[];
53extern void *gte_handlers[64];
54extern void *gte_handlers_nf[64];
55extern const char *gte_regnames[64];
56extern const char gte_cycletab[64];
57extern const uint64_t gte_reg_reads[64];
58extern const uint64_t gte_reg_writes[64];
59
60/* dummy */
61extern int FCR0, FCR31;
62
63/* mem */
64extern void *mem_rtab;
65extern void *mem_wtab;
66
67void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
68void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
69void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
70void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
71void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
72void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
73void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
74void jump_handle_swl(u32 addr, u32 data, u32 cycles);
75void jump_handle_swr(u32 addr, u32 data, u32 cycles);
76void rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
77void rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
78void rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
79void rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
80void rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
81void rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
82
83extern unsigned int address;
84extern void *psxH_ptr;
85extern void *zeromem_ptr;
86extern void *scratch_buf_ptr;
87
88// same as invalid_code, just a region for ram write checks (inclusive)
89extern u32 inv_code_start, inv_code_end;
90
91/* cycles/irqs */
92extern unsigned int next_interupt;
93extern int pending_exception;
94
95/* called by drc */
96void pcsx_mtc0(u32 reg, u32 val);
97void pcsx_mtc0_ds(u32 reg, u32 val);
98
99/* misc */
100extern void (*psxHLEt[])();
101
102extern void SysPrintf(const char *fmt, ...);
103
104#ifdef RAM_FIXED
105#define rdram ((u_int)0x80000000)
106#else
107#define rdram ((u_int)psxM)
108#endif
ARM optimized PCSX fork