[pcsx_rearmed.git] / libpcsxcore / new_dynarec / emu_if.h

#include "new_dynarec.h"
#include "../r3000a.h"

extern char invalid_code[0x100000];

/* weird stuff */
#define EAX 0
#define ECX 1

extern int dynarec_local[];

/* same as psxRegs.GPR.n.* */
extern int hi, lo;

/* same as psxRegs.CP0.n.* */
extern int reg_cop0[];
#define Status   psxRegs.CP0.n.Status
#define Cause    psxRegs.CP0.n.Cause
#define EPC      psxRegs.CP0.n.EPC
#define BadVAddr psxRegs.CP0.n.BadVAddr
#define Count    psxRegs.cycle // psxRegs.CP0.n.Count

/* COP2/GTE */
enum gte_opcodes {
	GTE_RTPS	= 0x01,
	GTE_NCLIP	= 0x06,
	GTE_OP		= 0x0c,
	GTE_DPCS	= 0x10,
	GTE_INTPL	= 0x11,
	GTE_MVMVA	= 0x12,
	GTE_NCDS	= 0x13,
	GTE_CDP		= 0x14,
	GTE_NCDT	= 0x16,
	GTE_NCCS	= 0x1b,
	GTE_CC		= 0x1c,
	GTE_NCS		= 0x1e,
	GTE_NCT		= 0x20,
	GTE_SQR		= 0x28,
	GTE_DCPL	= 0x29,
	GTE_DPCT	= 0x2a,
	GTE_AVSZ3	= 0x2d,
	GTE_AVSZ4	= 0x2e,
	GTE_RTPT	= 0x30,
	GTE_GPF		= 0x3d,
	GTE_GPL		= 0x3e,
	GTE_NCCT	= 0x3f,
};

extern int reg_cop2d[], reg_cop2c[];
extern void *gte_handlers[64];
extern void *gte_handlers_nf[64];
extern const char *gte_regnames[64];
extern const uint64_t gte_reg_reads[64];
extern const uint64_t gte_reg_writes[64];

/* mem */
extern void *mem_rtab;
extern void *mem_wtab;

void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
void jump_handle_swl(u32 addr, u32 data, u32 cycles);
void jump_handle_swr(u32 addr, u32 data, u32 cycles);
u32  rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
u32  rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
u32  rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
u32  rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
u32  rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
u32  rcnt2_read_count_m1(u32 addr, u32, u32 cycles);

extern unsigned int address;
extern unsigned int hack_addr;
extern void *psxH_ptr;
extern void *zeromem_ptr;
extern void *scratch_buf_ptr;

// same as invalid_code, just a region for ram write checks (inclusive)
// (psx/guest address range)
extern u32 inv_code_start, inv_code_end;

/* cycles/irqs */
extern u32 next_interupt;
extern int pending_exception;

/* called by drc */
void pcsx_mtc0(u32 reg, u32 val);
void pcsx_mtc0_ds(u32 reg, u32 val);

/* misc */
extern void SysPrintf(const char *fmt, ...);

#define rdram ((u_char *)psxM)
Commit	Line	Data
	1	#include "new_dynarec.h"
	2	#include "../r3000a.h"
	3
	4	extern char invalid_code[0x100000];
	5
	6	/* weird stuff */
	7	#define EAX 0
	8	#define ECX 1
	9
	10	extern int dynarec_local[];
	11
	12	/* same as psxRegs.GPR.n.* */
	13	extern int hi, lo;
	14
	15	/* same as psxRegs.CP0.n.* */
	16	extern int reg_cop0[];
	17	#define Status psxRegs.CP0.n.Status
	18	#define Cause psxRegs.CP0.n.Cause
	19	#define EPC psxRegs.CP0.n.EPC
	20	#define BadVAddr psxRegs.CP0.n.BadVAddr
	21	#define Count psxRegs.cycle // psxRegs.CP0.n.Count
	22
	23	/* COP2/GTE */
	24	enum gte_opcodes {
	25	GTE_RTPS = 0x01,
	26	GTE_NCLIP = 0x06,
	27	GTE_OP = 0x0c,
	28	GTE_DPCS = 0x10,
	29	GTE_INTPL = 0x11,
	30	GTE_MVMVA = 0x12,
	31	GTE_NCDS = 0x13,
	32	GTE_CDP = 0x14,
	33	GTE_NCDT = 0x16,
	34	GTE_NCCS = 0x1b,
	35	GTE_CC = 0x1c,
	36	GTE_NCS = 0x1e,
	37	GTE_NCT = 0x20,
	38	GTE_SQR = 0x28,
	39	GTE_DCPL = 0x29,
	40	GTE_DPCT = 0x2a,
	41	GTE_AVSZ3 = 0x2d,
	42	GTE_AVSZ4 = 0x2e,
	43	GTE_RTPT = 0x30,
	44	GTE_GPF = 0x3d,
	45	GTE_GPL = 0x3e,
	46	GTE_NCCT = 0x3f,
	47	};
	48
	49	extern int reg_cop2d[], reg_cop2c[];
	50	extern void *gte_handlers[64];
	51	extern void *gte_handlers_nf[64];
	52	extern const char *gte_regnames[64];
	53	extern const uint64_t gte_reg_reads[64];
	54	extern const uint64_t gte_reg_writes[64];
	55
	56	/* mem */
	57	extern void *mem_rtab;
	58	extern void *mem_wtab;
	59
	60	void jump_handler_read8(u32 addr, u32 *table, u32 cycles);
	61	void jump_handler_read16(u32 addr, u32 *table, u32 cycles);
	62	void jump_handler_read32(u32 addr, u32 *table, u32 cycles);
	63	void jump_handler_write8(u32 addr, u32 data, u32 cycles, u32 *table);
	64	void jump_handler_write16(u32 addr, u32 data, u32 cycles, u32 *table);
	65	void jump_handler_write32(u32 addr, u32 data, u32 cycles, u32 *table);
	66	void jump_handler_write_h(u32 addr, u32 data, u32 cycles, void *handler);
	67	void jump_handle_swl(u32 addr, u32 data, u32 cycles);
	68	void jump_handle_swr(u32 addr, u32 data, u32 cycles);
	69	u32 rcnt0_read_count_m0(u32 addr, u32, u32 cycles);
	70	u32 rcnt0_read_count_m1(u32 addr, u32, u32 cycles);
	71	u32 rcnt1_read_count_m0(u32 addr, u32, u32 cycles);
	72	u32 rcnt1_read_count_m1(u32 addr, u32, u32 cycles);
	73	u32 rcnt2_read_count_m0(u32 addr, u32, u32 cycles);
	74	u32 rcnt2_read_count_m1(u32 addr, u32, u32 cycles);
	75
	76	extern unsigned int address;
	77	extern unsigned int hack_addr;
	78	extern void *psxH_ptr;
	79	extern void *zeromem_ptr;
	80	extern void *scratch_buf_ptr;
	81
	82	// same as invalid_code, just a region for ram write checks (inclusive)
	83	// (psx/guest address range)
	84	extern u32 inv_code_start, inv_code_end;
	85
	86	/* cycles/irqs */
	87	extern u32 next_interupt;
	88	extern int pending_exception;
	89
	90	/* called by drc */
	91	void pcsx_mtc0(u32 reg, u32 val);
	92	void pcsx_mtc0_ds(u32 reg, u32 val);
	93
	94	/* misc */
	95	extern void SysPrintf(const char *fmt, ...);
	96
	97	#define rdram ((u_char *)psxM)