[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "linkage_offsets.h"


#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define add_jump_out		ESYM(add_jump_out)
#define new_recompile_block	ESYM(new_recompile_block)
#define ndrc_try_restore_block	ESYM(ndrc_try_restore_block)
#define get_addr		ESYM(get_addr)
#define get_addr_ht		ESYM(get_addr_ht)
#define gen_interupt		ESYM(gen_interupt)
#define invalidate_addr		ESYM(invalidate_addr)
#define gteCheckStallRaw	ESYM(gteCheckStallRaw)
#define psxException		ESYM(psxException)
#endif

	.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
@DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
@DRC_VAR(code, 4)
@DRC_VAR(cycle, 4)
@DRC_VAR(interrupt, 4)
@DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
DRC_VAR(ram_offset, 4)
DRC_VAR(mini_ht, 256)


#ifdef TEXRELS_FORBIDDEN
	.data
	.align 2
ptr_jump_in:
	.word	ESYM(jump_in)
ptr_hash_table:
	.word	ESYM(hash_table)
#endif


	.syntax unified
	.text
	.align	2

#ifndef HAVE_ARMV5
.macro blx rd
	mov	lr, pc
	bx	\rd
.endm
#endif

.macro load_varadr reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(\var-(1678f+8))
	movt	\reg, #:upper16:(\var-(1678f+8))
1678:
	add	\reg, pc
#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	movw	\reg, #:lower16:\var
	movt	\reg, #:upper16:\var
#else
	ldr	\reg, =\var
#endif
.endm

.macro load_varadr_ext reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
1678:
	ldr	\reg, [pc, \reg]
#else
	load_varadr \reg \var
#endif
.endm

.macro mov_16 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #\imm
#else
	mov	\reg, #(\imm & 0x00ff)
	orr	\reg, #(\imm & 0xff00)
#endif
.endm

.macro mov_24 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #(\imm & 0xffff)
	movt	\reg, #(\imm >> 16)
#else
	mov	\reg, #(\imm & 0x0000ff)
	orr	\reg, #(\imm & 0x00ff00)
	orr	\reg, #(\imm & 0xff0000)
#endif
.endm

/* r4 = virtual target address */
/* r5 = instruction to patch */
.macro dyna_linker_main
#ifndef NO_WRITE_EXEC
	load_varadr_ext r3, jump_in
	/* get_page */
	lsr     r2, r4, #12
	mov	r6, #4096
	bic	r2, r2, #0xe0000
	sub	r6, r6, #1
	cmp     r2, #0x1000
	ldr	r7, [r5]
	biclt   r2, #0x0e00
	and	r6, r6, r2
	cmp	r2, #2048
	add	r12, r7, #2
	orrcs	r2, r6, #2048
	ldr	r1, [r3, r2, lsl #2]
	lsl	r12, r12, #8
	add	r6, r5, r12, asr #6  /* old target */
	mov	r8, #0
	/* jump_in lookup */
1:
	movs	r0, r1
	beq	2f
	ldr	r3, [r1]	 /* ll_entry .vaddr */
	ldrd	r0, r1, [r0, #8] /* ll_entry .addr, .next */
	teq	r3, r4
	bne	1b
	teq	r0, r6
	moveq	pc, r0 /* Stale i-cache */
	mov	r8, r0
	b  	1b     /* jump_in may have dupes, continue search */
2:
	tst     r8, r8
	beq	3f     /* r4 not in jump_in */

	mov	r0, r4
	mov	r1, r6
	bl	add_jump_out
	sub	r2, r8, r5
	and	r1, r7, #0xff000000
	lsl	r2, r2, #6
	sub	r1, r1, #2
	add	r1, r1, r2, lsr #8
	str	r1, [r5]
	mov	pc, r8
3:
	mov	r0, r4
	bl	ndrc_try_restore_block
	tst	r0, r0
	movne	pc, r0
#else
	/* XXX: should be able to do better than this... */
	mov	r0, r4
	bl	get_addr_ht
	mov	pc, r0
#endif
.endm


FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	mov	r4, r0
	mov	r5, r1
10:
	dyna_linker_main

	mov	r0, r4
	bl	new_recompile_block
	tst	r0, r0
	beq	10b

	mov	r0, r4
	mov	r1, r0
	mov	r2, #(4<<2)  /* Address error (fetch) */

	/* r0 = instruction pointer */
	/* r1 = fault address */
	ldr	r3, [fp, #LO_reg_cop0+48] /* Status */
	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	r3, r3, #2
	str	r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
	str	r3, [fp, #LO_reg_cop0+48] /* Status */
	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
	mov	r0, #0x80000000
	orr	r0, r0, #0x80
	bl	get_addr_ht
	mov	pc, r0
	.size	dyna_linker, .-dyna_linker

	.align	2
FUNCTION(jump_vaddr_r0):
	eor	r2, r0, r0, lsl #16
	b	jump_vaddr
	.size	jump_vaddr_r0, .-jump_vaddr_r0
FUNCTION(jump_vaddr_r1):
	eor	r2, r1, r1, lsl #16
	mov	r0, r1
	b	jump_vaddr
	.size	jump_vaddr_r1, .-jump_vaddr_r1
FUNCTION(jump_vaddr_r2):
	mov	r0, r2
	eor	r2, r2, r2, lsl #16
	b	jump_vaddr
	.size	jump_vaddr_r2, .-jump_vaddr_r2
FUNCTION(jump_vaddr_r3):
	eor	r2, r3, r3, lsl #16
	mov	r0, r3
	b	jump_vaddr
	.size	jump_vaddr_r3, .-jump_vaddr_r3
FUNCTION(jump_vaddr_r4):
	eor	r2, r4, r4, lsl #16
	mov	r0, r4
	b	jump_vaddr
	.size	jump_vaddr_r4, .-jump_vaddr_r4
FUNCTION(jump_vaddr_r5):
	eor	r2, r5, r5, lsl #16
	mov	r0, r5
	b	jump_vaddr
	.size	jump_vaddr_r5, .-jump_vaddr_r5
FUNCTION(jump_vaddr_r6):
	eor	r2, r6, r6, lsl #16
	mov	r0, r6
	b	jump_vaddr
	.size	jump_vaddr_r6, .-jump_vaddr_r6
FUNCTION(jump_vaddr_r8):
	eor	r2, r8, r8, lsl #16
	mov	r0, r8
	b	jump_vaddr
	.size	jump_vaddr_r8, .-jump_vaddr_r8
FUNCTION(jump_vaddr_r9):
	eor	r2, r9, r9, lsl #16
	mov	r0, r9
	b	jump_vaddr
	.size	jump_vaddr_r9, .-jump_vaddr_r9
FUNCTION(jump_vaddr_r10):
	eor	r2, r10, r10, lsl #16
	mov	r0, r10
	b	jump_vaddr
	.size	jump_vaddr_r10, .-jump_vaddr_r10
FUNCTION(jump_vaddr_r12):
	eor	r2, r12, r12, lsl #16
	mov	r0, r12
	b	jump_vaddr
	.size	jump_vaddr_r12, .-jump_vaddr_r12
FUNCTION(jump_vaddr_r7):
	eor	r2, r7, r7, lsl #16
	add	r0, r7, #0
	.size	jump_vaddr_r7, .-jump_vaddr_r7
FUNCTION(jump_vaddr):
	load_varadr_ext r1, hash_table
	mvn	r3, #15
	and	r2, r3, r2, lsr #12
	ldr	r2, [r1, r2]!
	teq	r2, r0
	ldreq	pc, [r1, #8]
	ldr	r2, [r1, #4]
	teq	r2, r0
	ldreq	pc, [r1, #12]
	str	r10, [fp, #LO_cycle_count]
	bl	get_addr
	ldr	r10, [fp, #LO_cycle_count]
	mov	pc, r0
	.size	jump_vaddr, .-jump_vaddr

	.align	2

FUNCTION(verify_code):
	/* r1 = source */
	/* r2 = target */
	/* r3 = length */
	tst	r3, #4
	mov	r4, #0
	add	r3, r1, r3
	mov	r5, #0
	ldrne	r4, [r1], #4
	mov	r12, #0
	ldrne	r5, [r2], #4
	teq	r1, r3
	beq	.D3
.D2:
	ldr	r7, [r1], #4
	eor	r9, r4, r5
	ldr	r8, [r2], #4
	orrs	r9, r9, r12
	bne	.D4
	ldr	r4, [r1], #4
	eor	r12, r7, r8
	ldr	r5, [r2], #4
	cmp	r1, r3
	bcc	.D2
	teq	r7, r8
.D3:
	teqeq	r4, r5
.D4:
	ldr	r8, [fp, #LO_branch_target]
	moveq	pc, lr
.D5:
	bl	get_addr
	mov	pc, r0
	.size	verify_code, .-verify_code

	.align	2
FUNCTION(cc_interrupt):
	ldr	r0, [fp, #LO_last_count]
	mov	r1, #0
	add	r10, r0, r10
	str	r1, [fp, #LO_pending_exception]
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
@@	str	r10, [fp, #LO_reg_cop0+36]	/* Count - not on PSX */
	mov	r10, lr

	bl	gen_interupt
	mov	lr, r10
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r1, [fp, #LO_pending_exception]
	ldr	r2, [fp, #LO_stop]
	str	r0, [fp, #LO_last_count]
	sub	r10, r10, r0
	tst	r2, r2
	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	tst	r1, r1
	moveq	pc, lr
	ldr	r0, [fp, #LO_pcaddr]
	bl	get_addr_ht
	mov	pc, r0
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(fp_exception):
	mov	r2, #0x10000000
.E7:
	ldr	r1, [fp, #LO_reg_cop0+48] /* Status */
	mov	r3, #0x80000000
	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	r1, #2
	add	r2, r2, #0x2c
	str	r1, [fp, #LO_reg_cop0+48] /* Status */
	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
	add	r0, r3, #0x80
	bl	get_addr_ht
	mov	pc, r0
	.size	fp_exception, .-fp_exception
	.align	2
FUNCTION(fp_exception_ds):
	mov	r2, #0x90000000 /* Set high bit if delay slot */
	b	.E7
	.size	fp_exception_ds, .-fp_exception_ds

	.align	2
FUNCTION(jump_break_ds):
	mov	r0, #0x24
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	r0, #0x24
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	r0, #0x20
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_syscall):
	mov	r0, #0x20
	mov	r1, #0

call_psxException:
	ldr	r3, [fp, #LO_last_count]
	str	r2, [fp, #LO_pcaddr]
	add	r10, r3, r10
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	sub	r10, r10, r1
	str	r1, [fp, #LO_last_count]
	bl	get_addr_ht
	mov	pc, r0
	.size	jump_to_new_pc, .-jump_to_new_pc

	.align	2
FUNCTION(new_dyna_leave):
	ldr	r0, [fp, #LO_last_count]
	add	r12, fp, #28
	add	r10, r0, r10
	str	r10, [fp, #LO_cycle]
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	.size	new_dyna_leave, .-new_dyna_leave

	.align	2
FUNCTION(invalidate_addr_r0):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	b	invalidate_addr_call
	.size	invalidate_addr_r0, .-invalidate_addr_r0
	.align	2
FUNCTION(invalidate_addr_r1):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r1
	b	invalidate_addr_call
	.size	invalidate_addr_r1, .-invalidate_addr_r1
	.align	2
FUNCTION(invalidate_addr_r2):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r2
	b	invalidate_addr_call
	.size	invalidate_addr_r2, .-invalidate_addr_r2
	.align	2
FUNCTION(invalidate_addr_r3):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r3
	b	invalidate_addr_call
	.size	invalidate_addr_r3, .-invalidate_addr_r3
	.align	2
FUNCTION(invalidate_addr_r4):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r4
	b	invalidate_addr_call
	.size	invalidate_addr_r4, .-invalidate_addr_r4
	.align	2
FUNCTION(invalidate_addr_r5):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r5
	b	invalidate_addr_call
	.size	invalidate_addr_r5, .-invalidate_addr_r5
	.align	2
FUNCTION(invalidate_addr_r6):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r6
	b	invalidate_addr_call
	.size	invalidate_addr_r6, .-invalidate_addr_r6
	.align	2
FUNCTION(invalidate_addr_r7):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r7
	b	invalidate_addr_call
	.size	invalidate_addr_r7, .-invalidate_addr_r7
	.align	2
FUNCTION(invalidate_addr_r8):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r8
	b	invalidate_addr_call
	.size	invalidate_addr_r8, .-invalidate_addr_r8
	.align	2
FUNCTION(invalidate_addr_r9):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r9
	b	invalidate_addr_call
	.size	invalidate_addr_r9, .-invalidate_addr_r9
	.align	2
FUNCTION(invalidate_addr_r10):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r10
	b	invalidate_addr_call
	.size	invalidate_addr_r10, .-invalidate_addr_r10
	.align	2
FUNCTION(invalidate_addr_r12):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r12
	.size	invalidate_addr_r12, .-invalidate_addr_r12
	.align	2
invalidate_addr_call:
	ldr	r12, [fp, #LO_inv_code_start]
	ldr	lr, [fp, #LO_inv_code_end]
	cmp	r0, r12
	cmpcs   lr, r0
	blcc	invalidate_addr
	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	.size	invalidate_addr_call, .-invalidate_addr_call

	.align	2
FUNCTION(new_dyna_start):
	/* ip is stored to conform EABI alignment */
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	ldr	r0, [fp, #LO_pcaddr]
	bl	get_addr_ht
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	mov	pc, r0
	.size	new_dyna_start, .-new_dyna_start

/* --------------------------------------- */

.align	2

.macro pcsx_read_mem readop tab_shift
	/* r0 = address, r1 = handler_tab, r2 = cycles */
	lsl	r3, r0, #20
	lsr	r3, #(20+\tab_shift)
	ldr	r12, [fp, #LO_last_count]
	ldr	r1, [r1, r3, lsl #2]
	add	r2, r2, r12
	lsls	r1, #1
.if \tab_shift == 1
	lsl	r3, #1
	\readop	r0, [r1, r3]
.else
	\readop	r0, [r1, r3, lsl #\tab_shift]
.endif
	movcc	pc, lr
	str	r2, [fp, #LO_cycle]
	bx	r1
.endm

FUNCTION(jump_handler_read8):
	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_read_mem ldrbcc, 0

FUNCTION(jump_handler_read16):
	add     r1, #0x1000/4*4              @ shift to r16 part
	pcsx_read_mem ldrhcc, 1

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldrcc, 2


.macro memhandler_post
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
	str	r0, [fp, #LO_last_count]
	sub	r0, r2, r0
.endm

.macro pcsx_write_mem wrtop tab_shift
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	lsl	r12,r0, #20
	lsr	r12, #(20+\tab_shift)
	ldr	r3, [r3, r12, lsl #2]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	lsls	r3, #1
	mov     r0, r2                     @ cycle return in case of direct store
.if \tab_shift == 1
	lsl	r12, #1
	\wrtop	r1, [r3, r12]
.else
	\wrtop	r1, [r3, r12, lsl #\tab_shift]
.endif
	movcc	pc, lr
	ldr	r12, [fp, #LO_last_count]
	mov     r0, r1
	add	r2, r2, r12
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr
.endm

FUNCTION(jump_handler_write8):
	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_write_mem strbcc, 0

FUNCTION(jump_handler_write16):
	add     r3, #0x1000/4*4              @ shift to r16 part
	pcsx_write_mem strhcc, 1

FUNCTION(jump_handler_write32):
	pcsx_write_mem strcc, 2

FUNCTION(jump_handler_write_h):
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	ldr	r12, [fp, #LO_last_count]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	add	r2, r2, r12
	mov     r0, r1
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr

FUNCTION(jump_handle_swl):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	mov	r0, r2
	tst	r3, #2
	beq	101f
	tst	r3, #1
	beq	2f
3:
	str	r1, [r3, #-3]
	bx	lr
2:
	lsr	r2, r1, #8
	lsr	r1, #24
	strh	r2, [r3, #-2]
	strb	r1, [r3]
	bx	lr
101:
	tst	r3, #1
	lsrne	r1, #16		@ 1
	lsreq	r12, r1, #24	@ 0
	strhne	r1, [r3, #-1]
	strbeq	r12, [r3]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


FUNCTION(jump_handle_swr):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	and	r12,r3, #3
	mov	r0, r2
	cmp	r12,#2
	strbgt	r1, [r3]	@ 3
	strheq	r1, [r3]	@ 2
	cmp	r12,#1
	strlt	r1, [r3]	@ 0
	bxne	lr
	lsr	r2, r1, #8	@ 1
	strb	r1, [r3]
	strh	r2, [r3, #1]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


.macro rcntx_read_mode0 num
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
	mov	r0, r2, lsl #16
	sub	r0, r0, r3, lsl #16
	lsr	r0, #16
	bx	lr
.endm

FUNCTION(rcnt0_read_count_m0):
	rcntx_read_mode0 0

FUNCTION(rcnt1_read_count_m0):
	rcntx_read_mode0 1

FUNCTION(rcnt2_read_count_m0):
	rcntx_read_mode0 2

FUNCTION(rcnt0_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
	mov_16	r1, 0x3334
	sub	r2, r2, r3
	mul	r0, r1, r2		@ /= 5
	lsr	r0, #16
	bx	lr

FUNCTION(rcnt1_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
	mov_24	r1, 0x1e6cde
	sub	r2, r2, r3
	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
	bx	lr

FUNCTION(rcnt2_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
	mov	r0, r2, lsl #16-3
	sub	r0, r0, r3, lsl #16-3
	lsr	r0, #16			@ /= 8
	bx	lr

FUNCTION(call_gteStall):
	/* r0 = op_cycles, r1 = cycles */
	ldr	r2, [fp, #LO_last_count]
	str	lr, [fp, #LO_saved_lr]
	add	r1, r1, r2
	str	r1, [fp, #LO_cycle]
	add	r1, fp, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [fp, #LO_saved_lr]
	add	r10, r10, r0
	bx	lr

#ifdef HAVE_ARMV6

FUNCTION(get_reg):
	ldr	r12, [r0]
	and	r1, r1, #0xff
	ldr	r2, [r0, #4]
	orr	r1, r1, r1, lsl #8
	ldr	r3, [r0, #8]
	orr	r1, r1, r1, lsl #16   @ searched char in every byte
	ldrb    r0, [r0, #12]         @ last byte
	eor	r12, r12, r1
	eor	r2, r2, r1
	eor	r3, r3, r1
	cmp     r0, r1, lsr #24
	mov	r0, #12
	mvn	r1, #0                @ r1=~0
	bxeq	lr
	orr	r3, r3, #0xff000000   @ EXCLUDE_REG
	uadd8	r0, r12, r1           @ add and set GE bits when not 0 (match)
	mov	r12, #0
	sel	r0, r12, r1           @ 0 if no match, else ff in some byte
	uadd8	r2, r2, r1
	sel	r2, r12, r1
	uadd8	r3, r3, r1
	sel	r3, r12, r1
	mov	r12, #3
	clz     r0, r0                @ 0, 8, 16, 24 or 32
	clz     r2, r2
	clz     r3, r3
	sub	r0, r12, r0, lsr #3   @ 3, 2, 1, 0 or -1
	sub	r2, r12, r2, lsr #3
	sub	r3, r12, r3, lsr #3
	orr	r2, r2, #4
	orr	r3, r3, #8
	and	r0, r0, r2
	and	r0, r0, r3
	bx	lr

#endif /* HAVE_ARMV6 */

@ vim:filetype=armasm
Commit	Line	Data
	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "linkage_offsets.h"
	25
	26
	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
	29	#define add_jump_out ESYM(add_jump_out)
	30	#define new_recompile_block ESYM(new_recompile_block)
	31	#define ndrc_try_restore_block ESYM(ndrc_try_restore_block)
	32	#define get_addr ESYM(get_addr)
	33	#define get_addr_ht ESYM(get_addr_ht)
	34	#define gen_interupt ESYM(gen_interupt)
	35	#define invalidate_addr ESYM(invalidate_addr)
	36	#define gteCheckStallRaw ESYM(gteCheckStallRaw)
	37	#define psxException ESYM(psxException)
	38	#endif
	39
	40	.bss
	41	.align 4
	42	.global dynarec_local
	43	.type dynarec_local, %object
	44	.size dynarec_local, LO_dynarec_local_size
	45	dynarec_local:
	46	.space LO_dynarec_local_size
	47
	48	#define DRC_VAR_(name, vname, size_) \
	49	vname = dynarec_local + LO_##name; \
	50	.global vname; \
	51	.type vname, %object; \
	52	.size vname, size_
	53
	54	#define DRC_VAR(name, size_) \
	55	DRC_VAR_(name, ESYM(name), size_)
	56
	57	DRC_VAR(next_interupt, 4)
	58	DRC_VAR(cycle_count, 4)
	59	DRC_VAR(last_count, 4)
	60	DRC_VAR(pending_exception, 4)
	61	DRC_VAR(stop, 4)
	62	DRC_VAR(branch_target, 4)
	63	DRC_VAR(address, 4)
	64	DRC_VAR(hack_addr, 4)
	65	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	66
	67	/* psxRegs */
	68	@DRC_VAR(reg, 128)
	69	DRC_VAR(lo, 4)
	70	DRC_VAR(hi, 4)
	71	DRC_VAR(reg_cop0, 128)
	72	DRC_VAR(reg_cop2d, 128)
	73	DRC_VAR(reg_cop2c, 128)
	74	DRC_VAR(pcaddr, 4)
	75	@DRC_VAR(code, 4)
	76	@DRC_VAR(cycle, 4)
	77	@DRC_VAR(interrupt, 4)
	78	@DRC_VAR(intCycle, 256)
	79
	80	DRC_VAR(rcnts, 744)
	81	DRC_VAR(inv_code_start, 4)
	82	DRC_VAR(inv_code_end, 4)
	83	DRC_VAR(mem_rtab, 4)
	84	DRC_VAR(mem_wtab, 4)
	85	DRC_VAR(psxH_ptr, 4)
	86	DRC_VAR(zeromem_ptr, 4)
	87	DRC_VAR(invc_ptr, 4)
	88	DRC_VAR(scratch_buf_ptr, 4)
	89	DRC_VAR(ram_offset, 4)
	90	DRC_VAR(mini_ht, 256)
	91
	92
	93	#ifdef TEXRELS_FORBIDDEN
	94	.data
	95	.align 2
	96	ptr_jump_in:
	97	.word ESYM(jump_in)
	98	ptr_hash_table:
	99	.word ESYM(hash_table)
	100	#endif
	101
	102
	103	.syntax unified
	104	.text
	105	.align 2
	106
	107	#ifndef HAVE_ARMV5
	108	.macro blx rd
	109	mov lr, pc
	110	bx \rd
	111	.endm
	112	#endif
	113
	114	.macro load_varadr reg var
	115	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	116	movw \reg, #:lower16:(\var-(1678f+8))
	117	movt \reg, #:upper16:(\var-(1678f+8))
	118	1678:
	119	add \reg, pc
	120	#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	121	movw \reg, #:lower16:\var
	122	movt \reg, #:upper16:\var
	123	#else
	124	ldr \reg, =\var
	125	#endif
	126	.endm
	127
	128	.macro load_varadr_ext reg var
	129	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	130	movw \reg, #:lower16:(ptr_\var-(1678f+8))
	131	movt \reg, #:upper16:(ptr_\var-(1678f+8))
	132	1678:
	133	ldr \reg, [pc, \reg]
	134	#else
	135	load_varadr \reg \var
	136	#endif
	137	.endm
	138
	139	.macro mov_16 reg imm
	140	#ifdef HAVE_ARMV7
	141	movw \reg, #\imm
	142	#else
	143	mov \reg, #(\imm & 0x00ff)
	144	orr \reg, #(\imm & 0xff00)
	145	#endif
	146	.endm
	147
	148	.macro mov_24 reg imm
	149	#ifdef HAVE_ARMV7
	150	movw \reg, #(\imm & 0xffff)
	151	movt \reg, #(\imm >> 16)
	152	#else
	153	mov \reg, #(\imm & 0x0000ff)
	154	orr \reg, #(\imm & 0x00ff00)
	155	orr \reg, #(\imm & 0xff0000)
	156	#endif
	157	.endm
	158
	159	/* r4 = virtual target address */
	160	/* r5 = instruction to patch */
	161	.macro dyna_linker_main
	162	#ifndef NO_WRITE_EXEC
	163	load_varadr_ext r3, jump_in
	164	/* get_page */
	165	lsr r2, r4, #12
	166	mov r6, #4096
	167	bic r2, r2, #0xe0000
	168	sub r6, r6, #1
	169	cmp r2, #0x1000
	170	ldr r7, [r5]
	171	biclt r2, #0x0e00
	172	and r6, r6, r2
	173	cmp r2, #2048
	174	add r12, r7, #2
	175	orrcs r2, r6, #2048
	176	ldr r1, [r3, r2, lsl #2]
	177	lsl r12, r12, #8
	178	add r6, r5, r12, asr #6 /* old target */
	179	mov r8, #0
	180	/* jump_in lookup */
	181	1:
	182	movs r0, r1
	183	beq 2f
	184	ldr r3, [r1] /* ll_entry .vaddr */
	185	ldrd r0, r1, [r0, #8] /* ll_entry .addr, .next */
	186	teq r3, r4
	187	bne 1b
	188	teq r0, r6
	189	moveq pc, r0 /* Stale i-cache */
	190	mov r8, r0
	191	b 1b /* jump_in may have dupes, continue search */
	192	2:
	193	tst r8, r8
	194	beq 3f /* r4 not in jump_in */
	195
	196	mov r0, r4
	197	mov r1, r6
	198	bl add_jump_out
	199	sub r2, r8, r5
	200	and r1, r7, #0xff000000
	201	lsl r2, r2, #6
	202	sub r1, r1, #2
	203	add r1, r1, r2, lsr #8
	204	str r1, [r5]
	205	mov pc, r8
	206	3:
	207	mov r0, r4
	208	bl ndrc_try_restore_block
	209	tst r0, r0
	210	movne pc, r0
	211	#else
	212	/* XXX: should be able to do better than this... */
	213	mov r0, r4
	214	bl get_addr_ht
	215	mov pc, r0
	216	#endif
	217	.endm
	218
	219
	220	FUNCTION(dyna_linker):
	221	/* r0 = virtual target address */
	222	/* r1 = instruction to patch */
	223	mov r4, r0
	224	mov r5, r1
	225	10:
	226	dyna_linker_main
	227
	228	mov r0, r4
	229	bl new_recompile_block
	230	tst r0, r0
	231	beq 10b
	232
	233	mov r0, r4
	234	mov r1, r0
	235	mov r2, #(4<<2) /* Address error (fetch) */
	236
	237	/* r0 = instruction pointer */
	238	/* r1 = fault address */
	239	ldr r3, [fp, #LO_reg_cop0+48] /* Status */
	240	str r0, [fp, #LO_reg_cop0+56] /* EPC */
	241	orr r3, r3, #2
	242	str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
	243	str r3, [fp, #LO_reg_cop0+48] /* Status */
	244	str r2, [fp, #LO_reg_cop0+52] /* Cause */
	245	mov r0, #0x80000000
	246	orr r0, r0, #0x80
	247	bl get_addr_ht
	248	mov pc, r0
	249	.size dyna_linker, .-dyna_linker
	250
	251	.align 2
	252	FUNCTION(jump_vaddr_r0):
	253	eor r2, r0, r0, lsl #16
	254	b jump_vaddr
	255	.size jump_vaddr_r0, .-jump_vaddr_r0
	256	FUNCTION(jump_vaddr_r1):
	257	eor r2, r1, r1, lsl #16
	258	mov r0, r1
	259	b jump_vaddr
	260	.size jump_vaddr_r1, .-jump_vaddr_r1
	261	FUNCTION(jump_vaddr_r2):
	262	mov r0, r2
	263	eor r2, r2, r2, lsl #16
	264	b jump_vaddr
	265	.size jump_vaddr_r2, .-jump_vaddr_r2
	266	FUNCTION(jump_vaddr_r3):
	267	eor r2, r3, r3, lsl #16
	268	mov r0, r3
	269	b jump_vaddr
	270	.size jump_vaddr_r3, .-jump_vaddr_r3
	271	FUNCTION(jump_vaddr_r4):
	272	eor r2, r4, r4, lsl #16
	273	mov r0, r4
	274	b jump_vaddr
	275	.size jump_vaddr_r4, .-jump_vaddr_r4
	276	FUNCTION(jump_vaddr_r5):
	277	eor r2, r5, r5, lsl #16
	278	mov r0, r5
	279	b jump_vaddr
	280	.size jump_vaddr_r5, .-jump_vaddr_r5
	281	FUNCTION(jump_vaddr_r6):
	282	eor r2, r6, r6, lsl #16
	283	mov r0, r6
	284	b jump_vaddr
	285	.size jump_vaddr_r6, .-jump_vaddr_r6
	286	FUNCTION(jump_vaddr_r8):
	287	eor r2, r8, r8, lsl #16
	288	mov r0, r8
	289	b jump_vaddr
	290	.size jump_vaddr_r8, .-jump_vaddr_r8
	291	FUNCTION(jump_vaddr_r9):
	292	eor r2, r9, r9, lsl #16
	293	mov r0, r9
	294	b jump_vaddr
	295	.size jump_vaddr_r9, .-jump_vaddr_r9
	296	FUNCTION(jump_vaddr_r10):
	297	eor r2, r10, r10, lsl #16
	298	mov r0, r10
	299	b jump_vaddr
	300	.size jump_vaddr_r10, .-jump_vaddr_r10
	301	FUNCTION(jump_vaddr_r12):
	302	eor r2, r12, r12, lsl #16
	303	mov r0, r12
	304	b jump_vaddr
	305	.size jump_vaddr_r12, .-jump_vaddr_r12
	306	FUNCTION(jump_vaddr_r7):
	307	eor r2, r7, r7, lsl #16
	308	add r0, r7, #0
	309	.size jump_vaddr_r7, .-jump_vaddr_r7
	310	FUNCTION(jump_vaddr):
	311	load_varadr_ext r1, hash_table
	312	mvn r3, #15
	313	and r2, r3, r2, lsr #12
	314	ldr r2, [r1, r2]!
	315	teq r2, r0
	316	ldreq pc, [r1, #8]
	317	ldr r2, [r1, #4]
	318	teq r2, r0
	319	ldreq pc, [r1, #12]
	320	str r10, [fp, #LO_cycle_count]
	321	bl get_addr
	322	ldr r10, [fp, #LO_cycle_count]
	323	mov pc, r0
	324	.size jump_vaddr, .-jump_vaddr
	325
	326	.align 2
	327
	328	FUNCTION(verify_code):
	329	/* r1 = source */
	330	/* r2 = target */
	331	/* r3 = length */
	332	tst r3, #4
	333	mov r4, #0
	334	add r3, r1, r3
	335	mov r5, #0
	336	ldrne r4, [r1], #4
	337	mov r12, #0
	338	ldrne r5, [r2], #4
	339	teq r1, r3
	340	beq .D3
	341	.D2:
	342	ldr r7, [r1], #4
	343	eor r9, r4, r5
	344	ldr r8, [r2], #4
	345	orrs r9, r9, r12
	346	bne .D4
	347	ldr r4, [r1], #4
	348	eor r12, r7, r8
	349	ldr r5, [r2], #4
	350	cmp r1, r3
	351	bcc .D2
	352	teq r7, r8
	353	.D3:
	354	teqeq r4, r5
	355	.D4:
	356	ldr r8, [fp, #LO_branch_target]
	357	moveq pc, lr
	358	.D5:
	359	bl get_addr
	360	mov pc, r0
	361	.size verify_code, .-verify_code
	362
	363	.align 2
	364	FUNCTION(cc_interrupt):
	365	ldr r0, [fp, #LO_last_count]
	366	mov r1, #0
	367	add r10, r0, r10
	368	str r1, [fp, #LO_pending_exception]
	369	str r10, [fp, #LO_cycle] /* PCSX cycles */
	370	@@ str r10, [fp, #LO_reg_cop0+36] /* Count - not on PSX */
	371	mov r10, lr
	372
	373	bl gen_interupt
	374	mov lr, r10
	375	ldr r10, [fp, #LO_cycle]
	376	ldr r0, [fp, #LO_next_interupt]
	377	ldr r1, [fp, #LO_pending_exception]
	378	ldr r2, [fp, #LO_stop]
	379	str r0, [fp, #LO_last_count]
	380	sub r10, r10, r0
	381	tst r2, r2
	382	ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	383	tst r1, r1
	384	moveq pc, lr
	385	ldr r0, [fp, #LO_pcaddr]
	386	bl get_addr_ht
	387	mov pc, r0
	388	.size cc_interrupt, .-cc_interrupt
	389
	390	.align 2
	391	FUNCTION(fp_exception):
	392	mov r2, #0x10000000
	393	.E7:
	394	ldr r1, [fp, #LO_reg_cop0+48] /* Status */
	395	mov r3, #0x80000000
	396	str r0, [fp, #LO_reg_cop0+56] /* EPC */
	397	orr r1, #2
	398	add r2, r2, #0x2c
	399	str r1, [fp, #LO_reg_cop0+48] /* Status */
	400	str r2, [fp, #LO_reg_cop0+52] /* Cause */
	401	add r0, r3, #0x80
	402	bl get_addr_ht
	403	mov pc, r0
	404	.size fp_exception, .-fp_exception
	405	.align 2
	406	FUNCTION(fp_exception_ds):
	407	mov r2, #0x90000000 /* Set high bit if delay slot */
	408	b .E7
	409	.size fp_exception_ds, .-fp_exception_ds
	410
	411	.align 2
	412	FUNCTION(jump_break_ds):
	413	mov r0, #0x24
	414	mov r1, #1
	415	b call_psxException
	416	FUNCTION(jump_break):
	417	mov r0, #0x24
	418	mov r1, #0
	419	b call_psxException
	420	FUNCTION(jump_syscall_ds):
	421	mov r0, #0x20
	422	mov r1, #1
	423	b call_psxException
	424	FUNCTION(jump_syscall):
	425	mov r0, #0x20
	426	mov r1, #0
	427
	428	call_psxException:
	429	ldr r3, [fp, #LO_last_count]
	430	str r2, [fp, #LO_pcaddr]
	431	add r10, r3, r10
	432	str r10, [fp, #LO_cycle] /* PCSX cycles */
	433	bl psxException
	434
	435	/* note: psxException might do recursive recompiler call from it's HLE code,
	436	* so be ready for this */
	437	FUNCTION(jump_to_new_pc):
	438	ldr r1, [fp, #LO_next_interupt]
	439	ldr r10, [fp, #LO_cycle]
	440	ldr r0, [fp, #LO_pcaddr]
	441	sub r10, r10, r1
	442	str r1, [fp, #LO_last_count]
	443	bl get_addr_ht
	444	mov pc, r0
	445	.size jump_to_new_pc, .-jump_to_new_pc
	446
	447	.align 2
	448	FUNCTION(new_dyna_leave):
	449	ldr r0, [fp, #LO_last_count]
	450	add r12, fp, #28
	451	add r10, r0, r10
	452	str r10, [fp, #LO_cycle]
	453	ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	454	.size new_dyna_leave, .-new_dyna_leave
	455
	456	.align 2
	457	FUNCTION(invalidate_addr_r0):
	458	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	459	b invalidate_addr_call
	460	.size invalidate_addr_r0, .-invalidate_addr_r0
	461	.align 2
	462	FUNCTION(invalidate_addr_r1):
	463	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	464	mov r0, r1
	465	b invalidate_addr_call
	466	.size invalidate_addr_r1, .-invalidate_addr_r1
	467	.align 2
	468	FUNCTION(invalidate_addr_r2):
	469	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	470	mov r0, r2
	471	b invalidate_addr_call
	472	.size invalidate_addr_r2, .-invalidate_addr_r2
	473	.align 2
	474	FUNCTION(invalidate_addr_r3):
	475	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	476	mov r0, r3
	477	b invalidate_addr_call
	478	.size invalidate_addr_r3, .-invalidate_addr_r3
	479	.align 2
	480	FUNCTION(invalidate_addr_r4):
	481	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	482	mov r0, r4
	483	b invalidate_addr_call
	484	.size invalidate_addr_r4, .-invalidate_addr_r4
	485	.align 2
	486	FUNCTION(invalidate_addr_r5):
	487	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	488	mov r0, r5
	489	b invalidate_addr_call
	490	.size invalidate_addr_r5, .-invalidate_addr_r5
	491	.align 2
	492	FUNCTION(invalidate_addr_r6):
	493	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	494	mov r0, r6
	495	b invalidate_addr_call
	496	.size invalidate_addr_r6, .-invalidate_addr_r6
	497	.align 2
	498	FUNCTION(invalidate_addr_r7):
	499	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	500	mov r0, r7
	501	b invalidate_addr_call
	502	.size invalidate_addr_r7, .-invalidate_addr_r7
	503	.align 2
	504	FUNCTION(invalidate_addr_r8):
	505	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	506	mov r0, r8
	507	b invalidate_addr_call
	508	.size invalidate_addr_r8, .-invalidate_addr_r8
	509	.align 2
	510	FUNCTION(invalidate_addr_r9):
	511	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	512	mov r0, r9
	513	b invalidate_addr_call
	514	.size invalidate_addr_r9, .-invalidate_addr_r9
	515	.align 2
	516	FUNCTION(invalidate_addr_r10):
	517	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	518	mov r0, r10
	519	b invalidate_addr_call
	520	.size invalidate_addr_r10, .-invalidate_addr_r10
	521	.align 2
	522	FUNCTION(invalidate_addr_r12):
	523	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	524	mov r0, r12
	525	.size invalidate_addr_r12, .-invalidate_addr_r12
	526	.align 2
	527	invalidate_addr_call:
	528	ldr r12, [fp, #LO_inv_code_start]
	529	ldr lr, [fp, #LO_inv_code_end]
	530	cmp r0, r12
	531	cmpcs lr, r0
	532	blcc invalidate_addr
	533	ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	534	.size invalidate_addr_call, .-invalidate_addr_call
	535
	536	.align 2
	537	FUNCTION(new_dyna_start):
	538	/* ip is stored to conform EABI alignment */
	539	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	540	mov fp, r0 /* dynarec_local */
	541	ldr r0, [fp, #LO_pcaddr]
	542	bl get_addr_ht
	543	ldr r1, [fp, #LO_next_interupt]
	544	ldr r10, [fp, #LO_cycle]
	545	str r1, [fp, #LO_last_count]
	546	sub r10, r10, r1
	547	mov pc, r0
	548	.size new_dyna_start, .-new_dyna_start
	549
	550	/* --------------------------------------- */
	551
	552	.align 2
	553
	554	.macro pcsx_read_mem readop tab_shift
	555	/* r0 = address, r1 = handler_tab, r2 = cycles */
	556	lsl r3, r0, #20
	557	lsr r3, #(20+\tab_shift)
	558	ldr r12, [fp, #LO_last_count]
	559	ldr r1, [r1, r3, lsl #2]
	560	add r2, r2, r12
	561	lsls r1, #1
	562	.if \tab_shift == 1
	563	lsl r3, #1
	564	\readop r0, [r1, r3]
	565	.else
	566	\readop r0, [r1, r3, lsl #\tab_shift]
	567	.endif
	568	movcc pc, lr
	569	str r2, [fp, #LO_cycle]
	570	bx r1
	571	.endm
	572
	573	FUNCTION(jump_handler_read8):
	574	add r1, #0x1000/44 + 0x1000/24 @ shift to r8 part
	575	pcsx_read_mem ldrbcc, 0
	576
	577	FUNCTION(jump_handler_read16):
	578	add r1, #0x1000/4*4 @ shift to r16 part
	579	pcsx_read_mem ldrhcc, 1
	580
	581	FUNCTION(jump_handler_read32):
	582	pcsx_read_mem ldrcc, 2
	583
	584
	585	.macro memhandler_post
	586	ldr r0, [fp, #LO_next_interupt]
	587	ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
	588	str r0, [fp, #LO_last_count]
	589	sub r0, r2, r0
	590	.endm
	591
	592	.macro pcsx_write_mem wrtop tab_shift
	593	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	594	lsl r12,r0, #20
	595	lsr r12, #(20+\tab_shift)
	596	ldr r3, [r3, r12, lsl #2]
	597	str r0, [fp, #LO_address] @ some handlers still need it..
	598	lsls r3, #1
	599	mov r0, r2 @ cycle return in case of direct store
	600	.if \tab_shift == 1
	601	lsl r12, #1
	602	\wrtop r1, [r3, r12]
	603	.else
	604	\wrtop r1, [r3, r12, lsl #\tab_shift]
	605	.endif
	606	movcc pc, lr
	607	ldr r12, [fp, #LO_last_count]
	608	mov r0, r1
	609	add r2, r2, r12
	610	str r2, [fp, #LO_cycle]
	611
	612	str lr, [fp, #LO_saved_lr]
	613	blx r3
	614	ldr lr, [fp, #LO_saved_lr]
	615
	616	memhandler_post
	617	bx lr
	618	.endm
	619
	620	FUNCTION(jump_handler_write8):
	621	add r3, #0x1000/44 + 0x1000/24 @ shift to r8 part
	622	pcsx_write_mem strbcc, 0
	623
	624	FUNCTION(jump_handler_write16):
	625	add r3, #0x1000/4*4 @ shift to r16 part
	626	pcsx_write_mem strhcc, 1
	627
	628	FUNCTION(jump_handler_write32):
	629	pcsx_write_mem strcc, 2
	630
	631	FUNCTION(jump_handler_write_h):
	632	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	633	ldr r12, [fp, #LO_last_count]
	634	str r0, [fp, #LO_address] @ some handlers still need it..
	635	add r2, r2, r12
	636	mov r0, r1
	637	str r2, [fp, #LO_cycle]
	638
	639	str lr, [fp, #LO_saved_lr]
	640	blx r3
	641	ldr lr, [fp, #LO_saved_lr]
	642
	643	memhandler_post
	644	bx lr
	645
	646	FUNCTION(jump_handle_swl):
	647	/* r0 = address, r1 = data, r2 = cycles */
	648	ldr r3, [fp, #LO_mem_wtab]
	649	mov r12,r0,lsr #12
	650	ldr r3, [r3, r12, lsl #2]
	651	lsls r3, #1
	652	bcs 4f
	653	add r3, r0, r3
	654	mov r0, r2
	655	tst r3, #2
	656	beq 101f
	657	tst r3, #1
	658	beq 2f
	659	3:
	660	str r1, [r3, #-3]
	661	bx lr
	662	2:
	663	lsr r2, r1, #8
	664	lsr r1, #24
	665	strh r2, [r3, #-2]
	666	strb r1, [r3]
	667	bx lr
	668	101:
	669	tst r3, #1
	670	lsrne r1, #16 @ 1
	671	lsreq r12, r1, #24 @ 0
	672	strhne r1, [r3, #-1]
	673	strbeq r12, [r3]
	674	bx lr
	675	4:
	676	mov r0, r2
	677	@ b abort
	678	bx lr @ TODO?
	679
	680
	681	FUNCTION(jump_handle_swr):
	682	/* r0 = address, r1 = data, r2 = cycles */
	683	ldr r3, [fp, #LO_mem_wtab]
	684	mov r12,r0,lsr #12
	685	ldr r3, [r3, r12, lsl #2]
	686	lsls r3, #1
	687	bcs 4f
	688	add r3, r0, r3
	689	and r12,r3, #3
	690	mov r0, r2
	691	cmp r12,#2
	692	strbgt r1, [r3] @ 3
	693	strheq r1, [r3] @ 2
	694	cmp r12,#1
	695	strlt r1, [r3] @ 0
	696	bxne lr
	697	lsr r2, r1, #8 @ 1
	698	strb r1, [r3]
	699	strh r2, [r3, #1]
	700	bx lr
	701	4:
	702	mov r0, r2
	703	@ b abort
	704	bx lr @ TODO?
	705
	706
	707	.macro rcntx_read_mode0 num
	708	/* r0 = address, r2 = cycles */
	709	ldr r3, [fp, #LO_rcnts+64+74*\num] @ cycleStart
	710	mov r0, r2, lsl #16
	711	sub r0, r0, r3, lsl #16
	712	lsr r0, #16
	713	bx lr
	714	.endm
	715
	716	FUNCTION(rcnt0_read_count_m0):
	717	rcntx_read_mode0 0
	718
	719	FUNCTION(rcnt1_read_count_m0):
	720	rcntx_read_mode0 1
	721
	722	FUNCTION(rcnt2_read_count_m0):
	723	rcntx_read_mode0 2
	724
	725	FUNCTION(rcnt0_read_count_m1):
	726	/* r0 = address, r2 = cycles */
	727	ldr r3, [fp, #LO_rcnts+64+74*0] @ cycleStart
	728	mov_16 r1, 0x3334
	729	sub r2, r2, r3
	730	mul r0, r1, r2 @ /= 5
	731	lsr r0, #16
	732	bx lr
	733
	734	FUNCTION(rcnt1_read_count_m1):
	735	/* r0 = address, r2 = cycles */
	736	ldr r3, [fp, #LO_rcnts+64+74*1]
	737	mov_24 r1, 0x1e6cde
	738	sub r2, r2, r3
	739	umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
	740	bx lr
	741
	742	FUNCTION(rcnt2_read_count_m1):
	743	/* r0 = address, r2 = cycles */
	744	ldr r3, [fp, #LO_rcnts+64+74*2]
	745	mov r0, r2, lsl #16-3
	746	sub r0, r0, r3, lsl #16-3
	747	lsr r0, #16 @ /= 8
	748	bx lr
	749
	750	FUNCTION(call_gteStall):
	751	/* r0 = op_cycles, r1 = cycles */
	752	ldr r2, [fp, #LO_last_count]
	753	str lr, [fp, #LO_saved_lr]
	754	add r1, r1, r2
	755	str r1, [fp, #LO_cycle]
	756	add r1, fp, #LO_psxRegs
	757	bl gteCheckStallRaw
	758	ldr lr, [fp, #LO_saved_lr]
	759	add r10, r10, r0
	760	bx lr
	761
	762	#ifdef HAVE_ARMV6
	763
	764	FUNCTION(get_reg):
	765	ldr r12, [r0]
	766	and r1, r1, #0xff
	767	ldr r2, [r0, #4]
	768	orr r1, r1, r1, lsl #8
	769	ldr r3, [r0, #8]
	770	orr r1, r1, r1, lsl #16 @ searched char in every byte
	771	ldrb r0, [r0, #12] @ last byte
	772	eor r12, r12, r1
	773	eor r2, r2, r1
	774	eor r3, r3, r1
	775	cmp r0, r1, lsr #24
	776	mov r0, #12
	777	mvn r1, #0 @ r1=~0
	778	bxeq lr
	779	orr r3, r3, #0xff000000 @ EXCLUDE_REG
	780	uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
	781	mov r12, #0
	782	sel r0, r12, r1 @ 0 if no match, else ff in some byte
	783	uadd8 r2, r2, r1
	784	sel r2, r12, r1
	785	uadd8 r3, r3, r1
	786	sel r3, r12, r1
	787	mov r12, #3
	788	clz r0, r0 @ 0, 8, 16, 24 or 32
	789	clz r2, r2
	790	clz r3, r3
	791	sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
	792	sub r2, r12, r2, lsr #3
	793	sub r3, r12, r3, lsr #3
	794	orr r2, r2, #4
	795	orr r3, r3, #8
	796	and r0, r0, r2
	797	and r0, r0, r3
	798	bx lr
	799
	800	#endif /* HAVE_ARMV6 */
	801
	802	@ vim:filetype=armasm