[pcsx_rearmed.git] / libpcsxcore / new_dynarec / linkage_arm.S

/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
 *   linkage_arm.s for PCSX                                                *
 *   Copyright (C) 2009-2011 Ari64                                         *
 *   Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas                     *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */

#include "arm_features.h"
#include "new_dynarec_config.h"
#include "linkage_offsets.h"


#ifdef __MACH__
#define dynarec_local		ESYM(dynarec_local)
#define add_jump_out		ESYM(add_jump_out)
#define new_recompile_block	ESYM(new_recompile_block)
#define get_addr		ESYM(get_addr)
#define get_addr_ht		ESYM(get_addr_ht)
#define clean_blocks		ESYM(clean_blocks)
#define gen_interupt		ESYM(gen_interupt)
#define invalidate_addr		ESYM(invalidate_addr)
#define gteCheckStallRaw	ESYM(gteCheckStallRaw)
#define psxException		ESYM(psxException)
#endif

	.bss
	.align	4
	.global dynarec_local
	.type	dynarec_local, %object
	.size	dynarec_local, LO_dynarec_local_size
dynarec_local:
	.space	LO_dynarec_local_size

#define DRC_VAR_(name, vname, size_) \
	vname = dynarec_local + LO_##name; \
	.global vname; \
	.type	vname, %object; \
	.size	vname, size_

#define DRC_VAR(name, size_) \
	DRC_VAR_(name, ESYM(name), size_)

DRC_VAR(next_interupt, 4)
DRC_VAR(cycle_count, 4)
DRC_VAR(last_count, 4)
DRC_VAR(pending_exception, 4)
DRC_VAR(stop, 4)
DRC_VAR(branch_target, 4)
DRC_VAR(address, 4)
DRC_VAR(hack_addr, 4)
DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)

/* psxRegs */
@DRC_VAR(reg, 128)
DRC_VAR(lo, 4)
DRC_VAR(hi, 4)
DRC_VAR(reg_cop0, 128)
DRC_VAR(reg_cop2d, 128)
DRC_VAR(reg_cop2c, 128)
DRC_VAR(pcaddr, 4)
@DRC_VAR(code, 4)
@DRC_VAR(cycle, 4)
@DRC_VAR(interrupt, 4)
@DRC_VAR(intCycle, 256)

DRC_VAR(rcnts, 7*4*4)
DRC_VAR(inv_code_start, 4)
DRC_VAR(inv_code_end, 4)
DRC_VAR(mem_rtab, 4)
DRC_VAR(mem_wtab, 4)
DRC_VAR(psxH_ptr, 4)
DRC_VAR(zeromem_ptr, 4)
DRC_VAR(invc_ptr, 4)
DRC_VAR(scratch_buf_ptr, 4)
DRC_VAR(ram_offset, 4)
DRC_VAR(mini_ht, 256)
DRC_VAR(restore_candidate, 512)


#ifdef TEXRELS_FORBIDDEN
	.data
	.align 2
ptr_jump_in:
	.word	ESYM(jump_in)
ptr_jump_dirty:
	.word	ESYM(jump_dirty)
ptr_hash_table:
	.word	ESYM(hash_table)
#endif


	.syntax unified
	.text
	.align	2

#ifndef HAVE_ARMV5
.macro blx rd
	mov	lr, pc
	bx	\rd
.endm
#endif

.macro load_varadr reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(\var-(1678f+8))
	movt	\reg, #:upper16:(\var-(1678f+8))
1678:
	add	\reg, pc
#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	movw	\reg, #:lower16:\var
	movt	\reg, #:upper16:\var
#else
	ldr	\reg, =\var
#endif
.endm

.macro load_varadr_ext reg var
#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	movw	\reg, #:lower16:(ptr_\var-(1678f+8))
	movt	\reg, #:upper16:(ptr_\var-(1678f+8))
1678:
	ldr	\reg, [pc, \reg]
#else
	load_varadr \reg \var
#endif
.endm

.macro mov_16 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #\imm
#else
	mov	\reg, #(\imm & 0x00ff)
	orr	\reg, #(\imm & 0xff00)
#endif
.endm

.macro mov_24 reg imm
#ifdef HAVE_ARMV7
	movw	\reg, #(\imm & 0xffff)
	movt	\reg, #(\imm >> 16)
#else
	mov	\reg, #(\imm & 0x0000ff)
	orr	\reg, #(\imm & 0x00ff00)
	orr	\reg, #(\imm & 0xff0000)
#endif
.endm

/* r0 = virtual target address */
/* r1 = instruction to patch */
.macro dyna_linker_main
#ifndef NO_WRITE_EXEC
	load_varadr_ext r3, jump_in
	/* get_page */
	lsr     r2, r0, #12
	mov	r6, #4096
	bic	r2, r2, #0xe0000
	sub	r6, r6, #1
	cmp     r2, #0x1000
	ldr	r7, [r1]
	biclt   r2, #0x0e00
	and	r6, r6, r2
	cmp	r2, #2048
	add	r12, r7, #2
	orrcs	r2, r6, #2048
	ldr	r5, [r3, r2, lsl #2]
	lsl	r12, r12, #8
	add	r6, r1, r12, asr #6  /* old target */
	mov	r8, #0
	/* jump_in lookup */
1:
	movs	r4, r5
	beq	2f
	ldr	r3, [r5]	 /* ll_entry .vaddr */
	ldrd	r4, r5, [r4, #8] /* ll_entry .next, .addr */
	teq	r3, r0
	bne	1b
	teq	r4, r6
	moveq	pc, r4 /* Stale i-cache */
	mov	r8, r4
	b  	1b     /* jump_in may have dupes, continue search */
2:
	tst     r8, r8
	beq	3f     /* r0 not in jump_in */

	mov	r5, r1
	mov	r1, r6
	bl	add_jump_out
	sub	r2, r8, r5
	and	r1, r7, #0xff000000
	lsl	r2, r2, #6
	sub	r1, r1, #2
	add	r1, r1, r2, lsr #8
	str	r1, [r5]
	mov	pc, r8
3:
	/* hash_table lookup */
	cmp	r2, #2048
	load_varadr_ext r3, jump_dirty
	eor	r4, r0, r0, lsl #16
	lslcc	r2, r0, #9
	load_varadr_ext r6, hash_table
	lsr	r4, r4, #12
	lsrcc	r2, r2, #21
	bic	r4, r4, #15
	ldr	r5, [r3, r2, lsl #2]
	ldr	r7, [r6, r4]!
	teq	r7, r0
	ldreq	pc, [r6, #8]
	ldr	r7, [r6, #4]
	teq	r7, r0
	ldreq	pc, [r6, #12]
	/* jump_dirty lookup */
6:
	movs	r4, r5
	beq	8f
	ldr	r3, [r5]
	ldr	r5, [r4, #12]
	teq	r3, r0
	bne	6b
7:
	ldr	r1, [r4, #8]
	/* hash_table insert */
	ldr	r2, [r6]
	ldr	r3, [r6, #8]
	str	r0, [r6]
	str	r1, [r6, #8]
	str	r2, [r6, #4]
	str	r3, [r6, #12]
	mov	pc, r1
8:
#else
	/* XXX: should be able to do better than this... */
	bl	get_addr_ht
	mov	pc, r0
#endif
.endm


FUNCTION(dyna_linker):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main

	mov	r4, r0
	mov	r5, r1
	bl	new_recompile_block
	tst	r0, r0
	mov	r0, r4
	mov	r1, r5
	beq	dyna_linker
	/* pagefault */
	mov	r1, r0
	mov	r2, #8
	.size	dyna_linker, .-dyna_linker

FUNCTION(exec_pagefault):
	/* r0 = instruction pointer */
	/* r1 = fault address */
	/* r2 = cause */
	ldr	r3, [fp, #LO_reg_cop0+48] /* Status */
	mvn	r6, #0xF000000F
	ldr	r4, [fp, #LO_reg_cop0+16] /* Context */
	bic	r6, r6, #0x0F800000
	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	r3, r3, #2
	str	r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
	bic	r4, r4, r6
	str	r3, [fp, #LO_reg_cop0+48] /* Status */
	and	r5, r6, r1, lsr #9
	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
	and	r1, r1, r6, lsl #9
	str	r1, [fp, #LO_reg_cop0+40] /* EntryHi */
	orr	r4, r4, r5
	str	r4, [fp, #LO_reg_cop0+16] /* Context */
	mov	r0, #0x80000000
	bl	get_addr_ht
	mov	pc, r0
	.size	exec_pagefault, .-exec_pagefault

/* Special dynamic linker for the case where a page fault
   may occur in a branch delay slot */
FUNCTION(dyna_linker_ds):
	/* r0 = virtual target address */
	/* r1 = instruction to patch */
	dyna_linker_main

	mov	r4, r0
	bic	r0, r0, #7
	mov	r5, r1
	orr	r0, r0, #1
	bl	new_recompile_block
	tst	r0, r0
	mov	r0, r4
	mov	r1, r5
	beq	dyna_linker_ds
	/* pagefault */
	bic	r1, r0, #7
	mov	r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
	sub	r0, r1, #4
	b	exec_pagefault
	.size	dyna_linker_ds, .-dyna_linker_ds

	.align	2

FUNCTION(jump_vaddr_r0):
	eor	r2, r0, r0, lsl #16
	b	jump_vaddr
	.size	jump_vaddr_r0, .-jump_vaddr_r0
FUNCTION(jump_vaddr_r1):
	eor	r2, r1, r1, lsl #16
	mov	r0, r1
	b	jump_vaddr
	.size	jump_vaddr_r1, .-jump_vaddr_r1
FUNCTION(jump_vaddr_r2):
	mov	r0, r2
	eor	r2, r2, r2, lsl #16
	b	jump_vaddr
	.size	jump_vaddr_r2, .-jump_vaddr_r2
FUNCTION(jump_vaddr_r3):
	eor	r2, r3, r3, lsl #16
	mov	r0, r3
	b	jump_vaddr
	.size	jump_vaddr_r3, .-jump_vaddr_r3
FUNCTION(jump_vaddr_r4):
	eor	r2, r4, r4, lsl #16
	mov	r0, r4
	b	jump_vaddr
	.size	jump_vaddr_r4, .-jump_vaddr_r4
FUNCTION(jump_vaddr_r5):
	eor	r2, r5, r5, lsl #16
	mov	r0, r5
	b	jump_vaddr
	.size	jump_vaddr_r5, .-jump_vaddr_r5
FUNCTION(jump_vaddr_r6):
	eor	r2, r6, r6, lsl #16
	mov	r0, r6
	b	jump_vaddr
	.size	jump_vaddr_r6, .-jump_vaddr_r6
FUNCTION(jump_vaddr_r8):
	eor	r2, r8, r8, lsl #16
	mov	r0, r8
	b	jump_vaddr
	.size	jump_vaddr_r8, .-jump_vaddr_r8
FUNCTION(jump_vaddr_r9):
	eor	r2, r9, r9, lsl #16
	mov	r0, r9
	b	jump_vaddr
	.size	jump_vaddr_r9, .-jump_vaddr_r9
FUNCTION(jump_vaddr_r10):
	eor	r2, r10, r10, lsl #16
	mov	r0, r10
	b	jump_vaddr
	.size	jump_vaddr_r10, .-jump_vaddr_r10
FUNCTION(jump_vaddr_r12):
	eor	r2, r12, r12, lsl #16
	mov	r0, r12
	b	jump_vaddr
	.size	jump_vaddr_r12, .-jump_vaddr_r12
FUNCTION(jump_vaddr_r7):
	eor	r2, r7, r7, lsl #16
	add	r0, r7, #0
	.size	jump_vaddr_r7, .-jump_vaddr_r7
FUNCTION(jump_vaddr):
	load_varadr_ext r1, hash_table
	mvn	r3, #15
	and	r2, r3, r2, lsr #12
	ldr	r2, [r1, r2]!
	teq	r2, r0
	ldreq	pc, [r1, #8]
	ldr	r2, [r1, #4]
	teq	r2, r0
	ldreq	pc, [r1, #12]
	str	r10, [fp, #LO_cycle_count]
	bl	get_addr
	ldr	r10, [fp, #LO_cycle_count]
	mov	pc, r0
	.size	jump_vaddr, .-jump_vaddr

	.align	2

FUNCTION(verify_code_ds):
	str	r8, [fp, #LO_branch_target]  @ preserve HOST_BTREG?
FUNCTION(verify_code):
	/* r1 = source */
	/* r2 = target */
	/* r3 = length */
	tst	r3, #4
	mov	r4, #0
	add	r3, r1, r3
	mov	r5, #0
	ldrne	r4, [r1], #4
	mov	r12, #0
	ldrne	r5, [r2], #4
	teq	r1, r3
	beq	.D3
.D2:
	ldr	r7, [r1], #4
	eor	r9, r4, r5
	ldr	r8, [r2], #4
	orrs	r9, r9, r12
	bne	.D4
	ldr	r4, [r1], #4
	eor	r12, r7, r8
	ldr	r5, [r2], #4
	cmp	r1, r3
	bcc	.D2
	teq	r7, r8
.D3:
	teqeq	r4, r5
.D4:
	ldr	r8, [fp, #LO_branch_target]
	moveq	pc, lr
.D5:
	bl	get_addr
	mov	pc, r0
	.size	verify_code, .-verify_code
	.size	verify_code_ds, .-verify_code_ds

	.align	2
FUNCTION(cc_interrupt):
	ldr	r0, [fp, #LO_last_count]
	mov	r1, #0
	mov	r2, #0x1fc
	add	r10, r0, r10
	str	r1, [fp, #LO_pending_exception]
	and	r2, r2, r10, lsr #17
	add	r3, fp, #LO_restore_candidate
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
@@	str	r10, [fp, #LO_reg_cop0+36]	/* Count */
	ldr	r4, [r2, r3]
	mov	r10, lr
	tst	r4, r4
	bne	.E4
.E1:
	bl	gen_interupt
	mov	lr, r10
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r1, [fp, #LO_pending_exception]
	ldr	r2, [fp, #LO_stop]
	str	r0, [fp, #LO_last_count]
	sub	r10, r10, r0
	tst	r2, r2
	ldmfdne	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	tst	r1, r1
	moveq	pc, lr
.E2:
	ldr	r0, [fp, #LO_pcaddr]
	bl	get_addr_ht
	mov	pc, r0
.E4:
	/* Move 'dirty' blocks to the 'clean' list */
	lsl	r5, r2, #3
	str	r1, [r2, r3]
.E5:
	lsrs	r4, r4, #1
	mov	r0, r5
	add	r5, r5, #1
	blcs	clean_blocks
	tst	r5, #31
	bne	.E5
	b	.E1
	.size	cc_interrupt, .-cc_interrupt

	.align	2
FUNCTION(fp_exception):
	mov	r2, #0x10000000
.E7:
	ldr	r1, [fp, #LO_reg_cop0+48] /* Status */
	mov	r3, #0x80000000
	str	r0, [fp, #LO_reg_cop0+56] /* EPC */
	orr	r1, #2
	add	r2, r2, #0x2c
	str	r1, [fp, #LO_reg_cop0+48] /* Status */
	str	r2, [fp, #LO_reg_cop0+52] /* Cause */
	add	r0, r3, #0x80
	bl	get_addr_ht
	mov	pc, r0
	.size	fp_exception, .-fp_exception
	.align	2
FUNCTION(fp_exception_ds):
	mov	r2, #0x90000000 /* Set high bit if delay slot */
	b	.E7
	.size	fp_exception_ds, .-fp_exception_ds

	.align	2
FUNCTION(jump_break_ds):
	mov	r0, #0x24
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_break):
	mov	r0, #0x24
	mov	r1, #0
	b	call_psxException
FUNCTION(jump_syscall_ds):
	mov	r0, #0x20
	mov	r1, #1
	b	call_psxException
FUNCTION(jump_syscall):
	mov	r0, #0x20
	mov	r1, #0

call_psxException:
	ldr	r3, [fp, #LO_last_count]
	str	r2, [fp, #LO_pcaddr]
	add	r10, r3, r10
	str	r10, [fp, #LO_cycle]		/* PCSX cycles */
	bl	psxException

	/* note: psxException might do recursive recompiler call from it's HLE code,
	 * so be ready for this */
FUNCTION(jump_to_new_pc):
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	ldr	r0, [fp, #LO_pcaddr]
	sub	r10, r10, r1
	str	r1, [fp, #LO_last_count]
	bl	get_addr_ht
	mov	pc, r0
	.size	jump_to_new_pc, .-jump_to_new_pc

	.align	2
FUNCTION(new_dyna_leave):
	ldr	r0, [fp, #LO_last_count]
	add	r12, fp, #28
	add	r10, r0, r10
	str	r10, [fp, #LO_cycle]
	ldmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	.size	new_dyna_leave, .-new_dyna_leave

	.align	2
FUNCTION(invalidate_addr_r0):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	b	invalidate_addr_call
	.size	invalidate_addr_r0, .-invalidate_addr_r0
	.align	2
FUNCTION(invalidate_addr_r1):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r1
	b	invalidate_addr_call
	.size	invalidate_addr_r1, .-invalidate_addr_r1
	.align	2
FUNCTION(invalidate_addr_r2):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r2
	b	invalidate_addr_call
	.size	invalidate_addr_r2, .-invalidate_addr_r2
	.align	2
FUNCTION(invalidate_addr_r3):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r3
	b	invalidate_addr_call
	.size	invalidate_addr_r3, .-invalidate_addr_r3
	.align	2
FUNCTION(invalidate_addr_r4):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r4
	b	invalidate_addr_call
	.size	invalidate_addr_r4, .-invalidate_addr_r4
	.align	2
FUNCTION(invalidate_addr_r5):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r5
	b	invalidate_addr_call
	.size	invalidate_addr_r5, .-invalidate_addr_r5
	.align	2
FUNCTION(invalidate_addr_r6):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r6
	b	invalidate_addr_call
	.size	invalidate_addr_r6, .-invalidate_addr_r6
	.align	2
FUNCTION(invalidate_addr_r7):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r7
	b	invalidate_addr_call
	.size	invalidate_addr_r7, .-invalidate_addr_r7
	.align	2
FUNCTION(invalidate_addr_r8):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r8
	b	invalidate_addr_call
	.size	invalidate_addr_r8, .-invalidate_addr_r8
	.align	2
FUNCTION(invalidate_addr_r9):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r9
	b	invalidate_addr_call
	.size	invalidate_addr_r9, .-invalidate_addr_r9
	.align	2
FUNCTION(invalidate_addr_r10):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r10
	b	invalidate_addr_call
	.size	invalidate_addr_r10, .-invalidate_addr_r10
	.align	2
FUNCTION(invalidate_addr_r12):
	stmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	mov	r0, r12
	.size	invalidate_addr_r12, .-invalidate_addr_r12
	.align	2
invalidate_addr_call:
	ldr	r12, [fp, #LO_inv_code_start]
	ldr	lr, [fp, #LO_inv_code_end]
	cmp	r0, r12
	cmpcs   lr, r0
	blcc	invalidate_addr
	ldmia	fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	.size	invalidate_addr_call, .-invalidate_addr_call

	.align	2
FUNCTION(new_dyna_start):
	/* ip is stored to conform EABI alignment */
	stmfd	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	mov	fp, r0 /* dynarec_local */
	ldr	r0, [fp, #LO_pcaddr]
	bl	get_addr_ht
	ldr	r1, [fp, #LO_next_interupt]
	ldr	r10, [fp, #LO_cycle]
	str	r1, [fp, #LO_last_count]
	sub	r10, r10, r1
	mov	pc, r0
	.size	new_dyna_start, .-new_dyna_start

/* --------------------------------------- */

.align	2

.macro pcsx_read_mem readop tab_shift
	/* r0 = address, r1 = handler_tab, r2 = cycles */
	lsl	r3, r0, #20
	lsr	r3, #(20+\tab_shift)
	ldr	r12, [fp, #LO_last_count]
	ldr	r1, [r1, r3, lsl #2]
	add	r2, r2, r12
	lsls	r1, #1
.if \tab_shift == 1
	lsl	r3, #1
	\readop	r0, [r1, r3]
.else
	\readop	r0, [r1, r3, lsl #\tab_shift]
.endif
	movcc	pc, lr
	str	r2, [fp, #LO_cycle]
	bx	r1
.endm

FUNCTION(jump_handler_read8):
	add     r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_read_mem ldrbcc, 0

FUNCTION(jump_handler_read16):
	add     r1, #0x1000/4*4              @ shift to r16 part
	pcsx_read_mem ldrhcc, 1

FUNCTION(jump_handler_read32):
	pcsx_read_mem ldrcc, 2


.macro memhandler_post
	ldr	r0, [fp, #LO_next_interupt]
	ldr	r2, [fp, #LO_cycle]        @ memhandlers can modify cc, like dma
	str	r0, [fp, #LO_last_count]
	sub	r0, r2, r0
.endm

.macro pcsx_write_mem wrtop tab_shift
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	lsl	r12,r0, #20
	lsr	r12, #(20+\tab_shift)
	ldr	r3, [r3, r12, lsl #2]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	lsls	r3, #1
	mov     r0, r2                     @ cycle return in case of direct store
.if \tab_shift == 1
	lsl	r12, #1
	\wrtop	r1, [r3, r12]
.else
	\wrtop	r1, [r3, r12, lsl #\tab_shift]
.endif
	movcc	pc, lr
	ldr	r12, [fp, #LO_last_count]
	mov     r0, r1
	add	r2, r2, r12
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr
.endm

FUNCTION(jump_handler_write8):
	add     r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
	pcsx_write_mem strbcc, 0

FUNCTION(jump_handler_write16):
	add     r3, #0x1000/4*4              @ shift to r16 part
	pcsx_write_mem strhcc, 1

FUNCTION(jump_handler_write32):
	pcsx_write_mem strcc, 2

FUNCTION(jump_handler_write_h):
	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	ldr	r12, [fp, #LO_last_count]
	str	r0, [fp, #LO_address]      @ some handlers still need it..
	add	r2, r2, r12
	mov     r0, r1
	str	r2, [fp, #LO_cycle]

	str	lr, [fp, #LO_saved_lr]
	blx	r3
	ldr	lr, [fp, #LO_saved_lr]

	memhandler_post
	bx	lr

FUNCTION(jump_handle_swl):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	mov	r0, r2
	tst	r3, #2
	beq	101f
	tst	r3, #1
	beq	2f
3:
	str	r1, [r3, #-3]
	bx	lr
2:
	lsr	r2, r1, #8
	lsr	r1, #24
	strh	r2, [r3, #-2]
	strb	r1, [r3]
	bx	lr
101:
	tst	r3, #1
	lsrne	r1, #16		@ 1
	lsreq	r12, r1, #24	@ 0
	strhne	r1, [r3, #-1]
	strbeq	r12, [r3]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


FUNCTION(jump_handle_swr):
	/* r0 = address, r1 = data, r2 = cycles */
	ldr	r3, [fp, #LO_mem_wtab]
	mov	r12,r0,lsr #12
	ldr	r3, [r3, r12, lsl #2]
	lsls	r3, #1
	bcs	4f
	add	r3, r0, r3
	and	r12,r3, #3
	mov	r0, r2
	cmp	r12,#2
	strbgt	r1, [r3]	@ 3
	strheq	r1, [r3]	@ 2
	cmp	r12,#1
	strlt	r1, [r3]	@ 0
	bxne	lr
	lsr	r2, r1, #8	@ 1
	strb	r1, [r3]
	strh	r2, [r3, #1]
	bx	lr
4:
	mov	r0, r2
@	b	abort
	bx	lr		@ TODO?


.macro rcntx_read_mode0 num
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
	mov	r0, r2, lsl #16
	sub	r0, r0, r3, lsl #16
	lsr	r0, #16
	bx	lr
.endm

FUNCTION(rcnt0_read_count_m0):
	rcntx_read_mode0 0

FUNCTION(rcnt1_read_count_m0):
	rcntx_read_mode0 1

FUNCTION(rcnt2_read_count_m0):
	rcntx_read_mode0 2

FUNCTION(rcnt0_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
	mov_16	r1, 0x3334
	sub	r2, r2, r3
	mul	r0, r1, r2		@ /= 5
	lsr	r0, #16
	bx	lr

FUNCTION(rcnt1_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*1]
	mov_24	r1, 0x1e6cde
	sub	r2, r2, r3
	umull	r3, r0, r1, r2		@ ~ /= hsync_cycles, max ~0x1e6cdd
	bx	lr

FUNCTION(rcnt2_read_count_m1):
	/* r0 = address, r2 = cycles */
	ldr	r3, [fp, #LO_rcnts+6*4+7*4*2]
	mov	r0, r2, lsl #16-3
	sub	r0, r0, r3, lsl #16-3
	lsr	r0, #16			@ /= 8
	bx	lr

FUNCTION(call_gteStall):
	/* r0 = op_cycles, r1 = cycles */
	ldr	r2, [fp, #LO_last_count]
	str	lr, [fp, #LO_saved_lr]
	add	r1, r1, r2
	str	r1, [fp, #LO_cycle]
	add	r1, fp, #LO_psxRegs
	bl	gteCheckStallRaw
	ldr	lr, [fp, #LO_saved_lr]
	add	r10, r10, r0
	bx	lr

@ vim:filetype=armasm
Commit	Line	Data
	1	/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
	2	* linkage_arm.s for PCSX *
	3	* Copyright (C) 2009-2011 Ari64 *
	4	* Copyright (C) 2010-2013 Gražvydas "notaz" Ignotas *
	5	* *
	6	* This program is free software; you can redistribute it and/or modify *
	7	* it under the terms of the GNU General Public License as published by *
	8	* the Free Software Foundation; either version 2 of the License, or *
	9	* (at your option) any later version. *
	10	* *
	11	* This program is distributed in the hope that it will be useful, *
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	14	* GNU General Public License for more details. *
	15	* *
	16	* You should have received a copy of the GNU General Public License *
	17	* along with this program; if not, write to the *
	18	* Free Software Foundation, Inc., *
	19	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
	20	* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
	21
	22	#include "arm_features.h"
	23	#include "new_dynarec_config.h"
	24	#include "linkage_offsets.h"
	25
	26
	27	#ifdef __MACH__
	28	#define dynarec_local ESYM(dynarec_local)
	29	#define add_jump_out ESYM(add_jump_out)
	30	#define new_recompile_block ESYM(new_recompile_block)
	31	#define get_addr ESYM(get_addr)
	32	#define get_addr_ht ESYM(get_addr_ht)
	33	#define clean_blocks ESYM(clean_blocks)
	34	#define gen_interupt ESYM(gen_interupt)
	35	#define invalidate_addr ESYM(invalidate_addr)
	36	#define gteCheckStallRaw ESYM(gteCheckStallRaw)
	37	#define psxException ESYM(psxException)
	38	#endif
	39
	40	.bss
	41	.align 4
	42	.global dynarec_local
	43	.type dynarec_local, %object
	44	.size dynarec_local, LO_dynarec_local_size
	45	dynarec_local:
	46	.space LO_dynarec_local_size
	47
	48	#define DRC_VAR_(name, vname, size_) \
	49	vname = dynarec_local + LO_##name; \
	50	.global vname; \
	51	.type vname, %object; \
	52	.size vname, size_
	53
	54	#define DRC_VAR(name, size_) \
	55	DRC_VAR_(name, ESYM(name), size_)
	56
	57	DRC_VAR(next_interupt, 4)
	58	DRC_VAR(cycle_count, 4)
	59	DRC_VAR(last_count, 4)
	60	DRC_VAR(pending_exception, 4)
	61	DRC_VAR(stop, 4)
	62	DRC_VAR(branch_target, 4)
	63	DRC_VAR(address, 4)
	64	DRC_VAR(hack_addr, 4)
	65	DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
	66
	67	/* psxRegs */
	68	@DRC_VAR(reg, 128)
	69	DRC_VAR(lo, 4)
	70	DRC_VAR(hi, 4)
	71	DRC_VAR(reg_cop0, 128)
	72	DRC_VAR(reg_cop2d, 128)
	73	DRC_VAR(reg_cop2c, 128)
	74	DRC_VAR(pcaddr, 4)
	75	@DRC_VAR(code, 4)
	76	@DRC_VAR(cycle, 4)
	77	@DRC_VAR(interrupt, 4)
	78	@DRC_VAR(intCycle, 256)
	79
	80	DRC_VAR(rcnts, 744)
	81	DRC_VAR(inv_code_start, 4)
	82	DRC_VAR(inv_code_end, 4)
	83	DRC_VAR(mem_rtab, 4)
	84	DRC_VAR(mem_wtab, 4)
	85	DRC_VAR(psxH_ptr, 4)
	86	DRC_VAR(zeromem_ptr, 4)
	87	DRC_VAR(invc_ptr, 4)
	88	DRC_VAR(scratch_buf_ptr, 4)
	89	DRC_VAR(ram_offset, 4)
	90	DRC_VAR(mini_ht, 256)
	91	DRC_VAR(restore_candidate, 512)
	92
	93
	94	#ifdef TEXRELS_FORBIDDEN
	95	.data
	96	.align 2
	97	ptr_jump_in:
	98	.word ESYM(jump_in)
	99	ptr_jump_dirty:
	100	.word ESYM(jump_dirty)
	101	ptr_hash_table:
	102	.word ESYM(hash_table)
	103	#endif
	104
	105
	106	.syntax unified
	107	.text
	108	.align 2
	109
	110	#ifndef HAVE_ARMV5
	111	.macro blx rd
	112	mov lr, pc
	113	bx \rd
	114	.endm
	115	#endif
	116
	117	.macro load_varadr reg var
	118	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	119	movw \reg, #:lower16:(\var-(1678f+8))
	120	movt \reg, #:upper16:(\var-(1678f+8))
	121	1678:
	122	add \reg, pc
	123	#elif defined(HAVE_ARMV7) && !defined(__PIC__)
	124	movw \reg, #:lower16:\var
	125	movt \reg, #:upper16:\var
	126	#else
	127	ldr \reg, =\var
	128	#endif
	129	.endm
	130
	131	.macro load_varadr_ext reg var
	132	#if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
	133	movw \reg, #:lower16:(ptr_\var-(1678f+8))
	134	movt \reg, #:upper16:(ptr_\var-(1678f+8))
	135	1678:
	136	ldr \reg, [pc, \reg]
	137	#else
	138	load_varadr \reg \var
	139	#endif
	140	.endm
	141
	142	.macro mov_16 reg imm
	143	#ifdef HAVE_ARMV7
	144	movw \reg, #\imm
	145	#else
	146	mov \reg, #(\imm & 0x00ff)
	147	orr \reg, #(\imm & 0xff00)
	148	#endif
	149	.endm
	150
	151	.macro mov_24 reg imm
	152	#ifdef HAVE_ARMV7
	153	movw \reg, #(\imm & 0xffff)
	154	movt \reg, #(\imm >> 16)
	155	#else
	156	mov \reg, #(\imm & 0x0000ff)
	157	orr \reg, #(\imm & 0x00ff00)
	158	orr \reg, #(\imm & 0xff0000)
	159	#endif
	160	.endm
	161
	162	/* r0 = virtual target address */
	163	/* r1 = instruction to patch */
	164	.macro dyna_linker_main
	165	#ifndef NO_WRITE_EXEC
	166	load_varadr_ext r3, jump_in
	167	/* get_page */
	168	lsr r2, r0, #12
	169	mov r6, #4096
	170	bic r2, r2, #0xe0000
	171	sub r6, r6, #1
	172	cmp r2, #0x1000
	173	ldr r7, [r1]
	174	biclt r2, #0x0e00
	175	and r6, r6, r2
	176	cmp r2, #2048
	177	add r12, r7, #2
	178	orrcs r2, r6, #2048
	179	ldr r5, [r3, r2, lsl #2]
	180	lsl r12, r12, #8
	181	add r6, r1, r12, asr #6 /* old target */
	182	mov r8, #0
	183	/* jump_in lookup */
	184	1:
	185	movs r4, r5
	186	beq 2f
	187	ldr r3, [r5] /* ll_entry .vaddr */
	188	ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
	189	teq r3, r0
	190	bne 1b
	191	teq r4, r6
	192	moveq pc, r4 /* Stale i-cache */
	193	mov r8, r4
	194	b 1b /* jump_in may have dupes, continue search */
	195	2:
	196	tst r8, r8
	197	beq 3f /* r0 not in jump_in */
	198
	199	mov r5, r1
	200	mov r1, r6
	201	bl add_jump_out
	202	sub r2, r8, r5
	203	and r1, r7, #0xff000000
	204	lsl r2, r2, #6
	205	sub r1, r1, #2
	206	add r1, r1, r2, lsr #8
	207	str r1, [r5]
	208	mov pc, r8
	209	3:
	210	/* hash_table lookup */
	211	cmp r2, #2048
	212	load_varadr_ext r3, jump_dirty
	213	eor r4, r0, r0, lsl #16
	214	lslcc r2, r0, #9
	215	load_varadr_ext r6, hash_table
	216	lsr r4, r4, #12
	217	lsrcc r2, r2, #21
	218	bic r4, r4, #15
	219	ldr r5, [r3, r2, lsl #2]
	220	ldr r7, [r6, r4]!
	221	teq r7, r0
	222	ldreq pc, [r6, #8]
	223	ldr r7, [r6, #4]
	224	teq r7, r0
	225	ldreq pc, [r6, #12]
	226	/* jump_dirty lookup */
	227	6:
	228	movs r4, r5
	229	beq 8f
	230	ldr r3, [r5]
	231	ldr r5, [r4, #12]
	232	teq r3, r0
	233	bne 6b
	234	7:
	235	ldr r1, [r4, #8]
	236	/* hash_table insert */
	237	ldr r2, [r6]
	238	ldr r3, [r6, #8]
	239	str r0, [r6]
	240	str r1, [r6, #8]
	241	str r2, [r6, #4]
	242	str r3, [r6, #12]
	243	mov pc, r1
	244	8:
	245	#else
	246	/* XXX: should be able to do better than this... */
	247	bl get_addr_ht
	248	mov pc, r0
	249	#endif
	250	.endm
	251
	252
	253	FUNCTION(dyna_linker):
	254	/* r0 = virtual target address */
	255	/* r1 = instruction to patch */
	256	dyna_linker_main
	257
	258	mov r4, r0
	259	mov r5, r1
	260	bl new_recompile_block
	261	tst r0, r0
	262	mov r0, r4
	263	mov r1, r5
	264	beq dyna_linker
	265	/* pagefault */
	266	mov r1, r0
	267	mov r2, #8
	268	.size dyna_linker, .-dyna_linker
	269
	270	FUNCTION(exec_pagefault):
	271	/* r0 = instruction pointer */
	272	/* r1 = fault address */
	273	/* r2 = cause */
	274	ldr r3, [fp, #LO_reg_cop0+48] /* Status */
	275	mvn r6, #0xF000000F
	276	ldr r4, [fp, #LO_reg_cop0+16] /* Context */
	277	bic r6, r6, #0x0F800000
	278	str r0, [fp, #LO_reg_cop0+56] /* EPC */
	279	orr r3, r3, #2
	280	str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
	281	bic r4, r4, r6
	282	str r3, [fp, #LO_reg_cop0+48] /* Status */
	283	and r5, r6, r1, lsr #9
	284	str r2, [fp, #LO_reg_cop0+52] /* Cause */
	285	and r1, r1, r6, lsl #9
	286	str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
	287	orr r4, r4, r5
	288	str r4, [fp, #LO_reg_cop0+16] /* Context */
	289	mov r0, #0x80000000
	290	bl get_addr_ht
	291	mov pc, r0
	292	.size exec_pagefault, .-exec_pagefault
	293
	294	/* Special dynamic linker for the case where a page fault
	295	may occur in a branch delay slot */
	296	FUNCTION(dyna_linker_ds):
	297	/* r0 = virtual target address */
	298	/* r1 = instruction to patch */
	299	dyna_linker_main
	300
	301	mov r4, r0
	302	bic r0, r0, #7
	303	mov r5, r1
	304	orr r0, r0, #1
	305	bl new_recompile_block
	306	tst r0, r0
	307	mov r0, r4
	308	mov r1, r5
	309	beq dyna_linker_ds
	310	/* pagefault */
	311	bic r1, r0, #7
	312	mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
	313	sub r0, r1, #4
	314	b exec_pagefault
	315	.size dyna_linker_ds, .-dyna_linker_ds
	316
	317	.align 2
	318
	319	FUNCTION(jump_vaddr_r0):
	320	eor r2, r0, r0, lsl #16
	321	b jump_vaddr
	322	.size jump_vaddr_r0, .-jump_vaddr_r0
	323	FUNCTION(jump_vaddr_r1):
	324	eor r2, r1, r1, lsl #16
	325	mov r0, r1
	326	b jump_vaddr
	327	.size jump_vaddr_r1, .-jump_vaddr_r1
	328	FUNCTION(jump_vaddr_r2):
	329	mov r0, r2
	330	eor r2, r2, r2, lsl #16
	331	b jump_vaddr
	332	.size jump_vaddr_r2, .-jump_vaddr_r2
	333	FUNCTION(jump_vaddr_r3):
	334	eor r2, r3, r3, lsl #16
	335	mov r0, r3
	336	b jump_vaddr
	337	.size jump_vaddr_r3, .-jump_vaddr_r3
	338	FUNCTION(jump_vaddr_r4):
	339	eor r2, r4, r4, lsl #16
	340	mov r0, r4
	341	b jump_vaddr
	342	.size jump_vaddr_r4, .-jump_vaddr_r4
	343	FUNCTION(jump_vaddr_r5):
	344	eor r2, r5, r5, lsl #16
	345	mov r0, r5
	346	b jump_vaddr
	347	.size jump_vaddr_r5, .-jump_vaddr_r5
	348	FUNCTION(jump_vaddr_r6):
	349	eor r2, r6, r6, lsl #16
	350	mov r0, r6
	351	b jump_vaddr
	352	.size jump_vaddr_r6, .-jump_vaddr_r6
	353	FUNCTION(jump_vaddr_r8):
	354	eor r2, r8, r8, lsl #16
	355	mov r0, r8
	356	b jump_vaddr
	357	.size jump_vaddr_r8, .-jump_vaddr_r8
	358	FUNCTION(jump_vaddr_r9):
	359	eor r2, r9, r9, lsl #16
	360	mov r0, r9
	361	b jump_vaddr
	362	.size jump_vaddr_r9, .-jump_vaddr_r9
	363	FUNCTION(jump_vaddr_r10):
	364	eor r2, r10, r10, lsl #16
	365	mov r0, r10
	366	b jump_vaddr
	367	.size jump_vaddr_r10, .-jump_vaddr_r10
	368	FUNCTION(jump_vaddr_r12):
	369	eor r2, r12, r12, lsl #16
	370	mov r0, r12
	371	b jump_vaddr
	372	.size jump_vaddr_r12, .-jump_vaddr_r12
	373	FUNCTION(jump_vaddr_r7):
	374	eor r2, r7, r7, lsl #16
	375	add r0, r7, #0
	376	.size jump_vaddr_r7, .-jump_vaddr_r7
	377	FUNCTION(jump_vaddr):
	378	load_varadr_ext r1, hash_table
	379	mvn r3, #15
	380	and r2, r3, r2, lsr #12
	381	ldr r2, [r1, r2]!
	382	teq r2, r0
	383	ldreq pc, [r1, #8]
	384	ldr r2, [r1, #4]
	385	teq r2, r0
	386	ldreq pc, [r1, #12]
	387	str r10, [fp, #LO_cycle_count]
	388	bl get_addr
	389	ldr r10, [fp, #LO_cycle_count]
	390	mov pc, r0
	391	.size jump_vaddr, .-jump_vaddr
	392
	393	.align 2
	394
	395	FUNCTION(verify_code_ds):
	396	str r8, [fp, #LO_branch_target] @ preserve HOST_BTREG?
	397	FUNCTION(verify_code):
	398	/* r1 = source */
	399	/* r2 = target */
	400	/* r3 = length */
	401	tst r3, #4
	402	mov r4, #0
	403	add r3, r1, r3
	404	mov r5, #0
	405	ldrne r4, [r1], #4
	406	mov r12, #0
	407	ldrne r5, [r2], #4
	408	teq r1, r3
	409	beq .D3
	410	.D2:
	411	ldr r7, [r1], #4
	412	eor r9, r4, r5
	413	ldr r8, [r2], #4
	414	orrs r9, r9, r12
	415	bne .D4
	416	ldr r4, [r1], #4
	417	eor r12, r7, r8
	418	ldr r5, [r2], #4
	419	cmp r1, r3
	420	bcc .D2
	421	teq r7, r8
	422	.D3:
	423	teqeq r4, r5
	424	.D4:
	425	ldr r8, [fp, #LO_branch_target]
	426	moveq pc, lr
	427	.D5:
	428	bl get_addr
	429	mov pc, r0
	430	.size verify_code, .-verify_code
	431	.size verify_code_ds, .-verify_code_ds
	432
	433	.align 2
	434	FUNCTION(cc_interrupt):
	435	ldr r0, [fp, #LO_last_count]
	436	mov r1, #0
	437	mov r2, #0x1fc
	438	add r10, r0, r10
	439	str r1, [fp, #LO_pending_exception]
	440	and r2, r2, r10, lsr #17
	441	add r3, fp, #LO_restore_candidate
	442	str r10, [fp, #LO_cycle] /* PCSX cycles */
	443	@@ str r10, [fp, #LO_reg_cop0+36] /* Count */
	444	ldr r4, [r2, r3]
	445	mov r10, lr
	446	tst r4, r4
	447	bne .E4
	448	.E1:
	449	bl gen_interupt
	450	mov lr, r10
	451	ldr r10, [fp, #LO_cycle]
	452	ldr r0, [fp, #LO_next_interupt]
	453	ldr r1, [fp, #LO_pending_exception]
	454	ldr r2, [fp, #LO_stop]
	455	str r0, [fp, #LO_last_count]
	456	sub r10, r10, r0
	457	tst r2, r2
	458	ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	459	tst r1, r1
	460	moveq pc, lr
	461	.E2:
	462	ldr r0, [fp, #LO_pcaddr]
	463	bl get_addr_ht
	464	mov pc, r0
	465	.E4:
	466	/* Move 'dirty' blocks to the 'clean' list */
	467	lsl r5, r2, #3
	468	str r1, [r2, r3]
	469	.E5:
	470	lsrs r4, r4, #1
	471	mov r0, r5
	472	add r5, r5, #1
	473	blcs clean_blocks
	474	tst r5, #31
	475	bne .E5
	476	b .E1
	477	.size cc_interrupt, .-cc_interrupt
	478
	479	.align 2
	480	FUNCTION(fp_exception):
	481	mov r2, #0x10000000
	482	.E7:
	483	ldr r1, [fp, #LO_reg_cop0+48] /* Status */
	484	mov r3, #0x80000000
	485	str r0, [fp, #LO_reg_cop0+56] /* EPC */
	486	orr r1, #2
	487	add r2, r2, #0x2c
	488	str r1, [fp, #LO_reg_cop0+48] /* Status */
	489	str r2, [fp, #LO_reg_cop0+52] /* Cause */
	490	add r0, r3, #0x80
	491	bl get_addr_ht
	492	mov pc, r0
	493	.size fp_exception, .-fp_exception
	494	.align 2
	495	FUNCTION(fp_exception_ds):
	496	mov r2, #0x90000000 /* Set high bit if delay slot */
	497	b .E7
	498	.size fp_exception_ds, .-fp_exception_ds
	499
	500	.align 2
	501	FUNCTION(jump_break_ds):
	502	mov r0, #0x24
	503	mov r1, #1
	504	b call_psxException
	505	FUNCTION(jump_break):
	506	mov r0, #0x24
	507	mov r1, #0
	508	b call_psxException
	509	FUNCTION(jump_syscall_ds):
	510	mov r0, #0x20
	511	mov r1, #1
	512	b call_psxException
	513	FUNCTION(jump_syscall):
	514	mov r0, #0x20
	515	mov r1, #0
	516
	517	call_psxException:
	518	ldr r3, [fp, #LO_last_count]
	519	str r2, [fp, #LO_pcaddr]
	520	add r10, r3, r10
	521	str r10, [fp, #LO_cycle] /* PCSX cycles */
	522	bl psxException
	523
	524	/* note: psxException might do recursive recompiler call from it's HLE code,
	525	* so be ready for this */
	526	FUNCTION(jump_to_new_pc):
	527	ldr r1, [fp, #LO_next_interupt]
	528	ldr r10, [fp, #LO_cycle]
	529	ldr r0, [fp, #LO_pcaddr]
	530	sub r10, r10, r1
	531	str r1, [fp, #LO_last_count]
	532	bl get_addr_ht
	533	mov pc, r0
	534	.size jump_to_new_pc, .-jump_to_new_pc
	535
	536	.align 2
	537	FUNCTION(new_dyna_leave):
	538	ldr r0, [fp, #LO_last_count]
	539	add r12, fp, #28
	540	add r10, r0, r10
	541	str r10, [fp, #LO_cycle]
	542	ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
	543	.size new_dyna_leave, .-new_dyna_leave
	544
	545	.align 2
	546	FUNCTION(invalidate_addr_r0):
	547	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	548	b invalidate_addr_call
	549	.size invalidate_addr_r0, .-invalidate_addr_r0
	550	.align 2
	551	FUNCTION(invalidate_addr_r1):
	552	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	553	mov r0, r1
	554	b invalidate_addr_call
	555	.size invalidate_addr_r1, .-invalidate_addr_r1
	556	.align 2
	557	FUNCTION(invalidate_addr_r2):
	558	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	559	mov r0, r2
	560	b invalidate_addr_call
	561	.size invalidate_addr_r2, .-invalidate_addr_r2
	562	.align 2
	563	FUNCTION(invalidate_addr_r3):
	564	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	565	mov r0, r3
	566	b invalidate_addr_call
	567	.size invalidate_addr_r3, .-invalidate_addr_r3
	568	.align 2
	569	FUNCTION(invalidate_addr_r4):
	570	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	571	mov r0, r4
	572	b invalidate_addr_call
	573	.size invalidate_addr_r4, .-invalidate_addr_r4
	574	.align 2
	575	FUNCTION(invalidate_addr_r5):
	576	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	577	mov r0, r5
	578	b invalidate_addr_call
	579	.size invalidate_addr_r5, .-invalidate_addr_r5
	580	.align 2
	581	FUNCTION(invalidate_addr_r6):
	582	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	583	mov r0, r6
	584	b invalidate_addr_call
	585	.size invalidate_addr_r6, .-invalidate_addr_r6
	586	.align 2
	587	FUNCTION(invalidate_addr_r7):
	588	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	589	mov r0, r7
	590	b invalidate_addr_call
	591	.size invalidate_addr_r7, .-invalidate_addr_r7
	592	.align 2
	593	FUNCTION(invalidate_addr_r8):
	594	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	595	mov r0, r8
	596	b invalidate_addr_call
	597	.size invalidate_addr_r8, .-invalidate_addr_r8
	598	.align 2
	599	FUNCTION(invalidate_addr_r9):
	600	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	601	mov r0, r9
	602	b invalidate_addr_call
	603	.size invalidate_addr_r9, .-invalidate_addr_r9
	604	.align 2
	605	FUNCTION(invalidate_addr_r10):
	606	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	607	mov r0, r10
	608	b invalidate_addr_call
	609	.size invalidate_addr_r10, .-invalidate_addr_r10
	610	.align 2
	611	FUNCTION(invalidate_addr_r12):
	612	stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
	613	mov r0, r12
	614	.size invalidate_addr_r12, .-invalidate_addr_r12
	615	.align 2
	616	invalidate_addr_call:
	617	ldr r12, [fp, #LO_inv_code_start]
	618	ldr lr, [fp, #LO_inv_code_end]
	619	cmp r0, r12
	620	cmpcs lr, r0
	621	blcc invalidate_addr
	622	ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
	623	.size invalidate_addr_call, .-invalidate_addr_call
	624
	625	.align 2
	626	FUNCTION(new_dyna_start):
	627	/* ip is stored to conform EABI alignment */
	628	stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
	629	mov fp, r0 /* dynarec_local */
	630	ldr r0, [fp, #LO_pcaddr]
	631	bl get_addr_ht
	632	ldr r1, [fp, #LO_next_interupt]
	633	ldr r10, [fp, #LO_cycle]
	634	str r1, [fp, #LO_last_count]
	635	sub r10, r10, r1
	636	mov pc, r0
	637	.size new_dyna_start, .-new_dyna_start
	638
	639	/* --------------------------------------- */
	640
	641	.align 2
	642
	643	.macro pcsx_read_mem readop tab_shift
	644	/* r0 = address, r1 = handler_tab, r2 = cycles */
	645	lsl r3, r0, #20
	646	lsr r3, #(20+\tab_shift)
	647	ldr r12, [fp, #LO_last_count]
	648	ldr r1, [r1, r3, lsl #2]
	649	add r2, r2, r12
	650	lsls r1, #1
	651	.if \tab_shift == 1
	652	lsl r3, #1
	653	\readop r0, [r1, r3]
	654	.else
	655	\readop r0, [r1, r3, lsl #\tab_shift]
	656	.endif
	657	movcc pc, lr
	658	str r2, [fp, #LO_cycle]
	659	bx r1
	660	.endm
	661
	662	FUNCTION(jump_handler_read8):
	663	add r1, #0x1000/44 + 0x1000/24 @ shift to r8 part
	664	pcsx_read_mem ldrbcc, 0
	665
	666	FUNCTION(jump_handler_read16):
	667	add r1, #0x1000/4*4 @ shift to r16 part
	668	pcsx_read_mem ldrhcc, 1
	669
	670	FUNCTION(jump_handler_read32):
	671	pcsx_read_mem ldrcc, 2
	672
	673
	674	.macro memhandler_post
	675	ldr r0, [fp, #LO_next_interupt]
	676	ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
	677	str r0, [fp, #LO_last_count]
	678	sub r0, r2, r0
	679	.endm
	680
	681	.macro pcsx_write_mem wrtop tab_shift
	682	/* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
	683	lsl r12,r0, #20
	684	lsr r12, #(20+\tab_shift)
	685	ldr r3, [r3, r12, lsl #2]
	686	str r0, [fp, #LO_address] @ some handlers still need it..
	687	lsls r3, #1
	688	mov r0, r2 @ cycle return in case of direct store
	689	.if \tab_shift == 1
	690	lsl r12, #1
	691	\wrtop r1, [r3, r12]
	692	.else
	693	\wrtop r1, [r3, r12, lsl #\tab_shift]
	694	.endif
	695	movcc pc, lr
	696	ldr r12, [fp, #LO_last_count]
	697	mov r0, r1
	698	add r2, r2, r12
	699	str r2, [fp, #LO_cycle]
	700
	701	str lr, [fp, #LO_saved_lr]
	702	blx r3
	703	ldr lr, [fp, #LO_saved_lr]
	704
	705	memhandler_post
	706	bx lr
	707	.endm
	708
	709	FUNCTION(jump_handler_write8):
	710	add r3, #0x1000/44 + 0x1000/24 @ shift to r8 part
	711	pcsx_write_mem strbcc, 0
	712
	713	FUNCTION(jump_handler_write16):
	714	add r3, #0x1000/4*4 @ shift to r16 part
	715	pcsx_write_mem strhcc, 1
	716
	717	FUNCTION(jump_handler_write32):
	718	pcsx_write_mem strcc, 2
	719
	720	FUNCTION(jump_handler_write_h):
	721	/* r0 = address, r1 = data, r2 = cycles, r3 = handler */
	722	ldr r12, [fp, #LO_last_count]
	723	str r0, [fp, #LO_address] @ some handlers still need it..
	724	add r2, r2, r12
	725	mov r0, r1
	726	str r2, [fp, #LO_cycle]
	727
	728	str lr, [fp, #LO_saved_lr]
	729	blx r3
	730	ldr lr, [fp, #LO_saved_lr]
	731
	732	memhandler_post
	733	bx lr
	734
	735	FUNCTION(jump_handle_swl):
	736	/* r0 = address, r1 = data, r2 = cycles */
	737	ldr r3, [fp, #LO_mem_wtab]
	738	mov r12,r0,lsr #12
	739	ldr r3, [r3, r12, lsl #2]
	740	lsls r3, #1
	741	bcs 4f
	742	add r3, r0, r3
	743	mov r0, r2
	744	tst r3, #2
	745	beq 101f
	746	tst r3, #1
	747	beq 2f
	748	3:
	749	str r1, [r3, #-3]
	750	bx lr
	751	2:
	752	lsr r2, r1, #8
	753	lsr r1, #24
	754	strh r2, [r3, #-2]
	755	strb r1, [r3]
	756	bx lr
	757	101:
	758	tst r3, #1
	759	lsrne r1, #16 @ 1
	760	lsreq r12, r1, #24 @ 0
	761	strhne r1, [r3, #-1]
	762	strbeq r12, [r3]
	763	bx lr
	764	4:
	765	mov r0, r2
	766	@ b abort
	767	bx lr @ TODO?
	768
	769
	770	FUNCTION(jump_handle_swr):
	771	/* r0 = address, r1 = data, r2 = cycles */
	772	ldr r3, [fp, #LO_mem_wtab]
	773	mov r12,r0,lsr #12
	774	ldr r3, [r3, r12, lsl #2]
	775	lsls r3, #1
	776	bcs 4f
	777	add r3, r0, r3
	778	and r12,r3, #3
	779	mov r0, r2
	780	cmp r12,#2
	781	strbgt r1, [r3] @ 3
	782	strheq r1, [r3] @ 2
	783	cmp r12,#1
	784	strlt r1, [r3] @ 0
	785	bxne lr
	786	lsr r2, r1, #8 @ 1
	787	strb r1, [r3]
	788	strh r2, [r3, #1]
	789	bx lr
	790	4:
	791	mov r0, r2
	792	@ b abort
	793	bx lr @ TODO?
	794
	795
	796	.macro rcntx_read_mode0 num
	797	/* r0 = address, r2 = cycles */
	798	ldr r3, [fp, #LO_rcnts+64+74*\num] @ cycleStart
	799	mov r0, r2, lsl #16
	800	sub r0, r0, r3, lsl #16
	801	lsr r0, #16
	802	bx lr
	803	.endm
	804
	805	FUNCTION(rcnt0_read_count_m0):
	806	rcntx_read_mode0 0
	807
	808	FUNCTION(rcnt1_read_count_m0):
	809	rcntx_read_mode0 1
	810
	811	FUNCTION(rcnt2_read_count_m0):
	812	rcntx_read_mode0 2
	813
	814	FUNCTION(rcnt0_read_count_m1):
	815	/* r0 = address, r2 = cycles */
	816	ldr r3, [fp, #LO_rcnts+64+74*0] @ cycleStart
	817	mov_16 r1, 0x3334
	818	sub r2, r2, r3
	819	mul r0, r1, r2 @ /= 5
	820	lsr r0, #16
	821	bx lr
	822
	823	FUNCTION(rcnt1_read_count_m1):
	824	/* r0 = address, r2 = cycles */
	825	ldr r3, [fp, #LO_rcnts+64+74*1]
	826	mov_24 r1, 0x1e6cde
	827	sub r2, r2, r3
	828	umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
	829	bx lr
	830
	831	FUNCTION(rcnt2_read_count_m1):
	832	/* r0 = address, r2 = cycles */
	833	ldr r3, [fp, #LO_rcnts+64+74*2]
	834	mov r0, r2, lsl #16-3
	835	sub r0, r0, r3, lsl #16-3
	836	lsr r0, #16 @ /= 8
	837	bx lr
	838
	839	FUNCTION(call_gteStall):
	840	/* r0 = op_cycles, r1 = cycles */
	841	ldr r2, [fp, #LO_last_count]
	842	str lr, [fp, #LO_saved_lr]
	843	add r1, r1, r2
	844	str r1, [fp, #LO_cycle]
	845	add r1, fp, #LO_psxRegs
	846	bl gteCheckStallRaw
	847	ldr lr, [fp, #LO_saved_lr]
	848	add r10, r10, r0
	849	bx lr
	850
	851	@ vim:filetype=armasm