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drc: try to avoid some block trapping
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24#include <errno.h>
25#include <sys/mman.h>
26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32
33#include "new_dynarec_config.h"
34#include "../psxhle.h"
35#include "../psxinterpreter.h"
36#include "../gte.h"
37#include "emu_if.h" // emulator interface
38#include "arm_features.h"
39
40#define noinline __attribute__((noinline,noclone))
41#ifndef ARRAY_SIZE
42#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
43#endif
44#ifndef min
45#define min(a, b) ((b) < (a) ? (b) : (a))
46#endif
47#ifndef max
48#define max(a, b) ((b) > (a) ? (b) : (a))
49#endif
50
51//#define DISASM
52//#define ASSEM_PRINT
53//#define STAT_PRINT
54
55#ifdef ASSEM_PRINT
56#define assem_debug printf
57#else
58#define assem_debug(...)
59#endif
60//#define inv_debug printf
61#define inv_debug(...)
62
63#ifdef __i386__
64#include "assem_x86.h"
65#endif
66#ifdef __x86_64__
67#include "assem_x64.h"
68#endif
69#ifdef __arm__
70#include "assem_arm.h"
71#endif
72#ifdef __aarch64__
73#include "assem_arm64.h"
74#endif
75
76#define RAM_SIZE 0x200000
77#define MAXBLOCK 4096
78#define MAX_OUTPUT_BLOCK_SIZE 262144
79#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
80#define PAGE_COUNT 1024
81
82#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
83#define INVALIDATE_USE_COND_CALL
84#endif
85
86#ifdef VITA
87// apparently Vita has a 16MB limit, so either we cut tc in half,
88// or use this hack (it's a hack because tc size was designed to be power-of-2)
89#define TC_REDUCE_BYTES 4096
90#else
91#define TC_REDUCE_BYTES 0
92#endif
93
94struct ndrc_mem
95{
96 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
97 struct
98 {
99 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
100 const void *f[2048 / sizeof(void *)];
101 } tramp;
102};
103
104#ifdef BASE_ADDR_DYNAMIC
105static struct ndrc_mem *ndrc;
106#else
107static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
108static struct ndrc_mem *ndrc = &ndrc_;
109#endif
110
111// stubs
112enum stub_type {
113 CC_STUB = 1,
114 FP_STUB = 2,
115 LOADB_STUB = 3,
116 LOADH_STUB = 4,
117 LOADW_STUB = 5,
118 LOADD_STUB = 6,
119 LOADBU_STUB = 7,
120 LOADHU_STUB = 8,
121 STOREB_STUB = 9,
122 STOREH_STUB = 10,
123 STOREW_STUB = 11,
124 STORED_STUB = 12,
125 STORELR_STUB = 13,
126 INVCODE_STUB = 14,
127};
128
129// regmap_pre[i] - regs before [i] insn starts; dirty things here that
130// don't match .regmap will be written back
131// [i].regmap_entry - regs that must be set up if someone jumps here
132// [i].regmap - regs [i] insn will read/(over)write
133// branch_regs[i].* - same as above but for branches, takes delay slot into account
134struct regstat
135{
136 signed char regmap_entry[HOST_REGS];
137 signed char regmap[HOST_REGS];
138 uint64_t wasdirty;
139 uint64_t dirty;
140 uint64_t u;
141 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
142 u_int isconst; // ... but isconst is false when r2 is known
143 u_int loadedconst; // host regs that have constants loaded
144 u_int waswritten; // MIPS regs that were used as store base before
145};
146
147struct ht_entry
148{
149 u_int vaddr[2];
150 void *tcaddr[2];
151};
152
153struct code_stub
154{
155 enum stub_type type;
156 void *addr;
157 void *retaddr;
158 u_int a;
159 uintptr_t b;
160 uintptr_t c;
161 u_int d;
162 u_int e;
163};
164
165struct link_entry
166{
167 void *addr;
168 u_int target;
169 u_int internal;
170};
171
172struct block_info
173{
174 struct block_info *next;
175 const void *source;
176 const void *copy;
177 u_int start; // vaddr of the block start
178 u_int len; // of the whole block source
179 u_int tc_offs;
180 //u_int tc_len;
181 u_int reg_sv_flags;
182 u_char is_dirty;
183 u_char inv_near_misses;
184 u_short jump_in_cnt;
185 struct {
186 u_int vaddr;
187 void *addr;
188 } jump_in[0];
189};
190
191struct jump_info
192{
193 int alloc;
194 int count;
195 struct {
196 u_int target_vaddr;
197 void *stub;
198 } e[0];
199};
200
201static struct decoded_insn
202{
203 u_char itype;
204 u_char opcode;
205 u_char opcode2;
206 u_char rs1;
207 u_char rs2;
208 u_char rt1;
209 u_char rt2;
210 u_char use_lt1:1;
211 u_char bt:1;
212 u_char ooo:1;
213 u_char is_ds:1;
214 u_char is_jump:1;
215 u_char is_ujump:1;
216 u_char is_load:1;
217 u_char is_store:1;
218} dops[MAXBLOCK];
219
220 static u_char *out;
221 static struct ht_entry hash_table[65536];
222 static struct block_info *blocks[PAGE_COUNT];
223 static struct jump_info *jumps[PAGE_COUNT];
224 static u_int start;
225 static u_int *source;
226 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
227 static uint64_t gte_rt[MAXBLOCK];
228 static uint64_t gte_unneeded[MAXBLOCK];
229 static u_int smrv[32]; // speculated MIPS register values
230 static u_int smrv_strong; // mask or regs that are likely to have correct values
231 static u_int smrv_weak; // same, but somewhat less likely
232 static u_int smrv_strong_next; // same, but after current insn executes
233 static u_int smrv_weak_next;
234 static int imm[MAXBLOCK];
235 static u_int ba[MAXBLOCK];
236 static uint64_t unneeded_reg[MAXBLOCK];
237 static uint64_t branch_unneeded_reg[MAXBLOCK];
238 // see 'struct regstat' for a description
239 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
240 // contains 'real' consts at [i] insn, but may differ from what's actually
241 // loaded in host reg as 'final' value is always loaded, see get_final_value()
242 static uint32_t current_constmap[HOST_REGS];
243 static uint32_t constmap[MAXBLOCK][HOST_REGS];
244 static struct regstat regs[MAXBLOCK];
245 static struct regstat branch_regs[MAXBLOCK];
246 static signed char minimum_free_regs[MAXBLOCK];
247 static int ccadj[MAXBLOCK];
248 static int slen;
249 static void *instr_addr[MAXBLOCK];
250 static struct link_entry link_addr[MAXBLOCK];
251 static int linkcount;
252 static struct code_stub stubs[MAXBLOCK*3];
253 static int stubcount;
254 static u_int literals[1024][2];
255 static int literalcount;
256 static int is_delayslot;
257 static char shadow[1048576] __attribute__((aligned(16)));
258 static void *copy;
259 static u_int expirep;
260 static u_int stop_after_jal;
261 static u_int f1_hack;
262#ifdef STAT_PRINT
263 static int stat_bc_direct;
264 static int stat_bc_pre;
265 static int stat_bc_restore;
266 static int stat_ht_lookups;
267 static int stat_jump_in_lookups;
268 static int stat_restore_tries;
269 static int stat_restore_compares;
270 static int stat_inv_addr_calls;
271 static int stat_inv_hits;
272 static int stat_blocks;
273 static int stat_links;
274 #define stat_inc(s) s++
275 #define stat_dec(s) s--
276 #define stat_clear(s) s = 0
277#else
278 #define stat_inc(s)
279 #define stat_dec(s)
280 #define stat_clear(s)
281#endif
282
283 int new_dynarec_hacks;
284 int new_dynarec_hacks_pergame;
285 int new_dynarec_hacks_old;
286 int new_dynarec_did_compile;
287
288 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
289
290 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
291 extern int last_count; // last absolute target, often = next_interupt
292 extern int pcaddr;
293 extern int pending_exception;
294 extern int branch_target;
295 extern uintptr_t ram_offset;
296 extern uintptr_t mini_ht[32][2];
297
298 /* registers that may be allocated */
299 /* 1-31 gpr */
300#define LOREG 32 // lo
301#define HIREG 33 // hi
302//#define FSREG 34 // FPU status (FCSR)
303#define CSREG 35 // Coprocessor status
304#define CCREG 36 // Cycle count
305#define INVCP 37 // Pointer to invalid_code
306//#define MMREG 38 // Pointer to memory_map
307#define ROREG 39 // ram offset (if rdram!=0x80000000)
308#define TEMPREG 40
309#define FTEMP 40 // FPU temporary register
310#define PTEMP 41 // Prefetch temporary register
311//#define TLREG 42 // TLB mapping offset
312#define RHASH 43 // Return address hash
313#define RHTBL 44 // Return address hash table address
314#define RTEMP 45 // JR/JALR address register
315#define MAXREG 45
316#define AGEN1 46 // Address generation temporary register
317//#define AGEN2 47 // Address generation temporary register
318//#define MGEN1 48 // Maptable address generation temporary register
319//#define MGEN2 49 // Maptable address generation temporary register
320#define BTREG 50 // Branch target temporary register
321
322 /* instruction types */
323#define NOP 0 // No operation
324#define LOAD 1 // Load
325#define STORE 2 // Store
326#define LOADLR 3 // Unaligned load
327#define STORELR 4 // Unaligned store
328#define MOV 5 // Move
329#define ALU 6 // Arithmetic/logic
330#define MULTDIV 7 // Multiply/divide
331#define SHIFT 8 // Shift by register
332#define SHIFTIMM 9// Shift by immediate
333#define IMM16 10 // 16-bit immediate
334#define RJUMP 11 // Unconditional jump to register
335#define UJUMP 12 // Unconditional jump
336#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
337#define SJUMP 14 // Conditional branch (regimm format)
338#define COP0 15 // Coprocessor 0
339#define COP1 16 // Coprocessor 1
340#define C1LS 17 // Coprocessor 1 load/store
341//#define FJUMP 18 // Conditional branch (floating point)
342//#define FLOAT 19 // Floating point unit
343//#define FCONV 20 // Convert integer to float
344//#define FCOMP 21 // Floating point compare (sets FSREG)
345#define SYSCALL 22// SYSCALL,BREAK
346#define OTHER 23 // Other
347//#define SPAN 24 // Branch/delay slot spans 2 pages
348#define NI 25 // Not implemented
349#define HLECALL 26// PCSX fake opcodes for HLE
350#define COP2 27 // Coprocessor 2 move
351#define C2LS 28 // Coprocessor 2 load/store
352#define C2OP 29 // Coprocessor 2 operation
353#define INTCALL 30// Call interpreter to handle rare corner cases
354
355 /* branch codes */
356#define TAKEN 1
357#define NOTTAKEN 2
358#define NULLDS 3
359
360#define DJT_1 (void *)1l // no function, just a label in assem_debug log
361#define DJT_2 (void *)2l
362
363// asm linkage
364void dyna_linker();
365void cc_interrupt();
366void fp_exception();
367void fp_exception_ds();
368void jump_syscall (u_int u0, u_int u1, u_int pc);
369void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
370void jump_break (u_int u0, u_int u1, u_int pc);
371void jump_break_ds(u_int u0, u_int u1, u_int pc);
372void jump_to_new_pc();
373void call_gteStall();
374void new_dyna_leave();
375
376void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
377void *ndrc_get_addr_ht(u_int vaddr);
378void ndrc_invalidate_addr(u_int addr);
379void ndrc_add_jump_out(u_int vaddr, void *src);
380
381static int new_recompile_block(u_int addr);
382static void invalidate_block(struct block_info *block);
383
384// Needed by assembler
385static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
386static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
387static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
388static void load_all_regs(const signed char i_regmap[]);
389static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
390static void load_regs_entry(int t);
391static void load_all_consts(const signed char regmap[], u_int dirty, int i);
392static u_int get_host_reglist(const signed char *regmap);
393
394static int get_final_value(int hr, int i, int *value);
395static void add_stub(enum stub_type type, void *addr, void *retaddr,
396 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
397static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
398 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
399static void add_to_linker(void *addr, u_int target, int ext);
400static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
401 int addr, int *offset_reg, int *addr_reg_override);
402static void *get_direct_memhandler(void *table, u_int addr,
403 enum stub_type type, uintptr_t *addr_host);
404static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
405static void pass_args(int a0, int a1);
406static void emit_far_jump(const void *f);
407static void emit_far_call(const void *f);
408
409#ifdef VITA
410#include <psp2/kernel/sysmem.h>
411static int sceBlock;
412// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
413extern int getVMBlock();
414int _newlib_vm_size_user = sizeof(*ndrc);
415#endif
416
417static void mprotect_w_x(void *start, void *end, int is_x)
418{
419#ifdef NO_WRITE_EXEC
420 #if defined(VITA)
421 // *Open* enables write on all memory that was
422 // allocated by sceKernelAllocMemBlockForVM()?
423 if (is_x)
424 sceKernelCloseVMDomain();
425 else
426 sceKernelOpenVMDomain();
427 #else
428 u_long mstart = (u_long)start & ~4095ul;
429 u_long mend = (u_long)end;
430 if (mprotect((void *)mstart, mend - mstart,
431 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
432 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
433 #endif
434#endif
435}
436
437static void start_tcache_write(void *start, void *end)
438{
439 mprotect_w_x(start, end, 0);
440}
441
442static void end_tcache_write(void *start, void *end)
443{
444#if defined(__arm__) || defined(__aarch64__)
445 size_t len = (char *)end - (char *)start;
446 #if defined(__BLACKBERRY_QNX__)
447 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
448 #elif defined(__MACH__)
449 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
450 #elif defined(VITA)
451 sceKernelSyncVMDomain(sceBlock, start, len);
452 #elif defined(_3DS)
453 ctr_flush_invalidate_cache();
454 #elif defined(__aarch64__)
455 // as of 2021, __clear_cache() is still broken on arm64
456 // so here is a custom one :(
457 clear_cache_arm64(start, end);
458 #else
459 __clear_cache(start, end);
460 #endif
461 (void)len;
462#endif
463
464 mprotect_w_x(start, end, 1);
465}
466
467static void *start_block(void)
468{
469 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
470 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
471 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
472 start_tcache_write(out, end);
473 return out;
474}
475
476static void end_block(void *start)
477{
478 end_tcache_write(start, out);
479}
480
481// also takes care of w^x mappings when patching code
482static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
483
484static void mark_clear_cache(void *target)
485{
486 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
487 u_int mask = 1u << ((offset >> 12) & 31);
488 if (!(needs_clear_cache[offset >> 17] & mask)) {
489 char *start = (char *)((uintptr_t)target & ~4095l);
490 start_tcache_write(start, start + 4095);
491 needs_clear_cache[offset >> 17] |= mask;
492 }
493}
494
495// Clearing the cache is rather slow on ARM Linux, so mark the areas
496// that need to be cleared, and then only clear these areas once.
497static void do_clear_cache(void)
498{
499 int i, j;
500 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
501 {
502 u_int bitmap = needs_clear_cache[i];
503 if (!bitmap)
504 continue;
505 for (j = 0; j < 32; j++)
506 {
507 u_char *start, *end;
508 if (!(bitmap & (1u << j)))
509 continue;
510
511 start = ndrc->translation_cache + i*131072 + j*4096;
512 end = start + 4095;
513 for (j++; j < 32; j++) {
514 if (!(bitmap & (1u << j)))
515 break;
516 end += 4096;
517 }
518 end_tcache_write(start, end);
519 }
520 needs_clear_cache[i] = 0;
521 }
522}
523
524//#define DEBUG_CYCLE_COUNT 1
525
526#define NO_CYCLE_PENALTY_THR 12
527
528int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
529int cycle_multiplier_override;
530int cycle_multiplier_old;
531static int cycle_multiplier_active;
532
533static int CLOCK_ADJUST(int x)
534{
535 int m = cycle_multiplier_active;
536 int s = (x >> 31) | 1;
537 return (x * m + s * 50) / 100;
538}
539
540static int ds_writes_rjump_rs(int i)
541{
542 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
543}
544
545// psx addr mirror masking (for invalidation)
546static u_int pmmask(u_int vaddr)
547{
548 vaddr &= ~0xe0000000;
549 if (vaddr < 0x01000000)
550 vaddr &= ~0x00e00000; // RAM mirrors
551 return vaddr;
552}
553
554static u_int get_page(u_int vaddr)
555{
556 u_int page = pmmask(vaddr) >> 12;
557 if (page >= PAGE_COUNT / 2)
558 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
559 return page;
560}
561
562// get a page for looking for a block that has vaddr
563// (needed because the block may start in previous page)
564static u_int get_page_prev(u_int vaddr)
565{
566 assert(MAXBLOCK <= (1 << 12));
567 u_int page = get_page(vaddr);
568 if (page & 511)
569 page--;
570 return page;
571}
572
573static struct ht_entry *hash_table_get(u_int vaddr)
574{
575 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
576}
577
578static void hash_table_add(u_int vaddr, void *tcaddr)
579{
580 struct ht_entry *ht_bin = hash_table_get(vaddr);
581 assert(tcaddr);
582 ht_bin->vaddr[1] = ht_bin->vaddr[0];
583 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
584 ht_bin->vaddr[0] = vaddr;
585 ht_bin->tcaddr[0] = tcaddr;
586}
587
588static void hash_table_remove(int vaddr)
589{
590 //printf("remove hash: %x\n",vaddr);
591 struct ht_entry *ht_bin = hash_table_get(vaddr);
592 if (ht_bin->vaddr[1] == vaddr) {
593 ht_bin->vaddr[1] = -1;
594 ht_bin->tcaddr[1] = NULL;
595 }
596 if (ht_bin->vaddr[0] == vaddr) {
597 ht_bin->vaddr[0] = ht_bin->vaddr[1];
598 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
599 ht_bin->vaddr[1] = -1;
600 ht_bin->tcaddr[1] = NULL;
601 }
602}
603
604static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
605{
606 u_int i, j;
607 vaddr &= 0x1fffffff;
608 for (i = vaddr & ~0xfff; i < vaddr + len; i += 0x1000) {
609 // ram mirrors, but should not hurt bios
610 for (j = 0; j < 0x800000; j += 0x200000) {
611 invalid_code[(i|j) >> 12] =
612 invalid_code[(i|j|0x80000000u) >> 12] =
613 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
614 }
615 }
616 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
617 inv_code_start = inv_code_end = ~0;
618}
619
620static int doesnt_expire_soon(u_char *tcaddr)
621{
622 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
623 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
624}
625
626static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
627{
628 void *found_clean = NULL;
629 u_int i, page;
630
631 stat_inc(stat_restore_tries);
632 for (page = start_page; page <= end_page; page++) {
633 struct block_info *block;
634 for (block = blocks[page]; block != NULL; block = block->next) {
635 if (vaddr < block->start)
636 break;
637 if (!block->is_dirty || vaddr >= block->start + block->len)
638 continue;
639 for (i = 0; i < block->jump_in_cnt; i++)
640 if (block->jump_in[i].vaddr == vaddr)
641 break;
642 if (i == block->jump_in_cnt)
643 continue;
644 assert(block->source && block->copy);
645 stat_inc(stat_restore_compares);
646 if (memcmp(block->source, block->copy, block->len))
647 continue;
648
649 block->is_dirty = block->inv_near_misses = 0;
650 found_clean = block->jump_in[i].addr;
651 hash_table_add(vaddr, found_clean);
652 mark_invalid_code(block->start, block->len, 0);
653 stat_inc(stat_bc_restore);
654 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
655 return found_clean;
656 }
657 }
658 return NULL;
659}
660
661// Get address from virtual address
662// This is called from the recompiled JR/JALR instructions
663static void noinline *get_addr(u_int vaddr, int can_compile)
664{
665 u_int start_page = get_page_prev(vaddr);
666 u_int i, page, end_page = get_page(vaddr);
667 void *found_clean = NULL;
668
669 stat_inc(stat_jump_in_lookups);
670 for (page = start_page; page <= end_page; page++) {
671 const struct block_info *block;
672 for (block = blocks[page]; block != NULL; block = block->next) {
673 if (vaddr < block->start)
674 break;
675 if (block->is_dirty || vaddr >= block->start + block->len)
676 continue;
677 for (i = 0; i < block->jump_in_cnt; i++)
678 if (block->jump_in[i].vaddr == vaddr)
679 break;
680 if (i == block->jump_in_cnt)
681 continue;
682 found_clean = block->jump_in[i].addr;
683 hash_table_add(vaddr, found_clean);
684 return found_clean;
685 }
686 }
687 found_clean = try_restore_block(vaddr, start_page, end_page);
688 if (found_clean)
689 return found_clean;
690
691 if (!can_compile)
692 return NULL;
693
694 int r = new_recompile_block(vaddr);
695 if (r == 0)
696 return ndrc_get_addr_ht(vaddr);
697
698 // generate an address error
699 Status|=2;
700 Cause=(vaddr<<31)|(4<<2);
701 EPC=(vaddr&1)?vaddr-5:vaddr;
702 BadVAddr=(vaddr&~1);
703 return ndrc_get_addr_ht(0x80000080);
704}
705
706// Look up address in hash table first
707void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
708{
709 const struct ht_entry *ht_bin = hash_table_get(vaddr);
710 stat_inc(stat_ht_lookups);
711 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
712 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
713 return get_addr(vaddr, can_compile);
714}
715
716void *ndrc_get_addr_ht(u_int vaddr)
717{
718 return ndrc_get_addr_ht_param(vaddr, 1);
719}
720
721static void clear_all_regs(signed char regmap[])
722{
723 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
724}
725
726// get_reg: get allocated host reg from mips reg
727// returns -1 if no such mips reg was allocated
728#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
729
730extern signed char get_reg(const signed char regmap[], signed char r);
731
732#else
733
734static signed char get_reg(const signed char regmap[], signed char r)
735{
736 int hr;
737 for (hr = 0; hr < HOST_REGS; hr++) {
738 if (hr == EXCLUDE_REG)
739 continue;
740 if (regmap[hr] == r)
741 return hr;
742 }
743 return -1;
744}
745
746#endif
747
748// get reg as mask bit (1 << hr)
749static u_int get_regm(const signed char regmap[], signed char r)
750{
751 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
752}
753
754static signed char get_reg_temp(const signed char regmap[])
755{
756 int hr;
757 for (hr = 0; hr < HOST_REGS; hr++) {
758 if (hr == EXCLUDE_REG)
759 continue;
760 if (regmap[hr] == (signed char)-1)
761 return hr;
762 }
763 return -1;
764}
765
766// Find a register that is available for two consecutive cycles
767static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
768{
769 int hr;
770 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
771 return -1;
772}
773
774// reverse reg map: mips -> host
775#define RRMAP_SIZE 64
776static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
777 u_int *regs_can_change)
778{
779 u_int r, hr, hr_can_change = 0;
780 memset(rrmap, -1, RRMAP_SIZE);
781 for (hr = 0; hr < HOST_REGS; )
782 {
783 r = regmap[hr];
784 rrmap[r & (RRMAP_SIZE - 1)] = hr;
785 // only add mips $1-$31+$lo, others shifted out
786 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
787 hr++;
788 if (hr == EXCLUDE_REG)
789 hr++;
790 }
791 hr_can_change |= 1u << (rrmap[33] & 31);
792 hr_can_change |= 1u << (rrmap[CCREG] & 31);
793 hr_can_change &= ~(1u << 31);
794 *regs_can_change = hr_can_change;
795}
796
797// same as get_reg, but takes rrmap
798static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
799{
800 assert(0 <= r && r < RRMAP_SIZE);
801 return rrmap[r];
802}
803
804static int count_free_regs(const signed char regmap[])
805{
806 int count=0;
807 int hr;
808 for(hr=0;hr<HOST_REGS;hr++)
809 {
810 if(hr!=EXCLUDE_REG) {
811 if(regmap[hr]<0) count++;
812 }
813 }
814 return count;
815}
816
817static void dirty_reg(struct regstat *cur, signed char reg)
818{
819 int hr;
820 if (!reg) return;
821 hr = get_reg(cur->regmap, reg);
822 if (hr >= 0)
823 cur->dirty |= 1<<hr;
824}
825
826static void set_const(struct regstat *cur, signed char reg, uint32_t value)
827{
828 int hr;
829 if (!reg) return;
830 hr = get_reg(cur->regmap, reg);
831 if (hr >= 0) {
832 cur->isconst |= 1<<hr;
833 current_constmap[hr] = value;
834 }
835}
836
837static void clear_const(struct regstat *cur, signed char reg)
838{
839 int hr;
840 if (!reg) return;
841 hr = get_reg(cur->regmap, reg);
842 if (hr >= 0)
843 cur->isconst &= ~(1<<hr);
844}
845
846static int is_const(const struct regstat *cur, signed char reg)
847{
848 int hr;
849 if (reg < 0) return 0;
850 if (!reg) return 1;
851 hr = get_reg(cur->regmap, reg);
852 if (hr >= 0)
853 return (cur->isconst>>hr)&1;
854 return 0;
855}
856
857static uint32_t get_const(const struct regstat *cur, signed char reg)
858{
859 int hr;
860 if (!reg) return 0;
861 hr = get_reg(cur->regmap, reg);
862 if (hr >= 0)
863 return current_constmap[hr];
864
865 SysPrintf("Unknown constant in r%d\n", reg);
866 abort();
867}
868
869// Least soon needed registers
870// Look at the next ten instructions and see which registers
871// will be used. Try not to reallocate these.
872static void lsn(u_char hsn[], int i, int *preferred_reg)
873{
874 int j;
875 int b=-1;
876 for(j=0;j<9;j++)
877 {
878 if(i+j>=slen) {
879 j=slen-i-1;
880 break;
881 }
882 if (dops[i+j].is_ujump)
883 {
884 // Don't go past an unconditonal jump
885 j++;
886 break;
887 }
888 }
889 for(;j>=0;j--)
890 {
891 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
892 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
893 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
894 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
895 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
896 // Stores can allocate zero
897 hsn[dops[i+j].rs1]=j;
898 hsn[dops[i+j].rs2]=j;
899 }
900 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
901 hsn[ROREG] = j;
902 // On some architectures stores need invc_ptr
903 #if defined(HOST_IMM8)
904 if (dops[i+j].is_store)
905 hsn[INVCP] = j;
906 #endif
907 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
908 {
909 hsn[CCREG]=j;
910 b=j;
911 }
912 }
913 if(b>=0)
914 {
915 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
916 {
917 // Follow first branch
918 int t=(ba[i+b]-start)>>2;
919 j=7-b;if(t+j>=slen) j=slen-t-1;
920 for(;j>=0;j--)
921 {
922 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
923 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
924 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
925 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
926 }
927 }
928 // TODO: preferred register based on backward branch
929 }
930 // Delay slot should preferably not overwrite branch conditions or cycle count
931 if (i > 0 && dops[i-1].is_jump) {
932 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
933 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
934 hsn[CCREG]=1;
935 // ...or hash tables
936 hsn[RHASH]=1;
937 hsn[RHTBL]=1;
938 }
939 // Coprocessor load/store needs FTEMP, even if not declared
940 if(dops[i].itype==C2LS) {
941 hsn[FTEMP]=0;
942 }
943 // Load L/R also uses FTEMP as a temporary register
944 if(dops[i].itype==LOADLR) {
945 hsn[FTEMP]=0;
946 }
947 // Also SWL/SWR/SDL/SDR
948 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
949 hsn[FTEMP]=0;
950 }
951 // Don't remove the miniht registers
952 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
953 {
954 hsn[RHASH]=0;
955 hsn[RHTBL]=0;
956 }
957}
958
959// We only want to allocate registers if we're going to use them again soon
960static int needed_again(int r, int i)
961{
962 int j;
963 int b=-1;
964 int rn=10;
965
966 if (i > 0 && dops[i-1].is_ujump)
967 {
968 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
969 return 0; // Don't need any registers if exiting the block
970 }
971 for(j=0;j<9;j++)
972 {
973 if(i+j>=slen) {
974 j=slen-i-1;
975 break;
976 }
977 if (dops[i+j].is_ujump)
978 {
979 // Don't go past an unconditonal jump
980 j++;
981 break;
982 }
983 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
984 {
985 break;
986 }
987 }
988 for(;j>=1;j--)
989 {
990 if(dops[i+j].rs1==r) rn=j;
991 if(dops[i+j].rs2==r) rn=j;
992 if((unneeded_reg[i+j]>>r)&1) rn=10;
993 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
994 {
995 b=j;
996 }
997 }
998 if(rn<10) return 1;
999 (void)b;
1000 return 0;
1001}
1002
1003// Try to match register allocations at the end of a loop with those
1004// at the beginning
1005static int loop_reg(int i, int r, int hr)
1006{
1007 int j,k;
1008 for(j=0;j<9;j++)
1009 {
1010 if(i+j>=slen) {
1011 j=slen-i-1;
1012 break;
1013 }
1014 if (dops[i+j].is_ujump)
1015 {
1016 // Don't go past an unconditonal jump
1017 j++;
1018 break;
1019 }
1020 }
1021 k=0;
1022 if(i>0){
1023 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1024 k--;
1025 }
1026 for(;k<j;k++)
1027 {
1028 assert(r < 64);
1029 if((unneeded_reg[i+k]>>r)&1) return hr;
1030 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1031 {
1032 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
1033 {
1034 int t=(ba[i+k]-start)>>2;
1035 int reg=get_reg(regs[t].regmap_entry,r);
1036 if(reg>=0) return reg;
1037 //reg=get_reg(regs[t+1].regmap_entry,r);
1038 //if(reg>=0) return reg;
1039 }
1040 }
1041 }
1042 return hr;
1043}
1044
1045
1046// Allocate every register, preserving source/target regs
1047static void alloc_all(struct regstat *cur,int i)
1048{
1049 int hr;
1050
1051 for(hr=0;hr<HOST_REGS;hr++) {
1052 if(hr!=EXCLUDE_REG) {
1053 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1054 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1055 {
1056 cur->regmap[hr]=-1;
1057 cur->dirty&=~(1<<hr);
1058 }
1059 // Don't need zeros
1060 if(cur->regmap[hr]==0)
1061 {
1062 cur->regmap[hr]=-1;
1063 cur->dirty&=~(1<<hr);
1064 }
1065 }
1066 }
1067}
1068
1069#ifndef NDEBUG
1070static int host_tempreg_in_use;
1071
1072static void host_tempreg_acquire(void)
1073{
1074 assert(!host_tempreg_in_use);
1075 host_tempreg_in_use = 1;
1076}
1077
1078static void host_tempreg_release(void)
1079{
1080 host_tempreg_in_use = 0;
1081}
1082#else
1083static void host_tempreg_acquire(void) {}
1084static void host_tempreg_release(void) {}
1085#endif
1086
1087#ifdef ASSEM_PRINT
1088extern void gen_interupt();
1089extern void do_insn_cmp();
1090#define FUNCNAME(f) { f, " " #f }
1091static const struct {
1092 void *addr;
1093 const char *name;
1094} function_names[] = {
1095 FUNCNAME(cc_interrupt),
1096 FUNCNAME(gen_interupt),
1097 FUNCNAME(ndrc_get_addr_ht),
1098 FUNCNAME(jump_handler_read8),
1099 FUNCNAME(jump_handler_read16),
1100 FUNCNAME(jump_handler_read32),
1101 FUNCNAME(jump_handler_write8),
1102 FUNCNAME(jump_handler_write16),
1103 FUNCNAME(jump_handler_write32),
1104 FUNCNAME(ndrc_invalidate_addr),
1105 FUNCNAME(jump_to_new_pc),
1106 FUNCNAME(jump_break),
1107 FUNCNAME(jump_break_ds),
1108 FUNCNAME(jump_syscall),
1109 FUNCNAME(jump_syscall_ds),
1110 FUNCNAME(call_gteStall),
1111 FUNCNAME(new_dyna_leave),
1112 FUNCNAME(pcsx_mtc0),
1113 FUNCNAME(pcsx_mtc0_ds),
1114#ifdef DRC_DBG
1115 FUNCNAME(do_insn_cmp),
1116#endif
1117};
1118
1119static const char *func_name(const void *a)
1120{
1121 int i;
1122 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1123 if (function_names[i].addr == a)
1124 return function_names[i].name;
1125 return "";
1126}
1127#else
1128#define func_name(x) ""
1129#endif
1130
1131#ifdef __i386__
1132#include "assem_x86.c"
1133#endif
1134#ifdef __x86_64__
1135#include "assem_x64.c"
1136#endif
1137#ifdef __arm__
1138#include "assem_arm.c"
1139#endif
1140#ifdef __aarch64__
1141#include "assem_arm64.c"
1142#endif
1143
1144static void *get_trampoline(const void *f)
1145{
1146 size_t i;
1147
1148 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
1149 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
1150 break;
1151 }
1152 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
1153 SysPrintf("trampoline table is full, last func %p\n", f);
1154 abort();
1155 }
1156 if (ndrc->tramp.f[i] == NULL) {
1157 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1158 ndrc->tramp.f[i] = f;
1159 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
1160 }
1161 return &ndrc->tramp.ops[i];
1162}
1163
1164static void emit_far_jump(const void *f)
1165{
1166 if (can_jump_or_call(f)) {
1167 emit_jmp(f);
1168 return;
1169 }
1170
1171 f = get_trampoline(f);
1172 emit_jmp(f);
1173}
1174
1175static void emit_far_call(const void *f)
1176{
1177 if (can_jump_or_call(f)) {
1178 emit_call(f);
1179 return;
1180 }
1181
1182 f = get_trampoline(f);
1183 emit_call(f);
1184}
1185
1186// Check if an address is already compiled
1187// but don't return addresses which are about to expire from the cache
1188static void *check_addr(u_int vaddr)
1189{
1190 struct ht_entry *ht_bin = hash_table_get(vaddr);
1191 size_t i;
1192 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1193 if (ht_bin->vaddr[i] == vaddr)
1194 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1195 return ht_bin->tcaddr[i];
1196 }
1197
1198 // refactor to get_addr_nocompile?
1199 u_int start_page = get_page_prev(vaddr);
1200 u_int page, end_page = get_page(vaddr);
1201
1202 stat_inc(stat_jump_in_lookups);
1203 for (page = start_page; page <= end_page; page++) {
1204 const struct block_info *block;
1205 for (block = blocks[page]; block != NULL; block = block->next) {
1206 if (vaddr < block->start)
1207 break;
1208 if (block->is_dirty || vaddr >= block->start + block->len)
1209 continue;
1210 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1211 continue;
1212 for (i = 0; i < block->jump_in_cnt; i++)
1213 if (block->jump_in[i].vaddr == vaddr)
1214 break;
1215 if (i == block->jump_in_cnt)
1216 continue;
1217
1218 // Update existing entry with current address
1219 void *addr = block->jump_in[i].addr;
1220 if (ht_bin->vaddr[0] == vaddr) {
1221 ht_bin->tcaddr[0] = addr;
1222 return addr;
1223 }
1224 if (ht_bin->vaddr[1] == vaddr) {
1225 ht_bin->tcaddr[1] = addr;
1226 return addr;
1227 }
1228 // Insert into hash table with low priority.
1229 // Don't evict existing entries, as they are probably
1230 // addresses that are being accessed frequently.
1231 if (ht_bin->vaddr[0] == -1) {
1232 ht_bin->vaddr[0] = vaddr;
1233 ht_bin->tcaddr[0] = addr;
1234 }
1235 else if (ht_bin->vaddr[1] == -1) {
1236 ht_bin->vaddr[1] = vaddr;
1237 ht_bin->tcaddr[1] = addr;
1238 }
1239 return addr;
1240 }
1241 }
1242 return NULL;
1243}
1244
1245static void blocks_clear(struct block_info **head)
1246{
1247 struct block_info *cur, *next;
1248
1249 if ((cur = *head)) {
1250 *head = NULL;
1251 while (cur) {
1252 next = cur->next;
1253 free(cur);
1254 cur = next;
1255 }
1256 }
1257}
1258
1259static int blocks_remove_matching_addrs(struct block_info **head,
1260 u_int base_offs, int shift)
1261{
1262 struct block_info *next;
1263 int hit = 0;
1264 while (*head) {
1265 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1266 inv_debug("EXP: rm block %08x (tc_offs %zx)\n", (*head)->start, (*head)->tc_offs);
1267 invalidate_block(*head);
1268 next = (*head)->next;
1269 free(*head);
1270 *head = next;
1271 stat_dec(stat_blocks);
1272 hit = 1;
1273 }
1274 else
1275 {
1276 head = &((*head)->next);
1277 }
1278 }
1279 return hit;
1280}
1281
1282// This is called when we write to a compiled block (see do_invstub)
1283static void unlink_jumps_vaddr_range(u_int start, u_int end)
1284{
1285 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1286 int i;
1287
1288 for (page = start_page; page <= end_page; page++) {
1289 struct jump_info *ji = jumps[page];
1290 if (ji == NULL)
1291 continue;
1292 for (i = 0; i < ji->count; ) {
1293 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1294 i++;
1295 continue;
1296 }
1297
1298 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1299 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1300 void *host_addr = find_extjump_insn(ji->e[i].stub);
1301 mark_clear_cache(host_addr);
1302 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1303
1304 stat_dec(stat_links);
1305 ji->count--;
1306 if (i < ji->count) {
1307 ji->e[i] = ji->e[ji->count];
1308 continue;
1309 }
1310 i++;
1311 }
1312 }
1313}
1314
1315static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1316{
1317 int i;
1318 if (ji == NULL)
1319 return;
1320 for (i = 0; i < ji->count; ) {
1321 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1322 if (((tc_offs ^ base_offs) >> shift) != 0) {
1323 i++;
1324 continue;
1325 }
1326
1327 inv_debug("EXP: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, tc_offs);
1328 stat_dec(stat_links);
1329 ji->count--;
1330 if (i < ji->count) {
1331 ji->e[i] = ji->e[ji->count];
1332 continue;
1333 }
1334 i++;
1335 }
1336}
1337
1338static void invalidate_block(struct block_info *block)
1339{
1340 u_int i;
1341
1342 block->is_dirty = 1;
1343 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1344 for (i = 0; i < block->jump_in_cnt; i++)
1345 hash_table_remove(block->jump_in[i].vaddr);
1346}
1347
1348static int invalidate_range(u_int start, u_int end,
1349 u32 *inv_start_ret, u32 *inv_end_ret)
1350{
1351 struct block_info *last_block = NULL;
1352 u_int start_page = get_page_prev(start);
1353 u_int end_page = get_page(end - 1);
1354 u_int start_m = pmmask(start);
1355 u_int end_m = pmmask(end);
1356 u_int inv_start, inv_end;
1357 u_int blk_start_m, blk_end_m;
1358 u_int page;
1359 int hit = 0;
1360
1361 // additional area without code (to supplement invalid_code[]), [start, end)
1362 // avoids excessive ndrc_invalidate_addr() calls
1363 inv_start = start_m & ~0xfff;
1364 inv_end = end_m | 0xfff;
1365
1366 for (page = start_page; page <= end_page; page++) {
1367 struct block_info *block;
1368 for (block = blocks[page]; block != NULL; block = block->next) {
1369 if (block->is_dirty)
1370 continue;
1371 last_block = block;
1372 blk_end_m = pmmask(block->start + block->len);
1373 if (blk_end_m <= start_m) {
1374 inv_start = max(inv_start, blk_end_m);
1375 continue;
1376 }
1377 blk_start_m = pmmask(block->start);
1378 if (end_m <= blk_start_m) {
1379 inv_end = min(inv_end, blk_start_m - 1);
1380 continue;
1381 }
1382 if (!block->source) // "hack" block - leave it alone
1383 continue;
1384
1385 hit++;
1386 invalidate_block(block);
1387 stat_inc(stat_inv_hits);
1388 }
1389 }
1390
1391 if (!hit && last_block && last_block->source) {
1392 // could be some leftover unused block, uselessly trapping writes
1393 last_block->inv_near_misses++;
1394 if (last_block->inv_near_misses > 128) {
1395 invalidate_block(last_block);
1396 stat_inc(stat_inv_hits);
1397 hit++;
1398 }
1399 }
1400 if (hit) {
1401 do_clear_cache();
1402#ifdef USE_MINI_HT
1403 memset(mini_ht, -1, sizeof(mini_ht));
1404#endif
1405 }
1406
1407 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1408 // the whole page is empty now
1409 mark_invalid_code(start, 1, 1);
1410
1411 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1412 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1413 return hit;
1414}
1415
1416void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1417{
1418 invalidate_range(start, end, NULL, NULL);
1419}
1420
1421void ndrc_invalidate_addr(u_int addr)
1422{
1423 // this check is done by the caller
1424 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1425 int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end);
1426 if (ret)
1427 inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret);
1428 else
1429 inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end);
1430 stat_inc(stat_inv_addr_calls);
1431}
1432
1433// This is called when loading a save state.
1434// Anything could have changed, so invalidate everything.
1435void new_dynarec_invalidate_all_pages(void)
1436{
1437 struct block_info *block;
1438 u_int page;
1439 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1440 for (block = blocks[page]; block != NULL; block = block->next) {
1441 if (block->is_dirty)
1442 continue;
1443 if (!block->source) // hack block?
1444 continue;
1445 invalidate_block(block);
1446 }
1447 }
1448
1449 #ifdef USE_MINI_HT
1450 memset(mini_ht, -1, sizeof(mini_ht));
1451 #endif
1452 do_clear_cache();
1453}
1454
1455static void do_invstub(int n)
1456{
1457 literal_pool(20);
1458 u_int reglist = stubs[n].a;
1459 set_jump_target(stubs[n].addr, out);
1460 save_regs(reglist);
1461 if (stubs[n].b != 0)
1462 emit_mov(stubs[n].b, 0);
1463 emit_readword(&inv_code_start, 1);
1464 emit_readword(&inv_code_end, 2);
1465 emit_cmp(0, 1);
1466 emit_cmpcs(2, 0);
1467 void *jaddr = out;
1468 emit_jc(0);
1469 emit_far_call(ndrc_invalidate_addr);
1470 set_jump_target(jaddr, out);
1471 restore_regs(reglist);
1472 emit_jmp(stubs[n].retaddr); // return address
1473}
1474
1475// Add an entry to jump_out after making a link
1476// src should point to code by emit_extjump()
1477void ndrc_add_jump_out(u_int vaddr, void *src)
1478{
1479 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1480 u_int page = get_page(vaddr);
1481 struct jump_info *ji;
1482
1483 stat_inc(stat_links);
1484 check_extjump2(src);
1485 ji = jumps[page];
1486 if (ji == NULL) {
1487 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1488 ji->alloc = 16;
1489 ji->count = 0;
1490 }
1491 else if (ji->count >= ji->alloc) {
1492 ji->alloc += 16;
1493 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1494 }
1495 jumps[page] = ji;
1496 ji->e[ji->count].target_vaddr = vaddr;
1497 ji->e[ji->count].stub = src;
1498 ji->count++;
1499}
1500
1501/* Register allocation */
1502
1503// Note: registers are allocated clean (unmodified state)
1504// if you intend to modify the register, you must call dirty_reg().
1505static void alloc_reg(struct regstat *cur,int i,signed char reg)
1506{
1507 int r,hr;
1508 int preferred_reg = PREFERRED_REG_FIRST
1509 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1510 if (reg == CCREG) preferred_reg = HOST_CCREG;
1511 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1512 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1513 assert(reg >= 0);
1514
1515 // Don't allocate unused registers
1516 if((cur->u>>reg)&1) return;
1517
1518 // see if it's already allocated
1519 if (get_reg(cur->regmap, reg) >= 0)
1520 return;
1521
1522 // Keep the same mapping if the register was already allocated in a loop
1523 preferred_reg = loop_reg(i,reg,preferred_reg);
1524
1525 // Try to allocate the preferred register
1526 if(cur->regmap[preferred_reg]==-1) {
1527 cur->regmap[preferred_reg]=reg;
1528 cur->dirty&=~(1<<preferred_reg);
1529 cur->isconst&=~(1<<preferred_reg);
1530 return;
1531 }
1532 r=cur->regmap[preferred_reg];
1533 assert(r < 64);
1534 if((cur->u>>r)&1) {
1535 cur->regmap[preferred_reg]=reg;
1536 cur->dirty&=~(1<<preferred_reg);
1537 cur->isconst&=~(1<<preferred_reg);
1538 return;
1539 }
1540
1541 // Clear any unneeded registers
1542 // We try to keep the mapping consistent, if possible, because it
1543 // makes branches easier (especially loops). So we try to allocate
1544 // first (see above) before removing old mappings. If this is not
1545 // possible then go ahead and clear out the registers that are no
1546 // longer needed.
1547 for(hr=0;hr<HOST_REGS;hr++)
1548 {
1549 r=cur->regmap[hr];
1550 if(r>=0) {
1551 assert(r < 64);
1552 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1553 }
1554 }
1555
1556 // Try to allocate any available register, but prefer
1557 // registers that have not been used recently.
1558 if (i > 0) {
1559 for (hr = PREFERRED_REG_FIRST; ; ) {
1560 if (cur->regmap[hr] < 0) {
1561 int oldreg = regs[i-1].regmap[hr];
1562 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1563 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1564 {
1565 cur->regmap[hr]=reg;
1566 cur->dirty&=~(1<<hr);
1567 cur->isconst&=~(1<<hr);
1568 return;
1569 }
1570 }
1571 hr++;
1572 if (hr == EXCLUDE_REG)
1573 hr++;
1574 if (hr == HOST_REGS)
1575 hr = 0;
1576 if (hr == PREFERRED_REG_FIRST)
1577 break;
1578 }
1579 }
1580
1581 // Try to allocate any available register
1582 for (hr = PREFERRED_REG_FIRST; ; ) {
1583 if (cur->regmap[hr] < 0) {
1584 cur->regmap[hr]=reg;
1585 cur->dirty&=~(1<<hr);
1586 cur->isconst&=~(1<<hr);
1587 return;
1588 }
1589 hr++;
1590 if (hr == EXCLUDE_REG)
1591 hr++;
1592 if (hr == HOST_REGS)
1593 hr = 0;
1594 if (hr == PREFERRED_REG_FIRST)
1595 break;
1596 }
1597
1598 // Ok, now we have to evict someone
1599 // Pick a register we hopefully won't need soon
1600 u_char hsn[MAXREG+1];
1601 memset(hsn,10,sizeof(hsn));
1602 int j;
1603 lsn(hsn,i,&preferred_reg);
1604 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1605 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1606 if(i>0) {
1607 // Don't evict the cycle count at entry points, otherwise the entry
1608 // stub will have to write it.
1609 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1610 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1611 for(j=10;j>=3;j--)
1612 {
1613 // Alloc preferred register if available
1614 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1615 for(hr=0;hr<HOST_REGS;hr++) {
1616 // Evict both parts of a 64-bit register
1617 if(cur->regmap[hr]==r) {
1618 cur->regmap[hr]=-1;
1619 cur->dirty&=~(1<<hr);
1620 cur->isconst&=~(1<<hr);
1621 }
1622 }
1623 cur->regmap[preferred_reg]=reg;
1624 return;
1625 }
1626 for(r=1;r<=MAXREG;r++)
1627 {
1628 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1629 for(hr=0;hr<HOST_REGS;hr++) {
1630 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1631 if(cur->regmap[hr]==r) {
1632 cur->regmap[hr]=reg;
1633 cur->dirty&=~(1<<hr);
1634 cur->isconst&=~(1<<hr);
1635 return;
1636 }
1637 }
1638 }
1639 }
1640 }
1641 }
1642 }
1643 for(j=10;j>=0;j--)
1644 {
1645 for(r=1;r<=MAXREG;r++)
1646 {
1647 if(hsn[r]==j) {
1648 for(hr=0;hr<HOST_REGS;hr++) {
1649 if(cur->regmap[hr]==r) {
1650 cur->regmap[hr]=reg;
1651 cur->dirty&=~(1<<hr);
1652 cur->isconst&=~(1<<hr);
1653 return;
1654 }
1655 }
1656 }
1657 }
1658 }
1659 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1660}
1661
1662// Allocate a temporary register. This is done without regard to
1663// dirty status or whether the register we request is on the unneeded list
1664// Note: This will only allocate one register, even if called multiple times
1665static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1666{
1667 int r,hr;
1668 int preferred_reg = -1;
1669
1670 // see if it's already allocated
1671 for(hr=0;hr<HOST_REGS;hr++)
1672 {
1673 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1674 }
1675
1676 // Try to allocate any available register
1677 for(hr=HOST_REGS-1;hr>=0;hr--) {
1678 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1679 cur->regmap[hr]=reg;
1680 cur->dirty&=~(1<<hr);
1681 cur->isconst&=~(1<<hr);
1682 return;
1683 }
1684 }
1685
1686 // Find an unneeded register
1687 for(hr=HOST_REGS-1;hr>=0;hr--)
1688 {
1689 r=cur->regmap[hr];
1690 if(r>=0) {
1691 assert(r < 64);
1692 if((cur->u>>r)&1) {
1693 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1694 cur->regmap[hr]=reg;
1695 cur->dirty&=~(1<<hr);
1696 cur->isconst&=~(1<<hr);
1697 return;
1698 }
1699 }
1700 }
1701 }
1702
1703 // Ok, now we have to evict someone
1704 // Pick a register we hopefully won't need soon
1705 // TODO: we might want to follow unconditional jumps here
1706 // TODO: get rid of dupe code and make this into a function
1707 u_char hsn[MAXREG+1];
1708 memset(hsn,10,sizeof(hsn));
1709 int j;
1710 lsn(hsn,i,&preferred_reg);
1711 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1712 if(i>0) {
1713 // Don't evict the cycle count at entry points, otherwise the entry
1714 // stub will have to write it.
1715 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1716 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1717 for(j=10;j>=3;j--)
1718 {
1719 for(r=1;r<=MAXREG;r++)
1720 {
1721 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1722 for(hr=0;hr<HOST_REGS;hr++) {
1723 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1724 if(cur->regmap[hr]==r) {
1725 cur->regmap[hr]=reg;
1726 cur->dirty&=~(1<<hr);
1727 cur->isconst&=~(1<<hr);
1728 return;
1729 }
1730 }
1731 }
1732 }
1733 }
1734 }
1735 }
1736 for(j=10;j>=0;j--)
1737 {
1738 for(r=1;r<=MAXREG;r++)
1739 {
1740 if(hsn[r]==j) {
1741 for(hr=0;hr<HOST_REGS;hr++) {
1742 if(cur->regmap[hr]==r) {
1743 cur->regmap[hr]=reg;
1744 cur->dirty&=~(1<<hr);
1745 cur->isconst&=~(1<<hr);
1746 return;
1747 }
1748 }
1749 }
1750 }
1751 }
1752 SysPrintf("This shouldn't happen");abort();
1753}
1754
1755static void mov_alloc(struct regstat *current,int i)
1756{
1757 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1758 alloc_cc(current,i); // for stalls
1759 dirty_reg(current,CCREG);
1760 }
1761
1762 // Note: Don't need to actually alloc the source registers
1763 //alloc_reg(current,i,dops[i].rs1);
1764 alloc_reg(current,i,dops[i].rt1);
1765
1766 clear_const(current,dops[i].rs1);
1767 clear_const(current,dops[i].rt1);
1768 dirty_reg(current,dops[i].rt1);
1769}
1770
1771static void shiftimm_alloc(struct regstat *current,int i)
1772{
1773 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1774 {
1775 if(dops[i].rt1) {
1776 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1777 else dops[i].use_lt1=!!dops[i].rs1;
1778 alloc_reg(current,i,dops[i].rt1);
1779 dirty_reg(current,dops[i].rt1);
1780 if(is_const(current,dops[i].rs1)) {
1781 int v=get_const(current,dops[i].rs1);
1782 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1783 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1784 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1785 }
1786 else clear_const(current,dops[i].rt1);
1787 }
1788 }
1789 else
1790 {
1791 clear_const(current,dops[i].rs1);
1792 clear_const(current,dops[i].rt1);
1793 }
1794
1795 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1796 {
1797 assert(0);
1798 }
1799 if(dops[i].opcode2==0x3c) // DSLL32
1800 {
1801 assert(0);
1802 }
1803 if(dops[i].opcode2==0x3e) // DSRL32
1804 {
1805 assert(0);
1806 }
1807 if(dops[i].opcode2==0x3f) // DSRA32
1808 {
1809 assert(0);
1810 }
1811}
1812
1813static void shift_alloc(struct regstat *current,int i)
1814{
1815 if(dops[i].rt1) {
1816 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1817 {
1818 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1819 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1820 alloc_reg(current,i,dops[i].rt1);
1821 if(dops[i].rt1==dops[i].rs2) {
1822 alloc_reg_temp(current,i,-1);
1823 minimum_free_regs[i]=1;
1824 }
1825 } else { // DSLLV/DSRLV/DSRAV
1826 assert(0);
1827 }
1828 clear_const(current,dops[i].rs1);
1829 clear_const(current,dops[i].rs2);
1830 clear_const(current,dops[i].rt1);
1831 dirty_reg(current,dops[i].rt1);
1832 }
1833}
1834
1835static void alu_alloc(struct regstat *current,int i)
1836{
1837 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1838 if(dops[i].rt1) {
1839 if(dops[i].rs1&&dops[i].rs2) {
1840 alloc_reg(current,i,dops[i].rs1);
1841 alloc_reg(current,i,dops[i].rs2);
1842 }
1843 else {
1844 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1845 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1846 }
1847 alloc_reg(current,i,dops[i].rt1);
1848 }
1849 }
1850 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1851 if(dops[i].rt1) {
1852 alloc_reg(current,i,dops[i].rs1);
1853 alloc_reg(current,i,dops[i].rs2);
1854 alloc_reg(current,i,dops[i].rt1);
1855 }
1856 }
1857 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1858 if(dops[i].rt1) {
1859 if(dops[i].rs1&&dops[i].rs2) {
1860 alloc_reg(current,i,dops[i].rs1);
1861 alloc_reg(current,i,dops[i].rs2);
1862 }
1863 else
1864 {
1865 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1866 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1867 }
1868 alloc_reg(current,i,dops[i].rt1);
1869 }
1870 }
1871 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1872 assert(0);
1873 }
1874 clear_const(current,dops[i].rs1);
1875 clear_const(current,dops[i].rs2);
1876 clear_const(current,dops[i].rt1);
1877 dirty_reg(current,dops[i].rt1);
1878}
1879
1880static void imm16_alloc(struct regstat *current,int i)
1881{
1882 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1883 else dops[i].use_lt1=!!dops[i].rs1;
1884 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1885 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1886 assert(0);
1887 }
1888 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1889 clear_const(current,dops[i].rs1);
1890 clear_const(current,dops[i].rt1);
1891 }
1892 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1893 if(is_const(current,dops[i].rs1)) {
1894 int v=get_const(current,dops[i].rs1);
1895 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1896 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1897 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1898 }
1899 else clear_const(current,dops[i].rt1);
1900 }
1901 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1902 if(is_const(current,dops[i].rs1)) {
1903 int v=get_const(current,dops[i].rs1);
1904 set_const(current,dops[i].rt1,v+imm[i]);
1905 }
1906 else clear_const(current,dops[i].rt1);
1907 }
1908 else {
1909 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1910 }
1911 dirty_reg(current,dops[i].rt1);
1912}
1913
1914static void load_alloc(struct regstat *current,int i)
1915{
1916 clear_const(current,dops[i].rt1);
1917 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1918 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1919 if (needed_again(dops[i].rs1, i))
1920 alloc_reg(current, i, dops[i].rs1);
1921 if (ram_offset)
1922 alloc_reg(current, i, ROREG);
1923 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1924 alloc_reg(current,i,dops[i].rt1);
1925 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1926 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1927 {
1928 assert(0);
1929 }
1930 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1931 {
1932 assert(0);
1933 }
1934 dirty_reg(current,dops[i].rt1);
1935 // LWL/LWR need a temporary register for the old value
1936 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1937 {
1938 alloc_reg(current,i,FTEMP);
1939 alloc_reg_temp(current,i,-1);
1940 minimum_free_regs[i]=1;
1941 }
1942 }
1943 else
1944 {
1945 // Load to r0 or unneeded register (dummy load)
1946 // but we still need a register to calculate the address
1947 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1948 {
1949 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1950 }
1951 alloc_reg_temp(current,i,-1);
1952 minimum_free_regs[i]=1;
1953 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1954 {
1955 assert(0);
1956 }
1957 }
1958}
1959
1960static void store_alloc(struct regstat *current,int i)
1961{
1962 clear_const(current,dops[i].rs2);
1963 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1964 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs2);
1966 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1967 assert(0);
1968 }
1969 if (ram_offset)
1970 alloc_reg(current, i, ROREG);
1971 #if defined(HOST_IMM8)
1972 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1973 alloc_reg(current, i, INVCP);
1974 #endif
1975 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1976 alloc_reg(current,i,FTEMP);
1977 }
1978 // We need a temporary register for address generation
1979 alloc_reg_temp(current,i,-1);
1980 minimum_free_regs[i]=1;
1981}
1982
1983static void c1ls_alloc(struct regstat *current,int i)
1984{
1985 clear_const(current,dops[i].rt1);
1986 alloc_reg(current,i,CSREG); // Status
1987}
1988
1989static void c2ls_alloc(struct regstat *current,int i)
1990{
1991 clear_const(current,dops[i].rt1);
1992 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1993 alloc_reg(current,i,FTEMP);
1994 if (ram_offset)
1995 alloc_reg(current, i, ROREG);
1996 #if defined(HOST_IMM8)
1997 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1998 if (dops[i].opcode == 0x3a) // SWC2
1999 alloc_reg(current,i,INVCP);
2000 #endif
2001 // We need a temporary register for address generation
2002 alloc_reg_temp(current,i,-1);
2003 minimum_free_regs[i]=1;
2004}
2005
2006#ifndef multdiv_alloc
2007static void multdiv_alloc(struct regstat *current,int i)
2008{
2009 // case 0x18: MULT
2010 // case 0x19: MULTU
2011 // case 0x1A: DIV
2012 // case 0x1B: DIVU
2013 // case 0x1C: DMULT
2014 // case 0x1D: DMULTU
2015 // case 0x1E: DDIV
2016 // case 0x1F: DDIVU
2017 clear_const(current,dops[i].rs1);
2018 clear_const(current,dops[i].rs2);
2019 alloc_cc(current,i); // for stalls
2020 if(dops[i].rs1&&dops[i].rs2)
2021 {
2022 if((dops[i].opcode2&4)==0) // 32-bit
2023 {
2024 current->u&=~(1LL<<HIREG);
2025 current->u&=~(1LL<<LOREG);
2026 alloc_reg(current,i,HIREG);
2027 alloc_reg(current,i,LOREG);
2028 alloc_reg(current,i,dops[i].rs1);
2029 alloc_reg(current,i,dops[i].rs2);
2030 dirty_reg(current,HIREG);
2031 dirty_reg(current,LOREG);
2032 }
2033 else // 64-bit
2034 {
2035 assert(0);
2036 }
2037 }
2038 else
2039 {
2040 // Multiply by zero is zero.
2041 // MIPS does not have a divide by zero exception.
2042 // The result is undefined, we return zero.
2043 alloc_reg(current,i,HIREG);
2044 alloc_reg(current,i,LOREG);
2045 dirty_reg(current,HIREG);
2046 dirty_reg(current,LOREG);
2047 }
2048}
2049#endif
2050
2051static void cop0_alloc(struct regstat *current,int i)
2052{
2053 if(dops[i].opcode2==0) // MFC0
2054 {
2055 if(dops[i].rt1) {
2056 clear_const(current,dops[i].rt1);
2057 alloc_all(current,i);
2058 alloc_reg(current,i,dops[i].rt1);
2059 dirty_reg(current,dops[i].rt1);
2060 }
2061 }
2062 else if(dops[i].opcode2==4) // MTC0
2063 {
2064 if(dops[i].rs1){
2065 clear_const(current,dops[i].rs1);
2066 alloc_reg(current,i,dops[i].rs1);
2067 alloc_all(current,i);
2068 }
2069 else {
2070 alloc_all(current,i); // FIXME: Keep r0
2071 current->u&=~1LL;
2072 alloc_reg(current,i,0);
2073 }
2074 }
2075 else
2076 {
2077 // TLBR/TLBWI/TLBWR/TLBP/ERET
2078 assert(dops[i].opcode2==0x10);
2079 alloc_all(current,i);
2080 }
2081 minimum_free_regs[i]=HOST_REGS;
2082}
2083
2084static void cop2_alloc(struct regstat *current,int i)
2085{
2086 if (dops[i].opcode2 < 3) // MFC2/CFC2
2087 {
2088 alloc_cc(current,i); // for stalls
2089 dirty_reg(current,CCREG);
2090 if(dops[i].rt1){
2091 clear_const(current,dops[i].rt1);
2092 alloc_reg(current,i,dops[i].rt1);
2093 dirty_reg(current,dops[i].rt1);
2094 }
2095 }
2096 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2097 {
2098 if(dops[i].rs1){
2099 clear_const(current,dops[i].rs1);
2100 alloc_reg(current,i,dops[i].rs1);
2101 }
2102 else {
2103 current->u&=~1LL;
2104 alloc_reg(current,i,0);
2105 }
2106 }
2107 alloc_reg_temp(current,i,-1);
2108 minimum_free_regs[i]=1;
2109}
2110
2111static void c2op_alloc(struct regstat *current,int i)
2112{
2113 alloc_cc(current,i); // for stalls
2114 dirty_reg(current,CCREG);
2115 alloc_reg_temp(current,i,-1);
2116}
2117
2118static void syscall_alloc(struct regstat *current,int i)
2119{
2120 alloc_cc(current,i);
2121 dirty_reg(current,CCREG);
2122 alloc_all(current,i);
2123 minimum_free_regs[i]=HOST_REGS;
2124 current->isconst=0;
2125}
2126
2127static void delayslot_alloc(struct regstat *current,int i)
2128{
2129 switch(dops[i].itype) {
2130 case UJUMP:
2131 case CJUMP:
2132 case SJUMP:
2133 case RJUMP:
2134 case SYSCALL:
2135 case HLECALL:
2136 case IMM16:
2137 imm16_alloc(current,i);
2138 break;
2139 case LOAD:
2140 case LOADLR:
2141 load_alloc(current,i);
2142 break;
2143 case STORE:
2144 case STORELR:
2145 store_alloc(current,i);
2146 break;
2147 case ALU:
2148 alu_alloc(current,i);
2149 break;
2150 case SHIFT:
2151 shift_alloc(current,i);
2152 break;
2153 case MULTDIV:
2154 multdiv_alloc(current,i);
2155 break;
2156 case SHIFTIMM:
2157 shiftimm_alloc(current,i);
2158 break;
2159 case MOV:
2160 mov_alloc(current,i);
2161 break;
2162 case COP0:
2163 cop0_alloc(current,i);
2164 break;
2165 case COP1:
2166 break;
2167 case COP2:
2168 cop2_alloc(current,i);
2169 break;
2170 case C1LS:
2171 c1ls_alloc(current,i);
2172 break;
2173 case C2LS:
2174 c2ls_alloc(current,i);
2175 break;
2176 case C2OP:
2177 c2op_alloc(current,i);
2178 break;
2179 }
2180}
2181
2182static void add_stub(enum stub_type type, void *addr, void *retaddr,
2183 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2184{
2185 assert(stubcount < ARRAY_SIZE(stubs));
2186 stubs[stubcount].type = type;
2187 stubs[stubcount].addr = addr;
2188 stubs[stubcount].retaddr = retaddr;
2189 stubs[stubcount].a = a;
2190 stubs[stubcount].b = b;
2191 stubs[stubcount].c = c;
2192 stubs[stubcount].d = d;
2193 stubs[stubcount].e = e;
2194 stubcount++;
2195}
2196
2197static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2198 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2199{
2200 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2201}
2202
2203// Write out a single register
2204static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2205{
2206 int hr;
2207 for(hr=0;hr<HOST_REGS;hr++) {
2208 if(hr!=EXCLUDE_REG) {
2209 if(regmap[hr]==r) {
2210 if((dirty>>hr)&1) {
2211 assert(regmap[hr]<64);
2212 emit_storereg(r,hr);
2213 }
2214 }
2215 }
2216 }
2217}
2218
2219static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2220{
2221 //if(dirty_pre==dirty) return;
2222 int hr, r;
2223 for (hr = 0; hr < HOST_REGS; hr++) {
2224 r = pre[hr];
2225 if (r < 1 || r > 33 || ((u >> r) & 1))
2226 continue;
2227 if (((dirty_pre & ~dirty) >> hr) & 1)
2228 emit_storereg(r, hr);
2229 }
2230}
2231
2232// trashes r2
2233static void pass_args(int a0, int a1)
2234{
2235 if(a0==1&&a1==0) {
2236 // must swap
2237 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2238 }
2239 else if(a0!=0&&a1==0) {
2240 emit_mov(a1,1);
2241 if (a0>=0) emit_mov(a0,0);
2242 }
2243 else {
2244 if(a0>=0&&a0!=0) emit_mov(a0,0);
2245 if(a1>=0&&a1!=1) emit_mov(a1,1);
2246 }
2247}
2248
2249static void alu_assemble(int i, const struct regstat *i_regs)
2250{
2251 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2252 if(dops[i].rt1) {
2253 signed char s1,s2,t;
2254 t=get_reg(i_regs->regmap,dops[i].rt1);
2255 if(t>=0) {
2256 s1=get_reg(i_regs->regmap,dops[i].rs1);
2257 s2=get_reg(i_regs->regmap,dops[i].rs2);
2258 if(dops[i].rs1&&dops[i].rs2) {
2259 assert(s1>=0);
2260 assert(s2>=0);
2261 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2262 else emit_add(s1,s2,t);
2263 }
2264 else if(dops[i].rs1) {
2265 if(s1>=0) emit_mov(s1,t);
2266 else emit_loadreg(dops[i].rs1,t);
2267 }
2268 else if(dops[i].rs2) {
2269 if(s2>=0) {
2270 if(dops[i].opcode2&2) emit_neg(s2,t);
2271 else emit_mov(s2,t);
2272 }
2273 else {
2274 emit_loadreg(dops[i].rs2,t);
2275 if(dops[i].opcode2&2) emit_neg(t,t);
2276 }
2277 }
2278 else emit_zeroreg(t);
2279 }
2280 }
2281 }
2282 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2283 assert(0);
2284 }
2285 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2286 if(dops[i].rt1) {
2287 signed char s1l,s2l,t;
2288 {
2289 t=get_reg(i_regs->regmap,dops[i].rt1);
2290 //assert(t>=0);
2291 if(t>=0) {
2292 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2293 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2294 if(dops[i].rs2==0) // rx<r0
2295 {
2296 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2297 assert(s1l>=0);
2298 emit_shrimm(s1l,31,t);
2299 }
2300 else // SLTU (unsigned can not be less than zero, 0<0)
2301 emit_zeroreg(t);
2302 }
2303 else if(dops[i].rs1==0) // r0<rx
2304 {
2305 assert(s2l>=0);
2306 if(dops[i].opcode2==0x2a) // SLT
2307 emit_set_gz32(s2l,t);
2308 else // SLTU (set if not zero)
2309 emit_set_nz32(s2l,t);
2310 }
2311 else{
2312 assert(s1l>=0);assert(s2l>=0);
2313 if(dops[i].opcode2==0x2a) // SLT
2314 emit_set_if_less32(s1l,s2l,t);
2315 else // SLTU
2316 emit_set_if_carry32(s1l,s2l,t);
2317 }
2318 }
2319 }
2320 }
2321 }
2322 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2323 if(dops[i].rt1) {
2324 signed char s1l,s2l,tl;
2325 tl=get_reg(i_regs->regmap,dops[i].rt1);
2326 {
2327 if(tl>=0) {
2328 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2329 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2330 if(dops[i].rs1&&dops[i].rs2) {
2331 assert(s1l>=0);
2332 assert(s2l>=0);
2333 if(dops[i].opcode2==0x24) { // AND
2334 emit_and(s1l,s2l,tl);
2335 } else
2336 if(dops[i].opcode2==0x25) { // OR
2337 emit_or(s1l,s2l,tl);
2338 } else
2339 if(dops[i].opcode2==0x26) { // XOR
2340 emit_xor(s1l,s2l,tl);
2341 } else
2342 if(dops[i].opcode2==0x27) { // NOR
2343 emit_or(s1l,s2l,tl);
2344 emit_not(tl,tl);
2345 }
2346 }
2347 else
2348 {
2349 if(dops[i].opcode2==0x24) { // AND
2350 emit_zeroreg(tl);
2351 } else
2352 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2353 if(dops[i].rs1){
2354 if(s1l>=0) emit_mov(s1l,tl);
2355 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2356 }
2357 else
2358 if(dops[i].rs2){
2359 if(s2l>=0) emit_mov(s2l,tl);
2360 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2361 }
2362 else emit_zeroreg(tl);
2363 } else
2364 if(dops[i].opcode2==0x27) { // NOR
2365 if(dops[i].rs1){
2366 if(s1l>=0) emit_not(s1l,tl);
2367 else {
2368 emit_loadreg(dops[i].rs1,tl);
2369 emit_not(tl,tl);
2370 }
2371 }
2372 else
2373 if(dops[i].rs2){
2374 if(s2l>=0) emit_not(s2l,tl);
2375 else {
2376 emit_loadreg(dops[i].rs2,tl);
2377 emit_not(tl,tl);
2378 }
2379 }
2380 else emit_movimm(-1,tl);
2381 }
2382 }
2383 }
2384 }
2385 }
2386 }
2387}
2388
2389static void imm16_assemble(int i, const struct regstat *i_regs)
2390{
2391 if (dops[i].opcode==0x0f) { // LUI
2392 if(dops[i].rt1) {
2393 signed char t;
2394 t=get_reg(i_regs->regmap,dops[i].rt1);
2395 //assert(t>=0);
2396 if(t>=0) {
2397 if(!((i_regs->isconst>>t)&1))
2398 emit_movimm(imm[i]<<16,t);
2399 }
2400 }
2401 }
2402 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2403 if(dops[i].rt1) {
2404 signed char s,t;
2405 t=get_reg(i_regs->regmap,dops[i].rt1);
2406 s=get_reg(i_regs->regmap,dops[i].rs1);
2407 if(dops[i].rs1) {
2408 //assert(t>=0);
2409 //assert(s>=0);
2410 if(t>=0) {
2411 if(!((i_regs->isconst>>t)&1)) {
2412 if(s<0) {
2413 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2414 emit_addimm(t,imm[i],t);
2415 }else{
2416 if(!((i_regs->wasconst>>s)&1))
2417 emit_addimm(s,imm[i],t);
2418 else
2419 emit_movimm(constmap[i][s]+imm[i],t);
2420 }
2421 }
2422 }
2423 } else {
2424 if(t>=0) {
2425 if(!((i_regs->isconst>>t)&1))
2426 emit_movimm(imm[i],t);
2427 }
2428 }
2429 }
2430 }
2431 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2432 if(dops[i].rt1) {
2433 signed char sl,tl;
2434 tl=get_reg(i_regs->regmap,dops[i].rt1);
2435 sl=get_reg(i_regs->regmap,dops[i].rs1);
2436 if(tl>=0) {
2437 if(dops[i].rs1) {
2438 assert(sl>=0);
2439 emit_addimm(sl,imm[i],tl);
2440 } else {
2441 emit_movimm(imm[i],tl);
2442 }
2443 }
2444 }
2445 }
2446 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2447 if(dops[i].rt1) {
2448 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2449 signed char sl,t;
2450 t=get_reg(i_regs->regmap,dops[i].rt1);
2451 sl=get_reg(i_regs->regmap,dops[i].rs1);
2452 //assert(t>=0);
2453 if(t>=0) {
2454 if(dops[i].rs1>0) {
2455 if(dops[i].opcode==0x0a) { // SLTI
2456 if(sl<0) {
2457 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2458 emit_slti32(t,imm[i],t);
2459 }else{
2460 emit_slti32(sl,imm[i],t);
2461 }
2462 }
2463 else { // SLTIU
2464 if(sl<0) {
2465 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2466 emit_sltiu32(t,imm[i],t);
2467 }else{
2468 emit_sltiu32(sl,imm[i],t);
2469 }
2470 }
2471 }else{
2472 // SLTI(U) with r0 is just stupid,
2473 // nonetheless examples can be found
2474 if(dops[i].opcode==0x0a) // SLTI
2475 if(0<imm[i]) emit_movimm(1,t);
2476 else emit_zeroreg(t);
2477 else // SLTIU
2478 {
2479 if(imm[i]) emit_movimm(1,t);
2480 else emit_zeroreg(t);
2481 }
2482 }
2483 }
2484 }
2485 }
2486 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2487 if(dops[i].rt1) {
2488 signed char sl,tl;
2489 tl=get_reg(i_regs->regmap,dops[i].rt1);
2490 sl=get_reg(i_regs->regmap,dops[i].rs1);
2491 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2492 if(dops[i].opcode==0x0c) //ANDI
2493 {
2494 if(dops[i].rs1) {
2495 if(sl<0) {
2496 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2497 emit_andimm(tl,imm[i],tl);
2498 }else{
2499 if(!((i_regs->wasconst>>sl)&1))
2500 emit_andimm(sl,imm[i],tl);
2501 else
2502 emit_movimm(constmap[i][sl]&imm[i],tl);
2503 }
2504 }
2505 else
2506 emit_zeroreg(tl);
2507 }
2508 else
2509 {
2510 if(dops[i].rs1) {
2511 if(sl<0) {
2512 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2513 }
2514 if(dops[i].opcode==0x0d) { // ORI
2515 if(sl<0) {
2516 emit_orimm(tl,imm[i],tl);
2517 }else{
2518 if(!((i_regs->wasconst>>sl)&1))
2519 emit_orimm(sl,imm[i],tl);
2520 else
2521 emit_movimm(constmap[i][sl]|imm[i],tl);
2522 }
2523 }
2524 if(dops[i].opcode==0x0e) { // XORI
2525 if(sl<0) {
2526 emit_xorimm(tl,imm[i],tl);
2527 }else{
2528 if(!((i_regs->wasconst>>sl)&1))
2529 emit_xorimm(sl,imm[i],tl);
2530 else
2531 emit_movimm(constmap[i][sl]^imm[i],tl);
2532 }
2533 }
2534 }
2535 else {
2536 emit_movimm(imm[i],tl);
2537 }
2538 }
2539 }
2540 }
2541 }
2542}
2543
2544static void shiftimm_assemble(int i, const struct regstat *i_regs)
2545{
2546 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2547 {
2548 if(dops[i].rt1) {
2549 signed char s,t;
2550 t=get_reg(i_regs->regmap,dops[i].rt1);
2551 s=get_reg(i_regs->regmap,dops[i].rs1);
2552 //assert(t>=0);
2553 if(t>=0&&!((i_regs->isconst>>t)&1)){
2554 if(dops[i].rs1==0)
2555 {
2556 emit_zeroreg(t);
2557 }
2558 else
2559 {
2560 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2561 if(imm[i]) {
2562 if(dops[i].opcode2==0) // SLL
2563 {
2564 emit_shlimm(s<0?t:s,imm[i],t);
2565 }
2566 if(dops[i].opcode2==2) // SRL
2567 {
2568 emit_shrimm(s<0?t:s,imm[i],t);
2569 }
2570 if(dops[i].opcode2==3) // SRA
2571 {
2572 emit_sarimm(s<0?t:s,imm[i],t);
2573 }
2574 }else{
2575 // Shift by zero
2576 if(s>=0 && s!=t) emit_mov(s,t);
2577 }
2578 }
2579 }
2580 //emit_storereg(dops[i].rt1,t); //DEBUG
2581 }
2582 }
2583 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2584 {
2585 assert(0);
2586 }
2587 if(dops[i].opcode2==0x3c) // DSLL32
2588 {
2589 assert(0);
2590 }
2591 if(dops[i].opcode2==0x3e) // DSRL32
2592 {
2593 assert(0);
2594 }
2595 if(dops[i].opcode2==0x3f) // DSRA32
2596 {
2597 assert(0);
2598 }
2599}
2600
2601#ifndef shift_assemble
2602static void shift_assemble(int i, const struct regstat *i_regs)
2603{
2604 signed char s,t,shift;
2605 if (dops[i].rt1 == 0)
2606 return;
2607 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2608 t = get_reg(i_regs->regmap, dops[i].rt1);
2609 s = get_reg(i_regs->regmap, dops[i].rs1);
2610 shift = get_reg(i_regs->regmap, dops[i].rs2);
2611 if (t < 0)
2612 return;
2613
2614 if(dops[i].rs1==0)
2615 emit_zeroreg(t);
2616 else if(dops[i].rs2==0) {
2617 assert(s>=0);
2618 if(s!=t) emit_mov(s,t);
2619 }
2620 else {
2621 host_tempreg_acquire();
2622 emit_andimm(shift,31,HOST_TEMPREG);
2623 switch(dops[i].opcode2) {
2624 case 4: // SLLV
2625 emit_shl(s,HOST_TEMPREG,t);
2626 break;
2627 case 6: // SRLV
2628 emit_shr(s,HOST_TEMPREG,t);
2629 break;
2630 case 7: // SRAV
2631 emit_sar(s,HOST_TEMPREG,t);
2632 break;
2633 default:
2634 assert(0);
2635 }
2636 host_tempreg_release();
2637 }
2638}
2639
2640#endif
2641
2642enum {
2643 MTYPE_8000 = 0,
2644 MTYPE_8020,
2645 MTYPE_0000,
2646 MTYPE_A000,
2647 MTYPE_1F80,
2648};
2649
2650static int get_ptr_mem_type(u_int a)
2651{
2652 if(a < 0x00200000) {
2653 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2654 // return wrong, must use memhandler for BIOS self-test to pass
2655 // 007 does similar stuff from a00 mirror, weird stuff
2656 return MTYPE_8000;
2657 return MTYPE_0000;
2658 }
2659 if(0x1f800000 <= a && a < 0x1f801000)
2660 return MTYPE_1F80;
2661 if(0x80200000 <= a && a < 0x80800000)
2662 return MTYPE_8020;
2663 if(0xa0000000 <= a && a < 0xa0200000)
2664 return MTYPE_A000;
2665 return MTYPE_8000;
2666}
2667
2668static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2669{
2670 int r = get_reg(i_regs->regmap, ROREG);
2671 if (r < 0 && host_tempreg_free) {
2672 host_tempreg_acquire();
2673 emit_loadreg(ROREG, r = HOST_TEMPREG);
2674 }
2675 if (r < 0)
2676 abort();
2677 return r;
2678}
2679
2680static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2681 int addr, int *offset_reg, int *addr_reg_override)
2682{
2683 void *jaddr = NULL;
2684 int type = 0;
2685 int mr = dops[i].rs1;
2686 *offset_reg = -1;
2687 if(((smrv_strong|smrv_weak)>>mr)&1) {
2688 type=get_ptr_mem_type(smrv[mr]);
2689 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2690 }
2691 else {
2692 // use the mirror we are running on
2693 type=get_ptr_mem_type(start);
2694 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2695 }
2696
2697 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2698 host_tempreg_acquire();
2699 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2700 addr=*addr_reg_override=HOST_TEMPREG;
2701 type=0;
2702 }
2703 else if(type==MTYPE_0000) { // RAM 0 mirror
2704 host_tempreg_acquire();
2705 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2706 addr=*addr_reg_override=HOST_TEMPREG;
2707 type=0;
2708 }
2709 else if(type==MTYPE_A000) { // RAM A mirror
2710 host_tempreg_acquire();
2711 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2712 addr=*addr_reg_override=HOST_TEMPREG;
2713 type=0;
2714 }
2715 else if(type==MTYPE_1F80) { // scratchpad
2716 if (psxH == (void *)0x1f800000) {
2717 host_tempreg_acquire();
2718 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2719 emit_cmpimm(HOST_TEMPREG,0x1000);
2720 host_tempreg_release();
2721 jaddr=out;
2722 emit_jc(0);
2723 }
2724 else {
2725 // do the usual RAM check, jump will go to the right handler
2726 type=0;
2727 }
2728 }
2729
2730 if (type == 0) // need ram check
2731 {
2732 emit_cmpimm(addr,RAM_SIZE);
2733 jaddr = out;
2734 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2735 // Hint to branch predictor that the branch is unlikely to be taken
2736 if (dops[i].rs1 >= 28)
2737 emit_jno_unlikely(0);
2738 else
2739 #endif
2740 emit_jno(0);
2741 if (ram_offset != 0)
2742 *offset_reg = get_ro_reg(i_regs, 0);
2743 }
2744
2745 return jaddr;
2746}
2747
2748// return memhandler, or get directly accessable address and return 0
2749static void *get_direct_memhandler(void *table, u_int addr,
2750 enum stub_type type, uintptr_t *addr_host)
2751{
2752 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2753 uintptr_t l1, l2 = 0;
2754 l1 = ((uintptr_t *)table)[addr>>12];
2755 if (!(l1 & msb)) {
2756 uintptr_t v = l1 << 1;
2757 *addr_host = v + addr;
2758 return NULL;
2759 }
2760 else {
2761 l1 <<= 1;
2762 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2763 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2764 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2765 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2766 else
2767 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2768 if (!(l2 & msb)) {
2769 uintptr_t v = l2 << 1;
2770 *addr_host = v + (addr&0xfff);
2771 return NULL;
2772 }
2773 return (void *)(l2 << 1);
2774 }
2775}
2776
2777static u_int get_host_reglist(const signed char *regmap)
2778{
2779 u_int reglist = 0, hr;
2780 for (hr = 0; hr < HOST_REGS; hr++) {
2781 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2782 reglist |= 1 << hr;
2783 }
2784 return reglist;
2785}
2786
2787static u_int reglist_exclude(u_int reglist, int r1, int r2)
2788{
2789 if (r1 >= 0)
2790 reglist &= ~(1u << r1);
2791 if (r2 >= 0)
2792 reglist &= ~(1u << r2);
2793 return reglist;
2794}
2795
2796// find a temp caller-saved register not in reglist (so assumed to be free)
2797static int reglist_find_free(u_int reglist)
2798{
2799 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2800 if (free_regs == 0)
2801 return -1;
2802 return __builtin_ctz(free_regs);
2803}
2804
2805static void do_load_word(int a, int rt, int offset_reg)
2806{
2807 if (offset_reg >= 0)
2808 emit_ldr_dualindexed(offset_reg, a, rt);
2809 else
2810 emit_readword_indexed(0, a, rt);
2811}
2812
2813static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2814{
2815 if (offset_reg < 0) {
2816 emit_writeword_indexed(rt, ofs, a);
2817 return;
2818 }
2819 if (ofs != 0)
2820 emit_addimm(a, ofs, a);
2821 emit_str_dualindexed(offset_reg, a, rt);
2822 if (ofs != 0 && preseve_a)
2823 emit_addimm(a, -ofs, a);
2824}
2825
2826static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2827{
2828 if (offset_reg < 0) {
2829 emit_writehword_indexed(rt, ofs, a);
2830 return;
2831 }
2832 if (ofs != 0)
2833 emit_addimm(a, ofs, a);
2834 emit_strh_dualindexed(offset_reg, a, rt);
2835 if (ofs != 0 && preseve_a)
2836 emit_addimm(a, -ofs, a);
2837}
2838
2839static void do_store_byte(int a, int rt, int offset_reg)
2840{
2841 if (offset_reg >= 0)
2842 emit_strb_dualindexed(offset_reg, a, rt);
2843 else
2844 emit_writebyte_indexed(rt, 0, a);
2845}
2846
2847static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2848{
2849 int s,tl,addr;
2850 int offset;
2851 void *jaddr=0;
2852 int memtarget=0,c=0;
2853 int offset_reg = -1;
2854 int fastio_reg_override = -1;
2855 u_int reglist=get_host_reglist(i_regs->regmap);
2856 tl=get_reg(i_regs->regmap,dops[i].rt1);
2857 s=get_reg(i_regs->regmap,dops[i].rs1);
2858 offset=imm[i];
2859 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2860 if(s>=0) {
2861 c=(i_regs->wasconst>>s)&1;
2862 if (c) {
2863 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2864 }
2865 }
2866 //printf("load_assemble: c=%d\n",c);
2867 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2868 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2869 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2870 ||dops[i].rt1==0) {
2871 // could be FIFO, must perform the read
2872 // ||dummy read
2873 assem_debug("(forced read)\n");
2874 tl=get_reg_temp(i_regs->regmap);
2875 assert(tl>=0);
2876 }
2877 if(offset||s<0||c) addr=tl;
2878 else addr=s;
2879 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
2880 if(tl>=0) {
2881 //printf("load_assemble: c=%d\n",c);
2882 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2883 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2884 reglist&=~(1<<tl);
2885 if(!c) {
2886 #ifdef R29_HACK
2887 // Strmnnrmn's speed hack
2888 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2889 #endif
2890 {
2891 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2892 &offset_reg, &fastio_reg_override);
2893 }
2894 }
2895 else if (ram_offset && memtarget) {
2896 offset_reg = get_ro_reg(i_regs, 0);
2897 }
2898 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2899 switch (dops[i].opcode) {
2900 case 0x20: // LB
2901 if(!c||memtarget) {
2902 if(!dummy) {
2903 int a = tl;
2904 if (!c) a = addr;
2905 if (fastio_reg_override >= 0)
2906 a = fastio_reg_override;
2907
2908 if (offset_reg >= 0)
2909 emit_ldrsb_dualindexed(offset_reg, a, tl);
2910 else
2911 emit_movsbl_indexed(0, a, tl);
2912 }
2913 if(jaddr)
2914 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2915 }
2916 else
2917 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2918 break;
2919 case 0x21: // LH
2920 if(!c||memtarget) {
2921 if(!dummy) {
2922 int a = tl;
2923 if (!c) a = addr;
2924 if (fastio_reg_override >= 0)
2925 a = fastio_reg_override;
2926 if (offset_reg >= 0)
2927 emit_ldrsh_dualindexed(offset_reg, a, tl);
2928 else
2929 emit_movswl_indexed(0, a, tl);
2930 }
2931 if(jaddr)
2932 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2933 }
2934 else
2935 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2936 break;
2937 case 0x23: // LW
2938 if(!c||memtarget) {
2939 if(!dummy) {
2940 int a = addr;
2941 if (fastio_reg_override >= 0)
2942 a = fastio_reg_override;
2943 do_load_word(a, tl, offset_reg);
2944 }
2945 if(jaddr)
2946 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2947 }
2948 else
2949 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2950 break;
2951 case 0x24: // LBU
2952 if(!c||memtarget) {
2953 if(!dummy) {
2954 int a = tl;
2955 if (!c) a = addr;
2956 if (fastio_reg_override >= 0)
2957 a = fastio_reg_override;
2958
2959 if (offset_reg >= 0)
2960 emit_ldrb_dualindexed(offset_reg, a, tl);
2961 else
2962 emit_movzbl_indexed(0, a, tl);
2963 }
2964 if(jaddr)
2965 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2966 }
2967 else
2968 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2969 break;
2970 case 0x25: // LHU
2971 if(!c||memtarget) {
2972 if(!dummy) {
2973 int a = tl;
2974 if(!c) a = addr;
2975 if (fastio_reg_override >= 0)
2976 a = fastio_reg_override;
2977 if (offset_reg >= 0)
2978 emit_ldrh_dualindexed(offset_reg, a, tl);
2979 else
2980 emit_movzwl_indexed(0, a, tl);
2981 }
2982 if(jaddr)
2983 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2984 }
2985 else
2986 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2987 break;
2988 case 0x27: // LWU
2989 case 0x37: // LD
2990 default:
2991 assert(0);
2992 }
2993 }
2994 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2995 host_tempreg_release();
2996}
2997
2998#ifndef loadlr_assemble
2999static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3000{
3001 int s,tl,temp,temp2,addr;
3002 int offset;
3003 void *jaddr=0;
3004 int memtarget=0,c=0;
3005 int offset_reg = -1;
3006 int fastio_reg_override = -1;
3007 u_int reglist=get_host_reglist(i_regs->regmap);
3008 tl=get_reg(i_regs->regmap,dops[i].rt1);
3009 s=get_reg(i_regs->regmap,dops[i].rs1);
3010 temp=get_reg_temp(i_regs->regmap);
3011 temp2=get_reg(i_regs->regmap,FTEMP);
3012 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3013 assert(addr<0);
3014 offset=imm[i];
3015 reglist|=1<<temp;
3016 if(offset||s<0||c) addr=temp2;
3017 else addr=s;
3018 if(s>=0) {
3019 c=(i_regs->wasconst>>s)&1;
3020 if(c) {
3021 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3022 }
3023 }
3024 if(!c) {
3025 emit_shlimm(addr,3,temp);
3026 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3027 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3028 }else{
3029 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3030 }
3031 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3032 &offset_reg, &fastio_reg_override);
3033 }
3034 else {
3035 if (ram_offset && memtarget) {
3036 offset_reg = get_ro_reg(i_regs, 0);
3037 }
3038 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3039 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3040 }else{
3041 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3042 }
3043 }
3044 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3045 if(!c||memtarget) {
3046 int a = temp2;
3047 if (fastio_reg_override >= 0)
3048 a = fastio_reg_override;
3049 do_load_word(a, temp2, offset_reg);
3050 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3051 host_tempreg_release();
3052 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3053 }
3054 else
3055 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3056 if(dops[i].rt1) {
3057 assert(tl>=0);
3058 emit_andimm(temp,24,temp);
3059 if (dops[i].opcode==0x22) // LWL
3060 emit_xorimm(temp,24,temp);
3061 host_tempreg_acquire();
3062 emit_movimm(-1,HOST_TEMPREG);
3063 if (dops[i].opcode==0x26) {
3064 emit_shr(temp2,temp,temp2);
3065 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3066 }else{
3067 emit_shl(temp2,temp,temp2);
3068 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3069 }
3070 host_tempreg_release();
3071 emit_or(temp2,tl,tl);
3072 }
3073 //emit_storereg(dops[i].rt1,tl); // DEBUG
3074 }
3075 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3076 assert(0);
3077 }
3078}
3079#endif
3080
3081static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3082{
3083 int s,tl;
3084 int addr,temp;
3085 int offset;
3086 void *jaddr=0;
3087 enum stub_type type=0;
3088 int memtarget=0,c=0;
3089 int agr=AGEN1+(i&1);
3090 int offset_reg = -1;
3091 int fastio_reg_override = -1;
3092 u_int reglist=get_host_reglist(i_regs->regmap);
3093 tl=get_reg(i_regs->regmap,dops[i].rs2);
3094 s=get_reg(i_regs->regmap,dops[i].rs1);
3095 temp=get_reg(i_regs->regmap,agr);
3096 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3097 offset=imm[i];
3098 if(s>=0) {
3099 c=(i_regs->wasconst>>s)&1;
3100 if(c) {
3101 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3102 }
3103 }
3104 assert(tl>=0);
3105 assert(temp>=0);
3106 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3107 if(offset||s<0||c) addr=temp;
3108 else addr=s;
3109 if (!c) {
3110 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3111 &offset_reg, &fastio_reg_override);
3112 }
3113 else if (ram_offset && memtarget) {
3114 offset_reg = get_ro_reg(i_regs, 0);
3115 }
3116
3117 switch (dops[i].opcode) {
3118 case 0x28: // SB
3119 if(!c||memtarget) {
3120 int a = temp;
3121 if (!c) a = addr;
3122 if (fastio_reg_override >= 0)
3123 a = fastio_reg_override;
3124 do_store_byte(a, tl, offset_reg);
3125 }
3126 type = STOREB_STUB;
3127 break;
3128 case 0x29: // SH
3129 if(!c||memtarget) {
3130 int a = temp;
3131 if (!c) a = addr;
3132 if (fastio_reg_override >= 0)
3133 a = fastio_reg_override;
3134 do_store_hword(a, 0, tl, offset_reg, 1);
3135 }
3136 type = STOREH_STUB;
3137 break;
3138 case 0x2B: // SW
3139 if(!c||memtarget) {
3140 int a = addr;
3141 if (fastio_reg_override >= 0)
3142 a = fastio_reg_override;
3143 do_store_word(a, 0, tl, offset_reg, 1);
3144 }
3145 type = STOREW_STUB;
3146 break;
3147 case 0x3F: // SD
3148 default:
3149 assert(0);
3150 }
3151 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3152 host_tempreg_release();
3153 if(jaddr) {
3154 // PCSX store handlers don't check invcode again
3155 reglist|=1<<addr;
3156 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3157 jaddr=0;
3158 }
3159 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3160 if(!c||memtarget) {
3161 #ifdef DESTRUCTIVE_SHIFT
3162 // The x86 shift operation is 'destructive'; it overwrites the
3163 // source register, so we need to make a copy first and use that.
3164 addr=temp;
3165 #endif
3166 #if defined(HOST_IMM8)
3167 int ir=get_reg(i_regs->regmap,INVCP);
3168 assert(ir>=0);
3169 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3170 #else
3171 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3172 #endif
3173 #ifdef INVALIDATE_USE_COND_CALL
3174 emit_callne(invalidate_addr_reg[addr]);
3175 #else
3176 void *jaddr2 = out;
3177 emit_jne(0);
3178 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3179 #endif
3180 }
3181 }
3182 u_int addr_val=constmap[i][s]+offset;
3183 if(jaddr) {
3184 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3185 } else if(c&&!memtarget) {
3186 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3187 }
3188 // basic current block modification detection..
3189 // not looking back as that should be in mips cache already
3190 // (see Spyro2 title->attract mode)
3191 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3192 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3193 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3194 if(i_regs->regmap==regs[i].regmap) {
3195 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3196 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3197 emit_movimm(start+i*4+4,0);
3198 emit_writeword(0,&pcaddr);
3199 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3200 emit_far_call(ndrc_get_addr_ht);
3201 emit_jmpreg(0);
3202 }
3203 }
3204}
3205
3206static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3207{
3208 int s,tl;
3209 int temp;
3210 int offset;
3211 void *jaddr=0;
3212 void *case1, *case23, *case3;
3213 void *done0, *done1, *done2;
3214 int memtarget=0,c=0;
3215 int agr=AGEN1+(i&1);
3216 int offset_reg = -1;
3217 u_int reglist=get_host_reglist(i_regs->regmap);
3218 tl=get_reg(i_regs->regmap,dops[i].rs2);
3219 s=get_reg(i_regs->regmap,dops[i].rs1);
3220 temp=get_reg(i_regs->regmap,agr);
3221 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3222 offset=imm[i];
3223 if(s>=0) {
3224 c=(i_regs->isconst>>s)&1;
3225 if(c) {
3226 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3227 }
3228 }
3229 assert(tl>=0);
3230 assert(temp>=0);
3231 if(!c) {
3232 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3233 if(!offset&&s!=temp) emit_mov(s,temp);
3234 jaddr=out;
3235 emit_jno(0);
3236 }
3237 else
3238 {
3239 if(!memtarget||!dops[i].rs1) {
3240 jaddr=out;
3241 emit_jmp(0);
3242 }
3243 }
3244 if (ram_offset)
3245 offset_reg = get_ro_reg(i_regs, 0);
3246
3247 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3248 assert(0);
3249 }
3250
3251 emit_testimm(temp,2);
3252 case23=out;
3253 emit_jne(0);
3254 emit_testimm(temp,1);
3255 case1=out;
3256 emit_jne(0);
3257 // 0
3258 if (dops[i].opcode == 0x2A) { // SWL
3259 // Write msb into least significant byte
3260 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3261 do_store_byte(temp, tl, offset_reg);
3262 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3263 }
3264 else if (dops[i].opcode == 0x2E) { // SWR
3265 // Write entire word
3266 do_store_word(temp, 0, tl, offset_reg, 1);
3267 }
3268 done0 = out;
3269 emit_jmp(0);
3270 // 1
3271 set_jump_target(case1, out);
3272 if (dops[i].opcode == 0x2A) { // SWL
3273 // Write two msb into two least significant bytes
3274 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3275 do_store_hword(temp, -1, tl, offset_reg, 0);
3276 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3277 }
3278 else if (dops[i].opcode == 0x2E) { // SWR
3279 // Write 3 lsb into three most significant bytes
3280 do_store_byte(temp, tl, offset_reg);
3281 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3282 do_store_hword(temp, 1, tl, offset_reg, 0);
3283 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3284 }
3285 done1=out;
3286 emit_jmp(0);
3287 // 2,3
3288 set_jump_target(case23, out);
3289 emit_testimm(temp,1);
3290 case3 = out;
3291 emit_jne(0);
3292 // 2
3293 if (dops[i].opcode==0x2A) { // SWL
3294 // Write 3 msb into three least significant bytes
3295 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3296 do_store_hword(temp, -2, tl, offset_reg, 1);
3297 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3298 do_store_byte(temp, tl, offset_reg);
3299 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3300 }
3301 else if (dops[i].opcode == 0x2E) { // SWR
3302 // Write two lsb into two most significant bytes
3303 do_store_hword(temp, 0, tl, offset_reg, 1);
3304 }
3305 done2 = out;
3306 emit_jmp(0);
3307 // 3
3308 set_jump_target(case3, out);
3309 if (dops[i].opcode == 0x2A) { // SWL
3310 do_store_word(temp, -3, tl, offset_reg, 0);
3311 }
3312 else if (dops[i].opcode == 0x2E) { // SWR
3313 do_store_byte(temp, tl, offset_reg);
3314 }
3315 set_jump_target(done0, out);
3316 set_jump_target(done1, out);
3317 set_jump_target(done2, out);
3318 if (offset_reg == HOST_TEMPREG)
3319 host_tempreg_release();
3320 if(!c||!memtarget)
3321 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3322 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3323 #if defined(HOST_IMM8)
3324 int ir=get_reg(i_regs->regmap,INVCP);
3325 assert(ir>=0);
3326 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3327 #else
3328 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3329 #endif
3330 #ifdef INVALIDATE_USE_COND_CALL
3331 emit_callne(invalidate_addr_reg[temp]);
3332 #else
3333 void *jaddr2 = out;
3334 emit_jne(0);
3335 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3336 #endif
3337 }
3338}
3339
3340static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3341{
3342 if(dops[i].opcode2==0) // MFC0
3343 {
3344 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3345 u_int copr=(source[i]>>11)&0x1f;
3346 //assert(t>=0); // Why does this happen? OOT is weird
3347 if(t>=0&&dops[i].rt1!=0) {
3348 emit_readword(&reg_cop0[copr],t);
3349 }
3350 }
3351 else if(dops[i].opcode2==4) // MTC0
3352 {
3353 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3354 char copr=(source[i]>>11)&0x1f;
3355 assert(s>=0);
3356 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3357 if(copr==9||copr==11||copr==12||copr==13) {
3358 emit_readword(&last_count,HOST_TEMPREG);
3359 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3360 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3361 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3362 emit_writeword(HOST_CCREG,&Count);
3363 }
3364 // What a mess. The status register (12) can enable interrupts,
3365 // so needs a special case to handle a pending interrupt.
3366 // The interrupt must be taken immediately, because a subsequent
3367 // instruction might disable interrupts again.
3368 if(copr==12||copr==13) {
3369 if (is_delayslot) {
3370 // burn cycles to cause cc_interrupt, which will
3371 // reschedule next_interupt. Relies on CCREG from above.
3372 assem_debug("MTC0 DS %d\n", copr);
3373 emit_writeword(HOST_CCREG,&last_count);
3374 emit_movimm(0,HOST_CCREG);
3375 emit_storereg(CCREG,HOST_CCREG);
3376 emit_loadreg(dops[i].rs1,1);
3377 emit_movimm(copr,0);
3378 emit_far_call(pcsx_mtc0_ds);
3379 emit_loadreg(dops[i].rs1,s);
3380 return;
3381 }
3382 emit_movimm(start+i*4+4,HOST_TEMPREG);
3383 emit_writeword(HOST_TEMPREG,&pcaddr);
3384 emit_movimm(0,HOST_TEMPREG);
3385 emit_writeword(HOST_TEMPREG,&pending_exception);
3386 }
3387 if(s==HOST_CCREG)
3388 emit_loadreg(dops[i].rs1,1);
3389 else if(s!=1)
3390 emit_mov(s,1);
3391 emit_movimm(copr,0);
3392 emit_far_call(pcsx_mtc0);
3393 if(copr==9||copr==11||copr==12||copr==13) {
3394 emit_readword(&Count,HOST_CCREG);
3395 emit_readword(&next_interupt,HOST_TEMPREG);
3396 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3397 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3398 emit_writeword(HOST_TEMPREG,&last_count);
3399 emit_storereg(CCREG,HOST_CCREG);
3400 }
3401 if(copr==12||copr==13) {
3402 assert(!is_delayslot);
3403 emit_readword(&pending_exception,14);
3404 emit_test(14,14);
3405 void *jaddr = out;
3406 emit_jeq(0);
3407 emit_readword(&pcaddr, 0);
3408 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3409 emit_far_call(ndrc_get_addr_ht);
3410 emit_jmpreg(0);
3411 set_jump_target(jaddr, out);
3412 }
3413 emit_loadreg(dops[i].rs1,s);
3414 }
3415 else
3416 {
3417 assert(dops[i].opcode2==0x10);
3418 //if((source[i]&0x3f)==0x10) // RFE
3419 {
3420 emit_readword(&Status,0);
3421 emit_andimm(0,0x3c,1);
3422 emit_andimm(0,~0xf,0);
3423 emit_orrshr_imm(1,2,0);
3424 emit_writeword(0,&Status);
3425 }
3426 }
3427}
3428
3429static void cop1_unusable(int i, const struct regstat *i_regs)
3430{
3431 // XXX: should just just do the exception instead
3432 //if(!cop1_usable)
3433 {
3434 void *jaddr=out;
3435 emit_jmp(0);
3436 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3437 }
3438}
3439
3440static void cop1_assemble(int i, const struct regstat *i_regs)
3441{
3442 cop1_unusable(i, i_regs);
3443}
3444
3445static void c1ls_assemble(int i, const struct regstat *i_regs)
3446{
3447 cop1_unusable(i, i_regs);
3448}
3449
3450// FP_STUB
3451static void do_cop1stub(int n)
3452{
3453 literal_pool(256);
3454 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3455 set_jump_target(stubs[n].addr, out);
3456 int i=stubs[n].a;
3457// int rs=stubs[n].b;
3458 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3459 int ds=stubs[n].d;
3460 if(!ds) {
3461 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3462 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3463 }
3464 //else {printf("fp exception in delay slot\n");}
3465 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3466 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3467 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3468 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3469 emit_far_jump(ds?fp_exception_ds:fp_exception);
3470}
3471
3472static int cop2_is_stalling_op(int i, int *cycles)
3473{
3474 if (dops[i].opcode == 0x3a) { // SWC2
3475 *cycles = 0;
3476 return 1;
3477 }
3478 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3479 *cycles = 0;
3480 return 1;
3481 }
3482 if (dops[i].itype == C2OP) {
3483 *cycles = gte_cycletab[source[i] & 0x3f];
3484 return 1;
3485 }
3486 // ... what about MTC2/CTC2/LWC2?
3487 return 0;
3488}
3489
3490#if 0
3491static void log_gte_stall(int stall, u_int cycle)
3492{
3493 if ((u_int)stall <= 44)
3494 printf("x stall %2d %u\n", stall, cycle + last_count);
3495}
3496
3497static void emit_log_gte_stall(int i, int stall, u_int reglist)
3498{
3499 save_regs(reglist);
3500 if (stall > 0)
3501 emit_movimm(stall, 0);
3502 else
3503 emit_mov(HOST_TEMPREG, 0);
3504 emit_addimm(HOST_CCREG, ccadj[i], 1);
3505 emit_far_call(log_gte_stall);
3506 restore_regs(reglist);
3507}
3508#endif
3509
3510static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3511{
3512 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3513 int rtmp = reglist_find_free(reglist);
3514
3515 if (HACK_ENABLED(NDHACK_NO_STALLS))
3516 return;
3517 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3518 // happens occasionally... cc evicted? Don't bother then
3519 //printf("no cc %08x\n", start + i*4);
3520 return;
3521 }
3522 if (!dops[i].bt) {
3523 for (j = i - 1; j >= 0; j--) {
3524 //if (dops[j].is_ds) break;
3525 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3526 break;
3527 if (j > 0 && ccadj[j - 1] > ccadj[j])
3528 break;
3529 }
3530 j = max(j, 0);
3531 }
3532 cycles_passed = ccadj[i] - ccadj[j];
3533 if (other_gte_op_cycles >= 0)
3534 stall = other_gte_op_cycles - cycles_passed;
3535 else if (cycles_passed >= 44)
3536 stall = 0; // can't stall
3537 if (stall == -MAXBLOCK && rtmp >= 0) {
3538 // unknown stall, do the expensive runtime check
3539 assem_debug("; cop2_do_stall_check\n");
3540#if 0 // too slow
3541 save_regs(reglist);
3542 emit_movimm(gte_cycletab[op], 0);
3543 emit_addimm(HOST_CCREG, ccadj[i], 1);
3544 emit_far_call(call_gteStall);
3545 restore_regs(reglist);
3546#else
3547 host_tempreg_acquire();
3548 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3549 emit_addimm(rtmp, -ccadj[i], rtmp);
3550 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3551 emit_cmpimm(HOST_TEMPREG, 44);
3552 emit_cmovb_reg(rtmp, HOST_CCREG);
3553 //emit_log_gte_stall(i, 0, reglist);
3554 host_tempreg_release();
3555#endif
3556 }
3557 else if (stall > 0) {
3558 //emit_log_gte_stall(i, stall, reglist);
3559 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3560 }
3561
3562 // save gteBusyCycle, if needed
3563 if (gte_cycletab[op] == 0)
3564 return;
3565 other_gte_op_cycles = -1;
3566 for (j = i + 1; j < slen; j++) {
3567 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3568 break;
3569 if (dops[j].is_jump) {
3570 // check ds
3571 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3572 j++;
3573 break;
3574 }
3575 }
3576 if (other_gte_op_cycles >= 0)
3577 // will handle stall when assembling that op
3578 return;
3579 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3580 if (cycles_passed >= 44)
3581 return;
3582 assem_debug("; save gteBusyCycle\n");
3583 host_tempreg_acquire();
3584#if 0
3585 emit_readword(&last_count, HOST_TEMPREG);
3586 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3587 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3588 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3589 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3590#else
3591 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3592 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3593#endif
3594 host_tempreg_release();
3595}
3596
3597static int is_mflohi(int i)
3598{
3599 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3600}
3601
3602static int check_multdiv(int i, int *cycles)
3603{
3604 if (dops[i].itype != MULTDIV)
3605 return 0;
3606 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3607 *cycles = 11; // approx from 7 11 14
3608 else
3609 *cycles = 37;
3610 return 1;
3611}
3612
3613static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3614{
3615 int j, found = 0, c = 0;
3616 if (HACK_ENABLED(NDHACK_NO_STALLS))
3617 return;
3618 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3619 // happens occasionally... cc evicted? Don't bother then
3620 return;
3621 }
3622 for (j = i + 1; j < slen; j++) {
3623 if (dops[j].bt)
3624 break;
3625 if ((found = is_mflohi(j)))
3626 break;
3627 if (dops[j].is_jump) {
3628 // check ds
3629 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3630 j++;
3631 break;
3632 }
3633 }
3634 if (found)
3635 // handle all in multdiv_do_stall()
3636 return;
3637 check_multdiv(i, &c);
3638 assert(c > 0);
3639 assem_debug("; muldiv prepare stall %d\n", c);
3640 host_tempreg_acquire();
3641 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3642 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3643 host_tempreg_release();
3644}
3645
3646static void multdiv_do_stall(int i, const struct regstat *i_regs)
3647{
3648 int j, known_cycles = 0;
3649 u_int reglist = get_host_reglist(i_regs->regmap);
3650 int rtmp = get_reg_temp(i_regs->regmap);
3651 if (rtmp < 0)
3652 rtmp = reglist_find_free(reglist);
3653 if (HACK_ENABLED(NDHACK_NO_STALLS))
3654 return;
3655 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3656 // happens occasionally... cc evicted? Don't bother then
3657 //printf("no cc/rtmp %08x\n", start + i*4);
3658 return;
3659 }
3660 if (!dops[i].bt) {
3661 for (j = i - 1; j >= 0; j--) {
3662 if (dops[j].is_ds) break;
3663 if (check_multdiv(j, &known_cycles))
3664 break;
3665 if (is_mflohi(j))
3666 // already handled by this op
3667 return;
3668 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3669 break;
3670 }
3671 j = max(j, 0);
3672 }
3673 if (known_cycles > 0) {
3674 known_cycles -= ccadj[i] - ccadj[j];
3675 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3676 if (known_cycles > 0)
3677 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3678 return;
3679 }
3680 assem_debug("; muldiv stall unresolved\n");
3681 host_tempreg_acquire();
3682 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3683 emit_addimm(rtmp, -ccadj[i], rtmp);
3684 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3685 emit_cmpimm(HOST_TEMPREG, 37);
3686 emit_cmovb_reg(rtmp, HOST_CCREG);
3687 //emit_log_gte_stall(i, 0, reglist);
3688 host_tempreg_release();
3689}
3690
3691static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3692{
3693 switch (copr) {
3694 case 1:
3695 case 3:
3696 case 5:
3697 case 8:
3698 case 9:
3699 case 10:
3700 case 11:
3701 emit_readword(&reg_cop2d[copr],tl);
3702 emit_signextend16(tl,tl);
3703 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3704 break;
3705 case 7:
3706 case 16:
3707 case 17:
3708 case 18:
3709 case 19:
3710 emit_readword(&reg_cop2d[copr],tl);
3711 emit_andimm(tl,0xffff,tl);
3712 emit_writeword(tl,&reg_cop2d[copr]);
3713 break;
3714 case 15:
3715 emit_readword(&reg_cop2d[14],tl); // SXY2
3716 emit_writeword(tl,&reg_cop2d[copr]);
3717 break;
3718 case 28:
3719 case 29:
3720 c2op_mfc2_29_assemble(tl,temp);
3721 break;
3722 default:
3723 emit_readword(&reg_cop2d[copr],tl);
3724 break;
3725 }
3726}
3727
3728static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3729{
3730 switch (copr) {
3731 case 15:
3732 emit_readword(&reg_cop2d[13],temp); // SXY1
3733 emit_writeword(sl,&reg_cop2d[copr]);
3734 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3735 emit_readword(&reg_cop2d[14],temp); // SXY2
3736 emit_writeword(sl,&reg_cop2d[14]);
3737 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3738 break;
3739 case 28:
3740 emit_andimm(sl,0x001f,temp);
3741 emit_shlimm(temp,7,temp);
3742 emit_writeword(temp,&reg_cop2d[9]);
3743 emit_andimm(sl,0x03e0,temp);
3744 emit_shlimm(temp,2,temp);
3745 emit_writeword(temp,&reg_cop2d[10]);
3746 emit_andimm(sl,0x7c00,temp);
3747 emit_shrimm(temp,3,temp);
3748 emit_writeword(temp,&reg_cop2d[11]);
3749 emit_writeword(sl,&reg_cop2d[28]);
3750 break;
3751 case 30:
3752 emit_xorsar_imm(sl,sl,31,temp);
3753#if defined(HAVE_ARMV5) || defined(__aarch64__)
3754 emit_clz(temp,temp);
3755#else
3756 emit_movs(temp,HOST_TEMPREG);
3757 emit_movimm(0,temp);
3758 emit_jeq((int)out+4*4);
3759 emit_addpl_imm(temp,1,temp);
3760 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3761 emit_jns((int)out-2*4);
3762#endif
3763 emit_writeword(sl,&reg_cop2d[30]);
3764 emit_writeword(temp,&reg_cop2d[31]);
3765 break;
3766 case 31:
3767 break;
3768 default:
3769 emit_writeword(sl,&reg_cop2d[copr]);
3770 break;
3771 }
3772}
3773
3774static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3775{
3776 int s,tl;
3777 int ar;
3778 int offset;
3779 int memtarget=0,c=0;
3780 void *jaddr2=NULL;
3781 enum stub_type type;
3782 int agr=AGEN1+(i&1);
3783 int offset_reg = -1;
3784 int fastio_reg_override = -1;
3785 u_int reglist=get_host_reglist(i_regs->regmap);
3786 u_int copr=(source[i]>>16)&0x1f;
3787 s=get_reg(i_regs->regmap,dops[i].rs1);
3788 tl=get_reg(i_regs->regmap,FTEMP);
3789 offset=imm[i];
3790 assert(dops[i].rs1>0);
3791 assert(tl>=0);
3792
3793 if(i_regs->regmap[HOST_CCREG]==CCREG)
3794 reglist&=~(1<<HOST_CCREG);
3795
3796 // get the address
3797 if (dops[i].opcode==0x3a) { // SWC2
3798 ar=get_reg(i_regs->regmap,agr);
3799 if(ar<0) ar=get_reg_temp(i_regs->regmap);
3800 reglist|=1<<ar;
3801 } else { // LWC2
3802 ar=tl;
3803 }
3804 if(s>=0) c=(i_regs->wasconst>>s)&1;
3805 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3806 if (!offset&&!c&&s>=0) ar=s;
3807 assert(ar>=0);
3808
3809 cop2_do_stall_check(0, i, i_regs, reglist);
3810
3811 if (dops[i].opcode==0x3a) { // SWC2
3812 cop2_get_dreg(copr,tl,-1);
3813 type=STOREW_STUB;
3814 }
3815 else
3816 type=LOADW_STUB;
3817
3818 if(c&&!memtarget) {
3819 jaddr2=out;
3820 emit_jmp(0); // inline_readstub/inline_writestub?
3821 }
3822 else {
3823 if(!c) {
3824 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3825 &offset_reg, &fastio_reg_override);
3826 }
3827 else if (ram_offset && memtarget) {
3828 offset_reg = get_ro_reg(i_regs, 0);
3829 }
3830 switch (dops[i].opcode) {
3831 case 0x32: { // LWC2
3832 int a = ar;
3833 if (fastio_reg_override >= 0)
3834 a = fastio_reg_override;
3835 do_load_word(a, tl, offset_reg);
3836 break;
3837 }
3838 case 0x3a: { // SWC2
3839 #ifdef DESTRUCTIVE_SHIFT
3840 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3841 #endif
3842 int a = ar;
3843 if (fastio_reg_override >= 0)
3844 a = fastio_reg_override;
3845 do_store_word(a, 0, tl, offset_reg, 1);
3846 break;
3847 }
3848 default:
3849 assert(0);
3850 }
3851 }
3852 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3853 host_tempreg_release();
3854 if(jaddr2)
3855 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3856 if(dops[i].opcode==0x3a) // SWC2
3857 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3858#if defined(HOST_IMM8)
3859 int ir=get_reg(i_regs->regmap,INVCP);
3860 assert(ir>=0);
3861 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3862#else
3863 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3864#endif
3865 #ifdef INVALIDATE_USE_COND_CALL
3866 emit_callne(invalidate_addr_reg[ar]);
3867 #else
3868 void *jaddr3 = out;
3869 emit_jne(0);
3870 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3871 #endif
3872 }
3873 if (dops[i].opcode==0x32) { // LWC2
3874 host_tempreg_acquire();
3875 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3876 host_tempreg_release();
3877 }
3878}
3879
3880static void cop2_assemble(int i, const struct regstat *i_regs)
3881{
3882 u_int copr = (source[i]>>11) & 0x1f;
3883 signed char temp = get_reg_temp(i_regs->regmap);
3884
3885 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3886 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3887 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3888 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3889 reglist = reglist_exclude(reglist, tl, -1);
3890 }
3891 cop2_do_stall_check(0, i, i_regs, reglist);
3892 }
3893 if (dops[i].opcode2==0) { // MFC2
3894 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3895 if(tl>=0&&dops[i].rt1!=0)
3896 cop2_get_dreg(copr,tl,temp);
3897 }
3898 else if (dops[i].opcode2==4) { // MTC2
3899 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3900 cop2_put_dreg(copr,sl,temp);
3901 }
3902 else if (dops[i].opcode2==2) // CFC2
3903 {
3904 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3905 if(tl>=0&&dops[i].rt1!=0)
3906 emit_readword(&reg_cop2c[copr],tl);
3907 }
3908 else if (dops[i].opcode2==6) // CTC2
3909 {
3910 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3911 switch(copr) {
3912 case 4:
3913 case 12:
3914 case 20:
3915 case 26:
3916 case 27:
3917 case 29:
3918 case 30:
3919 emit_signextend16(sl,temp);
3920 break;
3921 case 31:
3922 c2op_ctc2_31_assemble(sl,temp);
3923 break;
3924 default:
3925 temp=sl;
3926 break;
3927 }
3928 emit_writeword(temp,&reg_cop2c[copr]);
3929 assert(sl>=0);
3930 }
3931}
3932
3933static void do_unalignedwritestub(int n)
3934{
3935 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3936 literal_pool(256);
3937 set_jump_target(stubs[n].addr, out);
3938
3939 int i=stubs[n].a;
3940 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3941 int addr=stubs[n].b;
3942 u_int reglist=stubs[n].e;
3943 signed char *i_regmap=i_regs->regmap;
3944 int temp2=get_reg(i_regmap,FTEMP);
3945 int rt;
3946 rt=get_reg(i_regmap,dops[i].rs2);
3947 assert(rt>=0);
3948 assert(addr>=0);
3949 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3950 reglist|=(1<<addr);
3951 reglist&=~(1<<temp2);
3952
3953 // don't bother with it and call write handler
3954 save_regs(reglist);
3955 pass_args(addr,rt);
3956 int cc=get_reg(i_regmap,CCREG);
3957 if(cc<0)
3958 emit_loadreg(CCREG,2);
3959 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
3960 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3961 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
3962 if(cc<0)
3963 emit_storereg(CCREG,2);
3964 restore_regs(reglist);
3965 emit_jmp(stubs[n].retaddr); // return address
3966}
3967
3968#ifndef multdiv_assemble
3969void multdiv_assemble(int i,struct regstat *i_regs)
3970{
3971 printf("Need multdiv_assemble for this architecture.\n");
3972 abort();
3973}
3974#endif
3975
3976static void mov_assemble(int i, const struct regstat *i_regs)
3977{
3978 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3979 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3980 if(dops[i].rt1) {
3981 signed char sl,tl;
3982 tl=get_reg(i_regs->regmap,dops[i].rt1);
3983 //assert(tl>=0);
3984 if(tl>=0) {
3985 sl=get_reg(i_regs->regmap,dops[i].rs1);
3986 if(sl>=0) emit_mov(sl,tl);
3987 else emit_loadreg(dops[i].rs1,tl);
3988 }
3989 }
3990 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3991 multdiv_do_stall(i, i_regs);
3992}
3993
3994// call interpreter, exception handler, things that change pc/regs/cycles ...
3995static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
3996{
3997 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3998 assert(ccreg==HOST_CCREG);
3999 assert(!is_delayslot);
4000 (void)ccreg;
4001
4002 emit_movimm(pc,3); // Get PC
4003 emit_readword(&last_count,2);
4004 emit_writeword(3,&psxRegs.pc);
4005 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4006 emit_add(2,HOST_CCREG,2);
4007 emit_writeword(2,&psxRegs.cycle);
4008 emit_far_call(func);
4009 emit_far_jump(jump_to_new_pc);
4010}
4011
4012static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4013{
4014 // 'break' tends to be littered around to catch things like
4015 // division by 0 and is almost never executed, so don't emit much code here
4016 void *func = (dops[i].opcode2 == 0x0C)
4017 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
4018 : (is_delayslot ? jump_break_ds : jump_break);
4019 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
4020 emit_movimm(start + i*4, 2); // pc
4021 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4022 emit_far_jump(func);
4023}
4024
4025static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4026{
4027 void *hlefunc = psxNULL;
4028 uint32_t hleCode = source[i] & 0x03ffffff;
4029 if (hleCode < ARRAY_SIZE(psxHLEt))
4030 hlefunc = psxHLEt[hleCode];
4031
4032 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4033}
4034
4035static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4036{
4037 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4038}
4039
4040static void speculate_mov(int rs,int rt)
4041{
4042 if(rt!=0) {
4043 smrv_strong_next|=1<<rt;
4044 smrv[rt]=smrv[rs];
4045 }
4046}
4047
4048static void speculate_mov_weak(int rs,int rt)
4049{
4050 if(rt!=0) {
4051 smrv_weak_next|=1<<rt;
4052 smrv[rt]=smrv[rs];
4053 }
4054}
4055
4056static void speculate_register_values(int i)
4057{
4058 if(i==0) {
4059 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4060 // gp,sp are likely to stay the same throughout the block
4061 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4062 smrv_weak_next=~smrv_strong_next;
4063 //printf(" llr %08x\n", smrv[4]);
4064 }
4065 smrv_strong=smrv_strong_next;
4066 smrv_weak=smrv_weak_next;
4067 switch(dops[i].itype) {
4068 case ALU:
4069 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4070 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4071 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4072 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4073 else {
4074 smrv_strong_next&=~(1<<dops[i].rt1);
4075 smrv_weak_next&=~(1<<dops[i].rt1);
4076 }
4077 break;
4078 case SHIFTIMM:
4079 smrv_strong_next&=~(1<<dops[i].rt1);
4080 smrv_weak_next&=~(1<<dops[i].rt1);
4081 // fallthrough
4082 case IMM16:
4083 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4084 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
4085 if(hr>=0) {
4086 if(get_final_value(hr,i,&value))
4087 smrv[dops[i].rt1]=value;
4088 else smrv[dops[i].rt1]=constmap[i][hr];
4089 smrv_strong_next|=1<<dops[i].rt1;
4090 }
4091 }
4092 else {
4093 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4094 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4095 }
4096 break;
4097 case LOAD:
4098 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4099 // special case for BIOS
4100 smrv[dops[i].rt1]=0xa0000000;
4101 smrv_strong_next|=1<<dops[i].rt1;
4102 break;
4103 }
4104 // fallthrough
4105 case SHIFT:
4106 case LOADLR:
4107 case MOV:
4108 smrv_strong_next&=~(1<<dops[i].rt1);
4109 smrv_weak_next&=~(1<<dops[i].rt1);
4110 break;
4111 case COP0:
4112 case COP2:
4113 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4114 smrv_strong_next&=~(1<<dops[i].rt1);
4115 smrv_weak_next&=~(1<<dops[i].rt1);
4116 }
4117 break;
4118 case C2LS:
4119 if (dops[i].opcode==0x32) { // LWC2
4120 smrv_strong_next&=~(1<<dops[i].rt1);
4121 smrv_weak_next&=~(1<<dops[i].rt1);
4122 }
4123 break;
4124 }
4125#if 0
4126 int r=4;
4127 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4128 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4129#endif
4130}
4131
4132static void ujump_assemble(int i, const struct regstat *i_regs);
4133static void rjump_assemble(int i, const struct regstat *i_regs);
4134static void cjump_assemble(int i, const struct regstat *i_regs);
4135static void sjump_assemble(int i, const struct regstat *i_regs);
4136
4137static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4138{
4139 int ds = 0;
4140 switch (dops[i].itype) {
4141 case ALU:
4142 alu_assemble(i, i_regs);
4143 break;
4144 case IMM16:
4145 imm16_assemble(i, i_regs);
4146 break;
4147 case SHIFT:
4148 shift_assemble(i, i_regs);
4149 break;
4150 case SHIFTIMM:
4151 shiftimm_assemble(i, i_regs);
4152 break;
4153 case LOAD:
4154 load_assemble(i, i_regs, ccadj_);
4155 break;
4156 case LOADLR:
4157 loadlr_assemble(i, i_regs, ccadj_);
4158 break;
4159 case STORE:
4160 store_assemble(i, i_regs, ccadj_);
4161 break;
4162 case STORELR:
4163 storelr_assemble(i, i_regs, ccadj_);
4164 break;
4165 case COP0:
4166 cop0_assemble(i, i_regs, ccadj_);
4167 break;
4168 case COP1:
4169 cop1_assemble(i, i_regs);
4170 break;
4171 case C1LS:
4172 c1ls_assemble(i, i_regs);
4173 break;
4174 case COP2:
4175 cop2_assemble(i, i_regs);
4176 break;
4177 case C2LS:
4178 c2ls_assemble(i, i_regs, ccadj_);
4179 break;
4180 case C2OP:
4181 c2op_assemble(i, i_regs);
4182 break;
4183 case MULTDIV:
4184 multdiv_assemble(i, i_regs);
4185 multdiv_prepare_stall(i, i_regs, ccadj_);
4186 break;
4187 case MOV:
4188 mov_assemble(i, i_regs);
4189 break;
4190 case SYSCALL:
4191 syscall_assemble(i, i_regs, ccadj_);
4192 break;
4193 case HLECALL:
4194 hlecall_assemble(i, i_regs, ccadj_);
4195 break;
4196 case INTCALL:
4197 intcall_assemble(i, i_regs, ccadj_);
4198 break;
4199 case UJUMP:
4200 ujump_assemble(i, i_regs);
4201 ds = 1;
4202 break;
4203 case RJUMP:
4204 rjump_assemble(i, i_regs);
4205 ds = 1;
4206 break;
4207 case CJUMP:
4208 cjump_assemble(i, i_regs);
4209 ds = 1;
4210 break;
4211 case SJUMP:
4212 sjump_assemble(i, i_regs);
4213 ds = 1;
4214 break;
4215 case NOP:
4216 case OTHER:
4217 case NI:
4218 // not handled, just skip
4219 break;
4220 default:
4221 assert(0);
4222 }
4223 return ds;
4224}
4225
4226static void ds_assemble(int i, const struct regstat *i_regs)
4227{
4228 speculate_register_values(i);
4229 is_delayslot = 1;
4230 switch (dops[i].itype) {
4231 case SYSCALL:
4232 case HLECALL:
4233 case INTCALL:
4234 case UJUMP:
4235 case RJUMP:
4236 case CJUMP:
4237 case SJUMP:
4238 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4239 break;
4240 default:
4241 assemble(i, i_regs, ccadj[i]);
4242 }
4243 is_delayslot = 0;
4244}
4245
4246// Is the branch target a valid internal jump?
4247static int internal_branch(int addr)
4248{
4249 if(addr&1) return 0; // Indirect (register) jump
4250 if(addr>=start && addr<start+slen*4-4)
4251 {
4252 return 1;
4253 }
4254 return 0;
4255}
4256
4257static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4258{
4259 int hr;
4260 for(hr=0;hr<HOST_REGS;hr++) {
4261 if(hr!=EXCLUDE_REG) {
4262 if(pre[hr]!=entry[hr]) {
4263 if(pre[hr]>=0) {
4264 if((dirty>>hr)&1) {
4265 if(get_reg(entry,pre[hr])<0) {
4266 assert(pre[hr]<64);
4267 if(!((u>>pre[hr])&1))
4268 emit_storereg(pre[hr],hr);
4269 }
4270 }
4271 }
4272 }
4273 }
4274 }
4275 // Move from one register to another (no writeback)
4276 for(hr=0;hr<HOST_REGS;hr++) {
4277 if(hr!=EXCLUDE_REG) {
4278 if(pre[hr]!=entry[hr]) {
4279 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4280 int nr;
4281 if((nr=get_reg(entry,pre[hr]))>=0) {
4282 emit_mov(hr,nr);
4283 }
4284 }
4285 }
4286 }
4287 }
4288}
4289
4290// Load the specified registers
4291// This only loads the registers given as arguments because
4292// we don't want to load things that will be overwritten
4293static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4294{
4295 int hr = get_reg(regmap, rs);
4296 if (hr >= 0 && entry[hr] != regmap[hr])
4297 emit_loadreg(regmap[hr], hr);
4298}
4299
4300static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4301{
4302 load_reg(entry, regmap, rs1);
4303 if (rs1 != rs2)
4304 load_reg(entry, regmap, rs2);
4305}
4306
4307// Load registers prior to the start of a loop
4308// so that they are not loaded within the loop
4309static void loop_preload(signed char pre[],signed char entry[])
4310{
4311 int hr;
4312 for (hr = 0; hr < HOST_REGS; hr++) {
4313 int r = entry[hr];
4314 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4315 assem_debug("loop preload:\n");
4316 if (r < TEMPREG)
4317 emit_loadreg(r, hr);
4318 }
4319 }
4320}
4321
4322// Generate address for load/store instruction
4323// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4324static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4325{
4326 if (dops[i].is_load || dops[i].is_store) {
4327 int ra=-1;
4328 int agr=AGEN1+(i&1);
4329 if(dops[i].itype==LOAD) {
4330 ra=get_reg(i_regs->regmap,dops[i].rt1);
4331 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4332 assert(ra>=0);
4333 }
4334 if(dops[i].itype==LOADLR) {
4335 ra=get_reg(i_regs->regmap,FTEMP);
4336 }
4337 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4338 ra=get_reg(i_regs->regmap,agr);
4339 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4340 }
4341 if(dops[i].itype==C2LS) {
4342 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4343 ra=get_reg(i_regs->regmap,FTEMP);
4344 else { // SWC1/SDC1/SWC2/SDC2
4345 ra=get_reg(i_regs->regmap,agr);
4346 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4347 }
4348 }
4349 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4350 if(ra>=0) {
4351 int offset=imm[i];
4352 int c=(i_regs->wasconst>>rs)&1;
4353 if(dops[i].rs1==0) {
4354 // Using r0 as a base address
4355 if(!entry||entry[ra]!=agr) {
4356 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4357 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4358 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4359 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4360 }else{
4361 emit_movimm(offset,ra);
4362 }
4363 } // else did it in the previous cycle
4364 }
4365 else if(rs<0) {
4366 if(!entry||entry[ra]!=dops[i].rs1)
4367 emit_loadreg(dops[i].rs1,ra);
4368 //if(!entry||entry[ra]!=dops[i].rs1)
4369 // printf("poor load scheduling!\n");
4370 }
4371 else if(c) {
4372 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4373 if(!entry||entry[ra]!=agr) {
4374 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4375 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4376 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4377 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4378 }else{
4379 emit_movimm(constmap[i][rs]+offset,ra);
4380 regs[i].loadedconst|=1<<ra;
4381 }
4382 } // else did it in the previous cycle
4383 } // else load_consts already did it
4384 }
4385 if(offset&&!c&&dops[i].rs1) {
4386 if(rs>=0) {
4387 emit_addimm(rs,offset,ra);
4388 }else{
4389 emit_addimm(ra,offset,ra);
4390 }
4391 }
4392 }
4393 }
4394 // Preload constants for next instruction
4395 if (dops[i+1].is_load || dops[i+1].is_store) {
4396 int agr,ra;
4397 // Actual address
4398 agr=AGEN1+((i+1)&1);
4399 ra=get_reg(i_regs->regmap,agr);
4400 if(ra>=0) {
4401 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4402 int offset=imm[i+1];
4403 int c=(regs[i+1].wasconst>>rs)&1;
4404 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4405 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4406 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4407 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4408 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4409 }else{
4410 emit_movimm(constmap[i+1][rs]+offset,ra);
4411 regs[i+1].loadedconst|=1<<ra;
4412 }
4413 }
4414 else if(dops[i+1].rs1==0) {
4415 // Using r0 as a base address
4416 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4417 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4418 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4419 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4420 }else{
4421 emit_movimm(offset,ra);
4422 }
4423 }
4424 }
4425 }
4426}
4427
4428static int get_final_value(int hr, int i, int *value)
4429{
4430 int reg=regs[i].regmap[hr];
4431 while(i<slen-1) {
4432 if(regs[i+1].regmap[hr]!=reg) break;
4433 if(!((regs[i+1].isconst>>hr)&1)) break;
4434 if(dops[i+1].bt) break;
4435 i++;
4436 }
4437 if(i<slen-1) {
4438 if (dops[i].is_jump) {
4439 *value=constmap[i][hr];
4440 return 1;
4441 }
4442 if(!dops[i+1].bt) {
4443 if (dops[i+1].is_jump) {
4444 // Load in delay slot, out-of-order execution
4445 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4446 {
4447 // Precompute load address
4448 *value=constmap[i][hr]+imm[i+2];
4449 return 1;
4450 }
4451 }
4452 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4453 {
4454 // Precompute load address
4455 *value=constmap[i][hr]+imm[i+1];
4456 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4457 return 1;
4458 }
4459 }
4460 }
4461 *value=constmap[i][hr];
4462 //printf("c=%lx\n",(long)constmap[i][hr]);
4463 if(i==slen-1) return 1;
4464 assert(reg < 64);
4465 return !((unneeded_reg[i+1]>>reg)&1);
4466}
4467
4468// Load registers with known constants
4469static void load_consts(signed char pre[],signed char regmap[],int i)
4470{
4471 int hr,hr2;
4472 // propagate loaded constant flags
4473 if(i==0||dops[i].bt)
4474 regs[i].loadedconst=0;
4475 else {
4476 for(hr=0;hr<HOST_REGS;hr++) {
4477 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4478 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4479 {
4480 regs[i].loadedconst|=1<<hr;
4481 }
4482 }
4483 }
4484 // Load 32-bit regs
4485 for(hr=0;hr<HOST_REGS;hr++) {
4486 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4487 //if(entry[hr]!=regmap[hr]) {
4488 if(!((regs[i].loadedconst>>hr)&1)) {
4489 assert(regmap[hr]<64);
4490 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4491 int value,similar=0;
4492 if(get_final_value(hr,i,&value)) {
4493 // see if some other register has similar value
4494 for(hr2=0;hr2<HOST_REGS;hr2++) {
4495 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4496 if(is_similar_value(value,constmap[i][hr2])) {
4497 similar=1;
4498 break;
4499 }
4500 }
4501 }
4502 if(similar) {
4503 int value2;
4504 if(get_final_value(hr2,i,&value2)) // is this needed?
4505 emit_movimm_from(value2,hr2,value,hr);
4506 else
4507 emit_movimm(value,hr);
4508 }
4509 else if(value==0) {
4510 emit_zeroreg(hr);
4511 }
4512 else {
4513 emit_movimm(value,hr);
4514 }
4515 }
4516 regs[i].loadedconst|=1<<hr;
4517 }
4518 }
4519 }
4520 }
4521}
4522
4523static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4524{
4525 int hr;
4526 // Load 32-bit regs
4527 for(hr=0;hr<HOST_REGS;hr++) {
4528 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4529 assert(regmap[hr] < 64);
4530 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4531 int value=constmap[i][hr];
4532 if(value==0) {
4533 emit_zeroreg(hr);
4534 }
4535 else {
4536 emit_movimm(value,hr);
4537 }
4538 }
4539 }
4540 }
4541}
4542
4543// Write out all dirty registers (except cycle count)
4544static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4545{
4546 int hr;
4547 for(hr=0;hr<HOST_REGS;hr++) {
4548 if(hr!=EXCLUDE_REG) {
4549 if(i_regmap[hr]>0) {
4550 if(i_regmap[hr]!=CCREG) {
4551 if((i_dirty>>hr)&1) {
4552 assert(i_regmap[hr]<64);
4553 emit_storereg(i_regmap[hr],hr);
4554 }
4555 }
4556 }
4557 }
4558 }
4559}
4560
4561// Write out dirty registers that we need to reload (pair with load_needed_regs)
4562// This writes the registers not written by store_regs_bt
4563static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4564{
4565 int hr;
4566 int t=(addr-start)>>2;
4567 for(hr=0;hr<HOST_REGS;hr++) {
4568 if(hr!=EXCLUDE_REG) {
4569 if(i_regmap[hr]>0) {
4570 if(i_regmap[hr]!=CCREG) {
4571 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4572 if((i_dirty>>hr)&1) {
4573 assert(i_regmap[hr]<64);
4574 emit_storereg(i_regmap[hr],hr);
4575 }
4576 }
4577 }
4578 }
4579 }
4580 }
4581}
4582
4583// Load all registers (except cycle count)
4584static void load_all_regs(const signed char i_regmap[])
4585{
4586 int hr;
4587 for(hr=0;hr<HOST_REGS;hr++) {
4588 if(hr!=EXCLUDE_REG) {
4589 if(i_regmap[hr]==0) {
4590 emit_zeroreg(hr);
4591 }
4592 else
4593 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4594 {
4595 emit_loadreg(i_regmap[hr],hr);
4596 }
4597 }
4598 }
4599}
4600
4601// Load all current registers also needed by next instruction
4602static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4603{
4604 int hr;
4605 for(hr=0;hr<HOST_REGS;hr++) {
4606 if(hr!=EXCLUDE_REG) {
4607 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4608 if(i_regmap[hr]==0) {
4609 emit_zeroreg(hr);
4610 }
4611 else
4612 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4613 {
4614 emit_loadreg(i_regmap[hr],hr);
4615 }
4616 }
4617 }
4618 }
4619}
4620
4621// Load all regs, storing cycle count if necessary
4622static void load_regs_entry(int t)
4623{
4624 int hr;
4625 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4626 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4627 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4628 emit_storereg(CCREG,HOST_CCREG);
4629 }
4630 // Load 32-bit regs
4631 for(hr=0;hr<HOST_REGS;hr++) {
4632 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4633 if(regs[t].regmap_entry[hr]==0) {
4634 emit_zeroreg(hr);
4635 }
4636 else if(regs[t].regmap_entry[hr]!=CCREG)
4637 {
4638 emit_loadreg(regs[t].regmap_entry[hr],hr);
4639 }
4640 }
4641 }
4642}
4643
4644// Store dirty registers prior to branch
4645static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4646{
4647 if(internal_branch(addr))
4648 {
4649 int t=(addr-start)>>2;
4650 int hr;
4651 for(hr=0;hr<HOST_REGS;hr++) {
4652 if(hr!=EXCLUDE_REG) {
4653 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4654 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4655 if((i_dirty>>hr)&1) {
4656 assert(i_regmap[hr]<64);
4657 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4658 emit_storereg(i_regmap[hr],hr);
4659 }
4660 }
4661 }
4662 }
4663 }
4664 }
4665 else
4666 {
4667 // Branch out of this block, write out all dirty regs
4668 wb_dirtys(i_regmap,i_dirty);
4669 }
4670}
4671
4672// Load all needed registers for branch target
4673static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4674{
4675 //if(addr>=start && addr<(start+slen*4))
4676 if(internal_branch(addr))
4677 {
4678 int t=(addr-start)>>2;
4679 int hr;
4680 // Store the cycle count before loading something else
4681 if(i_regmap[HOST_CCREG]!=CCREG) {
4682 assert(i_regmap[HOST_CCREG]==-1);
4683 }
4684 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4685 emit_storereg(CCREG,HOST_CCREG);
4686 }
4687 // Load 32-bit regs
4688 for(hr=0;hr<HOST_REGS;hr++) {
4689 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4690 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4691 if(regs[t].regmap_entry[hr]==0) {
4692 emit_zeroreg(hr);
4693 }
4694 else if(regs[t].regmap_entry[hr]!=CCREG)
4695 {
4696 emit_loadreg(regs[t].regmap_entry[hr],hr);
4697 }
4698 }
4699 }
4700 }
4701 }
4702}
4703
4704static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4705{
4706 if(addr>=start && addr<start+slen*4-4)
4707 {
4708 int t=(addr-start)>>2;
4709 int hr;
4710 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4711 for(hr=0;hr<HOST_REGS;hr++)
4712 {
4713 if(hr!=EXCLUDE_REG)
4714 {
4715 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4716 {
4717 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4718 {
4719 return 0;
4720 }
4721 else
4722 if((i_dirty>>hr)&1)
4723 {
4724 if(i_regmap[hr]<TEMPREG)
4725 {
4726 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4727 return 0;
4728 }
4729 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4730 {
4731 assert(0);
4732 }
4733 }
4734 }
4735 else // Same register but is it 32-bit or dirty?
4736 if(i_regmap[hr]>=0)
4737 {
4738 if(!((regs[t].dirty>>hr)&1))
4739 {
4740 if((i_dirty>>hr)&1)
4741 {
4742 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4743 {
4744 //printf("%x: dirty no match\n",addr);
4745 return 0;
4746 }
4747 }
4748 }
4749 }
4750 }
4751 }
4752 // Delay slots are not valid branch targets
4753 //if(t>0&&(dops[t-1].is_jump) return 0;
4754 // Delay slots require additional processing, so do not match
4755 if(dops[t].is_ds) return 0;
4756 }
4757 else
4758 {
4759 int hr;
4760 for(hr=0;hr<HOST_REGS;hr++)
4761 {
4762 if(hr!=EXCLUDE_REG)
4763 {
4764 if(i_regmap[hr]>=0)
4765 {
4766 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4767 {
4768 if((i_dirty>>hr)&1)
4769 {
4770 return 0;
4771 }
4772 }
4773 }
4774 }
4775 }
4776 }
4777 return 1;
4778}
4779
4780#ifdef DRC_DBG
4781static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4782{
4783 extern void do_insn_cmp();
4784 //extern int cycle;
4785 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4786
4787 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4788 save_regs(reglist);
4789 // write out changed consts to match the interpreter
4790 if (i > 0 && !dops[i].bt) {
4791 for (hr = 0; hr < HOST_REGS; hr++) {
4792 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4793 if (hr == EXCLUDE_REG || reg < 0)
4794 continue;
4795 if (!((regs[i-1].isconst >> hr) & 1))
4796 continue;
4797 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4798 continue;
4799 emit_movimm(constmap[i-1][hr],0);
4800 emit_storereg(reg, 0);
4801 }
4802 }
4803 emit_movimm(start+i*4,0);
4804 emit_writeword(0,&pcaddr);
4805 int cc = get_reg(regs[i].regmap_entry, CCREG);
4806 if (cc < 0)
4807 emit_loadreg(CCREG, cc = 0);
4808 emit_addimm(cc, ccadj_, 0);
4809 emit_writeword(0, &psxRegs.cycle);
4810 emit_far_call(do_insn_cmp);
4811 //emit_readword(&cycle,0);
4812 //emit_addimm(0,2,0);
4813 //emit_writeword(0,&cycle);
4814 (void)get_reg2;
4815 restore_regs(reglist);
4816 assem_debug("\\\\do_insn_cmp\n");
4817}
4818#else
4819#define drc_dbg_emit_do_cmp(x,y)
4820#endif
4821
4822// Used when a branch jumps into the delay slot of another branch
4823static void ds_assemble_entry(int i)
4824{
4825 int t = (ba[i] - start) >> 2;
4826 int ccadj_ = -CLOCK_ADJUST(1);
4827 if (!instr_addr[t])
4828 instr_addr[t] = out;
4829 assem_debug("Assemble delay slot at %x\n",ba[i]);
4830 assem_debug("<->\n");
4831 drc_dbg_emit_do_cmp(t, ccadj_);
4832 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4833 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4834 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4835 address_generation(t,&regs[t],regs[t].regmap_entry);
4836 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4837 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4838 if (dops[t].is_store)
4839 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
4840 is_delayslot=0;
4841 switch (dops[t].itype) {
4842 case SYSCALL:
4843 case HLECALL:
4844 case INTCALL:
4845 case UJUMP:
4846 case RJUMP:
4847 case CJUMP:
4848 case SJUMP:
4849 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4850 break;
4851 default:
4852 assemble(t, &regs[t], ccadj_);
4853 }
4854 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4855 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4856 if(internal_branch(ba[i]+4))
4857 assem_debug("branch: internal\n");
4858 else
4859 assem_debug("branch: external\n");
4860 assert(internal_branch(ba[i]+4));
4861 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4862 emit_jmp(0);
4863}
4864
4865// Load 2 immediates optimizing for small code size
4866static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4867{
4868 emit_movimm(imm1,rt1);
4869 emit_movimm_from(imm1,rt1,imm2,rt2);
4870}
4871
4872static void do_cc(int i, const signed char i_regmap[], int *adj,
4873 int addr, int taken, int invert)
4874{
4875 int count, count_plus2;
4876 void *jaddr;
4877 void *idle=NULL;
4878 int t=0;
4879 if(dops[i].itype==RJUMP)
4880 {
4881 *adj=0;
4882 }
4883 //if(ba[i]>=start && ba[i]<(start+slen*4))
4884 if(internal_branch(ba[i]))
4885 {
4886 t=(ba[i]-start)>>2;
4887 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4888 else *adj=ccadj[t];
4889 }
4890 else
4891 {
4892 *adj=0;
4893 }
4894 count = ccadj[i];
4895 count_plus2 = count + CLOCK_ADJUST(2);
4896 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4897 // Idle loop
4898 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4899 idle=out;
4900 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4901 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4902 jaddr=out;
4903 emit_jmp(0);
4904 }
4905 else if(*adj==0||invert) {
4906 int cycles = count_plus2;
4907 // faster loop HACK
4908#if 0
4909 if (t&&*adj) {
4910 int rel=t-i;
4911 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4912 cycles=*adj+count+2-*adj;
4913 }
4914#endif
4915 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4916 jaddr = out;
4917 emit_jns(0);
4918 }
4919 else
4920 {
4921 emit_cmpimm(HOST_CCREG, -count_plus2);
4922 jaddr = out;
4923 emit_jns(0);
4924 }
4925 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4926}
4927
4928static void do_ccstub(int n)
4929{
4930 literal_pool(256);
4931 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4932 set_jump_target(stubs[n].addr, out);
4933 int i=stubs[n].b;
4934 if(stubs[n].d==NULLDS) {
4935 // Delay slot instruction is nullified ("likely" branch)
4936 wb_dirtys(regs[i].regmap,regs[i].dirty);
4937 }
4938 else if(stubs[n].d!=TAKEN) {
4939 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4940 }
4941 else {
4942 if(internal_branch(ba[i]))
4943 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4944 }
4945 if(stubs[n].c!=-1)
4946 {
4947 // Save PC as return address
4948 emit_movimm(stubs[n].c,EAX);
4949 emit_writeword(EAX,&pcaddr);
4950 }
4951 else
4952 {
4953 // Return address depends on which way the branch goes
4954 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4955 {
4956 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4957 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4958 if(dops[i].rs1==0)
4959 {
4960 s1l=s2l;
4961 s2l=-1;
4962 }
4963 else if(dops[i].rs2==0)
4964 {
4965 s2l=-1;
4966 }
4967 assert(s1l>=0);
4968 #ifdef DESTRUCTIVE_WRITEBACK
4969 if(dops[i].rs1) {
4970 if((branch_regs[i].dirty>>s1l)&&1)
4971 emit_loadreg(dops[i].rs1,s1l);
4972 }
4973 else {
4974 if((branch_regs[i].dirty>>s1l)&1)
4975 emit_loadreg(dops[i].rs2,s1l);
4976 }
4977 if(s2l>=0)
4978 if((branch_regs[i].dirty>>s2l)&1)
4979 emit_loadreg(dops[i].rs2,s2l);
4980 #endif
4981 int hr=0;
4982 int addr=-1,alt=-1,ntaddr=-1;
4983 while(hr<HOST_REGS)
4984 {
4985 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4986 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4987 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4988 {
4989 addr=hr++;break;
4990 }
4991 hr++;
4992 }
4993 while(hr<HOST_REGS)
4994 {
4995 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4996 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
4997 branch_regs[i].regmap[hr]!=dops[i].rs2 )
4998 {
4999 alt=hr++;break;
5000 }
5001 hr++;
5002 }
5003 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5004 {
5005 while(hr<HOST_REGS)
5006 {
5007 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5008 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5009 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5010 {
5011 ntaddr=hr;break;
5012 }
5013 hr++;
5014 }
5015 assert(hr<HOST_REGS);
5016 }
5017 if((dops[i].opcode&0x2f)==4) // BEQ
5018 {
5019 #ifdef HAVE_CMOV_IMM
5020 if(s2l>=0) emit_cmp(s1l,s2l);
5021 else emit_test(s1l,s1l);
5022 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5023 #else
5024 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5025 if(s2l>=0) emit_cmp(s1l,s2l);
5026 else emit_test(s1l,s1l);
5027 emit_cmovne_reg(alt,addr);
5028 #endif
5029 }
5030 if((dops[i].opcode&0x2f)==5) // BNE
5031 {
5032 #ifdef HAVE_CMOV_IMM
5033 if(s2l>=0) emit_cmp(s1l,s2l);
5034 else emit_test(s1l,s1l);
5035 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5036 #else
5037 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5038 if(s2l>=0) emit_cmp(s1l,s2l);
5039 else emit_test(s1l,s1l);
5040 emit_cmovne_reg(alt,addr);
5041 #endif
5042 }
5043 if((dops[i].opcode&0x2f)==6) // BLEZ
5044 {
5045 //emit_movimm(ba[i],alt);
5046 //emit_movimm(start+i*4+8,addr);
5047 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5048 emit_cmpimm(s1l,1);
5049 emit_cmovl_reg(alt,addr);
5050 }
5051 if((dops[i].opcode&0x2f)==7) // BGTZ
5052 {
5053 //emit_movimm(ba[i],addr);
5054 //emit_movimm(start+i*4+8,ntaddr);
5055 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5056 emit_cmpimm(s1l,1);
5057 emit_cmovl_reg(ntaddr,addr);
5058 }
5059 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5060 {
5061 //emit_movimm(ba[i],alt);
5062 //emit_movimm(start+i*4+8,addr);
5063 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5064 emit_test(s1l,s1l);
5065 emit_cmovs_reg(alt,addr);
5066 }
5067 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5068 {
5069 //emit_movimm(ba[i],addr);
5070 //emit_movimm(start+i*4+8,alt);
5071 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5072 emit_test(s1l,s1l);
5073 emit_cmovs_reg(alt,addr);
5074 }
5075 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5076 if(source[i]&0x10000) // BC1T
5077 {
5078 //emit_movimm(ba[i],alt);
5079 //emit_movimm(start+i*4+8,addr);
5080 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5081 emit_testimm(s1l,0x800000);
5082 emit_cmovne_reg(alt,addr);
5083 }
5084 else // BC1F
5085 {
5086 //emit_movimm(ba[i],addr);
5087 //emit_movimm(start+i*4+8,alt);
5088 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5089 emit_testimm(s1l,0x800000);
5090 emit_cmovne_reg(alt,addr);
5091 }
5092 }
5093 emit_writeword(addr,&pcaddr);
5094 }
5095 else
5096 if(dops[i].itype==RJUMP)
5097 {
5098 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5099 if (ds_writes_rjump_rs(i)) {
5100 r=get_reg(branch_regs[i].regmap,RTEMP);
5101 }
5102 emit_writeword(r,&pcaddr);
5103 }
5104 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5105 }
5106 // Update cycle count
5107 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5108 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5109 emit_far_call(cc_interrupt);
5110 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5111 if(stubs[n].d==TAKEN) {
5112 if(internal_branch(ba[i]))
5113 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5114 else if(dops[i].itype==RJUMP) {
5115 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5116 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5117 else
5118 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5119 }
5120 }else if(stubs[n].d==NOTTAKEN) {
5121 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5122 else load_all_regs(branch_regs[i].regmap);
5123 }else if(stubs[n].d==NULLDS) {
5124 // Delay slot instruction is nullified ("likely" branch)
5125 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5126 else load_all_regs(regs[i].regmap);
5127 }else{
5128 load_all_regs(branch_regs[i].regmap);
5129 }
5130 if (stubs[n].retaddr)
5131 emit_jmp(stubs[n].retaddr);
5132 else
5133 do_jump_vaddr(stubs[n].e);
5134}
5135
5136static void add_to_linker(void *addr, u_int target, int is_internal)
5137{
5138 assert(linkcount < ARRAY_SIZE(link_addr));
5139 link_addr[linkcount].addr = addr;
5140 link_addr[linkcount].target = target;
5141 link_addr[linkcount].internal = is_internal;
5142 linkcount++;
5143}
5144
5145static void ujump_assemble_write_ra(int i)
5146{
5147 int rt;
5148 unsigned int return_address;
5149 rt=get_reg(branch_regs[i].regmap,31);
5150 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5151 //assert(rt>=0);
5152 return_address=start+i*4+8;
5153 if(rt>=0) {
5154 #ifdef USE_MINI_HT
5155 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5156 int temp=-1; // note: must be ds-safe
5157 #ifdef HOST_TEMPREG
5158 temp=HOST_TEMPREG;
5159 #endif
5160 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5161 else emit_movimm(return_address,rt);
5162 }
5163 else
5164 #endif
5165 {
5166 #ifdef REG_PREFETCH
5167 if(temp>=0)
5168 {
5169 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5170 }
5171 #endif
5172 emit_movimm(return_address,rt); // PC into link register
5173 #ifdef IMM_PREFETCH
5174 emit_prefetch(hash_table_get(return_address));
5175 #endif
5176 }
5177 }
5178}
5179
5180static void ujump_assemble(int i, const struct regstat *i_regs)
5181{
5182 int ra_done=0;
5183 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5184 address_generation(i+1,i_regs,regs[i].regmap_entry);
5185 #ifdef REG_PREFETCH
5186 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5187 if(dops[i].rt1==31&&temp>=0)
5188 {
5189 signed char *i_regmap=i_regs->regmap;
5190 int return_address=start+i*4+8;
5191 if(get_reg(branch_regs[i].regmap,31)>0)
5192 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5193 }
5194 #endif
5195 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5196 ujump_assemble_write_ra(i); // writeback ra for DS
5197 ra_done=1;
5198 }
5199 ds_assemble(i+1,i_regs);
5200 uint64_t bc_unneeded=branch_regs[i].u;
5201 bc_unneeded|=1|(1LL<<dops[i].rt1);
5202 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5203 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5204 if(!ra_done&&dops[i].rt1==31)
5205 ujump_assemble_write_ra(i);
5206 int cc,adj;
5207 cc=get_reg(branch_regs[i].regmap,CCREG);
5208 assert(cc==HOST_CCREG);
5209 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5210 #ifdef REG_PREFETCH
5211 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5212 #endif
5213 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5214 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5215 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5216 if(internal_branch(ba[i]))
5217 assem_debug("branch: internal\n");
5218 else
5219 assem_debug("branch: external\n");
5220 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5221 ds_assemble_entry(i);
5222 }
5223 else {
5224 add_to_linker(out,ba[i],internal_branch(ba[i]));
5225 emit_jmp(0);
5226 }
5227}
5228
5229static void rjump_assemble_write_ra(int i)
5230{
5231 int rt,return_address;
5232 assert(dops[i+1].rt1!=dops[i].rt1);
5233 assert(dops[i+1].rt2!=dops[i].rt1);
5234 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5235 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5236 assert(rt>=0);
5237 return_address=start+i*4+8;
5238 #ifdef REG_PREFETCH
5239 if(temp>=0)
5240 {
5241 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5242 }
5243 #endif
5244 emit_movimm(return_address,rt); // PC into link register
5245 #ifdef IMM_PREFETCH
5246 emit_prefetch(hash_table_get(return_address));
5247 #endif
5248}
5249
5250static void rjump_assemble(int i, const struct regstat *i_regs)
5251{
5252 int temp;
5253 int rs,cc;
5254 int ra_done=0;
5255 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5256 assert(rs>=0);
5257 if (ds_writes_rjump_rs(i)) {
5258 // Delay slot abuse, make a copy of the branch address register
5259 temp=get_reg(branch_regs[i].regmap,RTEMP);
5260 assert(temp>=0);
5261 assert(regs[i].regmap[temp]==RTEMP);
5262 emit_mov(rs,temp);
5263 rs=temp;
5264 }
5265 address_generation(i+1,i_regs,regs[i].regmap_entry);
5266 #ifdef REG_PREFETCH
5267 if(dops[i].rt1==31)
5268 {
5269 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5270 signed char *i_regmap=i_regs->regmap;
5271 int return_address=start+i*4+8;
5272 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5273 }
5274 }
5275 #endif
5276 #ifdef USE_MINI_HT
5277 if(dops[i].rs1==31) {
5278 int rh=get_reg(regs[i].regmap,RHASH);
5279 if(rh>=0) do_preload_rhash(rh);
5280 }
5281 #endif
5282 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5283 rjump_assemble_write_ra(i);
5284 ra_done=1;
5285 }
5286 ds_assemble(i+1,i_regs);
5287 uint64_t bc_unneeded=branch_regs[i].u;
5288 bc_unneeded|=1|(1LL<<dops[i].rt1);
5289 bc_unneeded&=~(1LL<<dops[i].rs1);
5290 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5291 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5292 if(!ra_done&&dops[i].rt1!=0)
5293 rjump_assemble_write_ra(i);
5294 cc=get_reg(branch_regs[i].regmap,CCREG);
5295 assert(cc==HOST_CCREG);
5296 (void)cc;
5297 #ifdef USE_MINI_HT
5298 int rh=get_reg(branch_regs[i].regmap,RHASH);
5299 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5300 if(dops[i].rs1==31) {
5301 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5302 do_preload_rhtbl(ht);
5303 do_rhash(rs,rh);
5304 }
5305 #endif
5306 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5307 #ifdef DESTRUCTIVE_WRITEBACK
5308 if((branch_regs[i].dirty>>rs)&1) {
5309 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5310 emit_loadreg(dops[i].rs1,rs);
5311 }
5312 }
5313 #endif
5314 #ifdef REG_PREFETCH
5315 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5316 #endif
5317 #ifdef USE_MINI_HT
5318 if(dops[i].rs1==31) {
5319 do_miniht_load(ht,rh);
5320 }
5321 #endif
5322 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5323 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5324 //assert(adj==0);
5325 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5326 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5327 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5328 // special case for RFE
5329 emit_jmp(0);
5330 else
5331 emit_jns(0);
5332 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5333 #ifdef USE_MINI_HT
5334 if(dops[i].rs1==31) {
5335 do_miniht_jump(rs,rh,ht);
5336 }
5337 else
5338 #endif
5339 {
5340 do_jump_vaddr(rs);
5341 }
5342 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5343 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5344 #endif
5345}
5346
5347static void cjump_assemble(int i, const struct regstat *i_regs)
5348{
5349 const signed char *i_regmap = i_regs->regmap;
5350 int cc;
5351 int match;
5352 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5353 assem_debug("match=%d\n",match);
5354 int s1l,s2l;
5355 int unconditional=0,nop=0;
5356 int invert=0;
5357 int internal=internal_branch(ba[i]);
5358 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5359 if(!match) invert=1;
5360 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5361 if(i>(ba[i]-start)>>2) invert=1;
5362 #endif
5363 #ifdef __aarch64__
5364 invert=1; // because of near cond. branches
5365 #endif
5366
5367 if(dops[i].ooo) {
5368 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5369 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5370 }
5371 else {
5372 s1l=get_reg(i_regmap,dops[i].rs1);
5373 s2l=get_reg(i_regmap,dops[i].rs2);
5374 }
5375 if(dops[i].rs1==0&&dops[i].rs2==0)
5376 {
5377 if(dops[i].opcode&1) nop=1;
5378 else unconditional=1;
5379 //assert(dops[i].opcode!=5);
5380 //assert(dops[i].opcode!=7);
5381 //assert(dops[i].opcode!=0x15);
5382 //assert(dops[i].opcode!=0x17);
5383 }
5384 else if(dops[i].rs1==0)
5385 {
5386 s1l=s2l;
5387 s2l=-1;
5388 }
5389 else if(dops[i].rs2==0)
5390 {
5391 s2l=-1;
5392 }
5393
5394 if(dops[i].ooo) {
5395 // Out of order execution (delay slot first)
5396 //printf("OOOE\n");
5397 address_generation(i+1,i_regs,regs[i].regmap_entry);
5398 ds_assemble(i+1,i_regs);
5399 int adj;
5400 uint64_t bc_unneeded=branch_regs[i].u;
5401 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5402 bc_unneeded|=1;
5403 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5404 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5405 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5406 cc=get_reg(branch_regs[i].regmap,CCREG);
5407 assert(cc==HOST_CCREG);
5408 if(unconditional)
5409 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5410 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5411 //assem_debug("cycle count (adj)\n");
5412 if(unconditional) {
5413 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5414 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5415 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5416 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5417 if(internal)
5418 assem_debug("branch: internal\n");
5419 else
5420 assem_debug("branch: external\n");
5421 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5422 ds_assemble_entry(i);
5423 }
5424 else {
5425 add_to_linker(out,ba[i],internal);
5426 emit_jmp(0);
5427 }
5428 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5429 if(((u_int)out)&7) emit_addnop(0);
5430 #endif
5431 }
5432 }
5433 else if(nop) {
5434 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5435 void *jaddr=out;
5436 emit_jns(0);
5437 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5438 }
5439 else {
5440 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5441 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5442 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5443
5444 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5445 assert(s1l>=0);
5446 if(dops[i].opcode==4) // BEQ
5447 {
5448 if(s2l>=0) emit_cmp(s1l,s2l);
5449 else emit_test(s1l,s1l);
5450 if(invert){
5451 nottaken=out;
5452 emit_jne(DJT_1);
5453 }else{
5454 add_to_linker(out,ba[i],internal);
5455 emit_jeq(0);
5456 }
5457 }
5458 if(dops[i].opcode==5) // BNE
5459 {
5460 if(s2l>=0) emit_cmp(s1l,s2l);
5461 else emit_test(s1l,s1l);
5462 if(invert){
5463 nottaken=out;
5464 emit_jeq(DJT_1);
5465 }else{
5466 add_to_linker(out,ba[i],internal);
5467 emit_jne(0);
5468 }
5469 }
5470 if(dops[i].opcode==6) // BLEZ
5471 {
5472 emit_cmpimm(s1l,1);
5473 if(invert){
5474 nottaken=out;
5475 emit_jge(DJT_1);
5476 }else{
5477 add_to_linker(out,ba[i],internal);
5478 emit_jl(0);
5479 }
5480 }
5481 if(dops[i].opcode==7) // BGTZ
5482 {
5483 emit_cmpimm(s1l,1);
5484 if(invert){
5485 nottaken=out;
5486 emit_jl(DJT_1);
5487 }else{
5488 add_to_linker(out,ba[i],internal);
5489 emit_jge(0);
5490 }
5491 }
5492 if(invert) {
5493 if(taken) set_jump_target(taken, out);
5494 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5495 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5496 if(adj) {
5497 emit_addimm(cc,-adj,cc);
5498 add_to_linker(out,ba[i],internal);
5499 }else{
5500 emit_addnop(13);
5501 add_to_linker(out,ba[i],internal*2);
5502 }
5503 emit_jmp(0);
5504 }else
5505 #endif
5506 {
5507 if(adj) emit_addimm(cc,-adj,cc);
5508 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5509 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5510 if(internal)
5511 assem_debug("branch: internal\n");
5512 else
5513 assem_debug("branch: external\n");
5514 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5515 ds_assemble_entry(i);
5516 }
5517 else {
5518 add_to_linker(out,ba[i],internal);
5519 emit_jmp(0);
5520 }
5521 }
5522 set_jump_target(nottaken, out);
5523 }
5524
5525 if(nottaken1) set_jump_target(nottaken1, out);
5526 if(adj) {
5527 if(!invert) emit_addimm(cc,adj,cc);
5528 }
5529 } // (!unconditional)
5530 } // if(ooo)
5531 else
5532 {
5533 // In-order execution (branch first)
5534 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5535 if(!unconditional&&!nop) {
5536 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5537 assert(s1l>=0);
5538 if((dops[i].opcode&0x2f)==4) // BEQ
5539 {
5540 if(s2l>=0) emit_cmp(s1l,s2l);
5541 else emit_test(s1l,s1l);
5542 nottaken=out;
5543 emit_jne(DJT_2);
5544 }
5545 if((dops[i].opcode&0x2f)==5) // BNE
5546 {
5547 if(s2l>=0) emit_cmp(s1l,s2l);
5548 else emit_test(s1l,s1l);
5549 nottaken=out;
5550 emit_jeq(DJT_2);
5551 }
5552 if((dops[i].opcode&0x2f)==6) // BLEZ
5553 {
5554 emit_cmpimm(s1l,1);
5555 nottaken=out;
5556 emit_jge(DJT_2);
5557 }
5558 if((dops[i].opcode&0x2f)==7) // BGTZ
5559 {
5560 emit_cmpimm(s1l,1);
5561 nottaken=out;
5562 emit_jl(DJT_2);
5563 }
5564 } // if(!unconditional)
5565 int adj;
5566 uint64_t ds_unneeded=branch_regs[i].u;
5567 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5568 ds_unneeded|=1;
5569 // branch taken
5570 if(!nop) {
5571 if(taken) set_jump_target(taken, out);
5572 assem_debug("1:\n");
5573 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5574 // load regs
5575 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5576 address_generation(i+1,&branch_regs[i],0);
5577 if (ram_offset)
5578 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5579 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5580 ds_assemble(i+1,&branch_regs[i]);
5581 cc=get_reg(branch_regs[i].regmap,CCREG);
5582 if(cc==-1) {
5583 emit_loadreg(CCREG,cc=HOST_CCREG);
5584 // CHECK: Is the following instruction (fall thru) allocated ok?
5585 }
5586 assert(cc==HOST_CCREG);
5587 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5588 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5589 assem_debug("cycle count (adj)\n");
5590 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5591 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5592 if(internal)
5593 assem_debug("branch: internal\n");
5594 else
5595 assem_debug("branch: external\n");
5596 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5597 ds_assemble_entry(i);
5598 }
5599 else {
5600 add_to_linker(out,ba[i],internal);
5601 emit_jmp(0);
5602 }
5603 }
5604 // branch not taken
5605 if(!unconditional) {
5606 if(nottaken1) set_jump_target(nottaken1, out);
5607 set_jump_target(nottaken, out);
5608 assem_debug("2:\n");
5609 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5610 // load regs
5611 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5612 address_generation(i+1,&branch_regs[i],0);
5613 if (ram_offset)
5614 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5615 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5616 ds_assemble(i+1,&branch_regs[i]);
5617 cc=get_reg(branch_regs[i].regmap,CCREG);
5618 if (cc == -1) {
5619 // Cycle count isn't in a register, temporarily load it then write it out
5620 emit_loadreg(CCREG,HOST_CCREG);
5621 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5622 void *jaddr=out;
5623 emit_jns(0);
5624 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5625 emit_storereg(CCREG,HOST_CCREG);
5626 }
5627 else{
5628 cc=get_reg(i_regmap,CCREG);
5629 assert(cc==HOST_CCREG);
5630 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5631 void *jaddr=out;
5632 emit_jns(0);
5633 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5634 }
5635 }
5636 }
5637}
5638
5639static void sjump_assemble(int i, const struct regstat *i_regs)
5640{
5641 const signed char *i_regmap = i_regs->regmap;
5642 int cc;
5643 int match;
5644 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5645 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5646 int s1l;
5647 int unconditional=0,nevertaken=0;
5648 int invert=0;
5649 int internal=internal_branch(ba[i]);
5650 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5651 if(!match) invert=1;
5652 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5653 if(i>(ba[i]-start)>>2) invert=1;
5654 #endif
5655 #ifdef __aarch64__
5656 invert=1; // because of near cond. branches
5657 #endif
5658
5659 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5660 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5661
5662 if(dops[i].ooo) {
5663 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5664 }
5665 else {
5666 s1l=get_reg(i_regmap,dops[i].rs1);
5667 }
5668 if(dops[i].rs1==0)
5669 {
5670 if(dops[i].opcode2&1) unconditional=1;
5671 else nevertaken=1;
5672 // These are never taken (r0 is never less than zero)
5673 //assert(dops[i].opcode2!=0);
5674 //assert(dops[i].opcode2!=2);
5675 //assert(dops[i].opcode2!=0x10);
5676 //assert(dops[i].opcode2!=0x12);
5677 }
5678
5679 if(dops[i].ooo) {
5680 // Out of order execution (delay slot first)
5681 //printf("OOOE\n");
5682 address_generation(i+1,i_regs,regs[i].regmap_entry);
5683 ds_assemble(i+1,i_regs);
5684 int adj;
5685 uint64_t bc_unneeded=branch_regs[i].u;
5686 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5687 bc_unneeded|=1;
5688 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5689 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5690 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5691 if(dops[i].rt1==31) {
5692 int rt,return_address;
5693 rt=get_reg(branch_regs[i].regmap,31);
5694 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5695 if(rt>=0) {
5696 // Save the PC even if the branch is not taken
5697 return_address=start+i*4+8;
5698 emit_movimm(return_address,rt); // PC into link register
5699 #ifdef IMM_PREFETCH
5700 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5701 #endif
5702 }
5703 }
5704 cc=get_reg(branch_regs[i].regmap,CCREG);
5705 assert(cc==HOST_CCREG);
5706 if(unconditional)
5707 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5708 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5709 assem_debug("cycle count (adj)\n");
5710 if(unconditional) {
5711 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5712 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5713 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5714 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5715 if(internal)
5716 assem_debug("branch: internal\n");
5717 else
5718 assem_debug("branch: external\n");
5719 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5720 ds_assemble_entry(i);
5721 }
5722 else {
5723 add_to_linker(out,ba[i],internal);
5724 emit_jmp(0);
5725 }
5726 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5727 if(((u_int)out)&7) emit_addnop(0);
5728 #endif
5729 }
5730 }
5731 else if(nevertaken) {
5732 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5733 void *jaddr=out;
5734 emit_jns(0);
5735 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5736 }
5737 else {
5738 void *nottaken = NULL;
5739 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5740 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5741 {
5742 assert(s1l>=0);
5743 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5744 {
5745 emit_test(s1l,s1l);
5746 if(invert){
5747 nottaken=out;
5748 emit_jns(DJT_1);
5749 }else{
5750 add_to_linker(out,ba[i],internal);
5751 emit_js(0);
5752 }
5753 }
5754 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5755 {
5756 emit_test(s1l,s1l);
5757 if(invert){
5758 nottaken=out;
5759 emit_js(DJT_1);
5760 }else{
5761 add_to_linker(out,ba[i],internal);
5762 emit_jns(0);
5763 }
5764 }
5765 }
5766
5767 if(invert) {
5768 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5769 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5770 if(adj) {
5771 emit_addimm(cc,-adj,cc);
5772 add_to_linker(out,ba[i],internal);
5773 }else{
5774 emit_addnop(13);
5775 add_to_linker(out,ba[i],internal*2);
5776 }
5777 emit_jmp(0);
5778 }else
5779 #endif
5780 {
5781 if(adj) emit_addimm(cc,-adj,cc);
5782 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5783 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5784 if(internal)
5785 assem_debug("branch: internal\n");
5786 else
5787 assem_debug("branch: external\n");
5788 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5789 ds_assemble_entry(i);
5790 }
5791 else {
5792 add_to_linker(out,ba[i],internal);
5793 emit_jmp(0);
5794 }
5795 }
5796 set_jump_target(nottaken, out);
5797 }
5798
5799 if(adj) {
5800 if(!invert) emit_addimm(cc,adj,cc);
5801 }
5802 } // (!unconditional)
5803 } // if(ooo)
5804 else
5805 {
5806 // In-order execution (branch first)
5807 //printf("IOE\n");
5808 void *nottaken = NULL;
5809 if(dops[i].rt1==31) {
5810 int rt,return_address;
5811 rt=get_reg(branch_regs[i].regmap,31);
5812 if(rt>=0) {
5813 // Save the PC even if the branch is not taken
5814 return_address=start+i*4+8;
5815 emit_movimm(return_address,rt); // PC into link register
5816 #ifdef IMM_PREFETCH
5817 emit_prefetch(hash_table_get(return_address));
5818 #endif
5819 }
5820 }
5821 if(!unconditional) {
5822 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5823 assert(s1l>=0);
5824 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5825 {
5826 emit_test(s1l,s1l);
5827 nottaken=out;
5828 emit_jns(DJT_1);
5829 }
5830 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5831 {
5832 emit_test(s1l,s1l);
5833 nottaken=out;
5834 emit_js(DJT_1);
5835 }
5836 } // if(!unconditional)
5837 int adj;
5838 uint64_t ds_unneeded=branch_regs[i].u;
5839 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5840 ds_unneeded|=1;
5841 // branch taken
5842 if(!nevertaken) {
5843 //assem_debug("1:\n");
5844 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5845 // load regs
5846 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5847 address_generation(i+1,&branch_regs[i],0);
5848 if (ram_offset)
5849 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5850 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5851 ds_assemble(i+1,&branch_regs[i]);
5852 cc=get_reg(branch_regs[i].regmap,CCREG);
5853 if(cc==-1) {
5854 emit_loadreg(CCREG,cc=HOST_CCREG);
5855 // CHECK: Is the following instruction (fall thru) allocated ok?
5856 }
5857 assert(cc==HOST_CCREG);
5858 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5859 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5860 assem_debug("cycle count (adj)\n");
5861 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5862 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5863 if(internal)
5864 assem_debug("branch: internal\n");
5865 else
5866 assem_debug("branch: external\n");
5867 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5868 ds_assemble_entry(i);
5869 }
5870 else {
5871 add_to_linker(out,ba[i],internal);
5872 emit_jmp(0);
5873 }
5874 }
5875 // branch not taken
5876 if(!unconditional) {
5877 set_jump_target(nottaken, out);
5878 assem_debug("1:\n");
5879 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5880 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5881 address_generation(i+1,&branch_regs[i],0);
5882 if (ram_offset)
5883 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5884 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5885 ds_assemble(i+1,&branch_regs[i]);
5886 cc=get_reg(branch_regs[i].regmap,CCREG);
5887 if (cc == -1) {
5888 // Cycle count isn't in a register, temporarily load it then write it out
5889 emit_loadreg(CCREG,HOST_CCREG);
5890 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5891 void *jaddr=out;
5892 emit_jns(0);
5893 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5894 emit_storereg(CCREG,HOST_CCREG);
5895 }
5896 else{
5897 cc=get_reg(i_regmap,CCREG);
5898 assert(cc==HOST_CCREG);
5899 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5900 void *jaddr=out;
5901 emit_jns(0);
5902 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5903 }
5904 }
5905 }
5906}
5907
5908static void check_regmap(signed char *regmap)
5909{
5910#ifndef NDEBUG
5911 int i,j;
5912 for (i = 0; i < HOST_REGS; i++) {
5913 if (regmap[i] < 0)
5914 continue;
5915 for (j = i + 1; j < HOST_REGS; j++)
5916 assert(regmap[i] != regmap[j]);
5917 }
5918#endif
5919}
5920
5921#ifdef DISASM
5922#include <inttypes.h>
5923static char insn[MAXBLOCK][10];
5924
5925#define set_mnemonic(i_, n_) \
5926 strcpy(insn[i_], n_)
5927
5928void print_regmap(const char *name, const signed char *regmap)
5929{
5930 char buf[5];
5931 int i, l;
5932 fputs(name, stdout);
5933 for (i = 0; i < HOST_REGS; i++) {
5934 l = 0;
5935 if (regmap[i] >= 0)
5936 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
5937 for (; l < 3; l++)
5938 buf[l] = ' ';
5939 buf[l] = 0;
5940 printf(" r%d=%s", i, buf);
5941 }
5942 fputs("\n", stdout);
5943}
5944
5945 /* disassembly */
5946void disassemble_inst(int i)
5947{
5948 if (dops[i].bt) printf("*"); else printf(" ");
5949 switch(dops[i].itype) {
5950 case UJUMP:
5951 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
5952 case CJUMP:
5953 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
5954 case SJUMP:
5955 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
5956 case RJUMP:
5957 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
5958 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
5959 else
5960 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5961 break;
5962 case IMM16:
5963 if(dops[i].opcode==0xf) //LUI
5964 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
5965 else
5966 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5967 break;
5968 case LOAD:
5969 case LOADLR:
5970 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5971 break;
5972 case STORE:
5973 case STORELR:
5974 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
5975 break;
5976 case ALU:
5977 case SHIFT:
5978 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
5979 break;
5980 case MULTDIV:
5981 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
5982 break;
5983 case SHIFTIMM:
5984 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
5985 break;
5986 case MOV:
5987 if((dops[i].opcode2&0x1d)==0x10)
5988 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
5989 else if((dops[i].opcode2&0x1d)==0x11)
5990 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
5991 else
5992 printf (" %x: %s\n",start+i*4,insn[i]);
5993 break;
5994 case COP0:
5995 if(dops[i].opcode2==0)
5996 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
5997 else if(dops[i].opcode2==4)
5998 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
5999 else printf (" %x: %s\n",start+i*4,insn[i]);
6000 break;
6001 case COP1:
6002 if(dops[i].opcode2<3)
6003 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6004 else if(dops[i].opcode2>3)
6005 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6006 else printf (" %x: %s\n",start+i*4,insn[i]);
6007 break;
6008 case COP2:
6009 if(dops[i].opcode2<3)
6010 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6011 else if(dops[i].opcode2>3)
6012 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6013 else printf (" %x: %s\n",start+i*4,insn[i]);
6014 break;
6015 case C1LS:
6016 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6017 break;
6018 case C2LS:
6019 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6020 break;
6021 case INTCALL:
6022 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6023 break;
6024 default:
6025 //printf (" %s %8x\n",insn[i],source[i]);
6026 printf (" %x: %s\n",start+i*4,insn[i]);
6027 }
6028 return;
6029 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6030 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6031 print_regmap("pre: ", regmap_pre[i]);
6032 print_regmap("entry: ", regs[i].regmap_entry);
6033 print_regmap("map: ", regs[i].regmap);
6034 if (dops[i].is_jump) {
6035 print_regmap("bentry:", branch_regs[i].regmap_entry);
6036 print_regmap("bmap: ", branch_regs[i].regmap);
6037 }
6038}
6039#else
6040#define set_mnemonic(i_, n_)
6041static void disassemble_inst(int i) {}
6042#endif // DISASM
6043
6044#define DRC_TEST_VAL 0x74657374
6045
6046static void new_dynarec_test(void)
6047{
6048 int (*testfunc)(void);
6049 void *beginning;
6050 int ret[2];
6051 size_t i;
6052
6053 // check structure linkage
6054 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6055 {
6056 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6057 }
6058
6059 SysPrintf("testing if we can run recompiled code @%p...\n", out);
6060 ((volatile u_int *)out)[0]++; // make cache dirty
6061
6062 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6063 out = ndrc->translation_cache;
6064 beginning = start_block();
6065 emit_movimm(DRC_TEST_VAL + i, 0); // test
6066 emit_ret();
6067 literal_pool(0);
6068 end_block(beginning);
6069 testfunc = beginning;
6070 ret[i] = testfunc();
6071 }
6072
6073 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6074 SysPrintf("test passed.\n");
6075 else
6076 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6077 out = ndrc->translation_cache;
6078}
6079
6080// clear the state completely, instead of just marking
6081// things invalid like invalidate_all_pages() does
6082void new_dynarec_clear_full(void)
6083{
6084 int n;
6085 out = ndrc->translation_cache;
6086 memset(invalid_code,1,sizeof(invalid_code));
6087 memset(hash_table,0xff,sizeof(hash_table));
6088 memset(mini_ht,-1,sizeof(mini_ht));
6089 memset(shadow,0,sizeof(shadow));
6090 copy=shadow;
6091 expirep = EXPIRITY_OFFSET;
6092 pending_exception=0;
6093 literalcount=0;
6094 stop_after_jal=0;
6095 inv_code_start=inv_code_end=~0;
6096 hack_addr=0;
6097 f1_hack=0;
6098 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6099 blocks_clear(&blocks[n]);
6100 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6101 free(jumps[n]);
6102 jumps[n] = NULL;
6103 }
6104 stat_clear(stat_blocks);
6105 stat_clear(stat_links);
6106
6107 cycle_multiplier_old = cycle_multiplier;
6108 new_dynarec_hacks_old = new_dynarec_hacks;
6109}
6110
6111void new_dynarec_init(void)
6112{
6113 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6114
6115#ifdef _3DS
6116 check_rosalina();
6117#endif
6118#ifdef BASE_ADDR_DYNAMIC
6119 #ifdef VITA
6120 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6121 if (sceBlock <= 0)
6122 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6123 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6124 if (ret < 0)
6125 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6126 sceKernelOpenVMDomain();
6127 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6128 #elif defined(_MSC_VER)
6129 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6130 PAGE_EXECUTE_READWRITE);
6131 #else
6132 uintptr_t desired_addr = 0;
6133 #ifdef __ELF__
6134 extern char _end;
6135 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6136 #endif
6137 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6138 PROT_READ | PROT_WRITE | PROT_EXEC,
6139 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6140 if (ndrc == MAP_FAILED) {
6141 SysPrintf("mmap() failed: %s\n", strerror(errno));
6142 abort();
6143 }
6144 #endif
6145#else
6146 #ifndef NO_WRITE_EXEC
6147 // not all systems allow execute in data segment by default
6148 // size must be 4K aligned for 3DS?
6149 if (mprotect(ndrc, sizeof(*ndrc),
6150 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6151 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6152 #endif
6153#endif
6154 out = ndrc->translation_cache;
6155 cycle_multiplier=200;
6156 new_dynarec_clear_full();
6157#ifdef HOST_IMM8
6158 // Copy this into local area so we don't have to put it in every literal pool
6159 invc_ptr=invalid_code;
6160#endif
6161 arch_init();
6162 new_dynarec_test();
6163 ram_offset=(uintptr_t)rdram-0x80000000;
6164 if (ram_offset!=0)
6165 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6166 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6167 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6168}
6169
6170void new_dynarec_cleanup(void)
6171{
6172 int n;
6173#ifdef BASE_ADDR_DYNAMIC
6174 #ifdef VITA
6175 // sceBlock is managed by retroarch's bootstrap code
6176 //sceKernelFreeMemBlock(sceBlock);
6177 //sceBlock = -1;
6178 #else
6179 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6180 SysPrintf("munmap() failed\n");
6181 #endif
6182#endif
6183 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6184 blocks_clear(&blocks[n]);
6185 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6186 free(jumps[n]);
6187 jumps[n] = NULL;
6188 }
6189 stat_clear(stat_blocks);
6190 stat_clear(stat_links);
6191 #ifdef ROM_COPY
6192 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6193 #endif
6194 new_dynarec_print_stats();
6195}
6196
6197static u_int *get_source_start(u_int addr, u_int *limit)
6198{
6199 if (addr < 0x00200000 ||
6200 (0xa0000000 <= addr && addr < 0xa0200000))
6201 {
6202 // used for BIOS calls mostly?
6203 *limit = (addr&0xa0000000)|0x00200000;
6204 return (u_int *)(rdram + (addr&0x1fffff));
6205 }
6206 else if (!Config.HLE && (
6207 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6208 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6209 {
6210 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6211 // but timings in PCSX are too tied to the interpreter's BIAS
6212 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6213 cycle_multiplier_active = 200;
6214
6215 *limit = (addr & 0xfff00000) | 0x80000;
6216 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6217 }
6218 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6219 *limit = (addr & 0x80600000) + 0x00200000;
6220 return (u_int *)(rdram + (addr&0x1fffff));
6221 }
6222 return NULL;
6223}
6224
6225static u_int scan_for_ret(u_int addr)
6226{
6227 u_int limit = 0;
6228 u_int *mem;
6229
6230 mem = get_source_start(addr, &limit);
6231 if (mem == NULL)
6232 return addr;
6233
6234 if (limit > addr + 0x1000)
6235 limit = addr + 0x1000;
6236 for (; addr < limit; addr += 4, mem++) {
6237 if (*mem == 0x03e00008) // jr $ra
6238 return addr + 8;
6239 }
6240 return addr;
6241}
6242
6243struct savestate_block {
6244 uint32_t addr;
6245 uint32_t regflags;
6246};
6247
6248static int addr_cmp(const void *p1_, const void *p2_)
6249{
6250 const struct savestate_block *p1 = p1_, *p2 = p2_;
6251 return p1->addr - p2->addr;
6252}
6253
6254int new_dynarec_save_blocks(void *save, int size)
6255{
6256 struct savestate_block *sblocks = save;
6257 int maxcount = size / sizeof(sblocks[0]);
6258 struct savestate_block tmp_blocks[1024];
6259 struct block_info *block;
6260 int p, s, d, o, bcnt;
6261 u_int addr;
6262
6263 o = 0;
6264 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6265 bcnt = 0;
6266 for (block = blocks[p]; block != NULL; block = block->next) {
6267 if (block->is_dirty)
6268 continue;
6269 tmp_blocks[bcnt].addr = block->start;
6270 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6271 bcnt++;
6272 }
6273 if (bcnt < 1)
6274 continue;
6275 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6276
6277 addr = tmp_blocks[0].addr;
6278 for (s = d = 0; s < bcnt; s++) {
6279 if (tmp_blocks[s].addr < addr)
6280 continue;
6281 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6282 tmp_blocks[d++] = tmp_blocks[s];
6283 addr = scan_for_ret(tmp_blocks[s].addr);
6284 }
6285
6286 if (o + d > maxcount)
6287 d = maxcount - o;
6288 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6289 o += d;
6290 }
6291
6292 return o * sizeof(sblocks[0]);
6293}
6294
6295void new_dynarec_load_blocks(const void *save, int size)
6296{
6297 const struct savestate_block *sblocks = save;
6298 int count = size / sizeof(sblocks[0]);
6299 struct block_info *block;
6300 u_int regs_save[32];
6301 u_int page;
6302 uint32_t f;
6303 int i, b;
6304
6305 // restore clean blocks, if any
6306 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6307 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6308 if (!block->is_dirty)
6309 continue;
6310 assert(block->source && block->copy);
6311 if (memcmp(block->source, block->copy, block->len))
6312 continue;
6313
6314 // see try_restore_block
6315 block->is_dirty = 0;
6316 mark_invalid_code(block->start, block->len, 0);
6317 i++;
6318 }
6319 }
6320 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6321
6322 // change GPRs for speculation to at least partially work..
6323 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6324 for (i = 1; i < 32; i++)
6325 psxRegs.GPR.r[i] = 0x80000000;
6326
6327 for (b = 0; b < count; b++) {
6328 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6329 if (f & 1)
6330 psxRegs.GPR.r[i] = 0x1f800000;
6331 }
6332
6333 ndrc_get_addr_ht(sblocks[b].addr);
6334
6335 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6336 if (f & 1)
6337 psxRegs.GPR.r[i] = 0x80000000;
6338 }
6339 }
6340
6341 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6342}
6343
6344void new_dynarec_print_stats(void)
6345{
6346#ifdef STAT_PRINT
6347 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6348 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6349 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6350 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6351 out - ndrc->translation_cache, stat_blocks, stat_links);
6352 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6353 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6354 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6355#endif
6356}
6357
6358static int apply_hacks(void)
6359{
6360 int i;
6361 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6362 return 0;
6363 /* special hack(s) */
6364 for (i = 0; i < slen - 4; i++)
6365 {
6366 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6367 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6368 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6369 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
6370 {
6371 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6372 dops[i + 3].itype = NOP;
6373 }
6374 }
6375 i = slen;
6376 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6377 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6378 && dops[i-7].itype == STORE)
6379 {
6380 i = i-8;
6381 if (dops[i].itype == IMM16)
6382 i--;
6383 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6384 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6385 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6386 {
6387 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6388 f1_hack = 1;
6389 return 1;
6390 }
6391 }
6392 return 0;
6393}
6394
6395static noinline void pass1_disassemble(u_int pagelimit)
6396{
6397 int i, j, done = 0, ni_count = 0;
6398 unsigned int type,op,op2;
6399
6400 for (i = 0; !done; i++)
6401 {
6402 memset(&dops[i], 0, sizeof(dops[i]));
6403 op2=0;
6404 minimum_free_regs[i]=0;
6405 dops[i].opcode=op=source[i]>>26;
6406 switch(op)
6407 {
6408 case 0x00: set_mnemonic(i, "special"); type=NI;
6409 op2=source[i]&0x3f;
6410 switch(op2)
6411 {
6412 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6413 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6414 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6415 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6416 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6417 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6418 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6419 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6420 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6421 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6422 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6423 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6424 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6425 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6426 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6427 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6428 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6429 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6430 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6431 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6432 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6433 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6434 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6435 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6436 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6437 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6438 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6439 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6440 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6441 case 0x30: set_mnemonic(i, "TGE"); type=NI; break;
6442 case 0x31: set_mnemonic(i, "TGEU"); type=NI; break;
6443 case 0x32: set_mnemonic(i, "TLT"); type=NI; break;
6444 case 0x33: set_mnemonic(i, "TLTU"); type=NI; break;
6445 case 0x34: set_mnemonic(i, "TEQ"); type=NI; break;
6446 case 0x36: set_mnemonic(i, "TNE"); type=NI; break;
6447#if 0
6448 case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break;
6449 case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break;
6450 case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break;
6451 case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break;
6452 case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break;
6453 case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break;
6454 case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break;
6455 case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break;
6456 case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break;
6457 case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break;
6458 case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break;
6459 case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break;
6460 case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break;
6461 case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break;
6462 case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break;
6463 case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break;
6464 case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break;
6465#endif
6466 }
6467 break;
6468 case 0x01: set_mnemonic(i, "regimm"); type=NI;
6469 op2=(source[i]>>16)&0x1f;
6470 switch(op2)
6471 {
6472 case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break;
6473 case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break;
6474 //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break;
6475 //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break;
6476 //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break;
6477 //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break;
6478 //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break;
6479 //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break;
6480 //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break;
6481 //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break;
6482 case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break;
6483 case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break;
6484 //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break;
6485 //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break;
6486 }
6487 break;
6488 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6489 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6490 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6491 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6492 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6493 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6494 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6495 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6496 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6497 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6498 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6499 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6500 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6501 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6502 case 0x10: set_mnemonic(i, "cop0"); type=NI;
6503 op2=(source[i]>>21)&0x1f;
6504 switch(op2)
6505 {
6506 case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break;
6507 case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break;
6508 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6509 case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break;
6510 case 0x10: set_mnemonic(i, "RFE"); type=COP0; break;
6511 }
6512 break;
6513 case 0x11: set_mnemonic(i, "cop1"); type=COP1;
6514 op2=(source[i]>>21)&0x1f;
6515 break;
6516#if 0
6517 case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break;
6518 case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break;
6519 case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break;
6520 case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break;
6521 case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break;
6522 case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break;
6523 case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break;
6524 case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break;
6525#endif
6526 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6527 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6528 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6529 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6530 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6531 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6532 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
6533#if 0
6534 case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break;
6535#endif
6536 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6537 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6538 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6539 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
6540#if 0
6541 case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break;
6542 case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break;
6543#endif
6544 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6545 case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break;
6546 case 0x30: set_mnemonic(i, "LL"); type=NI; break;
6547 case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break;
6548#if 0
6549 case 0x34: set_mnemonic(i, "LLD"); type=NI; break;
6550 case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break;
6551 case 0x37: set_mnemonic(i, "LD"); type=LOAD; break;
6552#endif
6553 case 0x38: set_mnemonic(i, "SC"); type=NI; break;
6554 case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break;
6555#if 0
6556 case 0x3C: set_mnemonic(i, "SCD"); type=NI; break;
6557 case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break;
6558 case 0x3F: set_mnemonic(i, "SD"); type=STORE; break;
6559#endif
6560 case 0x12: set_mnemonic(i, "COP2"); type=NI;
6561 op2=(source[i]>>21)&0x1f;
6562 //if (op2 & 0x10)
6563 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
6564 if (gte_handlers[source[i]&0x3f]!=NULL) {
6565#ifdef DISASM
6566 if (gte_regnames[source[i]&0x3f]!=NULL)
6567 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6568 else
6569 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6570#endif
6571 type=C2OP;
6572 }
6573 }
6574 else switch(op2)
6575 {
6576 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6577 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6578 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6579 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6580 }
6581 break;
6582 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6583 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6584 case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break;
6585 default: set_mnemonic(i, "???"); type=NI;
6586 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
6587 break;
6588 }
6589 dops[i].itype=type;
6590 dops[i].opcode2=op2;
6591 /* Get registers/immediates */
6592 dops[i].use_lt1=0;
6593 gte_rs[i]=gte_rt[i]=0;
6594 switch(type) {
6595 case LOAD:
6596 dops[i].rs1=(source[i]>>21)&0x1f;
6597 dops[i].rs2=0;
6598 dops[i].rt1=(source[i]>>16)&0x1f;
6599 dops[i].rt2=0;
6600 imm[i]=(short)source[i];
6601 break;
6602 case STORE:
6603 case STORELR:
6604 dops[i].rs1=(source[i]>>21)&0x1f;
6605 dops[i].rs2=(source[i]>>16)&0x1f;
6606 dops[i].rt1=0;
6607 dops[i].rt2=0;
6608 imm[i]=(short)source[i];
6609 break;
6610 case LOADLR:
6611 // LWL/LWR only load part of the register,
6612 // therefore the target register must be treated as a source too
6613 dops[i].rs1=(source[i]>>21)&0x1f;
6614 dops[i].rs2=(source[i]>>16)&0x1f;
6615 dops[i].rt1=(source[i]>>16)&0x1f;
6616 dops[i].rt2=0;
6617 imm[i]=(short)source[i];
6618 break;
6619 case IMM16:
6620 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6621 else dops[i].rs1=(source[i]>>21)&0x1f;
6622 dops[i].rs2=0;
6623 dops[i].rt1=(source[i]>>16)&0x1f;
6624 dops[i].rt2=0;
6625 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6626 imm[i]=(unsigned short)source[i];
6627 }else{
6628 imm[i]=(short)source[i];
6629 }
6630 break;
6631 case UJUMP:
6632 dops[i].rs1=0;
6633 dops[i].rs2=0;
6634 dops[i].rt1=0;
6635 dops[i].rt2=0;
6636 // The JAL instruction writes to r31.
6637 if (op&1) {
6638 dops[i].rt1=31;
6639 }
6640 dops[i].rs2=CCREG;
6641 break;
6642 case RJUMP:
6643 dops[i].rs1=(source[i]>>21)&0x1f;
6644 dops[i].rs2=0;
6645 dops[i].rt1=0;
6646 dops[i].rt2=0;
6647 // The JALR instruction writes to rd.
6648 if (op2&1) {
6649 dops[i].rt1=(source[i]>>11)&0x1f;
6650 }
6651 dops[i].rs2=CCREG;
6652 break;
6653 case CJUMP:
6654 dops[i].rs1=(source[i]>>21)&0x1f;
6655 dops[i].rs2=(source[i]>>16)&0x1f;
6656 dops[i].rt1=0;
6657 dops[i].rt2=0;
6658 if(op&2) { // BGTZ/BLEZ
6659 dops[i].rs2=0;
6660 }
6661 break;
6662 case SJUMP:
6663 dops[i].rs1=(source[i]>>21)&0x1f;
6664 dops[i].rs2=CCREG;
6665 dops[i].rt1=0;
6666 dops[i].rt2=0;
6667 if(op2&0x10) { // BxxAL
6668 dops[i].rt1=31;
6669 // NOTE: If the branch is not taken, r31 is still overwritten
6670 }
6671 break;
6672 case ALU:
6673 dops[i].rs1=(source[i]>>21)&0x1f; // source
6674 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6675 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6676 dops[i].rt2=0;
6677 break;
6678 case MULTDIV:
6679 dops[i].rs1=(source[i]>>21)&0x1f; // source
6680 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6681 dops[i].rt1=HIREG;
6682 dops[i].rt2=LOREG;
6683 break;
6684 case MOV:
6685 dops[i].rs1=0;
6686 dops[i].rs2=0;
6687 dops[i].rt1=0;
6688 dops[i].rt2=0;
6689 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6690 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6691 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6692 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6693 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6694 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
6695 break;
6696 case SHIFT:
6697 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6698 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6699 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6700 dops[i].rt2=0;
6701 break;
6702 case SHIFTIMM:
6703 dops[i].rs1=(source[i]>>16)&0x1f;
6704 dops[i].rs2=0;
6705 dops[i].rt1=(source[i]>>11)&0x1f;
6706 dops[i].rt2=0;
6707 imm[i]=(source[i]>>6)&0x1f;
6708 // DSxx32 instructions
6709 if(op2>=0x3c) imm[i]|=0x20;
6710 break;
6711 case COP0:
6712 dops[i].rs1=0;
6713 dops[i].rs2=0;
6714 dops[i].rt1=0;
6715 dops[i].rt2=0;
6716 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
6717 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
6718 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6719 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
6720 break;
6721 case COP1:
6722 dops[i].rs1=0;
6723 dops[i].rs2=0;
6724 dops[i].rt1=0;
6725 dops[i].rt2=0;
6726 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
6727 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
6728 dops[i].rs2=CSREG;
6729 break;
6730 case COP2:
6731 dops[i].rs1=0;
6732 dops[i].rs2=0;
6733 dops[i].rt1=0;
6734 dops[i].rt2=0;
6735 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6736 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6737 dops[i].rs2=CSREG;
6738 int gr=(source[i]>>11)&0x1F;
6739 switch(op2)
6740 {
6741 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6742 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6743 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6744 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6745 }
6746 break;
6747 case C1LS:
6748 dops[i].rs1=(source[i]>>21)&0x1F;
6749 dops[i].rs2=CSREG;
6750 dops[i].rt1=0;
6751 dops[i].rt2=0;
6752 imm[i]=(short)source[i];
6753 break;
6754 case C2LS:
6755 dops[i].rs1=(source[i]>>21)&0x1F;
6756 dops[i].rs2=0;
6757 dops[i].rt1=0;
6758 dops[i].rt2=0;
6759 imm[i]=(short)source[i];
6760 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
6761 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
6762 break;
6763 case C2OP:
6764 dops[i].rs1=0;
6765 dops[i].rs2=0;
6766 dops[i].rt1=0;
6767 dops[i].rt2=0;
6768 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
6769 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
6770 gte_rt[i]|=1ll<<63; // every op changes flags
6771 if((source[i]&0x3f)==GTE_MVMVA) {
6772 int v = (source[i] >> 15) & 3;
6773 gte_rs[i]&=~0xe3fll;
6774 if(v==3) gte_rs[i]|=0xe00ll;
6775 else gte_rs[i]|=3ll<<(v*2);
6776 }
6777 break;
6778 case SYSCALL:
6779 case HLECALL:
6780 case INTCALL:
6781 dops[i].rs1=CCREG;
6782 dops[i].rs2=0;
6783 dops[i].rt1=0;
6784 dops[i].rt2=0;
6785 break;
6786 default:
6787 dops[i].rs1=0;
6788 dops[i].rs2=0;
6789 dops[i].rt1=0;
6790 dops[i].rt2=0;
6791 }
6792 /* Calculate branch target addresses */
6793 if(type==UJUMP)
6794 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6795 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6796 ba[i]=start+i*4+8; // Ignore never taken branch
6797 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6798 ba[i]=start+i*4+8; // Ignore never taken branch
6799 else if(type==CJUMP||type==SJUMP)
6800 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6801 else ba[i]=-1;
6802
6803 /* simplify always (not)taken branches */
6804 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6805 dops[i].rs1 = dops[i].rs2 = 0;
6806 if (!(op & 1)) {
6807 dops[i].itype = type = UJUMP;
6808 dops[i].rs2 = CCREG;
6809 }
6810 }
6811 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6812 dops[i].itype = type = UJUMP;
6813
6814 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
6815 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
6816 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
6817 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
6818
6819 /* messy cases to just pass over to the interpreter */
6820 if (i > 0 && dops[i-1].is_jump) {
6821 int do_in_intrp=0;
6822 // branch in delay slot?
6823 if (dops[i].is_jump) {
6824 // don't handle first branch and call interpreter if it's hit
6825 SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start);
6826 do_in_intrp=1;
6827 }
6828 // basic load delay detection
6829 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
6830 int t=(ba[i-1]-start)/4;
6831 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
6832 // jump target wants DS result - potential load delay effect
6833 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6834 do_in_intrp=1;
6835 dops[t+1].bt=1; // expected return from interpreter
6836 }
6837 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6838 !(i>=3&&dops[i-3].is_jump)) {
6839 // v0 overwrite like this is a sign of trouble, bail out
6840 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6841 do_in_intrp=1;
6842 }
6843 }
6844 if (do_in_intrp) {
6845 memset(&dops[i-1], 0, sizeof(dops[i-1]));
6846 dops[i-1].itype = INTCALL;
6847 dops[i-1].rs1 = CCREG;
6848 ba[i-1] = -1;
6849 done = 2;
6850 i--; // don't compile the DS
6851 }
6852 }
6853
6854 /* Is this the end of the block? */
6855 if (i > 0 && dops[i-1].is_ujump) {
6856 if (dops[i-1].rt1 == 0) { // not jal
6857 int found_bbranch = 0, t = (ba[i-1] - start) / 4;
6858 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6859 // scan for a branch back to i+1
6860 for (j = t; j < t + 64; j++) {
6861 int tmpop = source[j] >> 26;
6862 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6863 int t2 = j + 1 + (int)(signed short)source[j];
6864 if (t2 == i + 1) {
6865 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6866 found_bbranch = 1;
6867 break;
6868 }
6869 }
6870 }
6871 }
6872 if (!found_bbranch)
6873 done = 2;
6874 }
6875 else {
6876 if(stop_after_jal) done=1;
6877 // Stop on BREAK
6878 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6879 }
6880 // Don't recompile stuff that's already compiled
6881 if(check_addr(start+i*4+4)) done=1;
6882 // Don't get too close to the limit
6883 if(i>MAXBLOCK/2) done=1;
6884 }
6885 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
6886 done = stop_after_jal ? 1 : 2;
6887 if (done == 2) {
6888 // Does the block continue due to a branch?
6889 for(j=i-1;j>=0;j--)
6890 {
6891 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
6892 if(ba[j]==start+i*4+4) done=j=0;
6893 if(ba[j]==start+i*4+8) done=j=0;
6894 }
6895 }
6896 //assert(i<MAXBLOCK-1);
6897 if(start+i*4==pagelimit-4) done=1;
6898 assert(start+i*4<pagelimit);
6899 if (i==MAXBLOCK-1) done=1;
6900 // Stop if we're compiling junk
6901 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
6902 done=stop_after_jal=1;
6903 SysPrintf("Disabled speculative precompilation\n");
6904 }
6905 }
6906 while (i > 0 && dops[i-1].is_jump)
6907 i--;
6908 assert(i > 0);
6909 assert(!dops[i-1].is_jump);
6910 slen = i;
6911}
6912
6913// Basic liveness analysis for MIPS registers
6914static noinline void pass2_unneeded_regs(int istart,int iend,int r)
6915{
6916 int i;
6917 uint64_t u,gte_u,b,gte_b;
6918 uint64_t temp_u,temp_gte_u=0;
6919 uint64_t gte_u_unknown=0;
6920 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6921 gte_u_unknown=~0ll;
6922 if(iend==slen-1) {
6923 u=1;
6924 gte_u=gte_u_unknown;
6925 }else{
6926 //u=unneeded_reg[iend+1];
6927 u=1;
6928 gte_u=gte_unneeded[iend+1];
6929 }
6930
6931 for (i=iend;i>=istart;i--)
6932 {
6933 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6934 if(dops[i].is_jump)
6935 {
6936 // If subroutine call, flag return address as a possible branch target
6937 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6938
6939 if(ba[i]<start || ba[i]>=(start+slen*4))
6940 {
6941 // Branch out of this block, flush all regs
6942 u=1;
6943 gte_u=gte_u_unknown;
6944 branch_unneeded_reg[i]=u;
6945 // Merge in delay slot
6946 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6947 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6948 u|=1;
6949 gte_u|=gte_rt[i+1];
6950 gte_u&=~gte_rs[i+1];
6951 }
6952 else
6953 {
6954 // Internal branch, flag target
6955 dops[(ba[i]-start)>>2].bt=1;
6956 if(ba[i]<=start+i*4) {
6957 // Backward branch
6958 if(dops[i].is_ujump)
6959 {
6960 // Unconditional branch
6961 temp_u=1;
6962 temp_gte_u=0;
6963 } else {
6964 // Conditional branch (not taken case)
6965 temp_u=unneeded_reg[i+2];
6966 temp_gte_u&=gte_unneeded[i+2];
6967 }
6968 // Merge in delay slot
6969 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6970 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6971 temp_u|=1;
6972 temp_gte_u|=gte_rt[i+1];
6973 temp_gte_u&=~gte_rs[i+1];
6974 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6975 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6976 temp_u|=1;
6977 temp_gte_u|=gte_rt[i];
6978 temp_gte_u&=~gte_rs[i];
6979 unneeded_reg[i]=temp_u;
6980 gte_unneeded[i]=temp_gte_u;
6981 // Only go three levels deep. This recursion can take an
6982 // excessive amount of time if there are a lot of nested loops.
6983 if(r<2) {
6984 pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1);
6985 }else{
6986 unneeded_reg[(ba[i]-start)>>2]=1;
6987 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6988 }
6989 } /*else*/ if(1) {
6990 if (dops[i].is_ujump)
6991 {
6992 // Unconditional branch
6993 u=unneeded_reg[(ba[i]-start)>>2];
6994 gte_u=gte_unneeded[(ba[i]-start)>>2];
6995 branch_unneeded_reg[i]=u;
6996 // Merge in delay slot
6997 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6998 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6999 u|=1;
7000 gte_u|=gte_rt[i+1];
7001 gte_u&=~gte_rs[i+1];
7002 } else {
7003 // Conditional branch
7004 b=unneeded_reg[(ba[i]-start)>>2];
7005 gte_b=gte_unneeded[(ba[i]-start)>>2];
7006 branch_unneeded_reg[i]=b;
7007 // Branch delay slot
7008 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7009 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7010 b|=1;
7011 gte_b|=gte_rt[i+1];
7012 gte_b&=~gte_rs[i+1];
7013 u&=b;
7014 gte_u&=gte_b;
7015 if(i<slen-1) {
7016 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7017 } else {
7018 branch_unneeded_reg[i]=1;
7019 }
7020 }
7021 }
7022 }
7023 }
7024 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7025 {
7026 // SYSCALL instruction (software interrupt)
7027 u=1;
7028 }
7029 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7030 {
7031 // ERET instruction (return from interrupt)
7032 u=1;
7033 }
7034 //u=1; // DEBUG
7035 // Written registers are unneeded
7036 u|=1LL<<dops[i].rt1;
7037 u|=1LL<<dops[i].rt2;
7038 gte_u|=gte_rt[i];
7039 // Accessed registers are needed
7040 u&=~(1LL<<dops[i].rs1);
7041 u&=~(1LL<<dops[i].rs2);
7042 gte_u&=~gte_rs[i];
7043 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7044 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7045 // Source-target dependencies
7046 // R0 is always unneeded
7047 u|=1;
7048 // Save it
7049 unneeded_reg[i]=u;
7050 gte_unneeded[i]=gte_u;
7051 /*
7052 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7053 printf("U:");
7054 int r;
7055 for(r=1;r<=CCREG;r++) {
7056 if((unneeded_reg[i]>>r)&1) {
7057 if(r==HIREG) printf(" HI");
7058 else if(r==LOREG) printf(" LO");
7059 else printf(" r%d",r);
7060 }
7061 }
7062 printf("\n");
7063 */
7064 }
7065}
7066
7067static noinline void pass3_register_alloc(u_int addr)
7068{
7069 struct regstat current; // Current register allocations/status
7070 clear_all_regs(current.regmap_entry);
7071 clear_all_regs(current.regmap);
7072 current.wasdirty = current.dirty = 0;
7073 current.u = unneeded_reg[0];
7074 alloc_reg(&current, 0, CCREG);
7075 dirty_reg(&current, CCREG);
7076 current.wasconst = 0;
7077 current.isconst = 0;
7078 current.loadedconst = 0;
7079 current.waswritten = 0;
7080 int ds=0;
7081 int cc=0;
7082 int hr;
7083 int i, j;
7084
7085 if (addr & 1) {
7086 // First instruction is delay slot
7087 cc=-1;
7088 dops[1].bt=1;
7089 ds=1;
7090 unneeded_reg[0]=1;
7091 current.regmap[HOST_BTREG]=BTREG;
7092 }
7093
7094 for(i=0;i<slen;i++)
7095 {
7096 if(dops[i].bt)
7097 {
7098 for(hr=0;hr<HOST_REGS;hr++)
7099 {
7100 // Is this really necessary?
7101 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7102 }
7103 current.isconst=0;
7104 current.waswritten=0;
7105 }
7106
7107 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7108 regs[i].wasconst=current.isconst;
7109 regs[i].wasdirty=current.dirty;
7110 regs[i].dirty=0;
7111 regs[i].u=0;
7112 regs[i].isconst=0;
7113 regs[i].loadedconst=0;
7114 if (!dops[i].is_jump) {
7115 if(i+1<slen) {
7116 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7117 current.u|=1;
7118 } else {
7119 current.u=1;
7120 }
7121 } else {
7122 if(i+1<slen) {
7123 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7124 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7125 current.u|=1;
7126 } else {
7127 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7128 abort();
7129 }
7130 }
7131 dops[i].is_ds=ds;
7132 if(ds) {
7133 ds=0; // Skip delay slot, already allocated as part of branch
7134 // ...but we need to alloc it in case something jumps here
7135 if(i+1<slen) {
7136 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7137 }else{
7138 current.u=branch_unneeded_reg[i-1];
7139 }
7140 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7141 current.u|=1;
7142 struct regstat temp;
7143 memcpy(&temp,&current,sizeof(current));
7144 temp.wasdirty=temp.dirty;
7145 // TODO: Take into account unconditional branches, as below
7146 delayslot_alloc(&temp,i);
7147 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7148 regs[i].wasdirty=temp.wasdirty;
7149 regs[i].dirty=temp.dirty;
7150 regs[i].isconst=0;
7151 regs[i].wasconst=0;
7152 current.isconst=0;
7153 // Create entry (branch target) regmap
7154 for(hr=0;hr<HOST_REGS;hr++)
7155 {
7156 int r=temp.regmap[hr];
7157 if(r>=0) {
7158 if(r!=regmap_pre[i][hr]) {
7159 regs[i].regmap_entry[hr]=-1;
7160 }
7161 else
7162 {
7163 assert(r < 64);
7164 if((current.u>>r)&1) {
7165 regs[i].regmap_entry[hr]=-1;
7166 regs[i].regmap[hr]=-1;
7167 //Don't clear regs in the delay slot as the branch might need them
7168 //current.regmap[hr]=-1;
7169 }else
7170 regs[i].regmap_entry[hr]=r;
7171 }
7172 } else {
7173 // First instruction expects CCREG to be allocated
7174 if(i==0&&hr==HOST_CCREG)
7175 regs[i].regmap_entry[hr]=CCREG;
7176 else
7177 regs[i].regmap_entry[hr]=-1;
7178 }
7179 }
7180 }
7181 else { // Not delay slot
7182 switch(dops[i].itype) {
7183 case UJUMP:
7184 //current.isconst=0; // DEBUG
7185 //current.wasconst=0; // DEBUG
7186 //regs[i].wasconst=0; // DEBUG
7187 clear_const(&current,dops[i].rt1);
7188 alloc_cc(&current,i);
7189 dirty_reg(&current,CCREG);
7190 if (dops[i].rt1==31) {
7191 alloc_reg(&current,i,31);
7192 dirty_reg(&current,31);
7193 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7194 //assert(dops[i+1].rt1!=dops[i].rt1);
7195 #ifdef REG_PREFETCH
7196 alloc_reg(&current,i,PTEMP);
7197 #endif
7198 }
7199 dops[i].ooo=1;
7200 delayslot_alloc(&current,i+1);
7201 //current.isconst=0; // DEBUG
7202 ds=1;
7203 //printf("i=%d, isconst=%x\n",i,current.isconst);
7204 break;
7205 case RJUMP:
7206 //current.isconst=0;
7207 //current.wasconst=0;
7208 //regs[i].wasconst=0;
7209 clear_const(&current,dops[i].rs1);
7210 clear_const(&current,dops[i].rt1);
7211 alloc_cc(&current,i);
7212 dirty_reg(&current,CCREG);
7213 if (!ds_writes_rjump_rs(i)) {
7214 alloc_reg(&current,i,dops[i].rs1);
7215 if (dops[i].rt1!=0) {
7216 alloc_reg(&current,i,dops[i].rt1);
7217 dirty_reg(&current,dops[i].rt1);
7218 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7219 assert(dops[i+1].rt1!=dops[i].rt1);
7220 #ifdef REG_PREFETCH
7221 alloc_reg(&current,i,PTEMP);
7222 #endif
7223 }
7224 #ifdef USE_MINI_HT
7225 if(dops[i].rs1==31) { // JALR
7226 alloc_reg(&current,i,RHASH);
7227 alloc_reg(&current,i,RHTBL);
7228 }
7229 #endif
7230 delayslot_alloc(&current,i+1);
7231 } else {
7232 // The delay slot overwrites our source register,
7233 // allocate a temporary register to hold the old value.
7234 current.isconst=0;
7235 current.wasconst=0;
7236 regs[i].wasconst=0;
7237 delayslot_alloc(&current,i+1);
7238 current.isconst=0;
7239 alloc_reg(&current,i,RTEMP);
7240 }
7241 //current.isconst=0; // DEBUG
7242 dops[i].ooo=1;
7243 ds=1;
7244 break;
7245 case CJUMP:
7246 //current.isconst=0;
7247 //current.wasconst=0;
7248 //regs[i].wasconst=0;
7249 clear_const(&current,dops[i].rs1);
7250 clear_const(&current,dops[i].rs2);
7251 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7252 {
7253 alloc_cc(&current,i);
7254 dirty_reg(&current,CCREG);
7255 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7256 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7257 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7258 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7259 // The delay slot overwrites one of our conditions.
7260 // Allocate the branch condition registers instead.
7261 current.isconst=0;
7262 current.wasconst=0;
7263 regs[i].wasconst=0;
7264 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7265 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7266 }
7267 else
7268 {
7269 dops[i].ooo=1;
7270 delayslot_alloc(&current,i+1);
7271 }
7272 }
7273 else
7274 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7275 {
7276 alloc_cc(&current,i);
7277 dirty_reg(&current,CCREG);
7278 alloc_reg(&current,i,dops[i].rs1);
7279 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7280 // The delay slot overwrites one of our conditions.
7281 // Allocate the branch condition registers instead.
7282 current.isconst=0;
7283 current.wasconst=0;
7284 regs[i].wasconst=0;
7285 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7286 }
7287 else
7288 {
7289 dops[i].ooo=1;
7290 delayslot_alloc(&current,i+1);
7291 }
7292 }
7293 else
7294 // Don't alloc the delay slot yet because we might not execute it
7295 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7296 {
7297 current.isconst=0;
7298 current.wasconst=0;
7299 regs[i].wasconst=0;
7300 alloc_cc(&current,i);
7301 dirty_reg(&current,CCREG);
7302 alloc_reg(&current,i,dops[i].rs1);
7303 alloc_reg(&current,i,dops[i].rs2);
7304 }
7305 else
7306 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7307 {
7308 current.isconst=0;
7309 current.wasconst=0;
7310 regs[i].wasconst=0;
7311 alloc_cc(&current,i);
7312 dirty_reg(&current,CCREG);
7313 alloc_reg(&current,i,dops[i].rs1);
7314 }
7315 ds=1;
7316 //current.isconst=0;
7317 break;
7318 case SJUMP:
7319 //current.isconst=0;
7320 //current.wasconst=0;
7321 //regs[i].wasconst=0;
7322 clear_const(&current,dops[i].rs1);
7323 clear_const(&current,dops[i].rt1);
7324 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7325 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7326 {
7327 alloc_cc(&current,i);
7328 dirty_reg(&current,CCREG);
7329 alloc_reg(&current,i,dops[i].rs1);
7330 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7331 alloc_reg(&current,i,31);
7332 dirty_reg(&current,31);
7333 //#ifdef REG_PREFETCH
7334 //alloc_reg(&current,i,PTEMP);
7335 //#endif
7336 }
7337 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7338 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7339 // Allocate the branch condition registers instead.
7340 current.isconst=0;
7341 current.wasconst=0;
7342 regs[i].wasconst=0;
7343 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7344 }
7345 else
7346 {
7347 dops[i].ooo=1;
7348 delayslot_alloc(&current,i+1);
7349 }
7350 }
7351 else
7352 // Don't alloc the delay slot yet because we might not execute it
7353 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7354 {
7355 current.isconst=0;
7356 current.wasconst=0;
7357 regs[i].wasconst=0;
7358 alloc_cc(&current,i);
7359 dirty_reg(&current,CCREG);
7360 alloc_reg(&current,i,dops[i].rs1);
7361 }
7362 ds=1;
7363 //current.isconst=0;
7364 break;
7365 case IMM16:
7366 imm16_alloc(&current,i);
7367 break;
7368 case LOAD:
7369 case LOADLR:
7370 load_alloc(&current,i);
7371 break;
7372 case STORE:
7373 case STORELR:
7374 store_alloc(&current,i);
7375 break;
7376 case ALU:
7377 alu_alloc(&current,i);
7378 break;
7379 case SHIFT:
7380 shift_alloc(&current,i);
7381 break;
7382 case MULTDIV:
7383 multdiv_alloc(&current,i);
7384 break;
7385 case SHIFTIMM:
7386 shiftimm_alloc(&current,i);
7387 break;
7388 case MOV:
7389 mov_alloc(&current,i);
7390 break;
7391 case COP0:
7392 cop0_alloc(&current,i);
7393 break;
7394 case COP1:
7395 break;
7396 case COP2:
7397 cop2_alloc(&current,i);
7398 break;
7399 case C1LS:
7400 c1ls_alloc(&current,i);
7401 break;
7402 case C2LS:
7403 c2ls_alloc(&current,i);
7404 break;
7405 case C2OP:
7406 c2op_alloc(&current,i);
7407 break;
7408 case SYSCALL:
7409 case HLECALL:
7410 case INTCALL:
7411 syscall_alloc(&current,i);
7412 break;
7413 }
7414
7415 // Create entry (branch target) regmap
7416 for(hr=0;hr<HOST_REGS;hr++)
7417 {
7418 int r,or;
7419 r=current.regmap[hr];
7420 if(r>=0) {
7421 if(r!=regmap_pre[i][hr]) {
7422 // TODO: delay slot (?)
7423 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7424 if(or<0||r>=TEMPREG){
7425 regs[i].regmap_entry[hr]=-1;
7426 }
7427 else
7428 {
7429 // Just move it to a different register
7430 regs[i].regmap_entry[hr]=r;
7431 // If it was dirty before, it's still dirty
7432 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
7433 }
7434 }
7435 else
7436 {
7437 // Unneeded
7438 if(r==0){
7439 regs[i].regmap_entry[hr]=0;
7440 }
7441 else
7442 {
7443 assert(r<64);
7444 if((current.u>>r)&1) {
7445 regs[i].regmap_entry[hr]=-1;
7446 //regs[i].regmap[hr]=-1;
7447 current.regmap[hr]=-1;
7448 }else
7449 regs[i].regmap_entry[hr]=r;
7450 }
7451 }
7452 } else {
7453 // Branches expect CCREG to be allocated at the target
7454 if(regmap_pre[i][hr]==CCREG)
7455 regs[i].regmap_entry[hr]=CCREG;
7456 else
7457 regs[i].regmap_entry[hr]=-1;
7458 }
7459 }
7460 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7461 }
7462
7463 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7464 current.waswritten|=1<<dops[i-1].rs1;
7465 current.waswritten&=~(1<<dops[i].rt1);
7466 current.waswritten&=~(1<<dops[i].rt2);
7467 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7468 current.waswritten&=~(1<<dops[i].rs1);
7469
7470 /* Branch post-alloc */
7471 if(i>0)
7472 {
7473 current.wasdirty=current.dirty;
7474 switch(dops[i-1].itype) {
7475 case UJUMP:
7476 memcpy(&branch_regs[i-1],&current,sizeof(current));
7477 branch_regs[i-1].isconst=0;
7478 branch_regs[i-1].wasconst=0;
7479 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7480 alloc_cc(&branch_regs[i-1],i-1);
7481 dirty_reg(&branch_regs[i-1],CCREG);
7482 if(dops[i-1].rt1==31) { // JAL
7483 alloc_reg(&branch_regs[i-1],i-1,31);
7484 dirty_reg(&branch_regs[i-1],31);
7485 }
7486 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7487 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7488 break;
7489 case RJUMP:
7490 memcpy(&branch_regs[i-1],&current,sizeof(current));
7491 branch_regs[i-1].isconst=0;
7492 branch_regs[i-1].wasconst=0;
7493 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7494 alloc_cc(&branch_regs[i-1],i-1);
7495 dirty_reg(&branch_regs[i-1],CCREG);
7496 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7497 if(dops[i-1].rt1!=0) { // JALR
7498 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7499 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7500 }
7501 #ifdef USE_MINI_HT
7502 if(dops[i-1].rs1==31) { // JALR
7503 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7504 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7505 }
7506 #endif
7507 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7508 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7509 break;
7510 case CJUMP:
7511 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7512 {
7513 alloc_cc(&current,i-1);
7514 dirty_reg(&current,CCREG);
7515 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7516 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7517 // The delay slot overwrote one of our conditions
7518 // Delay slot goes after the test (in order)
7519 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7520 current.u|=1;
7521 delayslot_alloc(&current,i);
7522 current.isconst=0;
7523 }
7524 else
7525 {
7526 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7527 // Alloc the branch condition registers
7528 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7529 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
7530 }
7531 memcpy(&branch_regs[i-1],&current,sizeof(current));
7532 branch_regs[i-1].isconst=0;
7533 branch_regs[i-1].wasconst=0;
7534 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7535 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7536 }
7537 else
7538 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7539 {
7540 alloc_cc(&current,i-1);
7541 dirty_reg(&current,CCREG);
7542 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7543 // The delay slot overwrote the branch condition
7544 // Delay slot goes after the test (in order)
7545 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7546 current.u|=1;
7547 delayslot_alloc(&current,i);
7548 current.isconst=0;
7549 }
7550 else
7551 {
7552 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7553 // Alloc the branch condition register
7554 alloc_reg(&current,i-1,dops[i-1].rs1);
7555 }
7556 memcpy(&branch_regs[i-1],&current,sizeof(current));
7557 branch_regs[i-1].isconst=0;
7558 branch_regs[i-1].wasconst=0;
7559 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7560 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7561 }
7562 else
7563 // Alloc the delay slot in case the branch is taken
7564 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
7565 {
7566 memcpy(&branch_regs[i-1],&current,sizeof(current));
7567 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7568 alloc_cc(&branch_regs[i-1],i);
7569 dirty_reg(&branch_regs[i-1],CCREG);
7570 delayslot_alloc(&branch_regs[i-1],i);
7571 branch_regs[i-1].isconst=0;
7572 alloc_reg(&current,i,CCREG); // Not taken path
7573 dirty_reg(&current,CCREG);
7574 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7575 }
7576 else
7577 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
7578 {
7579 memcpy(&branch_regs[i-1],&current,sizeof(current));
7580 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7581 alloc_cc(&branch_regs[i-1],i);
7582 dirty_reg(&branch_regs[i-1],CCREG);
7583 delayslot_alloc(&branch_regs[i-1],i);
7584 branch_regs[i-1].isconst=0;
7585 alloc_reg(&current,i,CCREG); // Not taken path
7586 dirty_reg(&current,CCREG);
7587 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7588 }
7589 break;
7590 case SJUMP:
7591 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
7592 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
7593 {
7594 alloc_cc(&current,i-1);
7595 dirty_reg(&current,CCREG);
7596 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7597 // The delay slot overwrote the branch condition
7598 // Delay slot goes after the test (in order)
7599 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7600 current.u|=1;
7601 delayslot_alloc(&current,i);
7602 current.isconst=0;
7603 }
7604 else
7605 {
7606 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7607 // Alloc the branch condition register
7608 alloc_reg(&current,i-1,dops[i-1].rs1);
7609 }
7610 memcpy(&branch_regs[i-1],&current,sizeof(current));
7611 branch_regs[i-1].isconst=0;
7612 branch_regs[i-1].wasconst=0;
7613 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7614 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7615 }
7616 else
7617 // Alloc the delay slot in case the branch is taken
7618 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
7619 {
7620 memcpy(&branch_regs[i-1],&current,sizeof(current));
7621 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7622 alloc_cc(&branch_regs[i-1],i);
7623 dirty_reg(&branch_regs[i-1],CCREG);
7624 delayslot_alloc(&branch_regs[i-1],i);
7625 branch_regs[i-1].isconst=0;
7626 alloc_reg(&current,i,CCREG); // Not taken path
7627 dirty_reg(&current,CCREG);
7628 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7629 }
7630 // FIXME: BLTZAL/BGEZAL
7631 if(dops[i-1].opcode2&0x10) { // BxxZAL
7632 alloc_reg(&branch_regs[i-1],i-1,31);
7633 dirty_reg(&branch_regs[i-1],31);
7634 }
7635 break;
7636 }
7637
7638 if (dops[i-1].is_ujump)
7639 {
7640 if(dops[i-1].rt1==31) // JAL/JALR
7641 {
7642 // Subroutine call will return here, don't alloc any registers
7643 current.dirty=0;
7644 clear_all_regs(current.regmap);
7645 alloc_reg(&current,i,CCREG);
7646 dirty_reg(&current,CCREG);
7647 }
7648 else if(i+1<slen)
7649 {
7650 // Internal branch will jump here, match registers to caller
7651 current.dirty=0;
7652 clear_all_regs(current.regmap);
7653 alloc_reg(&current,i,CCREG);
7654 dirty_reg(&current,CCREG);
7655 for(j=i-1;j>=0;j--)
7656 {
7657 if(ba[j]==start+i*4+4) {
7658 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7659 current.dirty=branch_regs[j].dirty;
7660 break;
7661 }
7662 }
7663 while(j>=0) {
7664 if(ba[j]==start+i*4+4) {
7665 for(hr=0;hr<HOST_REGS;hr++) {
7666 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7667 current.regmap[hr]=-1;
7668 }
7669 current.dirty&=branch_regs[j].dirty;
7670 }
7671 }
7672 j--;
7673 }
7674 }
7675 }
7676 }
7677
7678 // Count cycles in between branches
7679 ccadj[i] = CLOCK_ADJUST(cc);
7680 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
7681 {
7682 cc=0;
7683 }
7684#if !defined(DRC_DBG)
7685 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
7686 {
7687 // this should really be removed since the real stalls have been implemented,
7688 // but doing so causes sizeable perf regression against the older version
7689 u_int gtec = gte_cycletab[source[i] & 0x3f];
7690 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7691 }
7692 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7693 {
7694 cc+=4;
7695 }
7696 else if(dops[i].itype==C2LS)
7697 {
7698 // same as with C2OP
7699 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7700 }
7701#endif
7702 else
7703 {
7704 cc++;
7705 }
7706
7707 if(!dops[i].is_ds) {
7708 regs[i].dirty=current.dirty;
7709 regs[i].isconst=current.isconst;
7710 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7711 }
7712 for(hr=0;hr<HOST_REGS;hr++) {
7713 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7714 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7715 regs[i].wasconst&=~(1<<hr);
7716 }
7717 }
7718 }
7719 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7720 regs[i].waswritten=current.waswritten;
7721 }
7722}
7723
7724static noinline void pass4_cull_unused_regs(void)
7725{
7726 u_int last_needed_regs[4] = {0,0,0,0};
7727 u_int nr=0;
7728 int i;
7729
7730 for (i=slen-1;i>=0;i--)
7731 {
7732 int hr;
7733 __builtin_prefetch(regs[i-2].regmap);
7734 if(dops[i].is_jump)
7735 {
7736 if(ba[i]<start || ba[i]>=(start+slen*4))
7737 {
7738 // Branch out of this block, don't need anything
7739 nr=0;
7740 }
7741 else
7742 {
7743 // Internal branch
7744 // Need whatever matches the target
7745 nr=0;
7746 int t=(ba[i]-start)>>2;
7747 for(hr=0;hr<HOST_REGS;hr++)
7748 {
7749 if(regs[i].regmap_entry[hr]>=0) {
7750 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7751 }
7752 }
7753 }
7754 // Conditional branch may need registers for following instructions
7755 if (!dops[i].is_ujump)
7756 {
7757 if(i<slen-2) {
7758 nr |= last_needed_regs[(i+2) & 3];
7759 for(hr=0;hr<HOST_REGS;hr++)
7760 {
7761 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7762 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7763 }
7764 }
7765 }
7766 // Don't need stuff which is overwritten
7767 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7768 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7769 // Merge in delay slot
7770 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7771 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7772 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7773 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7774 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7775 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7776 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7777 nr |= get_regm(regmap_pre[i], ROREG);
7778 nr |= get_regm(regs[i].regmap_entry, ROREG);
7779 }
7780 if (dops[i+1].is_store) {
7781 nr |= get_regm(regmap_pre[i], INVCP);
7782 nr |= get_regm(regs[i].regmap_entry, INVCP);
7783 }
7784 }
7785 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7786 {
7787 // SYSCALL instruction (software interrupt)
7788 nr=0;
7789 }
7790 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7791 {
7792 // ERET instruction (return from interrupt)
7793 nr=0;
7794 }
7795 else // Non-branch
7796 {
7797 if(i<slen-1) {
7798 for(hr=0;hr<HOST_REGS;hr++) {
7799 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7800 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7801 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7802 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7803 }
7804 }
7805 }
7806 // Overwritten registers are not needed
7807 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7808 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7809 nr &= ~get_regm(regs[i].regmap, FTEMP);
7810 // Source registers are needed
7811 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7812 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7813 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7814 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7815 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7816 nr |= get_regm(regmap_pre[i], ROREG);
7817 nr |= get_regm(regs[i].regmap_entry, ROREG);
7818 }
7819 if (dops[i].is_store) {
7820 nr |= get_regm(regmap_pre[i], INVCP);
7821 nr |= get_regm(regs[i].regmap_entry, INVCP);
7822 }
7823
7824 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7825 for(hr=0;hr<HOST_REGS;hr++)
7826 {
7827 // Don't store a register immediately after writing it,
7828 // may prevent dual-issue.
7829 // But do so if this is a branch target, otherwise we
7830 // might have to load the register before the branch.
7831 if((regs[i].wasdirty>>hr)&1) {
7832 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7833 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7834 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7835 }
7836 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7837 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7838 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7839 }
7840 }
7841 }
7842 // Cycle count is needed at branches. Assume it is needed at the target too.
7843 if(i==0||dops[i].bt||dops[i].itype==CJUMP) {
7844 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7845 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7846 }
7847 // Save it
7848 last_needed_regs[i & 3] = nr;
7849
7850 // Deallocate unneeded registers
7851 for(hr=0;hr<HOST_REGS;hr++)
7852 {
7853 if(!((nr>>hr)&1)) {
7854 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7855 if(dops[i].is_jump)
7856 {
7857 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7858 if (dops[i+1].is_load || dops[i+1].is_store)
7859 map1 = ROREG;
7860 if (dops[i+1].is_store)
7861 map2 = INVCP;
7862 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7863 temp = FTEMP;
7864 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7865 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7866 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7867 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7868 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7869 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7870 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7871 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7872 {
7873 regs[i].regmap[hr]=-1;
7874 regs[i].isconst&=~(1<<hr);
7875 regs[i].dirty&=~(1<<hr);
7876 regs[i+1].wasdirty&=~(1<<hr);
7877 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7878 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7879 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7880 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7881 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7882 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7883 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7884 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7885 {
7886 branch_regs[i].regmap[hr]=-1;
7887 branch_regs[i].regmap_entry[hr]=-1;
7888 if (!dops[i].is_ujump)
7889 {
7890 if (i < slen-2) {
7891 regmap_pre[i+2][hr]=-1;
7892 regs[i+2].wasconst&=~(1<<hr);
7893 }
7894 }
7895 }
7896 }
7897 }
7898 else
7899 {
7900 // Non-branch
7901 if(i>0)
7902 {
7903 int map1 = -1, map2 = -1, temp=-1;
7904 if (dops[i].is_load || dops[i].is_store)
7905 map1 = ROREG;
7906 if (dops[i].is_store)
7907 map2 = INVCP;
7908 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7909 temp = FTEMP;
7910 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7911 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7912 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
7913 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7914 regs[i].regmap[hr] != CCREG)
7915 {
7916 if(i<slen-1&&!dops[i].is_ds) {
7917 assert(regs[i].regmap[hr]<64);
7918 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
7919 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
7920 {
7921 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
7922 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7923 }
7924 regmap_pre[i+1][hr]=-1;
7925 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
7926 regs[i+1].wasconst&=~(1<<hr);
7927 }
7928 regs[i].regmap[hr]=-1;
7929 regs[i].isconst&=~(1<<hr);
7930 regs[i].dirty&=~(1<<hr);
7931 regs[i+1].wasdirty&=~(1<<hr);
7932 }
7933 }
7934 }
7935 } // if needed
7936 } // for hr
7937 }
7938}
7939
7940// If a register is allocated during a loop, try to allocate it for the
7941// entire loop, if possible. This avoids loading/storing registers
7942// inside of the loop.
7943static noinline void pass5a_preallocate1(void)
7944{
7945 int i, j, hr;
7946 signed char f_regmap[HOST_REGS];
7947 clear_all_regs(f_regmap);
7948 for(i=0;i<slen-1;i++)
7949 {
7950 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
7951 {
7952 if(ba[i]>=start && ba[i]<(start+i*4))
7953 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
7954 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
7955 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
7956 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
7957 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
7958 {
7959 int t=(ba[i]-start)>>2;
7960 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
7961 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
7962 for(hr=0;hr<HOST_REGS;hr++)
7963 {
7964 if(regs[i].regmap[hr]>=0) {
7965 if(f_regmap[hr]!=regs[i].regmap[hr]) {
7966 // dealloc old register
7967 int n;
7968 for(n=0;n<HOST_REGS;n++)
7969 {
7970 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
7971 }
7972 // and alloc new one
7973 f_regmap[hr]=regs[i].regmap[hr];
7974 }
7975 }
7976 if(branch_regs[i].regmap[hr]>=0) {
7977 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
7978 // dealloc old register
7979 int n;
7980 for(n=0;n<HOST_REGS;n++)
7981 {
7982 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
7983 }
7984 // and alloc new one
7985 f_regmap[hr]=branch_regs[i].regmap[hr];
7986 }
7987 }
7988 if(dops[i].ooo) {
7989 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
7990 f_regmap[hr]=branch_regs[i].regmap[hr];
7991 }else{
7992 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
7993 f_regmap[hr]=branch_regs[i].regmap[hr];
7994 }
7995 // Avoid dirty->clean transition
7996 #ifdef DESTRUCTIVE_WRITEBACK
7997 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
7998 #endif
7999 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8000 // case above, however it's always a good idea. We can't hoist the
8001 // load if the register was already allocated, so there's no point
8002 // wasting time analyzing most of these cases. It only "succeeds"
8003 // when the mapping was different and the load can be replaced with
8004 // a mov, which is of negligible benefit. So such cases are
8005 // skipped below.
8006 if(f_regmap[hr]>0) {
8007 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8008 int r=f_regmap[hr];
8009 for(j=t;j<=i;j++)
8010 {
8011 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8012 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8013 assert(r < 64);
8014 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8015 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8016 int k;
8017 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8018 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8019 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8020 k=i;
8021 while(k>1&&regs[k-1].regmap[hr]==-1) {
8022 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8023 //printf("no free regs for store %x\n",start+(k-1)*4);
8024 break;
8025 }
8026 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8027 //printf("no-match due to different register\n");
8028 break;
8029 }
8030 if (dops[k-2].is_jump) {
8031 //printf("no-match due to branch\n");
8032 break;
8033 }
8034 // call/ret fast path assumes no registers allocated
8035 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8036 break;
8037 }
8038 k--;
8039 }
8040 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8041 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8042 while(k<i) {
8043 regs[k].regmap_entry[hr]=f_regmap[hr];
8044 regs[k].regmap[hr]=f_regmap[hr];
8045 regmap_pre[k+1][hr]=f_regmap[hr];
8046 regs[k].wasdirty&=~(1<<hr);
8047 regs[k].dirty&=~(1<<hr);
8048 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8049 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8050 regs[k].wasconst&=~(1<<hr);
8051 regs[k].isconst&=~(1<<hr);
8052 k++;
8053 }
8054 }
8055 else {
8056 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8057 break;
8058 }
8059 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8060 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8061 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8062 regs[i].regmap_entry[hr]=f_regmap[hr];
8063 regs[i].regmap[hr]=f_regmap[hr];
8064 regs[i].wasdirty&=~(1<<hr);
8065 regs[i].dirty&=~(1<<hr);
8066 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8067 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8068 regs[i].wasconst&=~(1<<hr);
8069 regs[i].isconst&=~(1<<hr);
8070 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8071 branch_regs[i].wasdirty&=~(1<<hr);
8072 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8073 branch_regs[i].regmap[hr]=f_regmap[hr];
8074 branch_regs[i].dirty&=~(1<<hr);
8075 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8076 branch_regs[i].wasconst&=~(1<<hr);
8077 branch_regs[i].isconst&=~(1<<hr);
8078 if (!dops[i].is_ujump) {
8079 regmap_pre[i+2][hr]=f_regmap[hr];
8080 regs[i+2].wasdirty&=~(1<<hr);
8081 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
8082 }
8083 }
8084 }
8085 for(k=t;k<j;k++) {
8086 // Alloc register clean at beginning of loop,
8087 // but may dirty it in pass 6
8088 regs[k].regmap_entry[hr]=f_regmap[hr];
8089 regs[k].regmap[hr]=f_regmap[hr];
8090 regs[k].dirty&=~(1<<hr);
8091 regs[k].wasconst&=~(1<<hr);
8092 regs[k].isconst&=~(1<<hr);
8093 if (dops[k].is_jump) {
8094 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8095 branch_regs[k].regmap[hr]=f_regmap[hr];
8096 branch_regs[k].dirty&=~(1<<hr);
8097 branch_regs[k].wasconst&=~(1<<hr);
8098 branch_regs[k].isconst&=~(1<<hr);
8099 if (!dops[k].is_ujump) {
8100 regmap_pre[k+2][hr]=f_regmap[hr];
8101 regs[k+2].wasdirty&=~(1<<hr);
8102 }
8103 }
8104 else
8105 {
8106 regmap_pre[k+1][hr]=f_regmap[hr];
8107 regs[k+1].wasdirty&=~(1<<hr);
8108 }
8109 }
8110 if(regs[j].regmap[hr]==f_regmap[hr])
8111 regs[j].regmap_entry[hr]=f_regmap[hr];
8112 break;
8113 }
8114 if(j==i) break;
8115 if(regs[j].regmap[hr]>=0)
8116 break;
8117 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8118 //printf("no-match due to different register\n");
8119 break;
8120 }
8121 if (dops[j].is_ujump)
8122 {
8123 // Stop on unconditional branch
8124 break;
8125 }
8126 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8127 {
8128 if(dops[j].ooo) {
8129 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8130 break;
8131 }else{
8132 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8133 break;
8134 }
8135 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8136 //printf("no-match due to different register (branch)\n");
8137 break;
8138 }
8139 }
8140 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8141 //printf("No free regs for store %x\n",start+j*4);
8142 break;
8143 }
8144 assert(f_regmap[hr]<64);
8145 }
8146 }
8147 }
8148 }
8149 }
8150 }else{
8151 // Non branch or undetermined branch target
8152 for(hr=0;hr<HOST_REGS;hr++)
8153 {
8154 if(hr!=EXCLUDE_REG) {
8155 if(regs[i].regmap[hr]>=0) {
8156 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8157 // dealloc old register
8158 int n;
8159 for(n=0;n<HOST_REGS;n++)
8160 {
8161 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8162 }
8163 // and alloc new one
8164 f_regmap[hr]=regs[i].regmap[hr];
8165 }
8166 }
8167 }
8168 }
8169 // Try to restore cycle count at branch targets
8170 if(dops[i].bt) {
8171 for(j=i;j<slen-1;j++) {
8172 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8173 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8174 //printf("no free regs for store %x\n",start+j*4);
8175 break;
8176 }
8177 }
8178 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8179 int k=i;
8180 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8181 while(k<j) {
8182 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8183 regs[k].regmap[HOST_CCREG]=CCREG;
8184 regmap_pre[k+1][HOST_CCREG]=CCREG;
8185 regs[k+1].wasdirty|=1<<HOST_CCREG;
8186 regs[k].dirty|=1<<HOST_CCREG;
8187 regs[k].wasconst&=~(1<<HOST_CCREG);
8188 regs[k].isconst&=~(1<<HOST_CCREG);
8189 k++;
8190 }
8191 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8192 }
8193 // Work backwards from the branch target
8194 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8195 {
8196 //printf("Extend backwards\n");
8197 int k;
8198 k=i;
8199 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8200 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8201 //printf("no free regs for store %x\n",start+(k-1)*4);
8202 break;
8203 }
8204 k--;
8205 }
8206 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8207 //printf("Extend CC, %x ->\n",start+k*4);
8208 while(k<=i) {
8209 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8210 regs[k].regmap[HOST_CCREG]=CCREG;
8211 regmap_pre[k+1][HOST_CCREG]=CCREG;
8212 regs[k+1].wasdirty|=1<<HOST_CCREG;
8213 regs[k].dirty|=1<<HOST_CCREG;
8214 regs[k].wasconst&=~(1<<HOST_CCREG);
8215 regs[k].isconst&=~(1<<HOST_CCREG);
8216 k++;
8217 }
8218 }
8219 else {
8220 //printf("Fail Extend CC, %x ->\n",start+k*4);
8221 }
8222 }
8223 }
8224 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8225 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8226 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8227 {
8228 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8229 }
8230 }
8231 }
8232}
8233
8234// This allocates registers (if possible) one instruction prior
8235// to use, which can avoid a load-use penalty on certain CPUs.
8236static noinline void pass5b_preallocate2(void)
8237{
8238 int i, hr;
8239 for(i=0;i<slen-1;i++)
8240 {
8241 if (!i || !dops[i-1].is_jump)
8242 {
8243 if(!dops[i+1].bt)
8244 {
8245 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8246 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8247 {
8248 if(dops[i+1].rs1) {
8249 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8250 {
8251 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8252 {
8253 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8254 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8255 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8256 regs[i].isconst&=~(1<<hr);
8257 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8258 constmap[i][hr]=constmap[i+1][hr];
8259 regs[i+1].wasdirty&=~(1<<hr);
8260 regs[i].dirty&=~(1<<hr);
8261 }
8262 }
8263 }
8264 if(dops[i+1].rs2) {
8265 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8266 {
8267 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8268 {
8269 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8270 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8271 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8272 regs[i].isconst&=~(1<<hr);
8273 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8274 constmap[i][hr]=constmap[i+1][hr];
8275 regs[i+1].wasdirty&=~(1<<hr);
8276 regs[i].dirty&=~(1<<hr);
8277 }
8278 }
8279 }
8280 // Preload target address for load instruction (non-constant)
8281 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8282 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8283 {
8284 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8285 {
8286 regs[i].regmap[hr]=dops[i+1].rs1;
8287 regmap_pre[i+1][hr]=dops[i+1].rs1;
8288 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8289 regs[i].isconst&=~(1<<hr);
8290 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8291 constmap[i][hr]=constmap[i+1][hr];
8292 regs[i+1].wasdirty&=~(1<<hr);
8293 regs[i].dirty&=~(1<<hr);
8294 }
8295 }
8296 }
8297 // Load source into target register
8298 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8299 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8300 {
8301 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8302 {
8303 regs[i].regmap[hr]=dops[i+1].rs1;
8304 regmap_pre[i+1][hr]=dops[i+1].rs1;
8305 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8306 regs[i].isconst&=~(1<<hr);
8307 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8308 constmap[i][hr]=constmap[i+1][hr];
8309 regs[i+1].wasdirty&=~(1<<hr);
8310 regs[i].dirty&=~(1<<hr);
8311 }
8312 }
8313 }
8314 // Address for store instruction (non-constant)
8315 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8316 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8317 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8318 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8319 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8320 else {
8321 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8322 regs[i+1].isconst&=~(1<<hr);
8323 }
8324 assert(hr>=0);
8325 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8326 {
8327 regs[i].regmap[hr]=dops[i+1].rs1;
8328 regmap_pre[i+1][hr]=dops[i+1].rs1;
8329 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8330 regs[i].isconst&=~(1<<hr);
8331 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8332 constmap[i][hr]=constmap[i+1][hr];
8333 regs[i+1].wasdirty&=~(1<<hr);
8334 regs[i].dirty&=~(1<<hr);
8335 }
8336 }
8337 }
8338 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8339 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8340 int nr;
8341 hr=get_reg(regs[i+1].regmap,FTEMP);
8342 assert(hr>=0);
8343 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8344 {
8345 regs[i].regmap[hr]=dops[i+1].rs1;
8346 regmap_pre[i+1][hr]=dops[i+1].rs1;
8347 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8348 regs[i].isconst&=~(1<<hr);
8349 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8350 constmap[i][hr]=constmap[i+1][hr];
8351 regs[i+1].wasdirty&=~(1<<hr);
8352 regs[i].dirty&=~(1<<hr);
8353 }
8354 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8355 {
8356 // move it to another register
8357 regs[i+1].regmap[hr]=-1;
8358 regmap_pre[i+2][hr]=-1;
8359 regs[i+1].regmap[nr]=FTEMP;
8360 regmap_pre[i+2][nr]=FTEMP;
8361 regs[i].regmap[nr]=dops[i+1].rs1;
8362 regmap_pre[i+1][nr]=dops[i+1].rs1;
8363 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8364 regs[i].isconst&=~(1<<nr);
8365 regs[i+1].isconst&=~(1<<nr);
8366 regs[i].dirty&=~(1<<nr);
8367 regs[i+1].wasdirty&=~(1<<nr);
8368 regs[i+1].dirty&=~(1<<nr);
8369 regs[i+2].wasdirty&=~(1<<nr);
8370 }
8371 }
8372 }
8373 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8374 hr = -1;
8375 if(dops[i+1].itype==LOAD)
8376 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8377 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8378 hr=get_reg(regs[i+1].regmap,FTEMP);
8379 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8380 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8381 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8382 }
8383 if(hr>=0&&regs[i].regmap[hr]<0) {
8384 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8385 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8386 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8387 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8388 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8389 regs[i].isconst&=~(1<<hr);
8390 regs[i+1].wasdirty&=~(1<<hr);
8391 regs[i].dirty&=~(1<<hr);
8392 }
8393 }
8394 }
8395 }
8396 }
8397 }
8398 }
8399}
8400
8401// Write back dirty registers as soon as we will no longer modify them,
8402// so that we don't end up with lots of writes at the branches.
8403static noinline void pass6_clean_registers(int istart, int iend, int wr)
8404{
8405 static u_int wont_dirty[MAXBLOCK];
8406 static u_int will_dirty[MAXBLOCK];
8407 int i;
8408 int r;
8409 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8410 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8411 if(iend==slen-1) {
8412 will_dirty_i=will_dirty_next=0;
8413 wont_dirty_i=wont_dirty_next=0;
8414 }else{
8415 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8416 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8417 }
8418 for (i=iend;i>=istart;i--)
8419 {
8420 signed char rregmap_i[RRMAP_SIZE];
8421 u_int hr_candirty = 0;
8422 assert(HOST_REGS < 32);
8423 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8424 __builtin_prefetch(regs[i-1].regmap);
8425 if(dops[i].is_jump)
8426 {
8427 signed char branch_rregmap_i[RRMAP_SIZE];
8428 u_int branch_hr_candirty = 0;
8429 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8430 if(ba[i]<start || ba[i]>=(start+slen*4))
8431 {
8432 // Branch out of this block, flush all regs
8433 will_dirty_i = 0;
8434 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8435 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8436 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8437 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8438 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8439 will_dirty_i &= branch_hr_candirty;
8440 if (dops[i].is_ujump)
8441 {
8442 // Unconditional branch
8443 wont_dirty_i = 0;
8444 // Merge in delay slot (will dirty)
8445 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8446 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8447 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8448 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8449 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8450 will_dirty_i &= hr_candirty;
8451 }
8452 else
8453 {
8454 // Conditional branch
8455 wont_dirty_i = wont_dirty_next;
8456 // Merge in delay slot (will dirty)
8457 // (the original code had no explanation why these 2 are commented out)
8458 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8459 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8460 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8461 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8462 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8463 will_dirty_i &= hr_candirty;
8464 }
8465 // Merge in delay slot (wont dirty)
8466 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8467 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8468 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8469 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8470 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8471 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8472 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8473 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8474 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8475 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8476 wont_dirty_i &= ~(1u << 31);
8477 if(wr) {
8478 #ifndef DESTRUCTIVE_WRITEBACK
8479 branch_regs[i].dirty&=wont_dirty_i;
8480 #endif
8481 branch_regs[i].dirty|=will_dirty_i;
8482 }
8483 }
8484 else
8485 {
8486 // Internal branch
8487 if(ba[i]<=start+i*4) {
8488 // Backward branch
8489 if (dops[i].is_ujump)
8490 {
8491 // Unconditional branch
8492 temp_will_dirty=0;
8493 temp_wont_dirty=0;
8494 // Merge in delay slot (will dirty)
8495 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8496 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8497 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8498 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8499 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8500 temp_will_dirty &= branch_hr_candirty;
8501 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8502 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8503 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8504 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8505 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8506 temp_will_dirty &= hr_candirty;
8507 } else {
8508 // Conditional branch (not taken case)
8509 temp_will_dirty=will_dirty_next;
8510 temp_wont_dirty=wont_dirty_next;
8511 // Merge in delay slot (will dirty)
8512 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8513 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8514 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8515 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8516 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8517 temp_will_dirty &= branch_hr_candirty;
8518 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8519 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8520 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8521 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8522 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8523 temp_will_dirty &= hr_candirty;
8524 }
8525 // Merge in delay slot (wont dirty)
8526 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8527 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8528 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8529 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8530 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8531 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8532 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8533 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8534 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8535 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8536 temp_wont_dirty &= ~(1u << 31);
8537 // Deal with changed mappings
8538 if(i<iend) {
8539 for(r=0;r<HOST_REGS;r++) {
8540 if(r!=EXCLUDE_REG) {
8541 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8542 temp_will_dirty&=~(1<<r);
8543 temp_wont_dirty&=~(1<<r);
8544 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8545 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8546 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8547 } else {
8548 temp_will_dirty|=1<<r;
8549 temp_wont_dirty|=1<<r;
8550 }
8551 }
8552 }
8553 }
8554 }
8555 if(wr) {
8556 will_dirty[i]=temp_will_dirty;
8557 wont_dirty[i]=temp_wont_dirty;
8558 pass6_clean_registers((ba[i]-start)>>2,i-1,0);
8559 }else{
8560 // Limit recursion. It can take an excessive amount
8561 // of time if there are a lot of nested loops.
8562 will_dirty[(ba[i]-start)>>2]=0;
8563 wont_dirty[(ba[i]-start)>>2]=-1;
8564 }
8565 }
8566 /*else*/ if(1)
8567 {
8568 if (dops[i].is_ujump)
8569 {
8570 // Unconditional branch
8571 will_dirty_i=0;
8572 wont_dirty_i=0;
8573 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
8574 for(r=0;r<HOST_REGS;r++) {
8575 if(r!=EXCLUDE_REG) {
8576 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8577 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
8578 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8579 }
8580 if(branch_regs[i].regmap[r]>=0) {
8581 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8582 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8583 }
8584 }
8585 }
8586 //}
8587 // Merge in delay slot
8588 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8589 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8590 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8591 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8592 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8593 will_dirty_i &= branch_hr_candirty;
8594 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8595 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8596 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8597 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8598 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8599 will_dirty_i &= hr_candirty;
8600 } else {
8601 // Conditional branch
8602 will_dirty_i=will_dirty_next;
8603 wont_dirty_i=wont_dirty_next;
8604 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
8605 for(r=0;r<HOST_REGS;r++) {
8606 if(r!=EXCLUDE_REG) {
8607 signed char target_reg=branch_regs[i].regmap[r];
8608 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8609 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
8610 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8611 }
8612 else if(target_reg>=0) {
8613 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8614 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8615 }
8616 }
8617 }
8618 // Merge in delay slot
8619 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8620 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8621 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8622 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8623 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8624 will_dirty_i &= branch_hr_candirty;
8625 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8626 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8627 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8628 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8629 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8630 will_dirty_i &= hr_candirty;
8631 }
8632 // Merge in delay slot (won't dirty)
8633 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8634 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8635 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8636 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8637 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8638 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8639 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8640 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8641 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8642 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8643 wont_dirty_i &= ~(1u << 31);
8644 if(wr) {
8645 #ifndef DESTRUCTIVE_WRITEBACK
8646 branch_regs[i].dirty&=wont_dirty_i;
8647 #endif
8648 branch_regs[i].dirty|=will_dirty_i;
8649 }
8650 }
8651 }
8652 }
8653 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8654 {
8655 // SYSCALL instruction (software interrupt)
8656 will_dirty_i=0;
8657 wont_dirty_i=0;
8658 }
8659 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8660 {
8661 // ERET instruction (return from interrupt)
8662 will_dirty_i=0;
8663 wont_dirty_i=0;
8664 }
8665 will_dirty_next=will_dirty_i;
8666 wont_dirty_next=wont_dirty_i;
8667 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8668 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8669 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8670 will_dirty_i &= hr_candirty;
8671 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8672 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8673 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8674 wont_dirty_i &= ~(1u << 31);
8675 if (i > istart && !dops[i].is_jump) {
8676 // Don't store a register immediately after writing it,
8677 // may prevent dual-issue.
8678 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8679 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8680 }
8681 // Save it
8682 will_dirty[i]=will_dirty_i;
8683 wont_dirty[i]=wont_dirty_i;
8684 // Mark registers that won't be dirtied as not dirty
8685 if(wr) {
8686 regs[i].dirty|=will_dirty_i;
8687 #ifndef DESTRUCTIVE_WRITEBACK
8688 regs[i].dirty&=wont_dirty_i;
8689 if(dops[i].is_jump)
8690 {
8691 if (i < iend-1 && !dops[i].is_ujump) {
8692 for(r=0;r<HOST_REGS;r++) {
8693 if(r!=EXCLUDE_REG) {
8694 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8695 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8696 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8697 }
8698 }
8699 }
8700 }
8701 else
8702 {
8703 if(i<iend) {
8704 for(r=0;r<HOST_REGS;r++) {
8705 if(r!=EXCLUDE_REG) {
8706 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8707 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8708 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8709 }
8710 }
8711 }
8712 }
8713 #endif
8714 }
8715 // Deal with changed mappings
8716 temp_will_dirty=will_dirty_i;
8717 temp_wont_dirty=wont_dirty_i;
8718 for(r=0;r<HOST_REGS;r++) {
8719 if(r!=EXCLUDE_REG) {
8720 int nr;
8721 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8722 if(wr) {
8723 #ifndef DESTRUCTIVE_WRITEBACK
8724 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8725 #endif
8726 regs[i].wasdirty|=will_dirty_i&(1<<r);
8727 }
8728 }
8729 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8730 // Register moved to a different register
8731 will_dirty_i&=~(1<<r);
8732 wont_dirty_i&=~(1<<r);
8733 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8734 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8735 if(wr) {
8736 #ifndef DESTRUCTIVE_WRITEBACK
8737 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8738 #endif
8739 regs[i].wasdirty|=will_dirty_i&(1<<r);
8740 }
8741 }
8742 else {
8743 will_dirty_i&=~(1<<r);
8744 wont_dirty_i&=~(1<<r);
8745 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8746 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8747 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8748 } else {
8749 wont_dirty_i|=1<<r;
8750 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8751 }
8752 }
8753 }
8754 }
8755 }
8756}
8757
8758static noinline void pass10_expire_blocks(void)
8759{
8760 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8761 // not sizeof(ndrc->translation_cache) due to vita hack
8762 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8763 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8764 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8765 int hit;
8766
8767 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8768 {
8769 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8770 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8771 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8772 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8773 inv_debug("EXP: base_offs %x/%x phase %u\n", base_offs,
8774 out - ndrc->translation_cache phase);
8775 }
8776
8777 if (!phase) {
8778 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8779 if (hit) {
8780 do_clear_cache();
8781 #ifdef USE_MINI_HT
8782 memset(mini_ht, -1, sizeof(mini_ht));
8783 #endif
8784 }
8785 }
8786 else
8787 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8788 }
8789}
8790
8791static struct block_info *new_block_info(u_int start, u_int len,
8792 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8793{
8794 struct block_info **b_pptr;
8795 struct block_info *block;
8796 u_int page = get_page(start);
8797
8798 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8799 assert(block);
8800 assert(jump_in_count > 0);
8801 block->source = source;
8802 block->copy = copy;
8803 block->start = start;
8804 block->len = len;
8805 block->reg_sv_flags = 0;
8806 block->tc_offs = beginning - ndrc->translation_cache;
8807 //block->tc_len = out - beginning;
8808 block->is_dirty = 0;
8809 block->inv_near_misses = 0;
8810 block->jump_in_cnt = jump_in_count;
8811
8812 // insert sorted by start mirror-unmasked vaddr
8813 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8814 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8815 block->next = *b_pptr;
8816 *b_pptr = block;
8817 break;
8818 }
8819 }
8820 stat_inc(stat_blocks);
8821 return block;
8822}
8823
8824static int new_recompile_block(u_int addr)
8825{
8826 u_int pagelimit = 0;
8827 u_int state_rflags = 0;
8828 int i;
8829
8830 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8831
8832 // this is just for speculation
8833 for (i = 1; i < 32; i++) {
8834 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8835 state_rflags |= 1 << i;
8836 }
8837
8838 assert(!(addr & 3));
8839 start = addr & ~3;
8840 new_dynarec_did_compile=1;
8841 if (Config.HLE && start == 0x80001000) // hlecall
8842 {
8843 // XXX: is this enough? Maybe check hleSoftCall?
8844 void *beginning = start_block();
8845
8846 emit_movimm(start,0);
8847 emit_writeword(0,&pcaddr);
8848 emit_far_jump(new_dyna_leave);
8849 literal_pool(0);
8850 end_block(beginning);
8851 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8852 block->jump_in[0].vaddr = start;
8853 block->jump_in[0].addr = beginning;
8854 return 0;
8855 }
8856 else if (f1_hack && hack_addr == 0) {
8857 void *beginning = start_block();
8858 emit_movimm(start, 0);
8859 emit_writeword(0, &hack_addr);
8860 emit_readword(&psxRegs.GPR.n.sp, 0);
8861 emit_readptr(&mem_rtab, 1);
8862 emit_shrimm(0, 12, 2);
8863 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8864 emit_addimm(0, 0x18, 0);
8865 emit_adds_ptr(1, 1, 1);
8866 emit_ldr_dualindexed(1, 0, 0);
8867 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8868 emit_far_call(ndrc_get_addr_ht);
8869 emit_jmpreg(0); // jr k0
8870 literal_pool(0);
8871 end_block(beginning);
8872
8873 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8874 block->jump_in[0].vaddr = start;
8875 block->jump_in[0].addr = beginning;
8876 SysPrintf("F1 hack to %08x\n", start);
8877 return 0;
8878 }
8879
8880 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
8881 ? cycle_multiplier_override : cycle_multiplier;
8882
8883 source = get_source_start(start, &pagelimit);
8884 if (source == NULL) {
8885 if (addr != hack_addr) {
8886 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8887 hack_addr = addr;
8888 }
8889 //abort();
8890 return -1;
8891 }
8892
8893 /* Pass 1: disassemble */
8894 /* Pass 2: register dependencies, branch targets */
8895 /* Pass 3: register allocation */
8896 /* Pass 4: branch dependencies */
8897 /* Pass 5: pre-alloc */
8898 /* Pass 6: optimize clean/dirty state */
8899 /* Pass 7: flag 32-bit registers */
8900 /* Pass 8: assembly */
8901 /* Pass 9: linker */
8902 /* Pass 10: garbage collection / free memory */
8903
8904 /* Pass 1 disassembly */
8905
8906 pass1_disassemble(pagelimit);
8907
8908 int clear_hack_addr = apply_hacks();
8909
8910 /* Pass 2 - Register dependencies and branch targets */
8911
8912 pass2_unneeded_regs(0,slen-1,0);
8913
8914 /* Pass 3 - Register allocation */
8915
8916 pass3_register_alloc(addr);
8917
8918 /* Pass 4 - Cull unused host registers */
8919
8920 pass4_cull_unused_regs();
8921
8922 /* Pass 5 - Pre-allocate registers */
8923
8924 pass5a_preallocate1();
8925 pass5b_preallocate2();
8926
8927 /* Pass 6 - Optimize clean/dirty state */
8928 pass6_clean_registers(0, slen-1, 1);
8929
8930 /* Pass 7 - Identify 32-bit registers */
8931 for (i=slen-1;i>=0;i--)
8932 {
8933 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8934 {
8935 // Conditional branch
8936 if((source[i]>>16)!=0x1000&&i<slen-2) {
8937 // Mark this address as a branch target since it may be called
8938 // upon return from interrupt
8939 dops[i+2].bt=1;
8940 }
8941 }
8942 }
8943
8944 /* Pass 8 - Assembly */
8945 linkcount=0;stubcount=0;
8946 is_delayslot=0;
8947 u_int dirty_pre=0;
8948 void *beginning=start_block();
8949 void *instr_addr0_override = NULL;
8950 int ds = 0;
8951
8952 if (start == 0x80030000) {
8953 // nasty hack for the fastbios thing
8954 // override block entry to this code
8955 instr_addr0_override = out;
8956 emit_movimm(start,0);
8957 // abuse io address var as a flag that we
8958 // have already returned here once
8959 emit_readword(&address,1);
8960 emit_writeword(0,&pcaddr);
8961 emit_writeword(0,&address);
8962 emit_cmp(0,1);
8963 #ifdef __aarch64__
8964 emit_jeq(out + 4*2);
8965 emit_far_jump(new_dyna_leave);
8966 #else
8967 emit_jne(new_dyna_leave);
8968 #endif
8969 }
8970 for(i=0;i<slen;i++)
8971 {
8972 __builtin_prefetch(regs[i+1].regmap);
8973 check_regmap(regmap_pre[i]);
8974 check_regmap(regs[i].regmap_entry);
8975 check_regmap(regs[i].regmap);
8976 //if(ds) printf("ds: ");
8977 disassemble_inst(i);
8978 if(ds) {
8979 ds=0; // Skip delay slot
8980 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
8981 instr_addr[i] = NULL;
8982 } else {
8983 speculate_register_values(i);
8984 #ifndef DESTRUCTIVE_WRITEBACK
8985 if (i < 2 || !dops[i-2].is_ujump)
8986 {
8987 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
8988 }
8989 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
8990 dirty_pre=branch_regs[i].dirty;
8991 }else{
8992 dirty_pre=regs[i].dirty;
8993 }
8994 #endif
8995 // write back
8996 if (i < 2 || !dops[i-2].is_ujump)
8997 {
8998 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
8999 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9000 }
9001 // branch target entry point
9002 instr_addr[i] = out;
9003 assem_debug("<->\n");
9004 drc_dbg_emit_do_cmp(i, ccadj[i]);
9005 if (clear_hack_addr) {
9006 emit_movimm(0, 0);
9007 emit_writeword(0, &hack_addr);
9008 clear_hack_addr = 0;
9009 }
9010
9011 // load regs
9012 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9013 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9014 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9015 address_generation(i,&regs[i],regs[i].regmap_entry);
9016 load_consts(regmap_pre[i],regs[i].regmap,i);
9017 if(dops[i].is_jump)
9018 {
9019 // Load the delay slot registers if necessary
9020 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9021 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9022 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9023 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9024 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9025 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9026 if (dops[i+1].is_store)
9027 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9028 }
9029 else if(i+1<slen)
9030 {
9031 // Preload registers for following instruction
9032 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9033 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9034 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9035 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9036 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9037 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9038 }
9039 // TODO: if(is_ooo(i)) address_generation(i+1);
9040 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9041 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9042 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9043 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9044 if (dops[i].is_store)
9045 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9046
9047 ds = assemble(i, &regs[i], ccadj[i]);
9048
9049 if (dops[i].is_ujump)
9050 literal_pool(1024);
9051 else
9052 literal_pool_jumpover(256);
9053 }
9054 }
9055
9056 assert(slen > 0);
9057 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9058 // no ending needed for this block since INTCALL never returns
9059 }
9060 // If the block did not end with an unconditional branch,
9061 // add a jump to the next instruction.
9062 else if (i > 1) {
9063 if (!dops[i-2].is_ujump) {
9064 assert(!dops[i-1].is_jump);
9065 assert(i==slen);
9066 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9067 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9068 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9069 emit_loadreg(CCREG,HOST_CCREG);
9070 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9071 }
9072 else
9073 {
9074 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9075 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9076 }
9077 add_to_linker(out,start+i*4,0);
9078 emit_jmp(0);
9079 }
9080 }
9081 else
9082 {
9083 assert(i>0);
9084 assert(!dops[i-1].is_jump);
9085 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9086 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9087 emit_loadreg(CCREG,HOST_CCREG);
9088 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9089 add_to_linker(out,start+i*4,0);
9090 emit_jmp(0);
9091 }
9092
9093 // TODO: delay slot stubs?
9094 // Stubs
9095 for(i=0;i<stubcount;i++)
9096 {
9097 switch(stubs[i].type)
9098 {
9099 case LOADB_STUB:
9100 case LOADH_STUB:
9101 case LOADW_STUB:
9102 case LOADD_STUB:
9103 case LOADBU_STUB:
9104 case LOADHU_STUB:
9105 do_readstub(i);break;
9106 case STOREB_STUB:
9107 case STOREH_STUB:
9108 case STOREW_STUB:
9109 case STORED_STUB:
9110 do_writestub(i);break;
9111 case CC_STUB:
9112 do_ccstub(i);break;
9113 case INVCODE_STUB:
9114 do_invstub(i);break;
9115 case FP_STUB:
9116 do_cop1stub(i);break;
9117 case STORELR_STUB:
9118 do_unalignedwritestub(i);break;
9119 }
9120 }
9121
9122 if (instr_addr0_override)
9123 instr_addr[0] = instr_addr0_override;
9124
9125#if 0
9126 /* check for improper expiration */
9127 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9128 int j;
9129 if (!jumps[i])
9130 continue;
9131 for (j = 0; j < jumps[i]->count; j++)
9132 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9133 }
9134#endif
9135
9136 /* Pass 9 - Linker */
9137 for(i=0;i<linkcount;i++)
9138 {
9139 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9140 literal_pool(64);
9141 if (!link_addr[i].internal)
9142 {
9143 void *stub = out;
9144 void *addr = check_addr(link_addr[i].target);
9145 emit_extjump(link_addr[i].addr, link_addr[i].target);
9146 if (addr) {
9147 set_jump_target(link_addr[i].addr, addr);
9148 ndrc_add_jump_out(link_addr[i].target,stub);
9149 }
9150 else
9151 set_jump_target(link_addr[i].addr, stub);
9152 }
9153 else
9154 {
9155 // Internal branch
9156 int target=(link_addr[i].target-start)>>2;
9157 assert(target>=0&&target<slen);
9158 assert(instr_addr[target]);
9159 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9160 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9161 //#else
9162 set_jump_target(link_addr[i].addr, instr_addr[target]);
9163 //#endif
9164 }
9165 }
9166
9167 u_int source_len = slen*4;
9168 if (dops[slen-1].itype == INTCALL && source_len > 4)
9169 // no need to treat the last instruction as compiled
9170 // as interpreter fully handles it
9171 source_len -= 4;
9172
9173 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9174 copy = shadow;
9175
9176 // External Branch Targets (jump_in)
9177 int jump_in_count = 1;
9178 assert(instr_addr[0]);
9179 for (i = 1; i < slen; i++)
9180 {
9181 if (dops[i].bt && instr_addr[i])
9182 jump_in_count++;
9183 }
9184
9185 struct block_info *block =
9186 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9187 block->reg_sv_flags = state_rflags;
9188
9189 int jump_in_i = 0;
9190 for (i = 0; i < slen; i++)
9191 {
9192 if ((i == 0 || dops[i].bt) && instr_addr[i])
9193 {
9194 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9195 u_int vaddr = start + i*4;
9196
9197 literal_pool(256);
9198 void *entry = out;
9199 load_regs_entry(i);
9200 if (entry == out)
9201 entry = instr_addr[i];
9202 else
9203 emit_jmp(instr_addr[i]);
9204
9205 block->jump_in[jump_in_i].vaddr = vaddr;
9206 block->jump_in[jump_in_i].addr = entry;
9207 jump_in_i++;
9208 }
9209 }
9210 assert(jump_in_i == jump_in_count);
9211 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9212 // Write out the literal pool if necessary
9213 literal_pool(0);
9214 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9215 // Align code
9216 if(((u_int)out)&7) emit_addnop(13);
9217 #endif
9218 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9219 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9220 memcpy(copy, source, source_len);
9221 copy += source_len;
9222
9223 end_block(beginning);
9224
9225 // If we're within 256K of the end of the buffer,
9226 // start over from the beginning. (Is 256K enough?)
9227 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9228 out = ndrc->translation_cache;
9229
9230 // Trap writes to any of the pages we compiled
9231 mark_invalid_code(start, slen*4, 0);
9232
9233 /* Pass 10 - Free memory by expiring oldest blocks */
9234
9235 pass10_expire_blocks();
9236
9237#ifdef ASSEM_PRINT
9238 fflush(stdout);
9239#endif
9240 stat_inc(stat_bc_direct);
9241 return 0;
9242}
9243
9244// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork