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drc: allow to execute bios even in hle mode
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24#include <errno.h>
25#include <sys/mman.h>
26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef HAVE_LIBNX
33#include <switch.h>
34static Jit g_jit;
35#endif
36
37#include "new_dynarec_config.h"
38#include "../psxhle.h"
39#include "../psxinterpreter.h"
40#include "../gte.h"
41#include "emu_if.h" // emulator interface
42#include "linkage_offsets.h"
43#include "compiler_features.h"
44#include "arm_features.h"
45
46#ifndef ARRAY_SIZE
47#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
48#endif
49#ifndef min
50#define min(a, b) ((b) < (a) ? (b) : (a))
51#endif
52#ifndef max
53#define max(a, b) ((b) > (a) ? (b) : (a))
54#endif
55
56//#define DISASM
57//#define ASSEM_PRINT
58//#define REGMAP_PRINT // with DISASM only
59//#define INV_DEBUG_W
60//#define STAT_PRINT
61
62#ifdef ASSEM_PRINT
63#define assem_debug printf
64#else
65#define assem_debug(...)
66#endif
67//#define inv_debug printf
68#define inv_debug(...)
69
70#ifdef __i386__
71#include "assem_x86.h"
72#endif
73#ifdef __x86_64__
74#include "assem_x64.h"
75#endif
76#ifdef __arm__
77#include "assem_arm.h"
78#endif
79#ifdef __aarch64__
80#include "assem_arm64.h"
81#endif
82
83#define RAM_SIZE 0x200000
84#define MAXBLOCK 2048
85#define MAX_OUTPUT_BLOCK_SIZE 262144
86#define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
87#define PAGE_COUNT 1024
88
89#if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
90#define INVALIDATE_USE_COND_CALL
91#endif
92
93#ifdef VITA
94// apparently Vita has a 16MB limit, so either we cut tc in half,
95// or use this hack (it's a hack because tc size was designed to be power-of-2)
96#define TC_REDUCE_BYTES 4096
97#else
98#define TC_REDUCE_BYTES 0
99#endif
100
101struct ndrc_tramp
102{
103 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
104 const void *f[2048 / sizeof(void *)];
105};
106
107struct ndrc_mem
108{
109 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
110 struct ndrc_tramp tramp;
111};
112
113#ifdef BASE_ADDR_DYNAMIC
114static struct ndrc_mem *ndrc;
115#else
116static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
117static struct ndrc_mem *ndrc = &ndrc_;
118#endif
119#ifdef TC_WRITE_OFFSET
120# ifdef __GLIBC__
121# include <sys/types.h>
122# include <sys/stat.h>
123# include <fcntl.h>
124# include <unistd.h>
125# endif
126static long ndrc_write_ofs;
127#define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
128#else
129#define NDRC_WRITE_OFFSET(x) (x)
130#endif
131
132// stubs
133enum stub_type {
134 CC_STUB = 1,
135 //FP_STUB = 2,
136 LOADB_STUB = 3,
137 LOADH_STUB = 4,
138 LOADW_STUB = 5,
139 //LOADD_STUB = 6,
140 LOADBU_STUB = 7,
141 LOADHU_STUB = 8,
142 STOREB_STUB = 9,
143 STOREH_STUB = 10,
144 STOREW_STUB = 11,
145 //STORED_STUB = 12,
146 STORELR_STUB = 13,
147 INVCODE_STUB = 14,
148 OVERFLOW_STUB = 15,
149 ALIGNMENT_STUB = 16,
150};
151
152// regmap_pre[i] - regs before [i] insn starts; dirty things here that
153// don't match .regmap will be written back
154// [i].regmap_entry - regs that must be set up if someone jumps here
155// [i].regmap - regs [i] insn will read/(over)write
156// branch_regs[i].* - same as above but for branches, takes delay slot into account
157struct regstat
158{
159 signed char regmap_entry[HOST_REGS];
160 signed char regmap[HOST_REGS];
161 u_int wasdirty;
162 u_int dirty;
163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
164 u_int isconst; // ... but isconst is false when r2 is known (hr)
165 u_int loadedconst; // host regs that have constants loaded
166 u_int noevict; // can't evict this hr (alloced by current op)
167 //u_int waswritten; // MIPS regs that were used as store base before
168 uint64_t u;
169};
170
171struct ht_entry
172{
173 u_int vaddr[2];
174 void *tcaddr[2];
175};
176
177struct code_stub
178{
179 enum stub_type type;
180 void *addr;
181 void *retaddr;
182 u_int a;
183 uintptr_t b;
184 uintptr_t c;
185 u_int d;
186 u_int e;
187};
188
189struct link_entry
190{
191 void *addr;
192 u_int target;
193 u_int internal;
194};
195
196struct block_info
197{
198 struct block_info *next;
199 const void *source;
200 const void *copy;
201 u_int start; // vaddr of the block start
202 u_int len; // of the whole block source
203 u_int tc_offs;
204 //u_int tc_len;
205 u_int reg_sv_flags;
206 u_char is_dirty;
207 u_char inv_near_misses;
208 u_short jump_in_cnt;
209 struct {
210 u_int vaddr;
211 void *addr;
212 } jump_in[0];
213};
214
215struct jump_info
216{
217 int alloc;
218 int count;
219 struct {
220 u_int target_vaddr;
221 void *stub;
222 } e[0];
223};
224
225static struct decoded_insn
226{
227 u_char itype;
228 u_char opcode; // bits 31-26
229 u_char opcode2; // (depends on opcode)
230 u_char rs1;
231 u_char rs2;
232 u_char rt1;
233 u_char rt2;
234 u_char use_lt1:1;
235 u_char bt:1;
236 u_char ooo:1;
237 u_char is_ds:1;
238 u_char is_jump:1;
239 u_char is_ujump:1;
240 u_char is_load:1;
241 u_char is_store:1;
242 u_char is_delay_load:1; // is_load + MFC/CFC
243 u_char is_exception:1; // unconditional, also interp. fallback
244 u_char may_except:1; // might generate an exception
245 u_char ls_type:2; // load/store type (ls_width_type)
246} dops[MAXBLOCK];
247
248enum ls_width_type {
249 LS_8 = 0, LS_16, LS_32, LS_LR
250};
251
252static struct compile_info
253{
254 int imm;
255 u_int ba;
256 int ccadj;
257 signed char min_free_regs;
258 signed char addr;
259 signed char reserved[2];
260} cinfo[MAXBLOCK];
261
262 static u_char *out;
263 static char invalid_code[0x100000];
264 static struct ht_entry hash_table[65536];
265 static struct block_info *blocks[PAGE_COUNT];
266 static struct jump_info *jumps[PAGE_COUNT];
267 static u_int start;
268 static u_int *source;
269 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
270 static uint64_t gte_rt[MAXBLOCK];
271 static uint64_t gte_unneeded[MAXBLOCK];
272 static u_int smrv[32]; // speculated MIPS register values
273 static u_int smrv_strong; // mask or regs that are likely to have correct values
274 static u_int smrv_weak; // same, but somewhat less likely
275 static u_int smrv_strong_next; // same, but after current insn executes
276 static u_int smrv_weak_next;
277 static uint64_t unneeded_reg[MAXBLOCK];
278 static uint64_t branch_unneeded_reg[MAXBLOCK];
279 // see 'struct regstat' for a description
280 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
281 // contains 'real' consts at [i] insn, but may differ from what's actually
282 // loaded in host reg as 'final' value is always loaded, see get_final_value()
283 static uint32_t current_constmap[HOST_REGS];
284 static uint32_t constmap[MAXBLOCK][HOST_REGS];
285 static struct regstat regs[MAXBLOCK];
286 static struct regstat branch_regs[MAXBLOCK];
287 static int slen;
288 static void *instr_addr[MAXBLOCK];
289 static struct link_entry link_addr[MAXBLOCK];
290 static int linkcount;
291 static struct code_stub stubs[MAXBLOCK*3];
292 static int stubcount;
293 static u_int literals[1024][2];
294 static int literalcount;
295 static int is_delayslot;
296 static char shadow[1048576] __attribute__((aligned(16)));
297 static void *copy;
298 static u_int expirep;
299 static u_int stop_after_jal;
300 static u_int f1_hack;
301#ifdef STAT_PRINT
302 static int stat_bc_direct;
303 static int stat_bc_pre;
304 static int stat_bc_restore;
305 static int stat_ht_lookups;
306 static int stat_jump_in_lookups;
307 static int stat_restore_tries;
308 static int stat_restore_compares;
309 static int stat_inv_addr_calls;
310 static int stat_inv_hits;
311 static int stat_blocks;
312 static int stat_links;
313 #define stat_inc(s) s++
314 #define stat_dec(s) s--
315 #define stat_clear(s) s = 0
316#else
317 #define stat_inc(s)
318 #define stat_dec(s)
319 #define stat_clear(s)
320#endif
321
322 int new_dynarec_hacks;
323 int new_dynarec_hacks_pergame;
324 int new_dynarec_hacks_old;
325 int new_dynarec_did_compile;
326
327 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
328
329 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0 (CCREG)
330 extern int last_count; // last absolute target, often = next_interupt
331 extern int pcaddr;
332 extern int pending_exception;
333 extern int branch_target;
334 extern uintptr_t ram_offset;
335 extern uintptr_t mini_ht[32][2];
336
337 /* registers that may be allocated */
338 /* 1-31 gpr */
339#define LOREG 32 // lo
340#define HIREG 33 // hi
341//#define FSREG 34 // FPU status (FCSR)
342//#define CSREG 35 // Coprocessor status
343#define CCREG 36 // Cycle count
344#define INVCP 37 // Pointer to invalid_code
345//#define MMREG 38 // Pointer to memory_map
346#define ROREG 39 // ram offset (if psxM != 0x80000000)
347#define TEMPREG 40
348#define FTEMP 40 // Load/store temporary register (was fpu)
349#define PTEMP 41 // Prefetch temporary register
350//#define TLREG 42 // TLB mapping offset
351#define RHASH 43 // Return address hash
352#define RHTBL 44 // Return address hash table address
353#define RTEMP 45 // JR/JALR address register
354#define MAXREG 45
355#define AGEN1 46 // Address generation temporary register (pass5b_preallocate2)
356//#define AGEN2 47 // Address generation temporary register
357
358 /* instruction types */
359#define NOP 0 // No operation
360#define LOAD 1 // Load
361#define STORE 2 // Store
362#define LOADLR 3 // Unaligned load
363#define STORELR 4 // Unaligned store
364#define MOV 5 // Move (hi/lo only)
365#define ALU 6 // Arithmetic/logic
366#define MULTDIV 7 // Multiply/divide
367#define SHIFT 8 // Shift by register
368#define SHIFTIMM 9// Shift by immediate
369#define IMM16 10 // 16-bit immediate
370#define RJUMP 11 // Unconditional jump to register
371#define UJUMP 12 // Unconditional jump
372#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
373#define SJUMP 14 // Conditional branch (regimm format)
374#define COP0 15 // Coprocessor 0
375#define RFE 16
376#define SYSCALL 22// SYSCALL,BREAK
377#define OTHER 23 // Other/unknown - do nothing
378#define HLECALL 26// PCSX fake opcodes for HLE
379#define COP2 27 // Coprocessor 2 move
380#define C2LS 28 // Coprocessor 2 load/store
381#define C2OP 29 // Coprocessor 2 operation
382#define INTCALL 30// Call interpreter to handle rare corner cases
383
384 /* branch codes */
385#define TAKEN 1
386#define NOTTAKEN 2
387
388#define DJT_1 (void *)1l // no function, just a label in assem_debug log
389#define DJT_2 (void *)2l
390
391// asm linkage
392void dyna_linker();
393void cc_interrupt();
394void jump_syscall (u_int u0, u_int u1, u_int pc);
395void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
396void jump_break (u_int u0, u_int u1, u_int pc);
397void jump_break_ds(u_int u0, u_int u1, u_int pc);
398void jump_overflow (u_int u0, u_int u1, u_int pc);
399void jump_overflow_ds(u_int u0, u_int u1, u_int pc);
400void jump_addrerror (u_int cause, u_int addr, u_int pc);
401void jump_addrerror_ds(u_int cause, u_int addr, u_int pc);
402void jump_to_new_pc();
403void call_gteStall();
404void new_dyna_leave();
405
406void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
407void *ndrc_get_addr_ht(u_int vaddr);
408void ndrc_add_jump_out(u_int vaddr, void *src);
409void ndrc_write_invalidate_one(u_int addr);
410static void ndrc_write_invalidate_many(u_int addr, u_int end);
411
412static int new_recompile_block(u_int addr);
413static void invalidate_block(struct block_info *block);
414static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_);
415
416// Needed by assembler
417static void wb_register(signed char r, const signed char regmap[], u_int dirty);
418static void wb_dirtys(const signed char i_regmap[], u_int i_dirty);
419static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr);
420static void load_all_regs(const signed char i_regmap[]);
421static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
422static void load_regs_entry(int t);
423static void load_all_consts(const signed char regmap[], u_int dirty, int i);
424static u_int get_host_reglist(const signed char *regmap);
425
426static int get_final_value(int hr, int i, u_int *value);
427static void add_stub(enum stub_type type, void *addr, void *retaddr,
428 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
429static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
430 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
431static void add_to_linker(void *addr, u_int target, int ext);
432static void *get_direct_memhandler(void *table, u_int addr,
433 enum stub_type type, uintptr_t *addr_host);
434static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
435static void pass_args(int a0, int a1);
436static void emit_far_jump(const void *f);
437static void emit_far_call(const void *f);
438
439#ifdef VITA
440#include <psp2/kernel/sysmem.h>
441static int sceBlock;
442// note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
443extern int getVMBlock();
444int _newlib_vm_size_user = sizeof(*ndrc);
445#endif
446
447static void mprotect_w_x(void *start, void *end, int is_x)
448{
449#ifdef NO_WRITE_EXEC
450 #if defined(VITA)
451 // *Open* enables write on all memory that was
452 // allocated by sceKernelAllocMemBlockForVM()?
453 if (is_x)
454 sceKernelCloseVMDomain();
455 else
456 sceKernelOpenVMDomain();
457 #elif defined(HAVE_LIBNX)
458 Result rc;
459 // check to avoid the full flush in jitTransitionToExecutable()
460 if (g_jit.type != JitType_CodeMemory) {
461 if (is_x)
462 rc = jitTransitionToExecutable(&g_jit);
463 else
464 rc = jitTransitionToWritable(&g_jit);
465 if (R_FAILED(rc))
466 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
467 }
468 #elif defined(TC_WRITE_OFFSET)
469 // separated rx and rw areas are always available
470 #else
471 u_long mstart = (u_long)start & ~4095ul;
472 u_long mend = (u_long)end;
473 if (mprotect((void *)mstart, mend - mstart,
474 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
475 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
476 #endif
477#endif
478}
479
480static void start_tcache_write(void *start, void *end)
481{
482 mprotect_w_x(start, end, 0);
483}
484
485static void end_tcache_write(void *start, void *end)
486{
487#if defined(__arm__) || defined(__aarch64__)
488 size_t len = (char *)end - (char *)start;
489 #if defined(__BLACKBERRY_QNX__)
490 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
491 #elif defined(__MACH__)
492 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
493 #elif defined(VITA)
494 sceKernelSyncVMDomain(sceBlock, start, len);
495 #elif defined(_3DS)
496 ctr_flush_invalidate_cache();
497 #elif defined(HAVE_LIBNX)
498 if (g_jit.type == JitType_CodeMemory) {
499 armDCacheClean(start, len);
500 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
501 // as of v4.2.1 libnx lacks isb
502 __asm__ volatile("isb" ::: "memory");
503 }
504 #elif defined(__aarch64__)
505 // as of 2021, __clear_cache() is still broken on arm64
506 // so here is a custom one :(
507 clear_cache_arm64(start, end);
508 #else
509 __clear_cache(start, end);
510 #endif
511 (void)len;
512#endif
513
514 mprotect_w_x(start, end, 1);
515}
516
517static void *start_block(void)
518{
519 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
520 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
521 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
522 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
523 return out;
524}
525
526static void end_block(void *start)
527{
528 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
529}
530
531#ifdef NDRC_CACHE_FLUSH_ALL
532
533static int needs_clear_cache;
534
535static void mark_clear_cache(void *target)
536{
537 if (!needs_clear_cache) {
538 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
539 needs_clear_cache = 1;
540 }
541}
542
543static void do_clear_cache(void)
544{
545 if (needs_clear_cache) {
546 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
547 needs_clear_cache = 0;
548 }
549}
550
551#else
552
553// also takes care of w^x mappings when patching code
554static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
555
556static void mark_clear_cache(void *target)
557{
558 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
559 u_int mask = 1u << ((offset >> 12) & 31);
560 if (!(needs_clear_cache[offset >> 17] & mask)) {
561 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
562 start_tcache_write(start, start + 4095);
563 needs_clear_cache[offset >> 17] |= mask;
564 }
565}
566
567// Clearing the cache is rather slow on ARM Linux, so mark the areas
568// that need to be cleared, and then only clear these areas once.
569static void do_clear_cache(void)
570{
571 int i, j;
572 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
573 {
574 u_int bitmap = needs_clear_cache[i];
575 if (!bitmap)
576 continue;
577 for (j = 0; j < 32; j++)
578 {
579 u_char *start, *end;
580 if (!(bitmap & (1u << j)))
581 continue;
582
583 start = ndrc->translation_cache + i*131072 + j*4096;
584 end = start + 4095;
585 for (j++; j < 32; j++) {
586 if (!(bitmap & (1u << j)))
587 break;
588 end += 4096;
589 }
590 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
591 }
592 needs_clear_cache[i] = 0;
593 }
594}
595
596#endif // NDRC_CACHE_FLUSH_ALL
597
598#define NO_CYCLE_PENALTY_THR 12
599
600int cycle_multiplier_old;
601static int cycle_multiplier_active;
602
603static int CLOCK_ADJUST(int x)
604{
605 int m = cycle_multiplier_active;
606 int s = (x >> 31) | 1;
607 return (x * m + s * 50) / 100;
608}
609
610static int ds_writes_rjump_rs(int i)
611{
612 return dops[i].rs1 != 0
613 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2
614 || dops[i].rs1 == dops[i].rt1); // overwrites itself - same effect
615}
616
617// psx addr mirror masking (for invalidation)
618static u_int pmmask(u_int vaddr)
619{
620 vaddr &= ~0xe0000000;
621 if (vaddr < 0x01000000)
622 vaddr &= ~0x00e00000; // RAM mirrors
623 return vaddr;
624}
625
626static u_int get_page(u_int vaddr)
627{
628 u_int page = pmmask(vaddr) >> 12;
629 if (page >= PAGE_COUNT / 2)
630 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
631 return page;
632}
633
634// get a page for looking for a block that has vaddr
635// (needed because the block may start in previous page)
636static u_int get_page_prev(u_int vaddr)
637{
638 assert(MAXBLOCK <= (1 << 12));
639 u_int page = get_page(vaddr);
640 if (page & 511)
641 page--;
642 return page;
643}
644
645static struct ht_entry *hash_table_get(u_int vaddr)
646{
647 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
648}
649
650static void hash_table_add(u_int vaddr, void *tcaddr)
651{
652 struct ht_entry *ht_bin = hash_table_get(vaddr);
653 assert(tcaddr);
654 ht_bin->vaddr[1] = ht_bin->vaddr[0];
655 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
656 ht_bin->vaddr[0] = vaddr;
657 ht_bin->tcaddr[0] = tcaddr;
658}
659
660static void hash_table_remove(int vaddr)
661{
662 //printf("remove hash: %x\n",vaddr);
663 struct ht_entry *ht_bin = hash_table_get(vaddr);
664 if (ht_bin->vaddr[1] == vaddr) {
665 ht_bin->vaddr[1] = -1;
666 ht_bin->tcaddr[1] = NULL;
667 }
668 if (ht_bin->vaddr[0] == vaddr) {
669 ht_bin->vaddr[0] = ht_bin->vaddr[1];
670 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
671 ht_bin->vaddr[1] = -1;
672 ht_bin->tcaddr[1] = NULL;
673 }
674}
675
676static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
677{
678 u_int vaddr_m = vaddr & 0x1fffffff;
679 u_int i, j;
680 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
681 // ram mirrors, but should not hurt bios
682 for (j = 0; j < 0x800000; j += 0x200000) {
683 invalid_code[(i|j) >> 12] =
684 invalid_code[(i|j|0x80000000u) >> 12] =
685 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
686 }
687 }
688 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
689 inv_code_start = inv_code_end = ~0;
690}
691
692static int doesnt_expire_soon(u_char *tcaddr)
693{
694 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
695 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
696}
697
698static unused void check_for_block_changes(u_int start, u_int end)
699{
700 u_int start_page = get_page_prev(start);
701 u_int end_page = get_page(end - 1);
702 u_int page;
703
704 for (page = start_page; page <= end_page; page++) {
705 struct block_info *block;
706 for (block = blocks[page]; block != NULL; block = block->next) {
707 if (block->is_dirty)
708 continue;
709 if (memcmp(block->source, block->copy, block->len)) {
710 printf("bad block %08x-%08x %016llx %016llx @%08x\n",
711 block->start, block->start + block->len,
712 *(long long *)block->source, *(long long *)block->copy, psxRegs.pc);
713 fflush(stdout);
714 abort();
715 }
716 }
717 }
718}
719
720static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
721{
722 void *found_clean = NULL;
723 u_int i, page;
724
725 stat_inc(stat_restore_tries);
726 for (page = start_page; page <= end_page; page++) {
727 struct block_info *block;
728 for (block = blocks[page]; block != NULL; block = block->next) {
729 if (vaddr < block->start)
730 break;
731 if (!block->is_dirty || vaddr >= block->start + block->len)
732 continue;
733 for (i = 0; i < block->jump_in_cnt; i++)
734 if (block->jump_in[i].vaddr == vaddr)
735 break;
736 if (i == block->jump_in_cnt)
737 continue;
738 assert(block->source && block->copy);
739 stat_inc(stat_restore_compares);
740 if (memcmp(block->source, block->copy, block->len))
741 continue;
742
743 block->is_dirty = block->inv_near_misses = 0;
744 found_clean = block->jump_in[i].addr;
745 hash_table_add(vaddr, found_clean);
746 mark_invalid_code(block->start, block->len, 0);
747 stat_inc(stat_bc_restore);
748 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
749 return found_clean;
750 }
751 }
752 return NULL;
753}
754
755// this doesn't normally happen
756static noinline u_int generate_exception(u_int pc)
757{
758 //if (execBreakCheck(&psxRegs, pc))
759 // return psxRegs.pc;
760
761 // generate an address or bus error
762 psxRegs.CP0.n.Cause &= 0x300;
763 psxRegs.CP0.n.EPC = pc;
764 if (pc & 3) {
765 psxRegs.CP0.n.Cause |= R3000E_AdEL << 2;
766 psxRegs.CP0.n.BadVAddr = pc;
767#ifdef DRC_DBG
768 last_count -= 2;
769#endif
770 } else
771 psxRegs.CP0.n.Cause |= R3000E_IBE << 2;
772 return (psxRegs.pc = 0x80000080);
773}
774
775// Get address from virtual address
776// This is called from the recompiled JR/JALR instructions
777static void noinline *get_addr(u_int vaddr, int can_compile)
778{
779 u_int start_page = get_page_prev(vaddr);
780 u_int i, page, end_page = get_page(vaddr);
781 void *found_clean = NULL;
782
783 stat_inc(stat_jump_in_lookups);
784 for (page = start_page; page <= end_page; page++) {
785 const struct block_info *block;
786 for (block = blocks[page]; block != NULL; block = block->next) {
787 if (vaddr < block->start)
788 break;
789 if (block->is_dirty || vaddr >= block->start + block->len)
790 continue;
791 for (i = 0; i < block->jump_in_cnt; i++)
792 if (block->jump_in[i].vaddr == vaddr)
793 break;
794 if (i == block->jump_in_cnt)
795 continue;
796 found_clean = block->jump_in[i].addr;
797 hash_table_add(vaddr, found_clean);
798 return found_clean;
799 }
800 }
801 found_clean = try_restore_block(vaddr, start_page, end_page);
802 if (found_clean)
803 return found_clean;
804
805 if (!can_compile)
806 return NULL;
807
808 int r = new_recompile_block(vaddr);
809 if (likely(r == 0))
810 return ndrc_get_addr_ht(vaddr);
811
812 return ndrc_get_addr_ht(generate_exception(vaddr));
813}
814
815// Look up address in hash table first
816void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
817{
818 //check_for_block_changes(vaddr, vaddr + MAXBLOCK);
819 const struct ht_entry *ht_bin = hash_table_get(vaddr);
820 u_int vaddr_a = vaddr & ~3;
821 stat_inc(stat_ht_lookups);
822 if (ht_bin->vaddr[0] == vaddr_a) return ht_bin->tcaddr[0];
823 if (ht_bin->vaddr[1] == vaddr_a) return ht_bin->tcaddr[1];
824 return get_addr(vaddr, can_compile);
825}
826
827void *ndrc_get_addr_ht(u_int vaddr)
828{
829 return ndrc_get_addr_ht_param(vaddr, 1);
830}
831
832static void clear_all_regs(signed char regmap[])
833{
834 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
835}
836
837// get_reg: get allocated host reg from mips reg
838// returns -1 if no such mips reg was allocated
839#if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
840
841extern signed char get_reg(const signed char regmap[], signed char r);
842
843#else
844
845static signed char get_reg(const signed char regmap[], signed char r)
846{
847 int hr;
848 for (hr = 0; hr < HOST_REGS; hr++) {
849 if (hr == EXCLUDE_REG)
850 continue;
851 if (regmap[hr] == r)
852 return hr;
853 }
854 return -1;
855}
856
857#endif
858
859// get reg suitable for writing
860static signed char get_reg_w(const signed char regmap[], signed char r)
861{
862 return r == 0 ? -1 : get_reg(regmap, r);
863}
864
865// get reg as mask bit (1 << hr)
866static u_int get_regm(const signed char regmap[], signed char r)
867{
868 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
869}
870
871static signed char get_reg_temp(const signed char regmap[])
872{
873 int hr;
874 for (hr = 0; hr < HOST_REGS; hr++) {
875 if (hr == EXCLUDE_REG)
876 continue;
877 if (regmap[hr] == (signed char)-1)
878 return hr;
879 }
880 return -1;
881}
882
883// Find a register that is available for two consecutive cycles
884static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
885{
886 int hr;
887 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
888 return -1;
889}
890
891// reverse reg map: mips -> host
892#define RRMAP_SIZE 64
893static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
894 u_int *regs_can_change)
895{
896 u_int r, hr, hr_can_change = 0;
897 memset(rrmap, -1, RRMAP_SIZE);
898 for (hr = 0; hr < HOST_REGS; )
899 {
900 r = regmap[hr];
901 rrmap[r & (RRMAP_SIZE - 1)] = hr;
902 // only add mips $1-$31+$lo, others shifted out
903 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
904 hr++;
905 if (hr == EXCLUDE_REG)
906 hr++;
907 }
908 hr_can_change |= 1u << (rrmap[33] & 31);
909 hr_can_change |= 1u << (rrmap[CCREG] & 31);
910 hr_can_change &= ~(1u << 31);
911 *regs_can_change = hr_can_change;
912}
913
914// same as get_reg, but takes rrmap
915static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
916{
917 assert(0 <= r && r < RRMAP_SIZE);
918 return rrmap[r];
919}
920
921static int count_free_regs(const signed char regmap[])
922{
923 int count=0;
924 int hr;
925 for(hr=0;hr<HOST_REGS;hr++)
926 {
927 if(hr!=EXCLUDE_REG) {
928 if(regmap[hr]<0) count++;
929 }
930 }
931 return count;
932}
933
934static void dirty_reg(struct regstat *cur, signed char reg)
935{
936 int hr;
937 if (!reg) return;
938 hr = get_reg(cur->regmap, reg);
939 if (hr >= 0)
940 cur->dirty |= 1<<hr;
941}
942
943static void set_const(struct regstat *cur, signed char reg, uint32_t value)
944{
945 int hr;
946 if (!reg) return;
947 hr = get_reg(cur->regmap, reg);
948 if (hr >= 0) {
949 cur->isconst |= 1<<hr;
950 current_constmap[hr] = value;
951 }
952}
953
954static void clear_const(struct regstat *cur, signed char reg)
955{
956 int hr;
957 if (!reg) return;
958 hr = get_reg(cur->regmap, reg);
959 if (hr >= 0)
960 cur->isconst &= ~(1<<hr);
961}
962
963static int is_const(const struct regstat *cur, signed char reg)
964{
965 int hr;
966 if (reg < 0) return 0;
967 if (!reg) return 1;
968 hr = get_reg(cur->regmap, reg);
969 if (hr >= 0)
970 return (cur->isconst>>hr)&1;
971 return 0;
972}
973
974static uint32_t get_const(const struct regstat *cur, signed char reg)
975{
976 int hr;
977 if (!reg) return 0;
978 hr = get_reg(cur->regmap, reg);
979 if (hr >= 0)
980 return current_constmap[hr];
981
982 SysPrintf("Unknown constant in r%d\n", reg);
983 abort();
984}
985
986// Least soon needed registers
987// Look at the next ten instructions and see which registers
988// will be used. Try not to reallocate these.
989static void lsn(u_char hsn[], int i)
990{
991 int j;
992 int b=-1;
993 for(j=0;j<9;j++)
994 {
995 if(i+j>=slen) {
996 j=slen-i-1;
997 break;
998 }
999 if (dops[i+j].is_ujump)
1000 {
1001 // Don't go past an unconditonal jump
1002 j++;
1003 break;
1004 }
1005 }
1006 for(;j>=0;j--)
1007 {
1008 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
1009 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
1010 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
1011 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
1012 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
1013 // Stores can allocate zero
1014 hsn[dops[i+j].rs1]=j;
1015 hsn[dops[i+j].rs2]=j;
1016 }
1017 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
1018 hsn[ROREG] = j;
1019 // On some architectures stores need invc_ptr
1020 #if defined(HOST_IMM8)
1021 if (dops[i+j].is_store)
1022 hsn[INVCP] = j;
1023 #endif
1024 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1025 {
1026 hsn[CCREG]=j;
1027 b=j;
1028 }
1029 }
1030 if(b>=0)
1031 {
1032 if(cinfo[i+b].ba>=start && cinfo[i+b].ba<(start+slen*4))
1033 {
1034 // Follow first branch
1035 int t=(cinfo[i+b].ba-start)>>2;
1036 j=7-b;if(t+j>=slen) j=slen-t-1;
1037 for(;j>=0;j--)
1038 {
1039 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
1040 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
1041 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
1042 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
1043 }
1044 }
1045 // TODO: preferred register based on backward branch
1046 }
1047 // Delay slot should preferably not overwrite branch conditions or cycle count
1048 if (i > 0 && dops[i-1].is_jump) {
1049 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
1050 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1051 hsn[CCREG]=1;
1052 // ...or hash tables
1053 hsn[RHASH]=1;
1054 hsn[RHTBL]=1;
1055 }
1056 // Coprocessor load/store needs FTEMP, even if not declared
1057 if(dops[i].itype==C2LS) {
1058 hsn[FTEMP]=0;
1059 }
1060 // Load/store L/R also uses FTEMP as a temporary register
1061 if (dops[i].itype == LOADLR || dops[i].itype == STORELR) {
1062 hsn[FTEMP]=0;
1063 }
1064 // Don't remove the miniht registers
1065 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1066 {
1067 hsn[RHASH]=0;
1068 hsn[RHTBL]=0;
1069 }
1070}
1071
1072// We only want to allocate registers if we're going to use them again soon
1073static int needed_again(int r, int i)
1074{
1075 int j;
1076 int b=-1;
1077 int rn=10;
1078
1079 if (i > 0 && dops[i-1].is_ujump)
1080 {
1081 if(cinfo[i-1].ba<start || cinfo[i-1].ba>start+slen*4-4)
1082 return 0; // Don't need any registers if exiting the block
1083 }
1084 for(j=0;j<9;j++)
1085 {
1086 if(i+j>=slen) {
1087 j=slen-i-1;
1088 break;
1089 }
1090 if (dops[i+j].is_ujump)
1091 {
1092 // Don't go past an unconditonal jump
1093 j++;
1094 break;
1095 }
1096 if (dops[i+j].is_exception)
1097 {
1098 break;
1099 }
1100 }
1101 for(;j>=1;j--)
1102 {
1103 if(dops[i+j].rs1==r) rn=j;
1104 if(dops[i+j].rs2==r) rn=j;
1105 if((unneeded_reg[i+j]>>r)&1) rn=10;
1106 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1107 {
1108 b=j;
1109 }
1110 }
1111 if(rn<10) return 1;
1112 (void)b;
1113 return 0;
1114}
1115
1116// Try to match register allocations at the end of a loop with those
1117// at the beginning
1118static int loop_reg(int i, int r, int hr)
1119{
1120 int j,k;
1121 for(j=0;j<9;j++)
1122 {
1123 if(i+j>=slen) {
1124 j=slen-i-1;
1125 break;
1126 }
1127 if (dops[i+j].is_ujump)
1128 {
1129 // Don't go past an unconditonal jump
1130 j++;
1131 break;
1132 }
1133 }
1134 k=0;
1135 if(i>0){
1136 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1137 k--;
1138 }
1139 for(;k<j;k++)
1140 {
1141 assert(r < 64);
1142 if((unneeded_reg[i+k]>>r)&1) return hr;
1143 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1144 {
1145 if(cinfo[i+k].ba>=start && cinfo[i+k].ba<(start+i*4))
1146 {
1147 int t=(cinfo[i+k].ba-start)>>2;
1148 int reg=get_reg(regs[t].regmap_entry,r);
1149 if(reg>=0) return reg;
1150 //reg=get_reg(regs[t+1].regmap_entry,r);
1151 //if(reg>=0) return reg;
1152 }
1153 }
1154 }
1155 return hr;
1156}
1157
1158
1159// Allocate every register, preserving source/target regs
1160static void alloc_all(struct regstat *cur,int i)
1161{
1162 int hr;
1163
1164 for(hr=0;hr<HOST_REGS;hr++) {
1165 if(hr!=EXCLUDE_REG) {
1166 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1167 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1168 {
1169 cur->regmap[hr]=-1;
1170 cur->dirty&=~(1<<hr);
1171 }
1172 // Don't need zeros
1173 if(cur->regmap[hr]==0)
1174 {
1175 cur->regmap[hr]=-1;
1176 cur->dirty&=~(1<<hr);
1177 }
1178 }
1179 }
1180}
1181
1182#ifndef NDEBUG
1183static int host_tempreg_in_use;
1184
1185static void host_tempreg_acquire(void)
1186{
1187 assert(!host_tempreg_in_use);
1188 host_tempreg_in_use = 1;
1189}
1190
1191static void host_tempreg_release(void)
1192{
1193 host_tempreg_in_use = 0;
1194}
1195#else
1196static void host_tempreg_acquire(void) {}
1197static void host_tempreg_release(void) {}
1198#endif
1199
1200#ifdef ASSEM_PRINT
1201extern void gen_interupt();
1202extern void do_insn_cmp();
1203#define FUNCNAME(f) { f, " " #f }
1204static const struct {
1205 void *addr;
1206 const char *name;
1207} function_names[] = {
1208 FUNCNAME(cc_interrupt),
1209 FUNCNAME(gen_interupt),
1210 FUNCNAME(ndrc_get_addr_ht),
1211 FUNCNAME(jump_handler_read8),
1212 FUNCNAME(jump_handler_read16),
1213 FUNCNAME(jump_handler_read32),
1214 FUNCNAME(jump_handler_write8),
1215 FUNCNAME(jump_handler_write16),
1216 FUNCNAME(jump_handler_write32),
1217 FUNCNAME(ndrc_write_invalidate_one),
1218 FUNCNAME(ndrc_write_invalidate_many),
1219 FUNCNAME(jump_to_new_pc),
1220 FUNCNAME(jump_break),
1221 FUNCNAME(jump_break_ds),
1222 FUNCNAME(jump_syscall),
1223 FUNCNAME(jump_syscall_ds),
1224 FUNCNAME(jump_overflow),
1225 FUNCNAME(jump_overflow_ds),
1226 FUNCNAME(jump_addrerror),
1227 FUNCNAME(jump_addrerror_ds),
1228 FUNCNAME(call_gteStall),
1229 FUNCNAME(new_dyna_leave),
1230 FUNCNAME(pcsx_mtc0),
1231 FUNCNAME(pcsx_mtc0_ds),
1232 FUNCNAME(execI),
1233#ifdef __aarch64__
1234 FUNCNAME(do_memhandler_pre),
1235 FUNCNAME(do_memhandler_post),
1236#endif
1237#ifdef DRC_DBG
1238# ifdef __aarch64__
1239 FUNCNAME(do_insn_cmp_arm64),
1240# else
1241 FUNCNAME(do_insn_cmp),
1242# endif
1243#endif
1244};
1245
1246static const char *func_name(const void *a)
1247{
1248 int i;
1249 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1250 if (function_names[i].addr == a)
1251 return function_names[i].name;
1252 return "";
1253}
1254
1255static const char *fpofs_name(u_int ofs)
1256{
1257 u_int *p = (u_int *)&dynarec_local + ofs/sizeof(u_int);
1258 static char buf[64];
1259 switch (ofs) {
1260 #define ofscase(x) case LO_##x: return " ; " #x
1261 ofscase(next_interupt);
1262 ofscase(cycle_count);
1263 ofscase(last_count);
1264 ofscase(pending_exception);
1265 ofscase(stop);
1266 ofscase(address);
1267 ofscase(lo);
1268 ofscase(hi);
1269 ofscase(PC);
1270 ofscase(cycle);
1271 ofscase(mem_rtab);
1272 ofscase(mem_wtab);
1273 ofscase(psxH_ptr);
1274 ofscase(invc_ptr);
1275 ofscase(ram_offset);
1276 #undef ofscase
1277 }
1278 buf[0] = 0;
1279 if (psxRegs.GPR.r <= p && p < &psxRegs.GPR.r[32])
1280 snprintf(buf, sizeof(buf), " ; r%d", (int)(p - psxRegs.GPR.r));
1281 else if (psxRegs.CP0.r <= p && p < &psxRegs.CP0.r[32])
1282 snprintf(buf, sizeof(buf), " ; cp0 $%d", (int)(p - psxRegs.CP0.r));
1283 else if (psxRegs.CP2D.r <= p && p < &psxRegs.CP2D.r[32])
1284 snprintf(buf, sizeof(buf), " ; cp2d $%d", (int)(p - psxRegs.CP2D.r));
1285 else if (psxRegs.CP2C.r <= p && p < &psxRegs.CP2C.r[32])
1286 snprintf(buf, sizeof(buf), " ; cp2c $%d", (int)(p - psxRegs.CP2C.r));
1287 return buf;
1288}
1289#else
1290#define func_name(x) ""
1291#define fpofs_name(x) ""
1292#endif
1293
1294#ifdef __i386__
1295#include "assem_x86.c"
1296#endif
1297#ifdef __x86_64__
1298#include "assem_x64.c"
1299#endif
1300#ifdef __arm__
1301#include "assem_arm.c"
1302#endif
1303#ifdef __aarch64__
1304#include "assem_arm64.c"
1305#endif
1306
1307static void *get_trampoline(const void *f)
1308{
1309 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1310 size_t i;
1311
1312 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1313 if (tramp->f[i] == f || tramp->f[i] == NULL)
1314 break;
1315 }
1316 if (i == ARRAY_SIZE(tramp->f)) {
1317 SysPrintf("trampoline table is full, last func %p\n", f);
1318 abort();
1319 }
1320 if (tramp->f[i] == NULL) {
1321 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1322 tramp->f[i] = f;
1323 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1324#ifdef HAVE_LIBNX
1325 // invalidate the RX mirror (unsure if necessary, but just in case...)
1326 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1327#endif
1328 }
1329 return &ndrc->tramp.ops[i];
1330}
1331
1332static void emit_far_jump(const void *f)
1333{
1334 if (can_jump_or_call(f)) {
1335 emit_jmp(f);
1336 return;
1337 }
1338
1339 f = get_trampoline(f);
1340 emit_jmp(f);
1341}
1342
1343static void emit_far_call(const void *f)
1344{
1345 if (can_jump_or_call(f)) {
1346 emit_call(f);
1347 return;
1348 }
1349
1350 f = get_trampoline(f);
1351 emit_call(f);
1352}
1353
1354// Check if an address is already compiled
1355// but don't return addresses which are about to expire from the cache
1356static void *check_addr(u_int vaddr)
1357{
1358 struct ht_entry *ht_bin = hash_table_get(vaddr);
1359 size_t i;
1360 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1361 if (ht_bin->vaddr[i] == vaddr)
1362 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1363 return ht_bin->tcaddr[i];
1364 }
1365
1366 // refactor to get_addr_nocompile?
1367 u_int start_page = get_page_prev(vaddr);
1368 u_int page, end_page = get_page(vaddr);
1369
1370 stat_inc(stat_jump_in_lookups);
1371 for (page = start_page; page <= end_page; page++) {
1372 const struct block_info *block;
1373 for (block = blocks[page]; block != NULL; block = block->next) {
1374 if (vaddr < block->start)
1375 break;
1376 if (block->is_dirty || vaddr >= block->start + block->len)
1377 continue;
1378 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1379 continue;
1380 for (i = 0; i < block->jump_in_cnt; i++)
1381 if (block->jump_in[i].vaddr == vaddr)
1382 break;
1383 if (i == block->jump_in_cnt)
1384 continue;
1385
1386 // Update existing entry with current address
1387 void *addr = block->jump_in[i].addr;
1388 if (ht_bin->vaddr[0] == vaddr) {
1389 ht_bin->tcaddr[0] = addr;
1390 return addr;
1391 }
1392 if (ht_bin->vaddr[1] == vaddr) {
1393 ht_bin->tcaddr[1] = addr;
1394 return addr;
1395 }
1396 // Insert into hash table with low priority.
1397 // Don't evict existing entries, as they are probably
1398 // addresses that are being accessed frequently.
1399 if (ht_bin->vaddr[0] == -1) {
1400 ht_bin->vaddr[0] = vaddr;
1401 ht_bin->tcaddr[0] = addr;
1402 }
1403 else if (ht_bin->vaddr[1] == -1) {
1404 ht_bin->vaddr[1] = vaddr;
1405 ht_bin->tcaddr[1] = addr;
1406 }
1407 return addr;
1408 }
1409 }
1410 return NULL;
1411}
1412
1413static void blocks_clear(struct block_info **head)
1414{
1415 struct block_info *cur, *next;
1416
1417 if ((cur = *head)) {
1418 *head = NULL;
1419 while (cur) {
1420 next = cur->next;
1421 free(cur);
1422 cur = next;
1423 }
1424 }
1425}
1426
1427static int blocks_remove_matching_addrs(struct block_info **head,
1428 u_int base_offs, int shift)
1429{
1430 struct block_info *next;
1431 int hit = 0;
1432 while (*head) {
1433 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1434 inv_debug("EXP: rm block %08x (tc_offs %x)\n", (*head)->start, (*head)->tc_offs);
1435 invalidate_block(*head);
1436 next = (*head)->next;
1437 free(*head);
1438 *head = next;
1439 stat_dec(stat_blocks);
1440 hit = 1;
1441 }
1442 else
1443 {
1444 head = &((*head)->next);
1445 }
1446 }
1447 return hit;
1448}
1449
1450// This is called when we write to a compiled block (see do_invstub)
1451static void unlink_jumps_vaddr_range(u_int start, u_int end)
1452{
1453 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1454 int i;
1455
1456 for (page = start_page; page <= end_page; page++) {
1457 struct jump_info *ji = jumps[page];
1458 if (ji == NULL)
1459 continue;
1460 for (i = 0; i < ji->count; ) {
1461 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1462 i++;
1463 continue;
1464 }
1465
1466 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1467 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1468 void *host_addr = find_extjump_insn(ji->e[i].stub);
1469 mark_clear_cache(host_addr);
1470 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1471
1472 stat_dec(stat_links);
1473 ji->count--;
1474 if (i < ji->count) {
1475 ji->e[i] = ji->e[ji->count];
1476 continue;
1477 }
1478 i++;
1479 }
1480 }
1481}
1482
1483static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1484{
1485 int i;
1486 if (ji == NULL)
1487 return;
1488 for (i = 0; i < ji->count; ) {
1489 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1490 if (((tc_offs ^ base_offs) >> shift) != 0) {
1491 i++;
1492 continue;
1493 }
1494
1495 inv_debug("EXP: rm link to %08x (tc_offs %x)\n", ji->e[i].target_vaddr, tc_offs);
1496 stat_dec(stat_links);
1497 ji->count--;
1498 if (i < ji->count) {
1499 ji->e[i] = ji->e[ji->count];
1500 continue;
1501 }
1502 i++;
1503 }
1504}
1505
1506static void invalidate_block(struct block_info *block)
1507{
1508 u_int i;
1509
1510 block->is_dirty = 1;
1511 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1512 for (i = 0; i < block->jump_in_cnt; i++)
1513 hash_table_remove(block->jump_in[i].vaddr);
1514}
1515
1516static int invalidate_range(u_int start, u_int end,
1517 u32 *inv_start_ret, u32 *inv_end_ret)
1518{
1519 struct block_info *last_block = NULL;
1520 u_int start_page = get_page_prev(start);
1521 u_int end_page = get_page(end - 1);
1522 u_int start_m = pmmask(start);
1523 u_int end_m = pmmask(end - 1);
1524 u_int inv_start, inv_end;
1525 u_int blk_start_m, blk_end_m;
1526 u_int page;
1527 int hit = 0;
1528
1529 // additional area without code (to supplement invalid_code[]), [start, end)
1530 // avoids excessive ndrc_write_invalidate*() calls
1531 inv_start = start_m & ~0xfff;
1532 inv_end = end_m | 0xfff;
1533
1534 for (page = start_page; page <= end_page; page++) {
1535 struct block_info *block;
1536 for (block = blocks[page]; block != NULL; block = block->next) {
1537 if (block->is_dirty)
1538 continue;
1539 last_block = block;
1540 blk_end_m = pmmask(block->start + block->len);
1541 if (blk_end_m <= start_m) {
1542 inv_start = max(inv_start, blk_end_m);
1543 continue;
1544 }
1545 blk_start_m = pmmask(block->start);
1546 if (end_m <= blk_start_m) {
1547 inv_end = min(inv_end, blk_start_m - 1);
1548 continue;
1549 }
1550 if (!block->source) // "hack" block - leave it alone
1551 continue;
1552
1553 hit++;
1554 invalidate_block(block);
1555 stat_inc(stat_inv_hits);
1556 }
1557 }
1558
1559 if (!hit && last_block && last_block->source) {
1560 // could be some leftover unused block, uselessly trapping writes
1561 last_block->inv_near_misses++;
1562 if (last_block->inv_near_misses > 128) {
1563 invalidate_block(last_block);
1564 stat_inc(stat_inv_hits);
1565 hit++;
1566 }
1567 }
1568 if (hit) {
1569 do_clear_cache();
1570#ifdef USE_MINI_HT
1571 memset(mini_ht, -1, sizeof(mini_ht));
1572#endif
1573 }
1574
1575 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1576 // the whole page is empty now
1577 mark_invalid_code(start, 1, 1);
1578
1579 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1580 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1581 return hit;
1582}
1583
1584void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1585{
1586 invalidate_range(start, end, NULL, NULL);
1587}
1588
1589static void ndrc_write_invalidate_many(u_int start, u_int end)
1590{
1591 // this check is done by the caller
1592 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1593 int ret = invalidate_range(start, end, &inv_code_start, &inv_code_end);
1594#ifdef INV_DEBUG_W
1595 int invc = invalid_code[start >> 12];
1596 u_int len = end - start;
1597 if (ret)
1598 printf("INV ADDR: %08x/%02x hit %d blocks\n", start, len, ret);
1599 else
1600 printf("INV ADDR: %08x/%02x miss, inv %08x-%08x invc %d->%d\n", start, len,
1601 inv_code_start, inv_code_end, invc, invalid_code[start >> 12]);
1602 check_for_block_changes(start, end);
1603#endif
1604 stat_inc(stat_inv_addr_calls);
1605 (void)ret;
1606}
1607
1608void ndrc_write_invalidate_one(u_int addr)
1609{
1610 ndrc_write_invalidate_many(addr, addr + 4);
1611}
1612
1613// This is called when loading a save state.
1614// Anything could have changed, so invalidate everything.
1615void new_dynarec_invalidate_all_pages(void)
1616{
1617 struct block_info *block;
1618 u_int page;
1619 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1620 for (block = blocks[page]; block != NULL; block = block->next) {
1621 if (block->is_dirty)
1622 continue;
1623 if (!block->source) // hack block?
1624 continue;
1625 invalidate_block(block);
1626 }
1627 }
1628
1629 #ifdef USE_MINI_HT
1630 memset(mini_ht, -1, sizeof(mini_ht));
1631 #endif
1632 do_clear_cache();
1633}
1634
1635// Add an entry to jump_out after making a link
1636// src should point to code by emit_extjump()
1637void ndrc_add_jump_out(u_int vaddr, void *src)
1638{
1639 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1640 u_int page = get_page(vaddr);
1641 struct jump_info *ji;
1642
1643 stat_inc(stat_links);
1644 check_extjump2(src);
1645 ji = jumps[page];
1646 if (ji == NULL) {
1647 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1648 ji->alloc = 16;
1649 ji->count = 0;
1650 }
1651 else if (ji->count >= ji->alloc) {
1652 ji->alloc += 16;
1653 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1654 }
1655 jumps[page] = ji;
1656 ji->e[ji->count].target_vaddr = vaddr;
1657 ji->e[ji->count].stub = src;
1658 ji->count++;
1659}
1660
1661/* Register allocation */
1662
1663static void alloc_set(struct regstat *cur, int reg, int hr)
1664{
1665 cur->regmap[hr] = reg;
1666 cur->dirty &= ~(1u << hr);
1667 cur->isconst &= ~(1u << hr);
1668 cur->noevict |= 1u << hr;
1669}
1670
1671static void evict_alloc_reg(struct regstat *cur, int i, int reg, int preferred_hr)
1672{
1673 u_char hsn[MAXREG+1];
1674 int j, r, hr;
1675 memset(hsn, 10, sizeof(hsn));
1676 lsn(hsn, i);
1677 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1678 if(i>0) {
1679 // Don't evict the cycle count at entry points, otherwise the entry
1680 // stub will have to write it.
1681 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1682 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1683 for(j=10;j>=3;j--)
1684 {
1685 // Alloc preferred register if available
1686 if (!((cur->noevict >> preferred_hr) & 1)
1687 && hsn[cur->regmap[preferred_hr]] == j)
1688 {
1689 alloc_set(cur, reg, preferred_hr);
1690 return;
1691 }
1692 for(r=1;r<=MAXREG;r++)
1693 {
1694 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1695 for(hr=0;hr<HOST_REGS;hr++) {
1696 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1697 continue;
1698 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1699 if(cur->regmap[hr]==r) {
1700 alloc_set(cur, reg, hr);
1701 return;
1702 }
1703 }
1704 }
1705 }
1706 }
1707 }
1708 }
1709 for(j=10;j>=0;j--)
1710 {
1711 for(r=1;r<=MAXREG;r++)
1712 {
1713 if(hsn[r]==j) {
1714 for(hr=0;hr<HOST_REGS;hr++) {
1715 if (hr == EXCLUDE_REG || ((cur->noevict >> hr) & 1))
1716 continue;
1717 if(cur->regmap[hr]==r) {
1718 alloc_set(cur, reg, hr);
1719 return;
1720 }
1721 }
1722 }
1723 }
1724 }
1725 SysPrintf("This shouldn't happen (evict_alloc_reg)\n");
1726 abort();
1727}
1728
1729// Note: registers are allocated clean (unmodified state)
1730// if you intend to modify the register, you must call dirty_reg().
1731static void alloc_reg(struct regstat *cur,int i,signed char reg)
1732{
1733 int r,hr;
1734 int preferred_reg = PREFERRED_REG_FIRST
1735 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1736 if (reg == CCREG) preferred_reg = HOST_CCREG;
1737 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1738 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1739 assert(reg >= 0);
1740
1741 // Don't allocate unused registers
1742 if((cur->u>>reg)&1) return;
1743
1744 // see if it's already allocated
1745 if ((hr = get_reg(cur->regmap, reg)) >= 0) {
1746 cur->noevict |= 1u << hr;
1747 return;
1748 }
1749
1750 // Keep the same mapping if the register was already allocated in a loop
1751 preferred_reg = loop_reg(i,reg,preferred_reg);
1752
1753 // Try to allocate the preferred register
1754 if (cur->regmap[preferred_reg] == -1) {
1755 alloc_set(cur, reg, preferred_reg);
1756 return;
1757 }
1758 r=cur->regmap[preferred_reg];
1759 assert(r < 64);
1760 if((cur->u>>r)&1) {
1761 alloc_set(cur, reg, preferred_reg);
1762 return;
1763 }
1764
1765 // Clear any unneeded registers
1766 // We try to keep the mapping consistent, if possible, because it
1767 // makes branches easier (especially loops). So we try to allocate
1768 // first (see above) before removing old mappings. If this is not
1769 // possible then go ahead and clear out the registers that are no
1770 // longer needed.
1771 for(hr=0;hr<HOST_REGS;hr++)
1772 {
1773 r=cur->regmap[hr];
1774 if(r>=0) {
1775 assert(r < 64);
1776 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1777 }
1778 }
1779
1780 // Try to allocate any available register, but prefer
1781 // registers that have not been used recently.
1782 if (i > 0) {
1783 for (hr = PREFERRED_REG_FIRST; ; ) {
1784 if (cur->regmap[hr] < 0) {
1785 int oldreg = regs[i-1].regmap[hr];
1786 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1787 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1788 {
1789 alloc_set(cur, reg, hr);
1790 return;
1791 }
1792 }
1793 hr++;
1794 if (hr == EXCLUDE_REG)
1795 hr++;
1796 if (hr == HOST_REGS)
1797 hr = 0;
1798 if (hr == PREFERRED_REG_FIRST)
1799 break;
1800 }
1801 }
1802
1803 // Try to allocate any available register
1804 for (hr = PREFERRED_REG_FIRST; ; ) {
1805 if (cur->regmap[hr] < 0) {
1806 alloc_set(cur, reg, hr);
1807 return;
1808 }
1809 hr++;
1810 if (hr == EXCLUDE_REG)
1811 hr++;
1812 if (hr == HOST_REGS)
1813 hr = 0;
1814 if (hr == PREFERRED_REG_FIRST)
1815 break;
1816 }
1817
1818 // Ok, now we have to evict someone
1819 // Pick a register we hopefully won't need soon
1820 evict_alloc_reg(cur, i, reg, preferred_reg);
1821}
1822
1823// Allocate a temporary register. This is done without regard to
1824// dirty status or whether the register we request is on the unneeded list
1825// Note: This will only allocate one register, even if called multiple times
1826static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1827{
1828 int r,hr;
1829
1830 // see if it's already allocated
1831 for (hr = 0; hr < HOST_REGS; hr++)
1832 {
1833 if (hr != EXCLUDE_REG && cur->regmap[hr] == reg) {
1834 cur->noevict |= 1u << hr;
1835 return;
1836 }
1837 }
1838
1839 // Try to allocate any available register
1840 for(hr=HOST_REGS-1;hr>=0;hr--) {
1841 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1842 alloc_set(cur, reg, hr);
1843 return;
1844 }
1845 }
1846
1847 // Find an unneeded register
1848 for(hr=HOST_REGS-1;hr>=0;hr--)
1849 {
1850 r=cur->regmap[hr];
1851 if(r>=0) {
1852 assert(r < 64);
1853 if((cur->u>>r)&1) {
1854 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1855 alloc_set(cur, reg, hr);
1856 return;
1857 }
1858 }
1859 }
1860 }
1861
1862 // Ok, now we have to evict someone
1863 // Pick a register we hopefully won't need soon
1864 evict_alloc_reg(cur, i, reg, 0);
1865}
1866
1867static void mov_alloc(struct regstat *current,int i)
1868{
1869 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1870 alloc_cc(current,i); // for stalls
1871 dirty_reg(current,CCREG);
1872 }
1873
1874 // Note: Don't need to actually alloc the source registers
1875 //alloc_reg(current,i,dops[i].rs1);
1876 alloc_reg(current,i,dops[i].rt1);
1877
1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rt1);
1880 dirty_reg(current,dops[i].rt1);
1881}
1882
1883static void shiftimm_alloc(struct regstat *current,int i)
1884{
1885 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1886 {
1887 if(dops[i].rt1) {
1888 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1889 else dops[i].use_lt1=!!dops[i].rs1;
1890 alloc_reg(current,i,dops[i].rt1);
1891 dirty_reg(current,dops[i].rt1);
1892 if(is_const(current,dops[i].rs1)) {
1893 int v=get_const(current,dops[i].rs1);
1894 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<cinfo[i].imm);
1895 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>cinfo[i].imm);
1896 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>cinfo[i].imm);
1897 }
1898 else clear_const(current,dops[i].rt1);
1899 }
1900 }
1901 else
1902 {
1903 clear_const(current,dops[i].rs1);
1904 clear_const(current,dops[i].rt1);
1905 }
1906
1907 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1908 {
1909 assert(0);
1910 }
1911 if(dops[i].opcode2==0x3c) // DSLL32
1912 {
1913 assert(0);
1914 }
1915 if(dops[i].opcode2==0x3e) // DSRL32
1916 {
1917 assert(0);
1918 }
1919 if(dops[i].opcode2==0x3f) // DSRA32
1920 {
1921 assert(0);
1922 }
1923}
1924
1925static void shift_alloc(struct regstat *current,int i)
1926{
1927 if(dops[i].rt1) {
1928 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1929 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1930 alloc_reg(current,i,dops[i].rt1);
1931 if(dops[i].rt1==dops[i].rs2) {
1932 alloc_reg_temp(current,i,-1);
1933 cinfo[i].min_free_regs=1;
1934 }
1935 clear_const(current,dops[i].rs1);
1936 clear_const(current,dops[i].rs2);
1937 clear_const(current,dops[i].rt1);
1938 dirty_reg(current,dops[i].rt1);
1939 }
1940}
1941
1942static void alu_alloc(struct regstat *current,int i)
1943{
1944 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1945 if(dops[i].rt1) {
1946 if(dops[i].rs1&&dops[i].rs2) {
1947 alloc_reg(current,i,dops[i].rs1);
1948 alloc_reg(current,i,dops[i].rs2);
1949 }
1950 else {
1951 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1952 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1953 }
1954 alloc_reg(current,i,dops[i].rt1);
1955 }
1956 if (dops[i].may_except) {
1957 alloc_cc_optional(current, i); // for exceptions
1958 alloc_reg_temp(current, i, -1);
1959 cinfo[i].min_free_regs = 1;
1960 }
1961 }
1962 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1963 if(dops[i].rt1) {
1964 alloc_reg(current,i,dops[i].rs1);
1965 alloc_reg(current,i,dops[i].rs2);
1966 alloc_reg(current,i,dops[i].rt1);
1967 }
1968 }
1969 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1970 if(dops[i].rt1) {
1971 if(dops[i].rs1&&dops[i].rs2) {
1972 alloc_reg(current,i,dops[i].rs1);
1973 alloc_reg(current,i,dops[i].rs2);
1974 }
1975 else
1976 {
1977 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1978 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1979 }
1980 alloc_reg(current,i,dops[i].rt1);
1981 }
1982 }
1983 clear_const(current,dops[i].rs1);
1984 clear_const(current,dops[i].rs2);
1985 clear_const(current,dops[i].rt1);
1986 dirty_reg(current,dops[i].rt1);
1987}
1988
1989static void imm16_alloc(struct regstat *current,int i)
1990{
1991 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1992 else dops[i].use_lt1=!!dops[i].rs1;
1993 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1994 if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1995 clear_const(current,dops[i].rs1);
1996 clear_const(current,dops[i].rt1);
1997 }
1998 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1999 if(is_const(current,dops[i].rs1)) {
2000 int v=get_const(current,dops[i].rs1);
2001 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&cinfo[i].imm);
2002 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|cinfo[i].imm);
2003 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^cinfo[i].imm);
2004 }
2005 else clear_const(current,dops[i].rt1);
2006 }
2007 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2008 if(is_const(current,dops[i].rs1)) {
2009 int v=get_const(current,dops[i].rs1);
2010 set_const(current,dops[i].rt1,v+cinfo[i].imm);
2011 }
2012 else clear_const(current,dops[i].rt1);
2013 if (dops[i].may_except) {
2014 alloc_cc_optional(current, i); // for exceptions
2015 alloc_reg_temp(current, i, -1);
2016 cinfo[i].min_free_regs = 1;
2017 }
2018 }
2019 else {
2020 set_const(current,dops[i].rt1,cinfo[i].imm<<16); // LUI
2021 }
2022 dirty_reg(current,dops[i].rt1);
2023}
2024
2025static void load_alloc(struct regstat *current,int i)
2026{
2027 int need_temp = 0;
2028 clear_const(current,dops[i].rt1);
2029 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
2030 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
2031 if (needed_again(dops[i].rs1, i))
2032 alloc_reg(current, i, dops[i].rs1);
2033 if (ram_offset)
2034 alloc_reg(current, i, ROREG);
2035 if (dops[i].may_except) {
2036 alloc_cc_optional(current, i); // for exceptions
2037 need_temp = 1;
2038 }
2039 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
2040 alloc_reg(current,i,dops[i].rt1);
2041 assert(get_reg_w(current->regmap, dops[i].rt1)>=0);
2042 dirty_reg(current,dops[i].rt1);
2043 // LWL/LWR need a temporary register for the old value
2044 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2045 {
2046 alloc_reg(current,i,FTEMP);
2047 need_temp = 1;
2048 }
2049 }
2050 else
2051 {
2052 // Load to r0 or unneeded register (dummy load)
2053 // but we still need a register to calculate the address
2054 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2055 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2056 need_temp = 1;
2057 }
2058 if (need_temp) {
2059 alloc_reg_temp(current, i, -1);
2060 cinfo[i].min_free_regs = 1;
2061 }
2062}
2063
2064// this may eat up to 7 registers
2065static void store_alloc(struct regstat *current, int i)
2066{
2067 clear_const(current,dops[i].rs2);
2068 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2069 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2070 alloc_reg(current,i,dops[i].rs2);
2071 if (ram_offset)
2072 alloc_reg(current, i, ROREG);
2073 #if defined(HOST_IMM8)
2074 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2075 alloc_reg(current, i, INVCP);
2076 #endif
2077 if (dops[i].opcode == 0x2a || dops[i].opcode == 0x2e) { // SWL/SWL
2078 alloc_reg(current,i,FTEMP);
2079 }
2080 if (dops[i].may_except)
2081 alloc_cc_optional(current, i); // for exceptions
2082 // We need a temporary register for address generation
2083 alloc_reg_temp(current,i,-1);
2084 cinfo[i].min_free_regs=1;
2085}
2086
2087static void c2ls_alloc(struct regstat *current, int i)
2088{
2089 clear_const(current,dops[i].rt1);
2090 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2091 alloc_reg(current,i,FTEMP);
2092 if (ram_offset)
2093 alloc_reg(current, i, ROREG);
2094 #if defined(HOST_IMM8)
2095 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2096 if (dops[i].opcode == 0x3a) // SWC2
2097 alloc_reg(current,i,INVCP);
2098 #endif
2099 if (dops[i].may_except)
2100 alloc_cc_optional(current, i); // for exceptions
2101 // We need a temporary register for address generation
2102 alloc_reg_temp(current,i,-1);
2103 cinfo[i].min_free_regs=1;
2104}
2105
2106#ifndef multdiv_alloc
2107static void multdiv_alloc(struct regstat *current,int i)
2108{
2109 // case 0x18: MULT
2110 // case 0x19: MULTU
2111 // case 0x1A: DIV
2112 // case 0x1B: DIVU
2113 clear_const(current,dops[i].rs1);
2114 clear_const(current,dops[i].rs2);
2115 alloc_cc(current,i); // for stalls
2116 dirty_reg(current,CCREG);
2117 current->u &= ~(1ull << HIREG);
2118 current->u &= ~(1ull << LOREG);
2119 alloc_reg(current, i, HIREG);
2120 alloc_reg(current, i, LOREG);
2121 dirty_reg(current, HIREG);
2122 dirty_reg(current, LOREG);
2123 if ((dops[i].opcode2 & 0x3e) == 0x1a || (dops[i].rs1 && dops[i].rs2)) // div(u)
2124 {
2125 alloc_reg(current, i, dops[i].rs1);
2126 alloc_reg(current, i, dops[i].rs2);
2127 }
2128 // else multiply by zero is zero
2129}
2130#endif
2131
2132static void cop0_alloc(struct regstat *current,int i)
2133{
2134 if(dops[i].opcode2==0) // MFC0
2135 {
2136 if(dops[i].rt1) {
2137 clear_const(current,dops[i].rt1);
2138 alloc_reg(current,i,dops[i].rt1);
2139 dirty_reg(current,dops[i].rt1);
2140 }
2141 }
2142 else if(dops[i].opcode2==4) // MTC0
2143 {
2144 if (((source[i]>>11)&0x1e) == 12) {
2145 alloc_cc(current, i);
2146 dirty_reg(current, CCREG);
2147 }
2148 if(dops[i].rs1){
2149 clear_const(current,dops[i].rs1);
2150 alloc_reg(current,i,dops[i].rs1);
2151 alloc_all(current,i);
2152 }
2153 else {
2154 alloc_all(current,i); // FIXME: Keep r0
2155 current->u&=~1LL;
2156 alloc_reg(current,i,0);
2157 }
2158 cinfo[i].min_free_regs = HOST_REGS;
2159 }
2160}
2161
2162static void rfe_alloc(struct regstat *current, int i)
2163{
2164 alloc_all(current, i);
2165 cinfo[i].min_free_regs = HOST_REGS;
2166}
2167
2168static void cop2_alloc(struct regstat *current,int i)
2169{
2170 if (dops[i].opcode2 < 3) // MFC2/CFC2
2171 {
2172 alloc_cc(current,i); // for stalls
2173 dirty_reg(current,CCREG);
2174 if(dops[i].rt1){
2175 clear_const(current,dops[i].rt1);
2176 alloc_reg(current,i,dops[i].rt1);
2177 dirty_reg(current,dops[i].rt1);
2178 }
2179 }
2180 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2181 {
2182 if(dops[i].rs1){
2183 clear_const(current,dops[i].rs1);
2184 alloc_reg(current,i,dops[i].rs1);
2185 }
2186 else {
2187 current->u&=~1LL;
2188 alloc_reg(current,i,0);
2189 }
2190 }
2191 alloc_reg_temp(current,i,-1);
2192 cinfo[i].min_free_regs=1;
2193}
2194
2195static void c2op_alloc(struct regstat *current,int i)
2196{
2197 alloc_cc(current,i); // for stalls
2198 dirty_reg(current,CCREG);
2199 alloc_reg_temp(current,i,-1);
2200}
2201
2202static void syscall_alloc(struct regstat *current,int i)
2203{
2204 alloc_cc(current,i);
2205 dirty_reg(current,CCREG);
2206 alloc_all(current,i);
2207 cinfo[i].min_free_regs=HOST_REGS;
2208 current->isconst=0;
2209}
2210
2211static void delayslot_alloc(struct regstat *current,int i)
2212{
2213 switch(dops[i].itype) {
2214 case UJUMP:
2215 case CJUMP:
2216 case SJUMP:
2217 case RJUMP:
2218 case SYSCALL:
2219 case HLECALL:
2220 case IMM16:
2221 imm16_alloc(current,i);
2222 break;
2223 case LOAD:
2224 case LOADLR:
2225 load_alloc(current,i);
2226 break;
2227 case STORE:
2228 case STORELR:
2229 store_alloc(current,i);
2230 break;
2231 case ALU:
2232 alu_alloc(current,i);
2233 break;
2234 case SHIFT:
2235 shift_alloc(current,i);
2236 break;
2237 case MULTDIV:
2238 multdiv_alloc(current,i);
2239 break;
2240 case SHIFTIMM:
2241 shiftimm_alloc(current,i);
2242 break;
2243 case MOV:
2244 mov_alloc(current,i);
2245 break;
2246 case COP0:
2247 cop0_alloc(current,i);
2248 break;
2249 case RFE:
2250 rfe_alloc(current,i);
2251 break;
2252 case COP2:
2253 cop2_alloc(current,i);
2254 break;
2255 case C2LS:
2256 c2ls_alloc(current,i);
2257 break;
2258 case C2OP:
2259 c2op_alloc(current,i);
2260 break;
2261 }
2262}
2263
2264static void add_stub(enum stub_type type, void *addr, void *retaddr,
2265 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2266{
2267 assert(stubcount < ARRAY_SIZE(stubs));
2268 stubs[stubcount].type = type;
2269 stubs[stubcount].addr = addr;
2270 stubs[stubcount].retaddr = retaddr;
2271 stubs[stubcount].a = a;
2272 stubs[stubcount].b = b;
2273 stubs[stubcount].c = c;
2274 stubs[stubcount].d = d;
2275 stubs[stubcount].e = e;
2276 stubcount++;
2277}
2278
2279static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2280 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2281{
2282 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2283}
2284
2285// Write out a single register
2286static void wb_register(signed char r, const signed char regmap[], u_int dirty)
2287{
2288 int hr;
2289 for(hr=0;hr<HOST_REGS;hr++) {
2290 if(hr!=EXCLUDE_REG) {
2291 if(regmap[hr]==r) {
2292 if((dirty>>hr)&1) {
2293 assert(regmap[hr]<64);
2294 emit_storereg(r,hr);
2295 }
2296 break;
2297 }
2298 }
2299 }
2300}
2301
2302static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2303{
2304 //if(dirty_pre==dirty) return;
2305 int hr, r;
2306 for (hr = 0; hr < HOST_REGS; hr++) {
2307 r = pre[hr];
2308 if (r < 1 || r > 33 || ((u >> r) & 1))
2309 continue;
2310 if (((dirty_pre & ~dirty) >> hr) & 1)
2311 emit_storereg(r, hr);
2312 }
2313}
2314
2315// trashes r2
2316static void pass_args(int a0, int a1)
2317{
2318 if(a0==1&&a1==0) {
2319 // must swap
2320 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2321 }
2322 else if(a0!=0&&a1==0) {
2323 emit_mov(a1,1);
2324 if (a0>=0) emit_mov(a0,0);
2325 }
2326 else {
2327 if(a0>=0&&a0!=0) emit_mov(a0,0);
2328 if(a1>=0&&a1!=1) emit_mov(a1,1);
2329 }
2330}
2331
2332static void alu_assemble(int i, const struct regstat *i_regs, int ccadj_)
2333{
2334 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2335 int do_oflow = dops[i].may_except; // ADD/SUB with exceptions enabled
2336 if (dops[i].rt1 || do_oflow) {
2337 int do_exception_check = 0;
2338 signed char s1, s2, t, tmp;
2339 t = get_reg_w(i_regs->regmap, dops[i].rt1);
2340 tmp = get_reg_temp(i_regs->regmap);
2341 if (do_oflow)
2342 assert(tmp >= 0);
2343 if (t < 0 && do_oflow)
2344 t = tmp;
2345 if (t >= 0) {
2346 s1 = get_reg(i_regs->regmap, dops[i].rs1);
2347 s2 = get_reg(i_regs->regmap, dops[i].rs2);
2348 if (dops[i].rs1 && dops[i].rs2) {
2349 assert(s1>=0);
2350 assert(s2>=0);
2351 if (dops[i].opcode2 & 2) {
2352 if (do_oflow) {
2353 emit_subs(s1, s2, tmp);
2354 do_exception_check = 1;
2355 }
2356 else
2357 emit_sub(s1,s2,t);
2358 }
2359 else {
2360 if (do_oflow) {
2361 emit_adds(s1, s2, tmp);
2362 do_exception_check = 1;
2363 }
2364 else
2365 emit_add(s1,s2,t);
2366 }
2367 }
2368 else if(dops[i].rs1) {
2369 if(s1>=0) emit_mov(s1,t);
2370 else emit_loadreg(dops[i].rs1,t);
2371 }
2372 else if(dops[i].rs2) {
2373 if (s2 < 0) {
2374 emit_loadreg(dops[i].rs2, t);
2375 s2 = t;
2376 }
2377 if (dops[i].opcode2 & 2) {
2378 if (do_oflow) {
2379 emit_negs(s2, tmp);
2380 do_exception_check = 1;
2381 }
2382 else
2383 emit_neg(s2, t);
2384 }
2385 else if (s2 != t)
2386 emit_mov(s2, t);
2387 }
2388 else
2389 emit_zeroreg(t);
2390 }
2391 if (do_exception_check) {
2392 void *jaddr = out;
2393 emit_jo(0);
2394 if (t >= 0 && tmp != t)
2395 emit_mov(tmp, t);
2396 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2397 }
2398 }
2399 }
2400 else if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2401 if(dops[i].rt1) {
2402 signed char s1l,s2l,t;
2403 {
2404 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2405 //assert(t>=0);
2406 if(t>=0) {
2407 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2408 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2409 if(dops[i].rs2==0) // rx<r0
2410 {
2411 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2412 assert(s1l>=0);
2413 emit_shrimm(s1l,31,t);
2414 }
2415 else // SLTU (unsigned can not be less than zero, 0<0)
2416 emit_zeroreg(t);
2417 }
2418 else if(dops[i].rs1==0) // r0<rx
2419 {
2420 assert(s2l>=0);
2421 if(dops[i].opcode2==0x2a) // SLT
2422 emit_set_gz32(s2l,t);
2423 else // SLTU (set if not zero)
2424 emit_set_nz32(s2l,t);
2425 }
2426 else{
2427 assert(s1l>=0);assert(s2l>=0);
2428 if(dops[i].opcode2==0x2a) // SLT
2429 emit_set_if_less32(s1l,s2l,t);
2430 else // SLTU
2431 emit_set_if_carry32(s1l,s2l,t);
2432 }
2433 }
2434 }
2435 }
2436 }
2437 else if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2438 if(dops[i].rt1) {
2439 signed char s1l,s2l,tl;
2440 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2441 {
2442 if(tl>=0) {
2443 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2444 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2445 if(dops[i].rs1&&dops[i].rs2) {
2446 assert(s1l>=0);
2447 assert(s2l>=0);
2448 if(dops[i].opcode2==0x24) { // AND
2449 emit_and(s1l,s2l,tl);
2450 } else
2451 if(dops[i].opcode2==0x25) { // OR
2452 emit_or(s1l,s2l,tl);
2453 } else
2454 if(dops[i].opcode2==0x26) { // XOR
2455 emit_xor(s1l,s2l,tl);
2456 } else
2457 if(dops[i].opcode2==0x27) { // NOR
2458 emit_or(s1l,s2l,tl);
2459 emit_not(tl,tl);
2460 }
2461 }
2462 else
2463 {
2464 if(dops[i].opcode2==0x24) { // AND
2465 emit_zeroreg(tl);
2466 } else
2467 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2468 if(dops[i].rs1){
2469 if(s1l>=0) emit_mov(s1l,tl);
2470 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2471 }
2472 else
2473 if(dops[i].rs2){
2474 if(s2l>=0) emit_mov(s2l,tl);
2475 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2476 }
2477 else emit_zeroreg(tl);
2478 } else
2479 if(dops[i].opcode2==0x27) { // NOR
2480 if(dops[i].rs1){
2481 if(s1l>=0) emit_not(s1l,tl);
2482 else {
2483 emit_loadreg(dops[i].rs1,tl);
2484 emit_not(tl,tl);
2485 }
2486 }
2487 else
2488 if(dops[i].rs2){
2489 if(s2l>=0) emit_not(s2l,tl);
2490 else {
2491 emit_loadreg(dops[i].rs2,tl);
2492 emit_not(tl,tl);
2493 }
2494 }
2495 else emit_movimm(-1,tl);
2496 }
2497 }
2498 }
2499 }
2500 }
2501 }
2502}
2503
2504static void imm16_assemble(int i, const struct regstat *i_regs, int ccadj_)
2505{
2506 if (dops[i].opcode==0x0f) { // LUI
2507 if(dops[i].rt1) {
2508 signed char t;
2509 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2510 //assert(t>=0);
2511 if(t>=0) {
2512 if(!((i_regs->isconst>>t)&1))
2513 emit_movimm(cinfo[i].imm<<16,t);
2514 }
2515 }
2516 }
2517 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2518 int is_addi = dops[i].may_except;
2519 if (dops[i].rt1 || is_addi) {
2520 signed char s, t, tmp;
2521 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2522 s=get_reg(i_regs->regmap,dops[i].rs1);
2523 if(dops[i].rs1) {
2524 tmp = get_reg_temp(i_regs->regmap);
2525 if (is_addi) {
2526 assert(tmp >= 0);
2527 if (t < 0) t = tmp;
2528 }
2529 if(t>=0) {
2530 if(!((i_regs->isconst>>t)&1)) {
2531 int sum, do_exception_check = 0;
2532 if (s < 0) {
2533 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2534 if (is_addi) {
2535 emit_addimm_and_set_flags3(t, cinfo[i].imm, tmp);
2536 do_exception_check = 1;
2537 }
2538 else
2539 emit_addimm(t, cinfo[i].imm, t);
2540 } else {
2541 if (!((i_regs->wasconst >> s) & 1)) {
2542 if (is_addi) {
2543 emit_addimm_and_set_flags3(s, cinfo[i].imm, tmp);
2544 do_exception_check = 1;
2545 }
2546 else
2547 emit_addimm(s, cinfo[i].imm, t);
2548 }
2549 else {
2550 int oflow = add_overflow(constmap[i][s], cinfo[i].imm, sum);
2551 if (is_addi && oflow)
2552 do_exception_check = 2;
2553 else
2554 emit_movimm(sum, t);
2555 }
2556 }
2557 if (do_exception_check) {
2558 void *jaddr = out;
2559 if (do_exception_check == 2)
2560 emit_jmp(0);
2561 else {
2562 emit_jo(0);
2563 if (tmp != t)
2564 emit_mov(tmp, t);
2565 }
2566 add_stub_r(OVERFLOW_STUB, jaddr, out, i, 0, i_regs, ccadj_, 0);
2567 }
2568 }
2569 }
2570 } else {
2571 if(t>=0) {
2572 if(!((i_regs->isconst>>t)&1))
2573 emit_movimm(cinfo[i].imm,t);
2574 }
2575 }
2576 }
2577 }
2578 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2579 if(dops[i].rt1) {
2580 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2581 signed char sl,t;
2582 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2583 sl=get_reg(i_regs->regmap,dops[i].rs1);
2584 //assert(t>=0);
2585 if(t>=0) {
2586 if(dops[i].rs1>0) {
2587 if(dops[i].opcode==0x0a) { // SLTI
2588 if(sl<0) {
2589 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2590 emit_slti32(t,cinfo[i].imm,t);
2591 }else{
2592 emit_slti32(sl,cinfo[i].imm,t);
2593 }
2594 }
2595 else { // SLTIU
2596 if(sl<0) {
2597 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2598 emit_sltiu32(t,cinfo[i].imm,t);
2599 }else{
2600 emit_sltiu32(sl,cinfo[i].imm,t);
2601 }
2602 }
2603 }else{
2604 // SLTI(U) with r0 is just stupid,
2605 // nonetheless examples can be found
2606 if(dops[i].opcode==0x0a) // SLTI
2607 if(0<cinfo[i].imm) emit_movimm(1,t);
2608 else emit_zeroreg(t);
2609 else // SLTIU
2610 {
2611 if(cinfo[i].imm) emit_movimm(1,t);
2612 else emit_zeroreg(t);
2613 }
2614 }
2615 }
2616 }
2617 }
2618 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2619 if(dops[i].rt1) {
2620 signed char sl,tl;
2621 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
2622 sl=get_reg(i_regs->regmap,dops[i].rs1);
2623 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2624 if(dops[i].opcode==0x0c) //ANDI
2625 {
2626 if(dops[i].rs1) {
2627 if(sl<0) {
2628 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2629 emit_andimm(tl,cinfo[i].imm,tl);
2630 }else{
2631 if(!((i_regs->wasconst>>sl)&1))
2632 emit_andimm(sl,cinfo[i].imm,tl);
2633 else
2634 emit_movimm(constmap[i][sl]&cinfo[i].imm,tl);
2635 }
2636 }
2637 else
2638 emit_zeroreg(tl);
2639 }
2640 else
2641 {
2642 if(dops[i].rs1) {
2643 if(sl<0) {
2644 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2645 }
2646 if(dops[i].opcode==0x0d) { // ORI
2647 if(sl<0) {
2648 emit_orimm(tl,cinfo[i].imm,tl);
2649 }else{
2650 if(!((i_regs->wasconst>>sl)&1))
2651 emit_orimm(sl,cinfo[i].imm,tl);
2652 else
2653 emit_movimm(constmap[i][sl]|cinfo[i].imm,tl);
2654 }
2655 }
2656 if(dops[i].opcode==0x0e) { // XORI
2657 if(sl<0) {
2658 emit_xorimm(tl,cinfo[i].imm,tl);
2659 }else{
2660 if(!((i_regs->wasconst>>sl)&1))
2661 emit_xorimm(sl,cinfo[i].imm,tl);
2662 else
2663 emit_movimm(constmap[i][sl]^cinfo[i].imm,tl);
2664 }
2665 }
2666 }
2667 else {
2668 emit_movimm(cinfo[i].imm,tl);
2669 }
2670 }
2671 }
2672 }
2673 }
2674}
2675
2676static void shiftimm_assemble(int i, const struct regstat *i_regs)
2677{
2678 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2679 {
2680 if(dops[i].rt1) {
2681 signed char s,t;
2682 t=get_reg_w(i_regs->regmap, dops[i].rt1);
2683 s=get_reg(i_regs->regmap,dops[i].rs1);
2684 //assert(t>=0);
2685 if(t>=0&&!((i_regs->isconst>>t)&1)){
2686 if(dops[i].rs1==0)
2687 {
2688 emit_zeroreg(t);
2689 }
2690 else
2691 {
2692 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2693 if(cinfo[i].imm) {
2694 if(dops[i].opcode2==0) // SLL
2695 {
2696 emit_shlimm(s<0?t:s,cinfo[i].imm,t);
2697 }
2698 if(dops[i].opcode2==2) // SRL
2699 {
2700 emit_shrimm(s<0?t:s,cinfo[i].imm,t);
2701 }
2702 if(dops[i].opcode2==3) // SRA
2703 {
2704 emit_sarimm(s<0?t:s,cinfo[i].imm,t);
2705 }
2706 }else{
2707 // Shift by zero
2708 if(s>=0 && s!=t) emit_mov(s,t);
2709 }
2710 }
2711 }
2712 //emit_storereg(dops[i].rt1,t); //DEBUG
2713 }
2714 }
2715 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2716 {
2717 assert(0);
2718 }
2719 if(dops[i].opcode2==0x3c) // DSLL32
2720 {
2721 assert(0);
2722 }
2723 if(dops[i].opcode2==0x3e) // DSRL32
2724 {
2725 assert(0);
2726 }
2727 if(dops[i].opcode2==0x3f) // DSRA32
2728 {
2729 assert(0);
2730 }
2731}
2732
2733#ifndef shift_assemble
2734static void shift_assemble(int i, const struct regstat *i_regs)
2735{
2736 signed char s,t,shift;
2737 if (dops[i].rt1 == 0)
2738 return;
2739 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2740 t = get_reg(i_regs->regmap, dops[i].rt1);
2741 s = get_reg(i_regs->regmap, dops[i].rs1);
2742 shift = get_reg(i_regs->regmap, dops[i].rs2);
2743 if (t < 0)
2744 return;
2745
2746 if(dops[i].rs1==0)
2747 emit_zeroreg(t);
2748 else if(dops[i].rs2==0) {
2749 assert(s>=0);
2750 if(s!=t) emit_mov(s,t);
2751 }
2752 else {
2753 host_tempreg_acquire();
2754 emit_andimm(shift,31,HOST_TEMPREG);
2755 switch(dops[i].opcode2) {
2756 case 4: // SLLV
2757 emit_shl(s,HOST_TEMPREG,t);
2758 break;
2759 case 6: // SRLV
2760 emit_shr(s,HOST_TEMPREG,t);
2761 break;
2762 case 7: // SRAV
2763 emit_sar(s,HOST_TEMPREG,t);
2764 break;
2765 default:
2766 assert(0);
2767 }
2768 host_tempreg_release();
2769 }
2770}
2771
2772#endif
2773
2774enum {
2775 MTYPE_8000 = 0,
2776 MTYPE_8020,
2777 MTYPE_0000,
2778 MTYPE_A000,
2779 MTYPE_1F80,
2780};
2781
2782static int get_ptr_mem_type(u_int a)
2783{
2784 if(a < 0x00200000) {
2785 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2786 // return wrong, must use memhandler for BIOS self-test to pass
2787 // 007 does similar stuff from a00 mirror, weird stuff
2788 return MTYPE_8000;
2789 return MTYPE_0000;
2790 }
2791 if(0x1f800000 <= a && a < 0x1f801000)
2792 return MTYPE_1F80;
2793 if(0x80200000 <= a && a < 0x80800000)
2794 return MTYPE_8020;
2795 if(0xa0000000 <= a && a < 0xa0200000)
2796 return MTYPE_A000;
2797 return MTYPE_8000;
2798}
2799
2800static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2801{
2802 int r = get_reg(i_regs->regmap, ROREG);
2803 if (r < 0 && host_tempreg_free) {
2804 host_tempreg_acquire();
2805 emit_loadreg(ROREG, r = HOST_TEMPREG);
2806 }
2807 if (r < 0)
2808 abort();
2809 return r;
2810}
2811
2812static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2813 int addr, int *offset_reg, int *addr_reg_override, int ccadj_)
2814{
2815 void *jaddr = NULL;
2816 int type = 0;
2817 int mr = dops[i].rs1;
2818 assert(addr >= 0);
2819 *offset_reg = -1;
2820 if(((smrv_strong|smrv_weak)>>mr)&1) {
2821 type=get_ptr_mem_type(smrv[mr]);
2822 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2823 }
2824 else {
2825 // use the mirror we are running on
2826 type=get_ptr_mem_type(start);
2827 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2828 }
2829
2830 if (dops[i].may_except) {
2831 // alignment check
2832 u_int op = dops[i].opcode;
2833 int mask = ((op & 0x37) == 0x21 || op == 0x25) ? 1 : 3; // LH/SH/LHU
2834 void *jaddr2;
2835 emit_testimm(addr, mask);
2836 jaddr2 = out;
2837 emit_jne(0);
2838 add_stub_r(ALIGNMENT_STUB, jaddr2, out, i, addr, i_regs, ccadj_, 0);
2839 }
2840
2841 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2842 host_tempreg_acquire();
2843 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2844 addr=*addr_reg_override=HOST_TEMPREG;
2845 type=0;
2846 }
2847 else if(type==MTYPE_0000) { // RAM 0 mirror
2848 host_tempreg_acquire();
2849 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2850 addr=*addr_reg_override=HOST_TEMPREG;
2851 type=0;
2852 }
2853 else if(type==MTYPE_A000) { // RAM A mirror
2854 host_tempreg_acquire();
2855 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2856 addr=*addr_reg_override=HOST_TEMPREG;
2857 type=0;
2858 }
2859 else if(type==MTYPE_1F80) { // scratchpad
2860 if (psxH == (void *)0x1f800000) {
2861 host_tempreg_acquire();
2862 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2863 emit_cmpimm(HOST_TEMPREG,0x1000);
2864 host_tempreg_release();
2865 jaddr=out;
2866 emit_jc(0);
2867 }
2868 else {
2869 // do the usual RAM check, jump will go to the right handler
2870 type=0;
2871 }
2872 }
2873
2874 if (type == 0) // need ram check
2875 {
2876 emit_cmpimm(addr,RAM_SIZE);
2877 jaddr = out;
2878 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2879 // Hint to branch predictor that the branch is unlikely to be taken
2880 if (dops[i].rs1 >= 28)
2881 emit_jno_unlikely(0);
2882 else
2883 #endif
2884 emit_jno(0);
2885 if (ram_offset != 0)
2886 *offset_reg = get_ro_reg(i_regs, 0);
2887 }
2888
2889 return jaddr;
2890}
2891
2892// return memhandler, or get directly accessable address and return 0
2893static void *get_direct_memhandler(void *table, u_int addr,
2894 enum stub_type type, uintptr_t *addr_host)
2895{
2896 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2897 uintptr_t l1, l2 = 0;
2898 l1 = ((uintptr_t *)table)[addr>>12];
2899 if (!(l1 & msb)) {
2900 uintptr_t v = l1 << 1;
2901 *addr_host = v + addr;
2902 return NULL;
2903 }
2904 else {
2905 l1 <<= 1;
2906 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2907 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2908 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2909 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2910 else
2911 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2912 if (!(l2 & msb)) {
2913 uintptr_t v = l2 << 1;
2914 *addr_host = v + (addr&0xfff);
2915 return NULL;
2916 }
2917 return (void *)(l2 << 1);
2918 }
2919}
2920
2921static u_int get_host_reglist(const signed char *regmap)
2922{
2923 u_int reglist = 0, hr;
2924 for (hr = 0; hr < HOST_REGS; hr++) {
2925 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2926 reglist |= 1 << hr;
2927 }
2928 return reglist;
2929}
2930
2931static u_int reglist_exclude(u_int reglist, int r1, int r2)
2932{
2933 if (r1 >= 0)
2934 reglist &= ~(1u << r1);
2935 if (r2 >= 0)
2936 reglist &= ~(1u << r2);
2937 return reglist;
2938}
2939
2940// find a temp caller-saved register not in reglist (so assumed to be free)
2941static int reglist_find_free(u_int reglist)
2942{
2943 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2944 if (free_regs == 0)
2945 return -1;
2946 return __builtin_ctz(free_regs);
2947}
2948
2949static void do_load_word(int a, int rt, int offset_reg)
2950{
2951 if (offset_reg >= 0)
2952 emit_ldr_dualindexed(offset_reg, a, rt);
2953 else
2954 emit_readword_indexed(0, a, rt);
2955}
2956
2957static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2958{
2959 if (offset_reg < 0) {
2960 emit_writeword_indexed(rt, ofs, a);
2961 return;
2962 }
2963 if (ofs != 0)
2964 emit_addimm(a, ofs, a);
2965 emit_str_dualindexed(offset_reg, a, rt);
2966 if (ofs != 0 && preseve_a)
2967 emit_addimm(a, -ofs, a);
2968}
2969
2970static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2971{
2972 if (offset_reg < 0) {
2973 emit_writehword_indexed(rt, ofs, a);
2974 return;
2975 }
2976 if (ofs != 0)
2977 emit_addimm(a, ofs, a);
2978 emit_strh_dualindexed(offset_reg, a, rt);
2979 if (ofs != 0 && preseve_a)
2980 emit_addimm(a, -ofs, a);
2981}
2982
2983static void do_store_byte(int a, int rt, int offset_reg)
2984{
2985 if (offset_reg >= 0)
2986 emit_strb_dualindexed(offset_reg, a, rt);
2987 else
2988 emit_writebyte_indexed(rt, 0, a);
2989}
2990
2991static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2992{
2993 int addr = cinfo[i].addr;
2994 int s,tl;
2995 int offset;
2996 void *jaddr=0;
2997 int memtarget=0,c=0;
2998 int offset_reg = -1;
2999 int fastio_reg_override = -1;
3000 u_int reglist=get_host_reglist(i_regs->regmap);
3001 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3002 s=get_reg(i_regs->regmap,dops[i].rs1);
3003 offset=cinfo[i].imm;
3004 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3005 if(s>=0) {
3006 c=(i_regs->wasconst>>s)&1;
3007 if (c) {
3008 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3009 }
3010 }
3011 //printf("load_assemble: c=%d\n",c);
3012 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3013 if(tl<0 && ((!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80) || dops[i].rt1==0)) {
3014 // could be FIFO, must perform the read
3015 // ||dummy read
3016 assem_debug("(forced read)\n");
3017 tl = get_reg_temp(i_regs->regmap); // may be == addr
3018 assert(tl>=0);
3019 }
3020 assert(addr >= 0);
3021 if(tl>=0) {
3022 //printf("load_assemble: c=%d\n",c);
3023 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
3024 reglist&=~(1<<tl);
3025 if(!c) {
3026 #ifdef R29_HACK
3027 // Strmnnrmn's speed hack
3028 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3029 #endif
3030 {
3031 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3032 &offset_reg, &fastio_reg_override, ccadj_);
3033 }
3034 }
3035 else if (ram_offset && memtarget) {
3036 offset_reg = get_ro_reg(i_regs, 0);
3037 }
3038 int dummy=(dops[i].rt1==0)||(tl!=get_reg_w(i_regs->regmap, dops[i].rt1)); // ignore loads to r0 and unneeded reg
3039 switch (dops[i].opcode) {
3040 case 0x20: // LB
3041 if(!c||memtarget) {
3042 if(!dummy) {
3043 int a = addr;
3044 if (fastio_reg_override >= 0)
3045 a = fastio_reg_override;
3046
3047 if (offset_reg >= 0)
3048 emit_ldrsb_dualindexed(offset_reg, a, tl);
3049 else
3050 emit_movsbl_indexed(0, a, tl);
3051 }
3052 if(jaddr)
3053 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3054 }
3055 else
3056 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3057 break;
3058 case 0x21: // LH
3059 if(!c||memtarget) {
3060 if(!dummy) {
3061 int a = addr;
3062 if (fastio_reg_override >= 0)
3063 a = fastio_reg_override;
3064 if (offset_reg >= 0)
3065 emit_ldrsh_dualindexed(offset_reg, a, tl);
3066 else
3067 emit_movswl_indexed(0, a, tl);
3068 }
3069 if(jaddr)
3070 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3071 }
3072 else
3073 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3074 break;
3075 case 0x23: // LW
3076 if(!c||memtarget) {
3077 if(!dummy) {
3078 int a = addr;
3079 if (fastio_reg_override >= 0)
3080 a = fastio_reg_override;
3081 do_load_word(a, tl, offset_reg);
3082 }
3083 if(jaddr)
3084 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3085 }
3086 else
3087 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3088 break;
3089 case 0x24: // LBU
3090 if(!c||memtarget) {
3091 if(!dummy) {
3092 int a = addr;
3093 if (fastio_reg_override >= 0)
3094 a = fastio_reg_override;
3095
3096 if (offset_reg >= 0)
3097 emit_ldrb_dualindexed(offset_reg, a, tl);
3098 else
3099 emit_movzbl_indexed(0, a, tl);
3100 }
3101 if(jaddr)
3102 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3103 }
3104 else
3105 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3106 break;
3107 case 0x25: // LHU
3108 if(!c||memtarget) {
3109 if(!dummy) {
3110 int a = addr;
3111 if (fastio_reg_override >= 0)
3112 a = fastio_reg_override;
3113 if (offset_reg >= 0)
3114 emit_ldrh_dualindexed(offset_reg, a, tl);
3115 else
3116 emit_movzwl_indexed(0, a, tl);
3117 }
3118 if(jaddr)
3119 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3120 }
3121 else
3122 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3123 break;
3124 default:
3125 assert(0);
3126 }
3127 } // tl >= 0
3128 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3129 host_tempreg_release();
3130}
3131
3132#ifndef loadlr_assemble
3133static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3134{
3135 int addr = cinfo[i].addr;
3136 int s,tl,temp,temp2;
3137 int offset;
3138 void *jaddr=0;
3139 int memtarget=0,c=0;
3140 int offset_reg = -1;
3141 int fastio_reg_override = -1;
3142 u_int reglist=get_host_reglist(i_regs->regmap);
3143 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3144 s=get_reg(i_regs->regmap,dops[i].rs1);
3145 temp=get_reg_temp(i_regs->regmap);
3146 temp2=get_reg(i_regs->regmap,FTEMP);
3147 offset=cinfo[i].imm;
3148 reglist|=1<<temp;
3149 assert(addr >= 0);
3150 if(s>=0) {
3151 c=(i_regs->wasconst>>s)&1;
3152 if(c) {
3153 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3154 }
3155 }
3156 if(!c) {
3157 emit_shlimm(addr,3,temp);
3158 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3159 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3160 }else{
3161 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3162 }
3163 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3164 &offset_reg, &fastio_reg_override, ccadj_);
3165 }
3166 else {
3167 if (ram_offset && memtarget) {
3168 offset_reg = get_ro_reg(i_regs, 0);
3169 }
3170 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3171 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3172 }else{
3173 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3174 }
3175 }
3176 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3177 if(!c||memtarget) {
3178 int a = temp2;
3179 if (fastio_reg_override >= 0)
3180 a = fastio_reg_override;
3181 do_load_word(a, temp2, offset_reg);
3182 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3183 host_tempreg_release();
3184 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3185 }
3186 else
3187 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3188 if(dops[i].rt1) {
3189 assert(tl>=0);
3190 emit_andimm(temp,24,temp);
3191 if (dops[i].opcode==0x22) // LWL
3192 emit_xorimm(temp,24,temp);
3193 host_tempreg_acquire();
3194 emit_movimm(-1,HOST_TEMPREG);
3195 if (dops[i].opcode==0x26) {
3196 emit_shr(temp2,temp,temp2);
3197 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3198 }else{
3199 emit_shl(temp2,temp,temp2);
3200 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3201 }
3202 host_tempreg_release();
3203 emit_or(temp2,tl,tl);
3204 }
3205 //emit_storereg(dops[i].rt1,tl); // DEBUG
3206 }
3207 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3208 assert(0);
3209 }
3210}
3211#endif
3212
3213static void do_invstub(int n)
3214{
3215 literal_pool(20);
3216 assem_debug("do_invstub %x\n", start + stubs[n].e*4);
3217 u_int reglist = stubs[n].a;
3218 u_int addrr = stubs[n].b;
3219 int ofs_start = stubs[n].c;
3220 int ofs_end = stubs[n].d;
3221 int len = ofs_end - ofs_start;
3222 u_int rightr = 0;
3223
3224 set_jump_target(stubs[n].addr, out);
3225 save_regs(reglist);
3226 if (addrr != 0 || ofs_start != 0)
3227 emit_addimm(addrr, ofs_start, 0);
3228 emit_readword(&inv_code_start, 2);
3229 emit_readword(&inv_code_end, 3);
3230 if (len != 0)
3231 emit_addimm(0, len + 4, (rightr = 1));
3232 emit_cmp(0, 2);
3233 emit_cmpcs(3, rightr);
3234 void *jaddr = out;
3235 emit_jc(0);
3236 void *func = (len != 0)
3237 ? (void *)ndrc_write_invalidate_many
3238 : (void *)ndrc_write_invalidate_one;
3239 emit_far_call(func);
3240 set_jump_target(jaddr, out);
3241 restore_regs(reglist);
3242 emit_jmp(stubs[n].retaddr);
3243}
3244
3245static void do_store_smc_check(int i, const struct regstat *i_regs, u_int reglist, int addr)
3246{
3247 if (HACK_ENABLED(NDHACK_NO_SMC_CHECK))
3248 return;
3249 // this can't be used any more since we started to check exact
3250 // block boundaries in invalidate_range()
3251 //if (i_regs->waswritten & (1<<dops[i].rs1))
3252 // return;
3253 // (naively) assume nobody will run code from stack
3254 if (dops[i].rs1 == 29)
3255 return;
3256
3257 int j, imm_maxdiff = 32, imm_min = cinfo[i].imm, imm_max = cinfo[i].imm, count = 1;
3258 if (i < slen - 1 && dops[i+1].is_store && dops[i+1].rs1 == dops[i].rs1
3259 && abs(cinfo[i+1].imm - cinfo[i].imm) <= imm_maxdiff)
3260 return;
3261 for (j = i - 1; j >= 0; j--) {
3262 if (!dops[j].is_store || dops[j].rs1 != dops[i].rs1
3263 || abs(cinfo[j].imm - cinfo[j+1].imm) > imm_maxdiff)
3264 break;
3265 count++;
3266 if (imm_min > cinfo[j].imm)
3267 imm_min = cinfo[j].imm;
3268 if (imm_max < cinfo[j].imm)
3269 imm_max = cinfo[j].imm;
3270 }
3271#if defined(HOST_IMM8)
3272 int ir = get_reg(i_regs->regmap, INVCP);
3273 assert(ir >= 0);
3274 host_tempreg_acquire();
3275 emit_ldrb_indexedsr12_reg(ir, addr, HOST_TEMPREG);
3276#else
3277 emit_cmpmem_indexedsr12_imm(invalid_code, addr, 1);
3278 #error not handled
3279#endif
3280#ifdef INVALIDATE_USE_COND_CALL
3281 if (count == 1) {
3282 emit_cmpimm(HOST_TEMPREG, 1);
3283 emit_callne(invalidate_addr_reg[addr]);
3284 host_tempreg_release();
3285 return;
3286 }
3287#endif
3288 void *jaddr = emit_cbz(HOST_TEMPREG, 0);
3289 host_tempreg_release();
3290 imm_min -= cinfo[i].imm;
3291 imm_max -= cinfo[i].imm;
3292 add_stub(INVCODE_STUB, jaddr, out, reglist|(1<<HOST_CCREG),
3293 addr, imm_min, imm_max, i);
3294}
3295
3296// determines if code overwrite checking is needed only
3297// (also true non-existent 0x20000000 mirror that shouldn't matter)
3298#define is_ram_addr(a) !((a) & 0x5f800000)
3299
3300static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3301{
3302 int s,tl;
3303 int addr = cinfo[i].addr;
3304 int offset;
3305 void *jaddr=0;
3306 enum stub_type type=0;
3307 int memtarget=0,c=0;
3308 int offset_reg = -1;
3309 int fastio_reg_override = -1;
3310 u_int addr_const = ~0;
3311 u_int reglist=get_host_reglist(i_regs->regmap);
3312 tl=get_reg(i_regs->regmap,dops[i].rs2);
3313 s=get_reg(i_regs->regmap,dops[i].rs1);
3314 offset=cinfo[i].imm;
3315 if(s>=0) {
3316 c=(i_regs->wasconst>>s)&1;
3317 if (c) {
3318 addr_const = constmap[i][s] + offset;
3319 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3320 }
3321 }
3322 assert(tl>=0);
3323 assert(addr >= 0);
3324 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3325 reglist |= 1u << addr;
3326 if (!c) {
3327 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3328 &offset_reg, &fastio_reg_override, ccadj_);
3329 }
3330 else if (ram_offset && memtarget) {
3331 offset_reg = get_ro_reg(i_regs, 0);
3332 }
3333
3334 switch (dops[i].opcode) {
3335 case 0x28: // SB
3336 if(!c||memtarget) {
3337 int a = addr;
3338 if (fastio_reg_override >= 0)
3339 a = fastio_reg_override;
3340 do_store_byte(a, tl, offset_reg);
3341 }
3342 type = STOREB_STUB;
3343 break;
3344 case 0x29: // SH
3345 if(!c||memtarget) {
3346 int a = addr;
3347 if (fastio_reg_override >= 0)
3348 a = fastio_reg_override;
3349 do_store_hword(a, 0, tl, offset_reg, 1);
3350 }
3351 type = STOREH_STUB;
3352 break;
3353 case 0x2B: // SW
3354 if(!c||memtarget) {
3355 int a = addr;
3356 if (fastio_reg_override >= 0)
3357 a = fastio_reg_override;
3358 do_store_word(a, 0, tl, offset_reg, 1);
3359 }
3360 type = STOREW_STUB;
3361 break;
3362 default:
3363 assert(0);
3364 }
3365 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3366 host_tempreg_release();
3367 if (jaddr) {
3368 // PCSX store handlers don't check invcode again
3369 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3370 }
3371 if (!c || is_ram_addr(addr_const))
3372 do_store_smc_check(i, i_regs, reglist, addr);
3373 if (c && !memtarget)
3374 inline_writestub(type, i, addr_const, i_regs->regmap, dops[i].rs2, ccadj_, reglist);
3375 // basic current block modification detection..
3376 // not looking back as that should be in mips cache already
3377 // (see Spyro2 title->attract mode)
3378 if (start + i*4 < addr_const && addr_const < start + slen*4) {
3379 SysPrintf("write to %08x hits block %08x, pc=%08x\n", addr_const, start, start+i*4);
3380 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3381 if(i_regs->regmap==regs[i].regmap) {
3382 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3383 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3384 emit_movimm(start+i*4+4,0);
3385 emit_writeword(0,&pcaddr);
3386 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3387 emit_far_call(ndrc_get_addr_ht);
3388 emit_jmpreg(0);
3389 }
3390 }
3391}
3392
3393static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3394{
3395 int addr = cinfo[i].addr;
3396 int s,tl;
3397 int offset;
3398 void *jaddr=0;
3399 void *case1, *case23, *case3;
3400 void *done0, *done1, *done2;
3401 int memtarget=0,c=0;
3402 int offset_reg = -1;
3403 u_int addr_const = ~0;
3404 u_int reglist = get_host_reglist(i_regs->regmap);
3405 tl=get_reg(i_regs->regmap,dops[i].rs2);
3406 s=get_reg(i_regs->regmap,dops[i].rs1);
3407 offset=cinfo[i].imm;
3408 if(s>=0) {
3409 c = (i_regs->isconst >> s) & 1;
3410 if (c) {
3411 addr_const = constmap[i][s] + offset;
3412 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3413 }
3414 }
3415 assert(tl>=0);
3416 assert(addr >= 0);
3417 reglist |= 1u << addr;
3418 if(!c) {
3419 emit_cmpimm(addr, RAM_SIZE);
3420 jaddr=out;
3421 emit_jno(0);
3422 }
3423 else
3424 {
3425 if(!memtarget||!dops[i].rs1) {
3426 jaddr=out;
3427 emit_jmp(0);
3428 }
3429 }
3430 if (ram_offset)
3431 offset_reg = get_ro_reg(i_regs, 0);
3432
3433 emit_testimm(addr,2);
3434 case23=out;
3435 emit_jne(0);
3436 emit_testimm(addr,1);
3437 case1=out;
3438 emit_jne(0);
3439 // 0
3440 if (dops[i].opcode == 0x2A) { // SWL
3441 // Write msb into least significant byte
3442 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3443 do_store_byte(addr, tl, offset_reg);
3444 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3445 }
3446 else if (dops[i].opcode == 0x2E) { // SWR
3447 // Write entire word
3448 do_store_word(addr, 0, tl, offset_reg, 1);
3449 }
3450 done0 = out;
3451 emit_jmp(0);
3452 // 1
3453 set_jump_target(case1, out);
3454 if (dops[i].opcode == 0x2A) { // SWL
3455 // Write two msb into two least significant bytes
3456 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3457 do_store_hword(addr, -1, tl, offset_reg, 1);
3458 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3459 }
3460 else if (dops[i].opcode == 0x2E) { // SWR
3461 // Write 3 lsb into three most significant bytes
3462 do_store_byte(addr, tl, offset_reg);
3463 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3464 do_store_hword(addr, 1, tl, offset_reg, 1);
3465 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3466 }
3467 done1=out;
3468 emit_jmp(0);
3469 // 2,3
3470 set_jump_target(case23, out);
3471 emit_testimm(addr,1);
3472 case3 = out;
3473 emit_jne(0);
3474 // 2
3475 if (dops[i].opcode==0x2A) { // SWL
3476 // Write 3 msb into three least significant bytes
3477 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3478 do_store_hword(addr, -2, tl, offset_reg, 1);
3479 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3480 do_store_byte(addr, tl, offset_reg);
3481 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3482 }
3483 else if (dops[i].opcode == 0x2E) { // SWR
3484 // Write two lsb into two most significant bytes
3485 do_store_hword(addr, 0, tl, offset_reg, 1);
3486 }
3487 done2 = out;
3488 emit_jmp(0);
3489 // 3
3490 set_jump_target(case3, out);
3491 if (dops[i].opcode == 0x2A) { // SWL
3492 do_store_word(addr, -3, tl, offset_reg, 1);
3493 }
3494 else if (dops[i].opcode == 0x2E) { // SWR
3495 do_store_byte(addr, tl, offset_reg);
3496 }
3497 set_jump_target(done0, out);
3498 set_jump_target(done1, out);
3499 set_jump_target(done2, out);
3500 if (offset_reg == HOST_TEMPREG)
3501 host_tempreg_release();
3502 if (!c || !memtarget)
3503 add_stub_r(STORELR_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3504 if (!c || is_ram_addr(addr_const))
3505 do_store_smc_check(i, i_regs, reglist, addr);
3506}
3507
3508static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3509{
3510 if(dops[i].opcode2==0) // MFC0
3511 {
3512 signed char t=get_reg_w(i_regs->regmap, dops[i].rt1);
3513 u_int copr=(source[i]>>11)&0x1f;
3514 if(t>=0&&dops[i].rt1!=0) {
3515 emit_readword(&reg_cop0[copr],t);
3516 }
3517 }
3518 else if(dops[i].opcode2==4) // MTC0
3519 {
3520 int s = get_reg(i_regs->regmap, dops[i].rs1);
3521 int cc = get_reg(i_regs->regmap, CCREG);
3522 char copr=(source[i]>>11)&0x1f;
3523 assert(s>=0);
3524 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3525 if (copr == 12 || copr == 13) {
3526 emit_readword(&last_count,HOST_TEMPREG);
3527 if (cc != HOST_CCREG)
3528 emit_loadreg(CCREG, HOST_CCREG);
3529 emit_add(HOST_CCREG, HOST_TEMPREG, HOST_CCREG);
3530 emit_addimm(HOST_CCREG, ccadj_ + 2, HOST_CCREG);
3531 emit_writeword(HOST_CCREG, &psxRegs.cycle);
3532 if (is_delayslot) {
3533 // burn cycles to cause cc_interrupt, which will
3534 // reschedule next_interupt. Relies on CCREG from above.
3535 assem_debug("MTC0 DS %d\n", copr);
3536 emit_writeword(HOST_CCREG,&last_count);
3537 emit_movimm(0,HOST_CCREG);
3538 emit_storereg(CCREG,HOST_CCREG);
3539 emit_loadreg(dops[i].rs1,1);
3540 emit_movimm(copr,0);
3541 emit_far_call(pcsx_mtc0_ds);
3542 emit_loadreg(dops[i].rs1,s);
3543 return;
3544 }
3545 emit_movimm(start+i*4+4,HOST_TEMPREG);
3546 emit_writeword(HOST_TEMPREG,&pcaddr);
3547 emit_movimm(0,HOST_TEMPREG);
3548 emit_writeword(HOST_TEMPREG,&pending_exception);
3549 }
3550 if( s != 1)
3551 emit_mov(s, 1);
3552 emit_movimm(copr, 0);
3553 emit_far_call(pcsx_mtc0);
3554 if (copr == 12 || copr == 13) {
3555 emit_readword(&psxRegs.cycle,HOST_CCREG);
3556 emit_readword(&last_count,HOST_TEMPREG);
3557 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3558 //emit_writeword(HOST_TEMPREG,&last_count);
3559 assert(!is_delayslot);
3560 emit_readword(&pending_exception,HOST_TEMPREG);
3561 emit_test(HOST_TEMPREG,HOST_TEMPREG);
3562 void *jaddr = out;
3563 emit_jeq(0);
3564 emit_readword(&pcaddr, 0);
3565 emit_far_call(ndrc_get_addr_ht);
3566 emit_jmpreg(0);
3567 set_jump_target(jaddr, out);
3568 emit_addimm(HOST_CCREG, -ccadj_ - 2, HOST_CCREG);
3569 if (cc != HOST_CCREG)
3570 emit_storereg(CCREG, HOST_CCREG);
3571 }
3572 emit_loadreg(dops[i].rs1,s);
3573 }
3574}
3575
3576static void rfe_assemble(int i, const struct regstat *i_regs)
3577{
3578 emit_readword(&psxRegs.CP0.n.SR, 0);
3579 emit_andimm(0, 0x3c, 1);
3580 emit_andimm(0, ~0xf, 0);
3581 emit_orrshr_imm(1, 2, 0);
3582 emit_writeword(0, &psxRegs.CP0.n.SR);
3583}
3584
3585static int cop2_is_stalling_op(int i, int *cycles)
3586{
3587 if (dops[i].opcode == 0x3a) { // SWC2
3588 *cycles = 0;
3589 return 1;
3590 }
3591 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3592 *cycles = 0;
3593 return 1;
3594 }
3595 if (dops[i].itype == C2OP) {
3596 *cycles = gte_cycletab[source[i] & 0x3f];
3597 return 1;
3598 }
3599 // ... what about MTC2/CTC2/LWC2?
3600 return 0;
3601}
3602
3603#if 0
3604static void log_gte_stall(int stall, u_int cycle)
3605{
3606 if ((u_int)stall <= 44)
3607 printf("x stall %2d %u\n", stall, cycle + last_count);
3608}
3609
3610static void emit_log_gte_stall(int i, int stall, u_int reglist)
3611{
3612 save_regs(reglist);
3613 if (stall > 0)
3614 emit_movimm(stall, 0);
3615 else
3616 emit_mov(HOST_TEMPREG, 0);
3617 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3618 emit_far_call(log_gte_stall);
3619 restore_regs(reglist);
3620}
3621#endif
3622
3623static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3624{
3625 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3626 int rtmp = reglist_find_free(reglist);
3627
3628 if (HACK_ENABLED(NDHACK_NO_STALLS))
3629 return;
3630 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3631 // happens occasionally... cc evicted? Don't bother then
3632 //printf("no cc %08x\n", start + i*4);
3633 return;
3634 }
3635 if (!dops[i].bt) {
3636 for (j = i - 1; j >= 0; j--) {
3637 //if (dops[j].is_ds) break;
3638 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3639 break;
3640 if (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj)
3641 break;
3642 }
3643 j = max(j, 0);
3644 }
3645 cycles_passed = cinfo[i].ccadj - cinfo[j].ccadj;
3646 if (other_gte_op_cycles >= 0)
3647 stall = other_gte_op_cycles - cycles_passed;
3648 else if (cycles_passed >= 44)
3649 stall = 0; // can't stall
3650 if (stall == -MAXBLOCK && rtmp >= 0) {
3651 // unknown stall, do the expensive runtime check
3652 assem_debug("; cop2_do_stall_check\n");
3653#if 0 // too slow
3654 save_regs(reglist);
3655 emit_movimm(gte_cycletab[op], 0);
3656 emit_addimm(HOST_CCREG, cinfo[i].ccadj, 1);
3657 emit_far_call(call_gteStall);
3658 restore_regs(reglist);
3659#else
3660 host_tempreg_acquire();
3661 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3662 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3663 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3664 emit_cmpimm(HOST_TEMPREG, 44);
3665 emit_cmovb_reg(rtmp, HOST_CCREG);
3666 //emit_log_gte_stall(i, 0, reglist);
3667 host_tempreg_release();
3668#endif
3669 }
3670 else if (stall > 0) {
3671 //emit_log_gte_stall(i, stall, reglist);
3672 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3673 }
3674
3675 // save gteBusyCycle, if needed
3676 if (gte_cycletab[op] == 0)
3677 return;
3678 other_gte_op_cycles = -1;
3679 for (j = i + 1; j < slen; j++) {
3680 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3681 break;
3682 if (dops[j].is_jump) {
3683 // check ds
3684 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3685 j++;
3686 break;
3687 }
3688 }
3689 if (other_gte_op_cycles >= 0)
3690 // will handle stall when assembling that op
3691 return;
3692 cycles_passed = cinfo[min(j, slen -1)].ccadj - cinfo[i].ccadj;
3693 if (cycles_passed >= 44)
3694 return;
3695 assem_debug("; save gteBusyCycle\n");
3696 host_tempreg_acquire();
3697#if 0
3698 emit_readword(&last_count, HOST_TEMPREG);
3699 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3700 emit_addimm(HOST_TEMPREG, cinfo[i].ccadj, HOST_TEMPREG);
3701 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3702 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3703#else
3704 emit_addimm(HOST_CCREG, cinfo[i].ccadj + gte_cycletab[op], HOST_TEMPREG);
3705 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3706#endif
3707 host_tempreg_release();
3708}
3709
3710static int is_mflohi(int i)
3711{
3712 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3713}
3714
3715static int check_multdiv(int i, int *cycles)
3716{
3717 if (dops[i].itype != MULTDIV)
3718 return 0;
3719 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3720 *cycles = 11; // approx from 7 11 14
3721 else
3722 *cycles = 37;
3723 return 1;
3724}
3725
3726static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3727{
3728 int j, found = 0, c = 0;
3729 if (HACK_ENABLED(NDHACK_NO_STALLS))
3730 return;
3731 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3732 // happens occasionally... cc evicted? Don't bother then
3733 return;
3734 }
3735 for (j = i + 1; j < slen; j++) {
3736 if (dops[j].bt)
3737 break;
3738 if ((found = is_mflohi(j)))
3739 break;
3740 if (dops[j].is_jump) {
3741 // check ds
3742 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3743 j++;
3744 break;
3745 }
3746 }
3747 if (found)
3748 // handle all in multdiv_do_stall()
3749 return;
3750 check_multdiv(i, &c);
3751 assert(c > 0);
3752 assem_debug("; muldiv prepare stall %d\n", c);
3753 host_tempreg_acquire();
3754 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3755 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3756 host_tempreg_release();
3757}
3758
3759static void multdiv_do_stall(int i, const struct regstat *i_regs)
3760{
3761 int j, known_cycles = 0;
3762 u_int reglist = get_host_reglist(i_regs->regmap);
3763 int rtmp = get_reg_temp(i_regs->regmap);
3764 if (rtmp < 0)
3765 rtmp = reglist_find_free(reglist);
3766 if (HACK_ENABLED(NDHACK_NO_STALLS))
3767 return;
3768 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3769 // happens occasionally... cc evicted? Don't bother then
3770 //printf("no cc/rtmp %08x\n", start + i*4);
3771 return;
3772 }
3773 if (!dops[i].bt) {
3774 for (j = i - 1; j >= 0; j--) {
3775 if (dops[j].is_ds) break;
3776 if (check_multdiv(j, &known_cycles))
3777 break;
3778 if (is_mflohi(j))
3779 // already handled by this op
3780 return;
3781 if (dops[j].bt || (j > 0 && cinfo[j - 1].ccadj > cinfo[j].ccadj))
3782 break;
3783 }
3784 j = max(j, 0);
3785 }
3786 if (known_cycles > 0) {
3787 known_cycles -= cinfo[i].ccadj - cinfo[j].ccadj;
3788 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3789 if (known_cycles > 0)
3790 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3791 return;
3792 }
3793 assem_debug("; muldiv stall unresolved\n");
3794 host_tempreg_acquire();
3795 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3796 emit_addimm(rtmp, -cinfo[i].ccadj, rtmp);
3797 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3798 emit_cmpimm(HOST_TEMPREG, 37);
3799 emit_cmovb_reg(rtmp, HOST_CCREG);
3800 //emit_log_gte_stall(i, 0, reglist);
3801 host_tempreg_release();
3802}
3803
3804static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3805{
3806 switch (copr) {
3807 case 1:
3808 case 3:
3809 case 5:
3810 case 8:
3811 case 9:
3812 case 10:
3813 case 11:
3814 emit_readword(&reg_cop2d[copr],tl);
3815 emit_signextend16(tl,tl);
3816 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3817 break;
3818 case 7:
3819 case 16:
3820 case 17:
3821 case 18:
3822 case 19:
3823 emit_readword(&reg_cop2d[copr],tl);
3824 emit_andimm(tl,0xffff,tl);
3825 emit_writeword(tl,&reg_cop2d[copr]);
3826 break;
3827 case 15:
3828 emit_readword(&reg_cop2d[14],tl); // SXY2
3829 emit_writeword(tl,&reg_cop2d[copr]);
3830 break;
3831 case 28:
3832 case 29:
3833 c2op_mfc2_29_assemble(tl,temp);
3834 break;
3835 default:
3836 emit_readword(&reg_cop2d[copr],tl);
3837 break;
3838 }
3839}
3840
3841static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3842{
3843 switch (copr) {
3844 case 15:
3845 emit_readword(&reg_cop2d[13],temp); // SXY1
3846 emit_writeword(sl,&reg_cop2d[copr]);
3847 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3848 emit_readword(&reg_cop2d[14],temp); // SXY2
3849 emit_writeword(sl,&reg_cop2d[14]);
3850 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3851 break;
3852 case 28:
3853 emit_andimm(sl,0x001f,temp);
3854 emit_shlimm(temp,7,temp);
3855 emit_writeword(temp,&reg_cop2d[9]);
3856 emit_andimm(sl,0x03e0,temp);
3857 emit_shlimm(temp,2,temp);
3858 emit_writeword(temp,&reg_cop2d[10]);
3859 emit_andimm(sl,0x7c00,temp);
3860 emit_shrimm(temp,3,temp);
3861 emit_writeword(temp,&reg_cop2d[11]);
3862 emit_writeword(sl,&reg_cop2d[28]);
3863 break;
3864 case 30:
3865 emit_xorsar_imm(sl,sl,31,temp);
3866#if defined(HAVE_ARMV5) || defined(__aarch64__)
3867 emit_clz(temp,temp);
3868#else
3869 emit_movs(temp,HOST_TEMPREG);
3870 emit_movimm(0,temp);
3871 emit_jeq((int)out+4*4);
3872 emit_addpl_imm(temp,1,temp);
3873 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3874 emit_jns((int)out-2*4);
3875#endif
3876 emit_writeword(sl,&reg_cop2d[30]);
3877 emit_writeword(temp,&reg_cop2d[31]);
3878 break;
3879 case 31:
3880 break;
3881 default:
3882 emit_writeword(sl,&reg_cop2d[copr]);
3883 break;
3884 }
3885}
3886
3887static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3888{
3889 int s,tl;
3890 int ar;
3891 int offset;
3892 int memtarget=0,c=0;
3893 void *jaddr2=NULL;
3894 enum stub_type type;
3895 int offset_reg = -1;
3896 int fastio_reg_override = -1;
3897 u_int addr_const = ~0;
3898 u_int reglist=get_host_reglist(i_regs->regmap);
3899 u_int copr=(source[i]>>16)&0x1f;
3900 s=get_reg(i_regs->regmap,dops[i].rs1);
3901 tl=get_reg(i_regs->regmap,FTEMP);
3902 offset=cinfo[i].imm;
3903 assert(tl>=0);
3904
3905 if(i_regs->regmap[HOST_CCREG]==CCREG)
3906 reglist&=~(1<<HOST_CCREG);
3907
3908 // get the address
3909 ar = cinfo[i].addr;
3910 assert(ar >= 0);
3911 if (dops[i].opcode==0x3a) { // SWC2
3912 reglist |= 1<<ar;
3913 }
3914 if (s >= 0) {
3915 c = (i_regs->isconst >> s) & 1;
3916 if (c) {
3917 addr_const = constmap[i][s] + offset;
3918 memtarget = ((signed int)addr_const) < (signed int)(0x80000000 + RAM_SIZE);
3919 }
3920 }
3921
3922 cop2_do_stall_check(0, i, i_regs, reglist);
3923
3924 if (dops[i].opcode==0x3a) { // SWC2
3925 cop2_get_dreg(copr,tl,-1);
3926 type=STOREW_STUB;
3927 }
3928 else
3929 type=LOADW_STUB;
3930
3931 if(c&&!memtarget) {
3932 jaddr2=out;
3933 emit_jmp(0); // inline_readstub/inline_writestub?
3934 }
3935 else {
3936 if(!c) {
3937 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3938 &offset_reg, &fastio_reg_override, ccadj_);
3939 }
3940 else if (ram_offset && memtarget) {
3941 offset_reg = get_ro_reg(i_regs, 0);
3942 }
3943 switch (dops[i].opcode) {
3944 case 0x32: { // LWC2
3945 int a = ar;
3946 if (fastio_reg_override >= 0)
3947 a = fastio_reg_override;
3948 do_load_word(a, tl, offset_reg);
3949 break;
3950 }
3951 case 0x3a: { // SWC2
3952 #ifdef DESTRUCTIVE_SHIFT
3953 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3954 #endif
3955 int a = ar;
3956 if (fastio_reg_override >= 0)
3957 a = fastio_reg_override;
3958 do_store_word(a, 0, tl, offset_reg, 1);
3959 break;
3960 }
3961 default:
3962 assert(0);
3963 }
3964 }
3965 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3966 host_tempreg_release();
3967 if(jaddr2)
3968 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3969 if (dops[i].opcode == 0x3a && (!c || is_ram_addr(addr_const))) // SWC2
3970 do_store_smc_check(i, i_regs, reglist, ar);
3971 if (dops[i].opcode == 0x32) { // LWC2
3972 host_tempreg_acquire();
3973 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3974 host_tempreg_release();
3975 }
3976}
3977
3978static void cop2_assemble(int i, const struct regstat *i_regs)
3979{
3980 u_int copr = (source[i]>>11) & 0x1f;
3981 signed char temp = get_reg_temp(i_regs->regmap);
3982
3983 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3984 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3985 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3986 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3987 reglist = reglist_exclude(reglist, tl, -1);
3988 }
3989 cop2_do_stall_check(0, i, i_regs, reglist);
3990 }
3991 if (dops[i].opcode2==0) { // MFC2
3992 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
3993 if(tl>=0&&dops[i].rt1!=0)
3994 cop2_get_dreg(copr,tl,temp);
3995 }
3996 else if (dops[i].opcode2==4) { // MTC2
3997 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3998 cop2_put_dreg(copr,sl,temp);
3999 }
4000 else if (dops[i].opcode2==2) // CFC2
4001 {
4002 signed char tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4003 if(tl>=0&&dops[i].rt1!=0)
4004 emit_readword(&reg_cop2c[copr],tl);
4005 }
4006 else if (dops[i].opcode2==6) // CTC2
4007 {
4008 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
4009 switch(copr) {
4010 case 4:
4011 case 12:
4012 case 20:
4013 case 26:
4014 case 27:
4015 case 29:
4016 case 30:
4017 emit_signextend16(sl,temp);
4018 break;
4019 case 31:
4020 c2op_ctc2_31_assemble(sl,temp);
4021 break;
4022 default:
4023 temp=sl;
4024 break;
4025 }
4026 emit_writeword(temp,&reg_cop2c[copr]);
4027 assert(sl>=0);
4028 }
4029}
4030
4031static void do_unalignedwritestub(int n)
4032{
4033 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4034 literal_pool(256);
4035 set_jump_target(stubs[n].addr, out);
4036
4037 int i=stubs[n].a;
4038 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4039 int addr=stubs[n].b;
4040 u_int reglist=stubs[n].e;
4041 signed char *i_regmap=i_regs->regmap;
4042 int temp2=get_reg(i_regmap,FTEMP);
4043 int rt;
4044 rt=get_reg(i_regmap,dops[i].rs2);
4045 assert(rt>=0);
4046 assert(addr>=0);
4047 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4048 reglist|=(1<<addr);
4049 reglist&=~(1<<temp2);
4050
4051 // don't bother with it and call write handler
4052 save_regs(reglist);
4053 pass_args(addr,rt);
4054 int cc=get_reg(i_regmap,CCREG);
4055 if(cc<0)
4056 emit_loadreg(CCREG,2);
4057 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4058 emit_movimm(start + i*4,3);
4059 emit_writeword(3,&psxRegs.pc);
4060 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4061 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4062 if(cc<0)
4063 emit_storereg(CCREG,2);
4064 restore_regs(reglist);
4065 emit_jmp(stubs[n].retaddr); // return address
4066}
4067
4068static void do_overflowstub(int n)
4069{
4070 assem_debug("do_overflowstub %x\n", start + (u_int)stubs[n].a * 4);
4071 literal_pool(24);
4072 int i = stubs[n].a;
4073 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4074 int ccadj = stubs[n].d;
4075 set_jump_target(stubs[n].addr, out);
4076 wb_dirtys(regs[i].regmap, regs[i].dirty);
4077 exception_assemble(i, i_regs, ccadj);
4078}
4079
4080static void do_alignmentstub(int n)
4081{
4082 assem_debug("do_alignmentstub %x\n", start + (u_int)stubs[n].a * 4);
4083 literal_pool(24);
4084 int i = stubs[n].a;
4085 struct regstat *i_regs = (struct regstat *)stubs[n].c;
4086 int ccadj = stubs[n].d;
4087 int is_store = dops[i].itype == STORE || dops[i].opcode == 0x3A; // SWC2
4088 int cause = (dops[i].opcode & 3) << 28;
4089 cause |= is_store ? (R3000E_AdES << 2) : (R3000E_AdEL << 2);
4090 set_jump_target(stubs[n].addr, out);
4091 wb_dirtys(regs[i].regmap, regs[i].dirty);
4092 if (stubs[n].b != 1)
4093 emit_mov(stubs[n].b, 1); // faulting address
4094 emit_movimm(cause, 0);
4095 exception_assemble(i, i_regs, ccadj);
4096}
4097
4098#ifndef multdiv_assemble
4099void multdiv_assemble(int i,struct regstat *i_regs)
4100{
4101 printf("Need multdiv_assemble for this architecture.\n");
4102 abort();
4103}
4104#endif
4105
4106static void mov_assemble(int i, const struct regstat *i_regs)
4107{
4108 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4109 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4110 if(dops[i].rt1) {
4111 signed char sl,tl;
4112 tl=get_reg_w(i_regs->regmap, dops[i].rt1);
4113 //assert(tl>=0);
4114 if(tl>=0) {
4115 sl=get_reg(i_regs->regmap,dops[i].rs1);
4116 if(sl>=0) emit_mov(sl,tl);
4117 else emit_loadreg(dops[i].rs1,tl);
4118 }
4119 }
4120 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4121 multdiv_do_stall(i, i_regs);
4122}
4123
4124// call interpreter, exception handler, things that change pc/regs/cycles ...
4125static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4126{
4127 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4128 assert(ccreg==HOST_CCREG);
4129 assert(!is_delayslot);
4130 (void)ccreg;
4131
4132 emit_movimm(pc,3); // Get PC
4133 emit_readword(&last_count,2);
4134 emit_writeword(3,&psxRegs.pc);
4135 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4136 emit_add(2,HOST_CCREG,2);
4137 emit_writeword(2,&psxRegs.cycle);
4138 emit_addimm_ptr(FP,(u_char *)&psxRegs - (u_char *)&dynarec_local,0);
4139 emit_far_call(func);
4140 emit_far_jump(jump_to_new_pc);
4141}
4142
4143static void exception_assemble(int i, const struct regstat *i_regs, int ccadj_)
4144{
4145 // 'break' tends to be littered around to catch things like
4146 // division by 0 and is almost never executed, so don't emit much code here
4147 void *func;
4148 if (dops[i].itype == ALU || dops[i].itype == IMM16)
4149 func = is_delayslot ? jump_overflow_ds : jump_overflow;
4150 else if (dops[i].itype == LOAD || dops[i].itype == STORE)
4151 func = is_delayslot ? jump_addrerror_ds : jump_addrerror;
4152 else if (dops[i].opcode2 == 0x0C)
4153 func = is_delayslot ? jump_syscall_ds : jump_syscall;
4154 else
4155 func = is_delayslot ? jump_break_ds : jump_break;
4156 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) // evicted
4157 emit_loadreg(CCREG, HOST_CCREG);
4158 emit_movimm(start + i*4, 2); // pc
4159 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4160 emit_far_jump(func);
4161}
4162
4163static void hlecall_bad()
4164{
4165 assert(0);
4166}
4167
4168static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4169{
4170 void *hlefunc = hlecall_bad;
4171 uint32_t hleCode = source[i] & 0x03ffffff;
4172 if (hleCode < ARRAY_SIZE(psxHLEt))
4173 hlefunc = psxHLEt[hleCode];
4174
4175 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4176}
4177
4178static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4179{
4180 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4181}
4182
4183static void speculate_mov(int rs,int rt)
4184{
4185 if(rt!=0) {
4186 smrv_strong_next|=1<<rt;
4187 smrv[rt]=smrv[rs];
4188 }
4189}
4190
4191static void speculate_mov_weak(int rs,int rt)
4192{
4193 if(rt!=0) {
4194 smrv_weak_next|=1<<rt;
4195 smrv[rt]=smrv[rs];
4196 }
4197}
4198
4199static void speculate_register_values(int i)
4200{
4201 if(i==0) {
4202 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4203 // gp,sp are likely to stay the same throughout the block
4204 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4205 smrv_weak_next=~smrv_strong_next;
4206 //printf(" llr %08x\n", smrv[4]);
4207 }
4208 smrv_strong=smrv_strong_next;
4209 smrv_weak=smrv_weak_next;
4210 switch(dops[i].itype) {
4211 case ALU:
4212 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4213 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4214 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4215 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4216 else {
4217 smrv_strong_next&=~(1<<dops[i].rt1);
4218 smrv_weak_next&=~(1<<dops[i].rt1);
4219 }
4220 break;
4221 case SHIFTIMM:
4222 smrv_strong_next&=~(1<<dops[i].rt1);
4223 smrv_weak_next&=~(1<<dops[i].rt1);
4224 // fallthrough
4225 case IMM16:
4226 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
4227 int hr = get_reg_w(regs[i].regmap, dops[i].rt1);
4228 u_int value;
4229 if(hr>=0) {
4230 if(get_final_value(hr,i,&value))
4231 smrv[dops[i].rt1]=value;
4232 else smrv[dops[i].rt1]=constmap[i][hr];
4233 smrv_strong_next|=1<<dops[i].rt1;
4234 }
4235 }
4236 else {
4237 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4238 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4239 }
4240 break;
4241 case LOAD:
4242 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4243 // special case for BIOS
4244 smrv[dops[i].rt1]=0xa0000000;
4245 smrv_strong_next|=1<<dops[i].rt1;
4246 break;
4247 }
4248 // fallthrough
4249 case SHIFT:
4250 case LOADLR:
4251 case MOV:
4252 smrv_strong_next&=~(1<<dops[i].rt1);
4253 smrv_weak_next&=~(1<<dops[i].rt1);
4254 break;
4255 case COP0:
4256 case COP2:
4257 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4258 smrv_strong_next&=~(1<<dops[i].rt1);
4259 smrv_weak_next&=~(1<<dops[i].rt1);
4260 }
4261 break;
4262 case C2LS:
4263 if (dops[i].opcode==0x32) { // LWC2
4264 smrv_strong_next&=~(1<<dops[i].rt1);
4265 smrv_weak_next&=~(1<<dops[i].rt1);
4266 }
4267 break;
4268 }
4269#if 0
4270 int r=4;
4271 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4272 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4273#endif
4274}
4275
4276static void ujump_assemble(int i, const struct regstat *i_regs);
4277static void rjump_assemble(int i, const struct regstat *i_regs);
4278static void cjump_assemble(int i, const struct regstat *i_regs);
4279static void sjump_assemble(int i, const struct regstat *i_regs);
4280
4281static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4282{
4283 int ds = 0;
4284 switch (dops[i].itype) {
4285 case ALU:
4286 alu_assemble(i, i_regs, ccadj_);
4287 break;
4288 case IMM16:
4289 imm16_assemble(i, i_regs, ccadj_);
4290 break;
4291 case SHIFT:
4292 shift_assemble(i, i_regs);
4293 break;
4294 case SHIFTIMM:
4295 shiftimm_assemble(i, i_regs);
4296 break;
4297 case LOAD:
4298 load_assemble(i, i_regs, ccadj_);
4299 break;
4300 case LOADLR:
4301 loadlr_assemble(i, i_regs, ccadj_);
4302 break;
4303 case STORE:
4304 store_assemble(i, i_regs, ccadj_);
4305 break;
4306 case STORELR:
4307 storelr_assemble(i, i_regs, ccadj_);
4308 break;
4309 case COP0:
4310 cop0_assemble(i, i_regs, ccadj_);
4311 break;
4312 case RFE:
4313 rfe_assemble(i, i_regs);
4314 break;
4315 case COP2:
4316 cop2_assemble(i, i_regs);
4317 break;
4318 case C2LS:
4319 c2ls_assemble(i, i_regs, ccadj_);
4320 break;
4321 case C2OP:
4322 c2op_assemble(i, i_regs);
4323 break;
4324 case MULTDIV:
4325 multdiv_assemble(i, i_regs);
4326 multdiv_prepare_stall(i, i_regs, ccadj_);
4327 break;
4328 case MOV:
4329 mov_assemble(i, i_regs);
4330 break;
4331 case SYSCALL:
4332 exception_assemble(i, i_regs, ccadj_);
4333 break;
4334 case HLECALL:
4335 hlecall_assemble(i, i_regs, ccadj_);
4336 break;
4337 case INTCALL:
4338 intcall_assemble(i, i_regs, ccadj_);
4339 break;
4340 case UJUMP:
4341 ujump_assemble(i, i_regs);
4342 ds = 1;
4343 break;
4344 case RJUMP:
4345 rjump_assemble(i, i_regs);
4346 ds = 1;
4347 break;
4348 case CJUMP:
4349 cjump_assemble(i, i_regs);
4350 ds = 1;
4351 break;
4352 case SJUMP:
4353 sjump_assemble(i, i_regs);
4354 ds = 1;
4355 break;
4356 case NOP:
4357 case OTHER:
4358 // not handled, just skip
4359 break;
4360 default:
4361 assert(0);
4362 }
4363 return ds;
4364}
4365
4366static void ds_assemble(int i, const struct regstat *i_regs)
4367{
4368 speculate_register_values(i);
4369 is_delayslot = 1;
4370 switch (dops[i].itype) {
4371 case SYSCALL:
4372 case HLECALL:
4373 case INTCALL:
4374 case UJUMP:
4375 case RJUMP:
4376 case CJUMP:
4377 case SJUMP:
4378 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4379 break;
4380 default:
4381 assemble(i, i_regs, cinfo[i].ccadj);
4382 }
4383 is_delayslot = 0;
4384}
4385
4386// Is the branch target a valid internal jump?
4387static int internal_branch(int addr)
4388{
4389 if(addr&1) return 0; // Indirect (register) jump
4390 if(addr>=start && addr<start+slen*4-4)
4391 {
4392 return 1;
4393 }
4394 return 0;
4395}
4396
4397static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4398{
4399 int hr;
4400 for(hr=0;hr<HOST_REGS;hr++) {
4401 if(hr!=EXCLUDE_REG) {
4402 if(pre[hr]!=entry[hr]) {
4403 if(pre[hr]>=0) {
4404 if((dirty>>hr)&1) {
4405 if(get_reg(entry,pre[hr])<0) {
4406 assert(pre[hr]<64);
4407 if(!((u>>pre[hr])&1))
4408 emit_storereg(pre[hr],hr);
4409 }
4410 }
4411 }
4412 }
4413 }
4414 }
4415 // Move from one register to another (no writeback)
4416 for(hr=0;hr<HOST_REGS;hr++) {
4417 if(hr!=EXCLUDE_REG) {
4418 if(pre[hr]!=entry[hr]) {
4419 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4420 int nr;
4421 if((nr=get_reg(entry,pre[hr]))>=0) {
4422 emit_mov(hr,nr);
4423 }
4424 }
4425 }
4426 }
4427 }
4428}
4429
4430// Load the specified registers
4431// This only loads the registers given as arguments because
4432// we don't want to load things that will be overwritten
4433static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4434{
4435 int hr = get_reg(regmap, rs);
4436 if (hr >= 0 && entry[hr] != regmap[hr])
4437 emit_loadreg(regmap[hr], hr);
4438}
4439
4440static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4441{
4442 load_reg(entry, regmap, rs1);
4443 if (rs1 != rs2)
4444 load_reg(entry, regmap, rs2);
4445}
4446
4447// Load registers prior to the start of a loop
4448// so that they are not loaded within the loop
4449static void loop_preload(signed char pre[],signed char entry[])
4450{
4451 int hr;
4452 for (hr = 0; hr < HOST_REGS; hr++) {
4453 int r = entry[hr];
4454 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4455 assem_debug("loop preload:\n");
4456 if (r < TEMPREG)
4457 emit_loadreg(r, hr);
4458 }
4459 }
4460}
4461
4462// Generate address for load/store instruction
4463// goes to AGEN (or temp) for writes, FTEMP for LOADLR and cop1/2 loads
4464// AGEN is assigned by pass5b_preallocate2
4465static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4466{
4467 if (dops[i].is_load || dops[i].is_store) {
4468 int ra = -1;
4469 int agr = AGEN1 + (i&1);
4470 if(dops[i].itype==LOAD) {
4471 if (!dops[i].may_except)
4472 ra = get_reg_w(i_regs->regmap, dops[i].rt1); // reuse dest for agen
4473 if (ra < 0)
4474 ra = get_reg_temp(i_regs->regmap);
4475 }
4476 if(dops[i].itype==LOADLR) {
4477 ra=get_reg(i_regs->regmap,FTEMP);
4478 }
4479 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4480 ra=get_reg(i_regs->regmap,agr);
4481 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4482 }
4483 if(dops[i].itype==C2LS) {
4484 if (dops[i].opcode == 0x32) // LWC2
4485 ra=get_reg(i_regs->regmap,FTEMP);
4486 else { // SWC2
4487 ra=get_reg(i_regs->regmap,agr);
4488 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4489 }
4490 }
4491 int rs = get_reg(i_regs->regmap, dops[i].rs1);
4492 //if(ra>=0)
4493 {
4494 int offset = cinfo[i].imm;
4495 int add_offset = offset != 0;
4496 int c = rs >= 0 && ((i_regs->wasconst >> rs) & 1);
4497 if(dops[i].rs1==0) {
4498 // Using r0 as a base address
4499 assert(ra >= 0);
4500 if(!entry||entry[ra]!=agr) {
4501 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4502 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4503 }else{
4504 emit_movimm(offset,ra);
4505 }
4506 } // else did it in the previous cycle
4507 cinfo[i].addr = ra;
4508 add_offset = 0;
4509 }
4510 else if (rs < 0) {
4511 assert(ra >= 0);
4512 if (!entry || entry[ra] != dops[i].rs1)
4513 emit_loadreg(dops[i].rs1, ra);
4514 cinfo[i].addr = ra;
4515 //if(!entry||entry[ra]!=dops[i].rs1)
4516 // printf("poor load scheduling!\n");
4517 }
4518 else if(c) {
4519 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4520 assert(ra >= 0);
4521 if(!entry||entry[ra]!=agr) {
4522 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4523 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4524 }else{
4525 emit_movimm(constmap[i][rs]+offset,ra);
4526 regs[i].loadedconst|=1<<ra;
4527 }
4528 } // else did it in the previous cycle
4529 cinfo[i].addr = ra;
4530 }
4531 else // else load_consts already did it
4532 cinfo[i].addr = rs;
4533 add_offset = 0;
4534 }
4535 else
4536 cinfo[i].addr = rs;
4537 if (add_offset) {
4538 assert(ra >= 0);
4539 if(rs>=0) {
4540 emit_addimm(rs,offset,ra);
4541 }else{
4542 emit_addimm(ra,offset,ra);
4543 }
4544 cinfo[i].addr = ra;
4545 }
4546 }
4547 assert(cinfo[i].addr >= 0);
4548 }
4549 // Preload constants for next instruction
4550 if (dops[i+1].is_load || dops[i+1].is_store) {
4551 int agr,ra;
4552 // Actual address
4553 agr=AGEN1+((i+1)&1);
4554 ra=get_reg(i_regs->regmap,agr);
4555 if(ra>=0) {
4556 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4557 int offset=cinfo[i+1].imm;
4558 int c=(regs[i+1].wasconst>>rs)&1;
4559 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4560 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4561 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4562 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4563 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4564 }else{
4565 emit_movimm(constmap[i+1][rs]+offset,ra);
4566 regs[i+1].loadedconst|=1<<ra;
4567 }
4568 }
4569 else if(dops[i+1].rs1==0) {
4570 // Using r0 as a base address
4571 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4572 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4573 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4574 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4575 }else{
4576 emit_movimm(offset,ra);
4577 }
4578 }
4579 }
4580 }
4581}
4582
4583static int get_final_value(int hr, int i, u_int *value)
4584{
4585 int reg=regs[i].regmap[hr];
4586 while(i<slen-1) {
4587 if(regs[i+1].regmap[hr]!=reg) break;
4588 if(!((regs[i+1].isconst>>hr)&1)) break;
4589 if(dops[i+1].bt) break;
4590 i++;
4591 }
4592 if(i<slen-1) {
4593 if (dops[i].is_jump) {
4594 *value=constmap[i][hr];
4595 return 1;
4596 }
4597 if(!dops[i+1].bt) {
4598 if (dops[i+1].is_jump) {
4599 // Load in delay slot, out-of-order execution
4600 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4601 {
4602 // Precompute load address
4603 *value=constmap[i][hr]+cinfo[i+2].imm;
4604 return 1;
4605 }
4606 }
4607 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4608 {
4609 // Precompute load address
4610 *value=constmap[i][hr]+cinfo[i+1].imm;
4611 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],cinfo[i+1].imm);
4612 return 1;
4613 }
4614 }
4615 }
4616 *value=constmap[i][hr];
4617 //printf("c=%lx\n",(long)constmap[i][hr]);
4618 if(i==slen-1) return 1;
4619 assert(reg < 64);
4620 return !((unneeded_reg[i+1]>>reg)&1);
4621}
4622
4623// Load registers with known constants
4624static void load_consts(signed char pre[],signed char regmap[],int i)
4625{
4626 int hr,hr2;
4627 // propagate loaded constant flags
4628 if(i==0||dops[i].bt)
4629 regs[i].loadedconst=0;
4630 else {
4631 for (hr = 0; hr < HOST_REGS; hr++) {
4632 if (hr == EXCLUDE_REG || regmap[hr] < 0 || pre[hr] != regmap[hr])
4633 continue;
4634 if ((((regs[i-1].isconst & regs[i-1].loadedconst) >> hr) & 1)
4635 && regmap[hr] == regs[i-1].regmap[hr])
4636 {
4637 regs[i].loadedconst |= 1u << hr;
4638 }
4639 }
4640 }
4641 // Load 32-bit regs
4642 for(hr=0;hr<HOST_REGS;hr++) {
4643 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4644 //if(entry[hr]!=regmap[hr]) {
4645 if(!((regs[i].loadedconst>>hr)&1)) {
4646 assert(regmap[hr]<64);
4647 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4648 u_int value, similar=0;
4649 if(get_final_value(hr,i,&value)) {
4650 // see if some other register has similar value
4651 for(hr2=0;hr2<HOST_REGS;hr2++) {
4652 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4653 if(is_similar_value(value,constmap[i][hr2])) {
4654 similar=1;
4655 break;
4656 }
4657 }
4658 }
4659 if(similar) {
4660 u_int value2;
4661 if(get_final_value(hr2,i,&value2)) // is this needed?
4662 emit_movimm_from(value2,hr2,value,hr);
4663 else
4664 emit_movimm(value,hr);
4665 }
4666 else if(value==0) {
4667 emit_zeroreg(hr);
4668 }
4669 else {
4670 emit_movimm(value,hr);
4671 }
4672 }
4673 regs[i].loadedconst|=1<<hr;
4674 }
4675 }
4676 }
4677 }
4678}
4679
4680static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4681{
4682 int hr;
4683 // Load 32-bit regs
4684 for(hr=0;hr<HOST_REGS;hr++) {
4685 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4686 assert(regmap[hr] < 64);
4687 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4688 int value=constmap[i][hr];
4689 if(value==0) {
4690 emit_zeroreg(hr);
4691 }
4692 else {
4693 emit_movimm(value,hr);
4694 }
4695 }
4696 }
4697 }
4698}
4699
4700// Write out all dirty registers (except cycle count)
4701#ifndef wb_dirtys
4702static void wb_dirtys(const signed char i_regmap[], u_int i_dirty)
4703{
4704 int hr;
4705 for(hr=0;hr<HOST_REGS;hr++) {
4706 if(hr!=EXCLUDE_REG) {
4707 if(i_regmap[hr]>0) {
4708 if(i_regmap[hr]!=CCREG) {
4709 if((i_dirty>>hr)&1) {
4710 assert(i_regmap[hr]<64);
4711 emit_storereg(i_regmap[hr],hr);
4712 }
4713 }
4714 }
4715 }
4716 }
4717}
4718#endif
4719
4720// Write out dirty registers that we need to reload (pair with load_needed_regs)
4721// This writes the registers not written by store_regs_bt
4722static void wb_needed_dirtys(const signed char i_regmap[], u_int i_dirty, int addr)
4723{
4724 int hr;
4725 int t=(addr-start)>>2;
4726 for(hr=0;hr<HOST_REGS;hr++) {
4727 if(hr!=EXCLUDE_REG) {
4728 if(i_regmap[hr]>0) {
4729 if(i_regmap[hr]!=CCREG) {
4730 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4731 if((i_dirty>>hr)&1) {
4732 assert(i_regmap[hr]<64);
4733 emit_storereg(i_regmap[hr],hr);
4734 }
4735 }
4736 }
4737 }
4738 }
4739 }
4740}
4741
4742// Load all registers (except cycle count)
4743#ifndef load_all_regs
4744static void load_all_regs(const signed char i_regmap[])
4745{
4746 int hr;
4747 for(hr=0;hr<HOST_REGS;hr++) {
4748 if(hr!=EXCLUDE_REG) {
4749 if(i_regmap[hr]==0) {
4750 emit_zeroreg(hr);
4751 }
4752 else
4753 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4754 {
4755 emit_loadreg(i_regmap[hr],hr);
4756 }
4757 }
4758 }
4759}
4760#endif
4761
4762// Load all current registers also needed by next instruction
4763static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4764{
4765 signed char regmap_sel[HOST_REGS];
4766 int hr;
4767 for (hr = 0; hr < HOST_REGS; hr++) {
4768 regmap_sel[hr] = -1;
4769 if (hr != EXCLUDE_REG)
4770 if (next_regmap[hr] == i_regmap[hr] || get_reg(next_regmap, i_regmap[hr]) >= 0)
4771 regmap_sel[hr] = i_regmap[hr];
4772 }
4773 load_all_regs(regmap_sel);
4774}
4775
4776// Load all regs, storing cycle count if necessary
4777static void load_regs_entry(int t)
4778{
4779 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4780 else if(cinfo[t].ccadj) emit_addimm(HOST_CCREG,-cinfo[t].ccadj,HOST_CCREG);
4781 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4782 emit_storereg(CCREG,HOST_CCREG);
4783 }
4784 load_all_regs(regs[t].regmap_entry);
4785}
4786
4787// Store dirty registers prior to branch
4788static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4789{
4790 if(internal_branch(addr))
4791 {
4792 int t=(addr-start)>>2;
4793 int hr;
4794 for(hr=0;hr<HOST_REGS;hr++) {
4795 if(hr!=EXCLUDE_REG) {
4796 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4797 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4798 if((i_dirty>>hr)&1) {
4799 assert(i_regmap[hr]<64);
4800 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4801 emit_storereg(i_regmap[hr],hr);
4802 }
4803 }
4804 }
4805 }
4806 }
4807 }
4808 else
4809 {
4810 // Branch out of this block, write out all dirty regs
4811 wb_dirtys(i_regmap,i_dirty);
4812 }
4813}
4814
4815// Load all needed registers for branch target
4816static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4817{
4818 //if(addr>=start && addr<(start+slen*4))
4819 if(internal_branch(addr))
4820 {
4821 int t=(addr-start)>>2;
4822 int hr;
4823 // Store the cycle count before loading something else
4824 if(i_regmap[HOST_CCREG]!=CCREG) {
4825 assert(i_regmap[HOST_CCREG]==-1);
4826 }
4827 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4828 emit_storereg(CCREG,HOST_CCREG);
4829 }
4830 // Load 32-bit regs
4831 for(hr=0;hr<HOST_REGS;hr++) {
4832 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4833 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4834 if(regs[t].regmap_entry[hr]==0) {
4835 emit_zeroreg(hr);
4836 }
4837 else if(regs[t].regmap_entry[hr]!=CCREG)
4838 {
4839 emit_loadreg(regs[t].regmap_entry[hr],hr);
4840 }
4841 }
4842 }
4843 }
4844 }
4845}
4846
4847static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4848{
4849 if(addr>=start && addr<start+slen*4-4)
4850 {
4851 int t=(addr-start)>>2;
4852 int hr;
4853 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4854 for(hr=0;hr<HOST_REGS;hr++)
4855 {
4856 if(hr!=EXCLUDE_REG)
4857 {
4858 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4859 {
4860 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4861 {
4862 return 0;
4863 }
4864 else
4865 if((i_dirty>>hr)&1)
4866 {
4867 if(i_regmap[hr]<TEMPREG)
4868 {
4869 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4870 return 0;
4871 }
4872 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4873 {
4874 assert(0);
4875 }
4876 }
4877 }
4878 else // Same register but is it 32-bit or dirty?
4879 if(i_regmap[hr]>=0)
4880 {
4881 if(!((regs[t].dirty>>hr)&1))
4882 {
4883 if((i_dirty>>hr)&1)
4884 {
4885 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4886 {
4887 //printf("%x: dirty no match\n",addr);
4888 return 0;
4889 }
4890 }
4891 }
4892 }
4893 }
4894 }
4895 // Delay slots are not valid branch targets
4896 //if(t>0&&(dops[t-1].is_jump) return 0;
4897 // Delay slots require additional processing, so do not match
4898 if(dops[t].is_ds) return 0;
4899 }
4900 else
4901 {
4902 int hr;
4903 for(hr=0;hr<HOST_REGS;hr++)
4904 {
4905 if(hr!=EXCLUDE_REG)
4906 {
4907 if(i_regmap[hr]>=0)
4908 {
4909 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4910 {
4911 if((i_dirty>>hr)&1)
4912 {
4913 return 0;
4914 }
4915 }
4916 }
4917 }
4918 }
4919 }
4920 return 1;
4921}
4922
4923#ifdef DRC_DBG
4924static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4925{
4926 extern void do_insn_cmp();
4927 //extern int cycle;
4928 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4929 reglist |= get_host_reglist(regs[i].regmap_entry);
4930 reglist &= DRC_DBG_REGMASK;
4931
4932 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4933 save_regs(reglist);
4934 // write out changed consts to match the interpreter
4935 if (i > 0 && !dops[i].bt) {
4936 for (hr = 0; hr < HOST_REGS; hr++) {
4937 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4938 if (hr == EXCLUDE_REG || reg <= 0)
4939 continue;
4940 if (!((regs[i-1].isconst >> hr) & 1))
4941 continue;
4942 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4943 continue;
4944 emit_movimm(constmap[i-1][hr],0);
4945 emit_storereg(reg, 0);
4946 }
4947 }
4948 if (dops[i].opcode == 0x0f) { // LUI
4949 emit_movimm(cinfo[i].imm << 16, 0);
4950 emit_storereg(dops[i].rt1, 0);
4951 }
4952 emit_movimm(start+i*4,0);
4953 emit_writeword(0,&pcaddr);
4954 int cc = get_reg(regs[i].regmap_entry, CCREG);
4955 if (cc < 0)
4956 emit_loadreg(CCREG, cc = 0);
4957 emit_addimm(cc, ccadj_, 0);
4958 emit_writeword(0, &psxRegs.cycle);
4959 emit_far_call(do_insn_cmp);
4960 //emit_readword(&cycle,0);
4961 //emit_addimm(0,2,0);
4962 //emit_writeword(0,&cycle);
4963 (void)get_reg2;
4964 restore_regs(reglist);
4965 assem_debug("\\\\do_insn_cmp\n");
4966}
4967static void drc_dbg_emit_wb_dirtys(int i, const struct regstat *i_regs)
4968{
4969 // write-out non-consts, consts are likely different because of get_final_value()
4970 if (i_regs->dirty & ~i_regs->loadedconst) {
4971 assem_debug("/ drc_dbg_wb\n");
4972 wb_dirtys(i_regs->regmap, i_regs->dirty & ~i_regs->loadedconst);
4973 assem_debug("\\ drc_dbg_wb\n");
4974 }
4975}
4976#else
4977#define drc_dbg_emit_do_cmp(x,y)
4978#define drc_dbg_emit_wb_dirtys(x,y)
4979#endif
4980
4981// Used when a branch jumps into the delay slot of another branch
4982static void ds_assemble_entry(int i)
4983{
4984 int t = (cinfo[i].ba - start) >> 2;
4985 int ccadj_ = -CLOCK_ADJUST(1);
4986 if (!instr_addr[t])
4987 instr_addr[t] = out;
4988 assem_debug("Assemble delay slot at %x\n",cinfo[i].ba);
4989 assem_debug("<->\n");
4990 drc_dbg_emit_do_cmp(t, ccadj_);
4991 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4992 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4993 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4994 address_generation(t,&regs[t],regs[t].regmap_entry);
4995 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4996 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4997 if (dops[t].is_store)
4998 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
4999 is_delayslot=0;
5000 switch (dops[t].itype) {
5001 case SYSCALL:
5002 case HLECALL:
5003 case INTCALL:
5004 case UJUMP:
5005 case RJUMP:
5006 case CJUMP:
5007 case SJUMP:
5008 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
5009 break;
5010 default:
5011 assemble(t, &regs[t], ccadj_);
5012 }
5013 store_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5014 load_regs_bt(regs[t].regmap,regs[t].dirty,cinfo[i].ba+4);
5015 if(internal_branch(cinfo[i].ba+4))
5016 assem_debug("branch: internal\n");
5017 else
5018 assem_debug("branch: external\n");
5019 assert(internal_branch(cinfo[i].ba+4));
5020 add_to_linker(out,cinfo[i].ba+4,internal_branch(cinfo[i].ba+4));
5021 emit_jmp(0);
5022}
5023
5024// Load 2 immediates optimizing for small code size
5025static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
5026{
5027 emit_movimm(imm1,rt1);
5028 emit_movimm_from(imm1,rt1,imm2,rt2);
5029}
5030
5031static void do_cc(int i, const signed char i_regmap[], int *adj,
5032 int addr, int taken, int invert)
5033{
5034 int count, count_plus2;
5035 void *jaddr;
5036 void *idle=NULL;
5037 int t=0;
5038 if(dops[i].itype==RJUMP)
5039 {
5040 *adj=0;
5041 }
5042 //if(cinfo[i].ba>=start && cinfo[i].ba<(start+slen*4))
5043 if(internal_branch(cinfo[i].ba))
5044 {
5045 t=(cinfo[i].ba-start)>>2;
5046 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
5047 else *adj=cinfo[t].ccadj;
5048 }
5049 else
5050 {
5051 *adj=0;
5052 }
5053 count = cinfo[i].ccadj;
5054 count_plus2 = count + CLOCK_ADJUST(2);
5055 if(taken==TAKEN && i==(cinfo[i].ba-start)>>2 && source[i+1]==0) {
5056 // Idle loop
5057 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5058 idle=out;
5059 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5060 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5061 jaddr=out;
5062 emit_jmp(0);
5063 }
5064 else if(*adj==0||invert) {
5065 int cycles = count_plus2;
5066 // faster loop HACK
5067#if 0
5068 if (t&&*adj) {
5069 int rel=t-i;
5070 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5071 cycles=*adj+count+2-*adj;
5072 }
5073#endif
5074 emit_addimm_and_set_flags(cycles, HOST_CCREG);
5075 jaddr = out;
5076 emit_jns(0);
5077 }
5078 else
5079 {
5080 emit_cmpimm(HOST_CCREG, -count_plus2);
5081 jaddr = out;
5082 emit_jns(0);
5083 }
5084 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
5085}
5086
5087static void do_ccstub(int n)
5088{
5089 literal_pool(256);
5090 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
5091 set_jump_target(stubs[n].addr, out);
5092 int i=stubs[n].b;
5093 if (stubs[n].d != TAKEN) {
5094 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5095 }
5096 else {
5097 if(internal_branch(cinfo[i].ba))
5098 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5099 }
5100 if(stubs[n].c!=-1)
5101 {
5102 // Save PC as return address
5103 emit_movimm(stubs[n].c,0);
5104 emit_writeword(0,&pcaddr);
5105 }
5106 else
5107 {
5108 // Return address depends on which way the branch goes
5109 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5110 {
5111 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5112 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5113 if(dops[i].rs1==0)
5114 {
5115 s1l=s2l;
5116 s2l=-1;
5117 }
5118 else if(dops[i].rs2==0)
5119 {
5120 s2l=-1;
5121 }
5122 assert(s1l>=0);
5123 #ifdef DESTRUCTIVE_WRITEBACK
5124 if(dops[i].rs1) {
5125 if((branch_regs[i].dirty>>s1l)&&1)
5126 emit_loadreg(dops[i].rs1,s1l);
5127 }
5128 else {
5129 if((branch_regs[i].dirty>>s1l)&1)
5130 emit_loadreg(dops[i].rs2,s1l);
5131 }
5132 if(s2l>=0)
5133 if((branch_regs[i].dirty>>s2l)&1)
5134 emit_loadreg(dops[i].rs2,s2l);
5135 #endif
5136 int hr=0;
5137 int addr=-1,alt=-1,ntaddr=-1;
5138 while(hr<HOST_REGS)
5139 {
5140 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5141 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5142 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5143 {
5144 addr=hr++;break;
5145 }
5146 hr++;
5147 }
5148 while(hr<HOST_REGS)
5149 {
5150 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5151 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5152 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5153 {
5154 alt=hr++;break;
5155 }
5156 hr++;
5157 }
5158 if ((dops[i].opcode & 0x3e) == 6) // BLEZ/BGTZ needs another register
5159 {
5160 while(hr<HOST_REGS)
5161 {
5162 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5163 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5164 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5165 {
5166 ntaddr=hr;break;
5167 }
5168 hr++;
5169 }
5170 assert(hr<HOST_REGS);
5171 }
5172 if (dops[i].opcode == 4) // BEQ
5173 {
5174 #ifdef HAVE_CMOV_IMM
5175 if(s2l>=0) emit_cmp(s1l,s2l);
5176 else emit_test(s1l,s1l);
5177 emit_cmov2imm_e_ne_compact(cinfo[i].ba,start+i*4+8,addr);
5178 #else
5179 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,alt);
5180 if(s2l>=0) emit_cmp(s1l,s2l);
5181 else emit_test(s1l,s1l);
5182 emit_cmovne_reg(alt,addr);
5183 #endif
5184 }
5185 else if (dops[i].opcode == 5) // BNE
5186 {
5187 #ifdef HAVE_CMOV_IMM
5188 if(s2l>=0) emit_cmp(s1l,s2l);
5189 else emit_test(s1l,s1l);
5190 emit_cmov2imm_e_ne_compact(start+i*4+8,cinfo[i].ba,addr);
5191 #else
5192 emit_mov2imm_compact(start+i*4+8,addr,cinfo[i].ba,alt);
5193 if(s2l>=0) emit_cmp(s1l,s2l);
5194 else emit_test(s1l,s1l);
5195 emit_cmovne_reg(alt,addr);
5196 #endif
5197 }
5198 else if (dops[i].opcode == 6) // BLEZ
5199 {
5200 //emit_movimm(cinfo[i].ba,alt);
5201 //emit_movimm(start+i*4+8,addr);
5202 emit_mov2imm_compact(cinfo[i].ba,alt,start+i*4+8,addr);
5203 emit_cmpimm(s1l,1);
5204 emit_cmovl_reg(alt,addr);
5205 }
5206 else if (dops[i].opcode == 7) // BGTZ
5207 {
5208 //emit_movimm(cinfo[i].ba,addr);
5209 //emit_movimm(start+i*4+8,ntaddr);
5210 emit_mov2imm_compact(cinfo[i].ba,addr,start+i*4+8,ntaddr);
5211 emit_cmpimm(s1l,1);
5212 emit_cmovl_reg(ntaddr,addr);
5213 }
5214 else if (dops[i].itype == SJUMP) // BLTZ/BGEZ
5215 {
5216 //emit_movimm(cinfo[i].ba,alt);
5217 //emit_movimm(start+i*4+8,addr);
5218 if (dops[i].rs1) {
5219 emit_mov2imm_compact(cinfo[i].ba,
5220 (dops[i].opcode2 & 1) ? addr : alt, start + i*4 + 8,
5221 (dops[i].opcode2 & 1) ? alt : addr);
5222 emit_test(s1l,s1l);
5223 emit_cmovs_reg(alt,addr);
5224 }
5225 else
5226 emit_movimm((dops[i].opcode2 & 1) ? cinfo[i].ba : start + i*4 + 8, addr);
5227 }
5228 emit_writeword(addr, &pcaddr);
5229 }
5230 else
5231 if(dops[i].itype==RJUMP)
5232 {
5233 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5234 if (ds_writes_rjump_rs(i)) {
5235 r=get_reg(branch_regs[i].regmap,RTEMP);
5236 }
5237 emit_writeword(r,&pcaddr);
5238 }
5239 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5240 }
5241 // Update cycle count
5242 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5243 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5244 emit_far_call(cc_interrupt);
5245 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5246 if(stubs[n].d==TAKEN) {
5247 if(internal_branch(cinfo[i].ba))
5248 load_needed_regs(branch_regs[i].regmap,regs[(cinfo[i].ba-start)>>2].regmap_entry);
5249 else if(dops[i].itype==RJUMP) {
5250 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5251 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5252 else
5253 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5254 }
5255 }else if(stubs[n].d==NOTTAKEN) {
5256 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5257 else load_all_regs(branch_regs[i].regmap);
5258 }else{
5259 load_all_regs(branch_regs[i].regmap);
5260 }
5261 if (stubs[n].retaddr)
5262 emit_jmp(stubs[n].retaddr);
5263 else
5264 do_jump_vaddr(stubs[n].e);
5265}
5266
5267static void add_to_linker(void *addr, u_int target, int is_internal)
5268{
5269 assert(linkcount < ARRAY_SIZE(link_addr));
5270 link_addr[linkcount].addr = addr;
5271 link_addr[linkcount].target = target;
5272 link_addr[linkcount].internal = is_internal;
5273 linkcount++;
5274}
5275
5276static void ujump_assemble_write_ra(int i)
5277{
5278 int rt;
5279 unsigned int return_address;
5280 rt=get_reg(branch_regs[i].regmap,31);
5281 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5282 //assert(rt>=0);
5283 return_address=start+i*4+8;
5284 if(rt>=0) {
5285 #ifdef USE_MINI_HT
5286 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5287 int temp=-1; // note: must be ds-safe
5288 #ifdef HOST_TEMPREG
5289 temp=HOST_TEMPREG;
5290 #endif
5291 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5292 else emit_movimm(return_address,rt);
5293 }
5294 else
5295 #endif
5296 {
5297 #ifdef REG_PREFETCH
5298 if(temp>=0)
5299 {
5300 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5301 }
5302 #endif
5303 if (!((regs[i].loadedconst >> rt) & 1))
5304 emit_movimm(return_address, rt); // PC into link register
5305 #ifdef IMM_PREFETCH
5306 emit_prefetch(hash_table_get(return_address));
5307 #endif
5308 }
5309 }
5310}
5311
5312static void ujump_assemble(int i, const struct regstat *i_regs)
5313{
5314 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5315 address_generation(i+1,i_regs,regs[i].regmap_entry);
5316 #ifdef REG_PREFETCH
5317 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5318 if(dops[i].rt1==31&&temp>=0)
5319 {
5320 signed char *i_regmap=i_regs->regmap;
5321 int return_address=start+i*4+8;
5322 if(get_reg(branch_regs[i].regmap,31)>0)
5323 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5324 }
5325 #endif
5326 if (dops[i].rt1 == 31)
5327 ujump_assemble_write_ra(i); // writeback ra for DS
5328 ds_assemble(i+1,i_regs);
5329 uint64_t bc_unneeded=branch_regs[i].u;
5330 bc_unneeded|=1|(1LL<<dops[i].rt1);
5331 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5332 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5333 int cc,adj;
5334 cc=get_reg(branch_regs[i].regmap,CCREG);
5335 assert(cc==HOST_CCREG);
5336 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5337 #ifdef REG_PREFETCH
5338 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5339 #endif
5340 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5341 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5342 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5343 if(internal_branch(cinfo[i].ba))
5344 assem_debug("branch: internal\n");
5345 else
5346 assem_debug("branch: external\n");
5347 if (internal_branch(cinfo[i].ba) && dops[(cinfo[i].ba-start)>>2].is_ds) {
5348 ds_assemble_entry(i);
5349 }
5350 else {
5351 add_to_linker(out,cinfo[i].ba,internal_branch(cinfo[i].ba));
5352 emit_jmp(0);
5353 }
5354}
5355
5356static void rjump_assemble_write_ra(int i)
5357{
5358 int rt,return_address;
5359 rt=get_reg_w(branch_regs[i].regmap, dops[i].rt1);
5360 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5361 assert(rt>=0);
5362 return_address=start+i*4+8;
5363 #ifdef REG_PREFETCH
5364 if(temp>=0)
5365 {
5366 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5367 }
5368 #endif
5369 if (!((regs[i].loadedconst >> rt) & 1))
5370 emit_movimm(return_address, rt); // PC into link register
5371 #ifdef IMM_PREFETCH
5372 emit_prefetch(hash_table_get(return_address));
5373 #endif
5374}
5375
5376static void rjump_assemble(int i, const struct regstat *i_regs)
5377{
5378 int temp;
5379 int rs,cc;
5380 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5381 assert(rs>=0);
5382 if (ds_writes_rjump_rs(i)) {
5383 // Delay slot abuse, make a copy of the branch address register
5384 temp=get_reg(branch_regs[i].regmap,RTEMP);
5385 assert(temp>=0);
5386 assert(regs[i].regmap[temp]==RTEMP);
5387 emit_mov(rs,temp);
5388 rs=temp;
5389 }
5390 address_generation(i+1,i_regs,regs[i].regmap_entry);
5391 #ifdef REG_PREFETCH
5392 if(dops[i].rt1==31)
5393 {
5394 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5395 signed char *i_regmap=i_regs->regmap;
5396 int return_address=start+i*4+8;
5397 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5398 }
5399 }
5400 #endif
5401 #ifdef USE_MINI_HT
5402 if(dops[i].rs1==31) {
5403 int rh=get_reg(regs[i].regmap,RHASH);
5404 if(rh>=0) do_preload_rhash(rh);
5405 }
5406 #endif
5407 if (dops[i].rt1 != 0)
5408 rjump_assemble_write_ra(i);
5409 ds_assemble(i+1,i_regs);
5410 uint64_t bc_unneeded=branch_regs[i].u;
5411 bc_unneeded|=1|(1LL<<dops[i].rt1);
5412 bc_unneeded&=~(1LL<<dops[i].rs1);
5413 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5414 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5415 cc=get_reg(branch_regs[i].regmap,CCREG);
5416 assert(cc==HOST_CCREG);
5417 (void)cc;
5418 #ifdef USE_MINI_HT
5419 int rh=get_reg(branch_regs[i].regmap,RHASH);
5420 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5421 if(dops[i].rs1==31) {
5422 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5423 do_preload_rhtbl(ht);
5424 do_rhash(rs,rh);
5425 }
5426 #endif
5427 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5428 #ifdef DESTRUCTIVE_WRITEBACK
5429 if((branch_regs[i].dirty>>rs)&1) {
5430 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5431 emit_loadreg(dops[i].rs1,rs);
5432 }
5433 }
5434 #endif
5435 #ifdef REG_PREFETCH
5436 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5437 #endif
5438 #ifdef USE_MINI_HT
5439 if(dops[i].rs1==31) {
5440 do_miniht_load(ht,rh);
5441 }
5442 #endif
5443 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5444 //if(adj) emit_addimm(cc,2*(cinfo[i].ccadj+2-adj),cc); // ??? - Shouldn't happen
5445 //assert(adj==0);
5446 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5447 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5448 if (dops[i+1].itype == RFE)
5449 // special case for RFE
5450 emit_jmp(0);
5451 else
5452 emit_jns(0);
5453 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5454 #ifdef USE_MINI_HT
5455 if(dops[i].rs1==31) {
5456 do_miniht_jump(rs,rh,ht);
5457 }
5458 else
5459 #endif
5460 {
5461 do_jump_vaddr(rs);
5462 }
5463 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5464 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5465 #endif
5466}
5467
5468static void cjump_assemble(int i, const struct regstat *i_regs)
5469{
5470 const signed char *i_regmap = i_regs->regmap;
5471 int cc;
5472 int match;
5473 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5474 assem_debug("match=%d\n",match);
5475 int s1l,s2l;
5476 int unconditional=0,nop=0;
5477 int invert=0;
5478 int internal=internal_branch(cinfo[i].ba);
5479 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5480 if(!match) invert=1;
5481 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5482 if(i>(cinfo[i].ba-start)>>2) invert=1;
5483 #endif
5484 #ifdef __aarch64__
5485 invert=1; // because of near cond. branches
5486 #endif
5487
5488 if(dops[i].ooo) {
5489 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5490 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5491 }
5492 else {
5493 s1l=get_reg(i_regmap,dops[i].rs1);
5494 s2l=get_reg(i_regmap,dops[i].rs2);
5495 }
5496 if(dops[i].rs1==0&&dops[i].rs2==0)
5497 {
5498 if(dops[i].opcode&1) nop=1;
5499 else unconditional=1;
5500 //assert(dops[i].opcode!=5);
5501 //assert(dops[i].opcode!=7);
5502 //assert(dops[i].opcode!=0x15);
5503 //assert(dops[i].opcode!=0x17);
5504 }
5505 else if(dops[i].rs1==0)
5506 {
5507 s1l=s2l;
5508 s2l=-1;
5509 }
5510 else if(dops[i].rs2==0)
5511 {
5512 s2l=-1;
5513 }
5514
5515 if(dops[i].ooo) {
5516 // Out of order execution (delay slot first)
5517 //printf("OOOE\n");
5518 address_generation(i+1,i_regs,regs[i].regmap_entry);
5519 ds_assemble(i+1,i_regs);
5520 int adj;
5521 uint64_t bc_unneeded=branch_regs[i].u;
5522 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5523 bc_unneeded|=1;
5524 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5525 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5526 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5527 cc=get_reg(branch_regs[i].regmap,CCREG);
5528 assert(cc==HOST_CCREG);
5529 if(unconditional)
5530 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5531 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5532 //assem_debug("cycle count (adj)\n");
5533 if(unconditional) {
5534 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5535 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5536 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5537 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5538 if(internal)
5539 assem_debug("branch: internal\n");
5540 else
5541 assem_debug("branch: external\n");
5542 if (internal && dops[(cinfo[i].ba-start)>>2].is_ds) {
5543 ds_assemble_entry(i);
5544 }
5545 else {
5546 add_to_linker(out,cinfo[i].ba,internal);
5547 emit_jmp(0);
5548 }
5549 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5550 if(((u_int)out)&7) emit_addnop(0);
5551 #endif
5552 }
5553 }
5554 else if(nop) {
5555 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5556 void *jaddr=out;
5557 emit_jns(0);
5558 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5559 }
5560 else {
5561 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5562 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5563 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5564
5565 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5566 assert(s1l>=0);
5567 if(dops[i].opcode==4) // BEQ
5568 {
5569 if(s2l>=0) emit_cmp(s1l,s2l);
5570 else emit_test(s1l,s1l);
5571 if(invert){
5572 nottaken=out;
5573 emit_jne(DJT_1);
5574 }else{
5575 add_to_linker(out,cinfo[i].ba,internal);
5576 emit_jeq(0);
5577 }
5578 }
5579 if(dops[i].opcode==5) // BNE
5580 {
5581 if(s2l>=0) emit_cmp(s1l,s2l);
5582 else emit_test(s1l,s1l);
5583 if(invert){
5584 nottaken=out;
5585 emit_jeq(DJT_1);
5586 }else{
5587 add_to_linker(out,cinfo[i].ba,internal);
5588 emit_jne(0);
5589 }
5590 }
5591 if(dops[i].opcode==6) // BLEZ
5592 {
5593 emit_cmpimm(s1l,1);
5594 if(invert){
5595 nottaken=out;
5596 emit_jge(DJT_1);
5597 }else{
5598 add_to_linker(out,cinfo[i].ba,internal);
5599 emit_jl(0);
5600 }
5601 }
5602 if(dops[i].opcode==7) // BGTZ
5603 {
5604 emit_cmpimm(s1l,1);
5605 if(invert){
5606 nottaken=out;
5607 emit_jl(DJT_1);
5608 }else{
5609 add_to_linker(out,cinfo[i].ba,internal);
5610 emit_jge(0);
5611 }
5612 }
5613 if(invert) {
5614 if(taken) set_jump_target(taken, out);
5615 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5616 if (match && (!internal || !dops[(cinfo[i].ba-start)>>2].is_ds)) {
5617 if(adj) {
5618 emit_addimm(cc,-adj,cc);
5619 add_to_linker(out,cinfo[i].ba,internal);
5620 }else{
5621 emit_addnop(13);
5622 add_to_linker(out,cinfo[i].ba,internal*2);
5623 }
5624 emit_jmp(0);
5625 }else
5626 #endif
5627 {
5628 if(adj) emit_addimm(cc,-adj,cc);
5629 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5630 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5631 if(internal)
5632 assem_debug("branch: internal\n");
5633 else
5634 assem_debug("branch: external\n");
5635 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5636 ds_assemble_entry(i);
5637 }
5638 else {
5639 add_to_linker(out,cinfo[i].ba,internal);
5640 emit_jmp(0);
5641 }
5642 }
5643 set_jump_target(nottaken, out);
5644 }
5645
5646 if(nottaken1) set_jump_target(nottaken1, out);
5647 if(adj) {
5648 if(!invert) emit_addimm(cc,adj,cc);
5649 }
5650 } // (!unconditional)
5651 } // if(ooo)
5652 else
5653 {
5654 // In-order execution (branch first)
5655 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5656 if(!unconditional&&!nop) {
5657 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5658 assert(s1l>=0);
5659 if((dops[i].opcode&0x2f)==4) // BEQ
5660 {
5661 if(s2l>=0) emit_cmp(s1l,s2l);
5662 else emit_test(s1l,s1l);
5663 nottaken=out;
5664 emit_jne(DJT_2);
5665 }
5666 if((dops[i].opcode&0x2f)==5) // BNE
5667 {
5668 if(s2l>=0) emit_cmp(s1l,s2l);
5669 else emit_test(s1l,s1l);
5670 nottaken=out;
5671 emit_jeq(DJT_2);
5672 }
5673 if((dops[i].opcode&0x2f)==6) // BLEZ
5674 {
5675 emit_cmpimm(s1l,1);
5676 nottaken=out;
5677 emit_jge(DJT_2);
5678 }
5679 if((dops[i].opcode&0x2f)==7) // BGTZ
5680 {
5681 emit_cmpimm(s1l,1);
5682 nottaken=out;
5683 emit_jl(DJT_2);
5684 }
5685 } // if(!unconditional)
5686 int adj;
5687 uint64_t ds_unneeded=branch_regs[i].u;
5688 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5689 ds_unneeded|=1;
5690 // branch taken
5691 if(!nop) {
5692 if(taken) set_jump_target(taken, out);
5693 assem_debug("1:\n");
5694 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5695 // load regs
5696 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5697 address_generation(i+1,&branch_regs[i],0);
5698 if (ram_offset)
5699 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5700 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5701 ds_assemble(i+1,&branch_regs[i]);
5702 drc_dbg_emit_wb_dirtys(i+1, &branch_regs[i]);
5703 cc=get_reg(branch_regs[i].regmap,CCREG);
5704 if(cc==-1) {
5705 emit_loadreg(CCREG,cc=HOST_CCREG);
5706 // CHECK: Is the following instruction (fall thru) allocated ok?
5707 }
5708 assert(cc==HOST_CCREG);
5709 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5710 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5711 assem_debug("cycle count (adj)\n");
5712 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5713 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5714 if(internal)
5715 assem_debug("branch: internal\n");
5716 else
5717 assem_debug("branch: external\n");
5718 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5719 ds_assemble_entry(i);
5720 }
5721 else {
5722 add_to_linker(out,cinfo[i].ba,internal);
5723 emit_jmp(0);
5724 }
5725 }
5726 // branch not taken
5727 if(!unconditional) {
5728 if(nottaken1) set_jump_target(nottaken1, out);
5729 set_jump_target(nottaken, out);
5730 assem_debug("2:\n");
5731 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5732 // load regs
5733 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5734 address_generation(i+1,&branch_regs[i],0);
5735 if (ram_offset)
5736 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5737 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5738 ds_assemble(i+1,&branch_regs[i]);
5739 cc=get_reg(branch_regs[i].regmap,CCREG);
5740 if (cc == -1) {
5741 // Cycle count isn't in a register, temporarily load it then write it out
5742 emit_loadreg(CCREG,HOST_CCREG);
5743 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
5744 void *jaddr=out;
5745 emit_jns(0);
5746 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5747 emit_storereg(CCREG,HOST_CCREG);
5748 }
5749 else{
5750 cc=get_reg(i_regmap,CCREG);
5751 assert(cc==HOST_CCREG);
5752 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5753 void *jaddr=out;
5754 emit_jns(0);
5755 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5756 }
5757 }
5758 }
5759}
5760
5761static void sjump_assemble(int i, const struct regstat *i_regs)
5762{
5763 const signed char *i_regmap = i_regs->regmap;
5764 int cc;
5765 int match;
5766 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5767 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5768 int s1l;
5769 int unconditional=0,nevertaken=0;
5770 int invert=0;
5771 int internal=internal_branch(cinfo[i].ba);
5772 if(i==(cinfo[i].ba-start)>>2) assem_debug("idle loop\n");
5773 if(!match) invert=1;
5774 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5775 if(i>(cinfo[i].ba-start)>>2) invert=1;
5776 #endif
5777 #ifdef __aarch64__
5778 invert=1; // because of near cond. branches
5779 #endif
5780
5781 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5782 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5783
5784 if(dops[i].ooo) {
5785 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5786 }
5787 else {
5788 s1l=get_reg(i_regmap,dops[i].rs1);
5789 }
5790 if(dops[i].rs1==0)
5791 {
5792 if(dops[i].opcode2&1) unconditional=1;
5793 else nevertaken=1;
5794 // These are never taken (r0 is never less than zero)
5795 //assert(dops[i].opcode2!=0);
5796 //assert(dops[i].opcode2!=2);
5797 //assert(dops[i].opcode2!=0x10);
5798 //assert(dops[i].opcode2!=0x12);
5799 }
5800
5801 if(dops[i].ooo) {
5802 // Out of order execution (delay slot first)
5803 //printf("OOOE\n");
5804 address_generation(i+1,i_regs,regs[i].regmap_entry);
5805 ds_assemble(i+1,i_regs);
5806 int adj;
5807 uint64_t bc_unneeded=branch_regs[i].u;
5808 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5809 bc_unneeded|=1;
5810 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5811 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5812 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5813 if(dops[i].rt1==31) {
5814 int rt,return_address;
5815 rt=get_reg(branch_regs[i].regmap,31);
5816 //assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5817 if(rt>=0) {
5818 // Save the PC even if the branch is not taken
5819 return_address=start+i*4+8;
5820 emit_movimm(return_address,rt); // PC into link register
5821 #ifdef IMM_PREFETCH
5822 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5823 #endif
5824 }
5825 }
5826 cc=get_reg(branch_regs[i].regmap,CCREG);
5827 assert(cc==HOST_CCREG);
5828 if(unconditional)
5829 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5830 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?cinfo[i].ba:-1,unconditional);
5831 assem_debug("cycle count (adj)\n");
5832 if(unconditional) {
5833 do_cc(i,branch_regs[i].regmap,&adj,cinfo[i].ba,TAKEN,0);
5834 if(i!=(cinfo[i].ba-start)>>2 || source[i+1]!=0) {
5835 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5836 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5837 if(internal)
5838 assem_debug("branch: internal\n");
5839 else
5840 assem_debug("branch: external\n");
5841 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5842 ds_assemble_entry(i);
5843 }
5844 else {
5845 add_to_linker(out,cinfo[i].ba,internal);
5846 emit_jmp(0);
5847 }
5848 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5849 if(((u_int)out)&7) emit_addnop(0);
5850 #endif
5851 }
5852 }
5853 else if(nevertaken) {
5854 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
5855 void *jaddr=out;
5856 emit_jns(0);
5857 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5858 }
5859 else {
5860 void *nottaken = NULL;
5861 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5862 if(adj&&!invert) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5863 {
5864 assert(s1l>=0);
5865 if ((dops[i].opcode2 & 1) == 0) // BLTZ/BLTZAL
5866 {
5867 emit_test(s1l,s1l);
5868 if(invert){
5869 nottaken=out;
5870 emit_jns(DJT_1);
5871 }else{
5872 add_to_linker(out,cinfo[i].ba,internal);
5873 emit_js(0);
5874 }
5875 }
5876 else // BGEZ/BGEZAL
5877 {
5878 emit_test(s1l,s1l);
5879 if(invert){
5880 nottaken=out;
5881 emit_js(DJT_1);
5882 }else{
5883 add_to_linker(out,cinfo[i].ba,internal);
5884 emit_jns(0);
5885 }
5886 }
5887 }
5888
5889 if(invert) {
5890 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5891 if (match && (!internal || !dops[(cinfo[i].ba - start) >> 2].is_ds)) {
5892 if(adj) {
5893 emit_addimm(cc,-adj,cc);
5894 add_to_linker(out,cinfo[i].ba,internal);
5895 }else{
5896 emit_addnop(13);
5897 add_to_linker(out,cinfo[i].ba,internal*2);
5898 }
5899 emit_jmp(0);
5900 }else
5901 #endif
5902 {
5903 if(adj) emit_addimm(cc,-adj,cc);
5904 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5905 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5906 if(internal)
5907 assem_debug("branch: internal\n");
5908 else
5909 assem_debug("branch: external\n");
5910 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5911 ds_assemble_entry(i);
5912 }
5913 else {
5914 add_to_linker(out,cinfo[i].ba,internal);
5915 emit_jmp(0);
5916 }
5917 }
5918 set_jump_target(nottaken, out);
5919 }
5920
5921 if(adj) {
5922 if(!invert) emit_addimm(cc,adj,cc);
5923 }
5924 } // (!unconditional)
5925 } // if(ooo)
5926 else
5927 {
5928 // In-order execution (branch first)
5929 //printf("IOE\n");
5930 void *nottaken = NULL;
5931 if (!unconditional && !nevertaken) {
5932 assert(s1l >= 0);
5933 emit_test(s1l, s1l);
5934 }
5935 if (dops[i].rt1 == 31) {
5936 int rt, return_address;
5937 rt = get_reg(branch_regs[i].regmap,31);
5938 if(rt >= 0) {
5939 // Save the PC even if the branch is not taken
5940 return_address = start + i*4+8;
5941 emit_movimm(return_address, rt); // PC into link register
5942 #ifdef IMM_PREFETCH
5943 emit_prefetch(hash_table_get(return_address));
5944 #endif
5945 }
5946 }
5947 if (!unconditional && !nevertaken) {
5948 nottaken = out;
5949 if (!(dops[i].opcode2 & 1)) // BLTZ/BLTZAL
5950 emit_jns(DJT_1);
5951 else // BGEZ/BGEZAL
5952 emit_js(DJT_1);
5953 }
5954 int adj;
5955 uint64_t ds_unneeded=branch_regs[i].u;
5956 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5957 ds_unneeded|=1;
5958 // branch taken
5959 if(!nevertaken) {
5960 //assem_debug("1:\n");
5961 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5962 // load regs
5963 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5964 address_generation(i+1,&branch_regs[i],0);
5965 if (ram_offset)
5966 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5967 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5968 ds_assemble(i+1,&branch_regs[i]);
5969 cc=get_reg(branch_regs[i].regmap,CCREG);
5970 if(cc==-1) {
5971 emit_loadreg(CCREG,cc=HOST_CCREG);
5972 // CHECK: Is the following instruction (fall thru) allocated ok?
5973 }
5974 assert(cc==HOST_CCREG);
5975 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5976 do_cc(i,i_regmap,&adj,cinfo[i].ba,TAKEN,0);
5977 assem_debug("cycle count (adj)\n");
5978 if(adj) emit_addimm(cc, cinfo[i].ccadj + CLOCK_ADJUST(2) - adj, cc);
5979 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,cinfo[i].ba);
5980 if(internal)
5981 assem_debug("branch: internal\n");
5982 else
5983 assem_debug("branch: external\n");
5984 if (internal && dops[(cinfo[i].ba - start) >> 2].is_ds) {
5985 ds_assemble_entry(i);
5986 }
5987 else {
5988 add_to_linker(out,cinfo[i].ba,internal);
5989 emit_jmp(0);
5990 }
5991 }
5992 // branch not taken
5993 if(!unconditional) {
5994 if (!nevertaken) {
5995 assert(nottaken);
5996 set_jump_target(nottaken, out);
5997 }
5998 assem_debug("1:\n");
5999 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
6000 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
6001 address_generation(i+1,&branch_regs[i],0);
6002 if (ram_offset)
6003 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
6004 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
6005 ds_assemble(i+1,&branch_regs[i]);
6006 cc=get_reg(branch_regs[i].regmap,CCREG);
6007 if (cc == -1) {
6008 // Cycle count isn't in a register, temporarily load it then write it out
6009 emit_loadreg(CCREG,HOST_CCREG);
6010 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), HOST_CCREG);
6011 void *jaddr=out;
6012 emit_jns(0);
6013 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6014 emit_storereg(CCREG,HOST_CCREG);
6015 }
6016 else{
6017 cc=get_reg(i_regmap,CCREG);
6018 assert(cc==HOST_CCREG);
6019 emit_addimm_and_set_flags(cinfo[i].ccadj + CLOCK_ADJUST(2), cc);
6020 void *jaddr=out;
6021 emit_jns(0);
6022 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
6023 }
6024 }
6025 }
6026}
6027
6028static void check_regmap(signed char *regmap)
6029{
6030#ifndef NDEBUG
6031 int i,j;
6032 for (i = 0; i < HOST_REGS; i++) {
6033 if (regmap[i] < 0)
6034 continue;
6035 for (j = i + 1; j < HOST_REGS; j++)
6036 assert(regmap[i] != regmap[j]);
6037 }
6038#endif
6039}
6040
6041#ifdef DISASM
6042#include <inttypes.h>
6043static char insn[MAXBLOCK][10];
6044
6045#define set_mnemonic(i_, n_) \
6046 strcpy(insn[i_], n_)
6047
6048void print_regmap(const char *name, const signed char *regmap)
6049{
6050 char buf[5];
6051 int i, l;
6052 fputs(name, stdout);
6053 for (i = 0; i < HOST_REGS; i++) {
6054 l = 0;
6055 if (regmap[i] >= 0)
6056 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6057 for (; l < 3; l++)
6058 buf[l] = ' ';
6059 buf[l] = 0;
6060 printf(" r%d=%s", i, buf);
6061 }
6062 fputs("\n", stdout);
6063}
6064
6065 /* disassembly */
6066void disassemble_inst(int i)
6067{
6068 if (dops[i].bt) printf("*"); else printf(" ");
6069 switch(dops[i].itype) {
6070 case UJUMP:
6071 printf (" %x: %s %8x\n",start+i*4,insn[i],cinfo[i].ba);break;
6072 case CJUMP:
6073 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):cinfo[i].ba);break;
6074 case SJUMP:
6075 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6076 case RJUMP:
6077 if (dops[i].opcode2 == 9 && dops[i].rt1 != 31)
6078 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6079 else
6080 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6081 break;
6082 case IMM16:
6083 if(dops[i].opcode==0xf) //LUI
6084 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,cinfo[i].imm&0xffff);
6085 else
6086 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6087 break;
6088 case LOAD:
6089 case LOADLR:
6090 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6091 break;
6092 case STORE:
6093 case STORELR:
6094 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,cinfo[i].imm);
6095 break;
6096 case ALU:
6097 case SHIFT:
6098 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6099 break;
6100 case MULTDIV:
6101 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6102 break;
6103 case SHIFTIMM:
6104 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,cinfo[i].imm);
6105 break;
6106 case MOV:
6107 if((dops[i].opcode2&0x1d)==0x10)
6108 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6109 else if((dops[i].opcode2&0x1d)==0x11)
6110 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6111 else
6112 printf (" %x: %s\n",start+i*4,insn[i]);
6113 break;
6114 case COP0:
6115 if(dops[i].opcode2==0)
6116 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6117 else if(dops[i].opcode2==4)
6118 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6119 else printf (" %x: %s\n",start+i*4,insn[i]);
6120 break;
6121 case COP2:
6122 if(dops[i].opcode2<3)
6123 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6124 else if(dops[i].opcode2>3)
6125 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6126 else printf (" %x: %s\n",start+i*4,insn[i]);
6127 break;
6128 case C2LS:
6129 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,cinfo[i].imm);
6130 break;
6131 case INTCALL:
6132 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6133 break;
6134 default:
6135 //printf (" %s %8x\n",insn[i],source[i]);
6136 printf (" %x: %s\n",start+i*4,insn[i]);
6137 }
6138 #ifndef REGMAP_PRINT
6139 return;
6140 #endif
6141 printf("D: %x WD: %x U: %"PRIx64" hC: %x hWC: %x hLC: %x\n",
6142 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i],
6143 regs[i].isconst, regs[i].wasconst, regs[i].loadedconst);
6144 print_regmap("pre: ", regmap_pre[i]);
6145 print_regmap("entry: ", regs[i].regmap_entry);
6146 print_regmap("map: ", regs[i].regmap);
6147 if (dops[i].is_jump) {
6148 print_regmap("bentry:", branch_regs[i].regmap_entry);
6149 print_regmap("bmap: ", branch_regs[i].regmap);
6150 }
6151}
6152#else
6153#define set_mnemonic(i_, n_)
6154static void disassemble_inst(int i) {}
6155#endif // DISASM
6156
6157#define DRC_TEST_VAL 0x74657374
6158
6159static noinline void new_dynarec_test(void)
6160{
6161 int (*testfunc)(void);
6162 void *beginning;
6163 int ret[2];
6164 size_t i;
6165
6166 // check structure linkage
6167 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6168 {
6169 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6170 }
6171
6172 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6173 new_dynarec_test, out);
6174 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6175
6176 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6177 out = ndrc->translation_cache;
6178 beginning = start_block();
6179 emit_movimm(DRC_TEST_VAL + i, 0); // test
6180 emit_ret();
6181 literal_pool(0);
6182 end_block(beginning);
6183 testfunc = beginning;
6184 ret[i] = testfunc();
6185 }
6186
6187 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6188 SysPrintf("test passed.\n");
6189 else
6190 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6191 out = ndrc->translation_cache;
6192}
6193
6194// clear the state completely, instead of just marking
6195// things invalid like invalidate_all_pages() does
6196void new_dynarec_clear_full(void)
6197{
6198 int n;
6199 out = ndrc->translation_cache;
6200 memset(invalid_code,1,sizeof(invalid_code));
6201 memset(hash_table,0xff,sizeof(hash_table));
6202 memset(mini_ht,-1,sizeof(mini_ht));
6203 memset(shadow,0,sizeof(shadow));
6204 copy=shadow;
6205 expirep = EXPIRITY_OFFSET;
6206 pending_exception=0;
6207 literalcount=0;
6208 stop_after_jal=0;
6209 inv_code_start=inv_code_end=~0;
6210 hack_addr=0;
6211 f1_hack=0;
6212 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6213 blocks_clear(&blocks[n]);
6214 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6215 free(jumps[n]);
6216 jumps[n] = NULL;
6217 }
6218 stat_clear(stat_blocks);
6219 stat_clear(stat_links);
6220
6221 cycle_multiplier_old = Config.cycle_multiplier;
6222 new_dynarec_hacks_old = new_dynarec_hacks;
6223}
6224
6225void new_dynarec_init(void)
6226{
6227 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6228
6229#ifdef _3DS
6230 check_rosalina();
6231#endif
6232#ifdef BASE_ADDR_DYNAMIC
6233 #ifdef VITA
6234 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6235 if (sceBlock <= 0)
6236 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6237 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6238 if (ret < 0)
6239 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6240 sceKernelOpenVMDomain();
6241 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6242 #elif defined(_MSC_VER)
6243 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6244 PAGE_EXECUTE_READWRITE);
6245 #elif defined(HAVE_LIBNX)
6246 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6247 if (R_FAILED(rc))
6248 SysPrintf("jitCreate failed: %08x\n", rc);
6249 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6250 jitTransitionToWritable(&g_jit);
6251 ndrc = g_jit.rx_addr;
6252 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6253 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6254 #else
6255 uintptr_t desired_addr = 0;
6256 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6257 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6258 int fd = -1;
6259 #ifdef __ELF__
6260 extern char _end;
6261 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6262 #endif
6263 #ifdef TC_WRITE_OFFSET
6264 // mostly for testing
6265 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6266 ftruncate(fd, sizeof(*ndrc));
6267 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6268 (flags = MAP_SHARED), fd, 0);
6269 assert(mw != MAP_FAILED);
6270 prot = PROT_READ | PROT_EXEC;
6271 #endif
6272 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6273 if (ndrc == MAP_FAILED) {
6274 SysPrintf("mmap() failed: %s\n", strerror(errno));
6275 abort();
6276 }
6277 #ifdef TC_WRITE_OFFSET
6278 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6279 #endif
6280 #endif
6281#else
6282 #ifndef NO_WRITE_EXEC
6283 // not all systems allow execute in data segment by default
6284 // size must be 4K aligned for 3DS?
6285 if (mprotect(ndrc, sizeof(*ndrc),
6286 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6287 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6288 #endif
6289#endif
6290 out = ndrc->translation_cache;
6291 new_dynarec_clear_full();
6292#ifdef HOST_IMM8
6293 // Copy this into local area so we don't have to put it in every literal pool
6294 invc_ptr=invalid_code;
6295#endif
6296 arch_init();
6297 new_dynarec_test();
6298 ram_offset = (uintptr_t)psxM - 0x80000000;
6299 if (ram_offset!=0)
6300 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6301 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6302 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6303}
6304
6305void new_dynarec_cleanup(void)
6306{
6307 int n;
6308#ifdef BASE_ADDR_DYNAMIC
6309 #ifdef VITA
6310 // sceBlock is managed by retroarch's bootstrap code
6311 //sceKernelFreeMemBlock(sceBlock);
6312 //sceBlock = -1;
6313 #elif defined(HAVE_LIBNX)
6314 jitClose(&g_jit);
6315 ndrc = NULL;
6316 #else
6317 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6318 SysPrintf("munmap() failed\n");
6319 ndrc = NULL;
6320 #endif
6321#endif
6322 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6323 blocks_clear(&blocks[n]);
6324 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6325 free(jumps[n]);
6326 jumps[n] = NULL;
6327 }
6328 stat_clear(stat_blocks);
6329 stat_clear(stat_links);
6330 new_dynarec_print_stats();
6331}
6332
6333static u_int *get_source_start(u_int addr, u_int *limit)
6334{
6335 if (addr < 0x00800000
6336 || (0x80000000 <= addr && addr < 0x80800000)
6337 || (0xa0000000 <= addr && addr < 0xa0800000))
6338 {
6339 // used for BIOS calls mostly?
6340 *limit = (addr & 0xa0600000) + 0x00200000;
6341 return (u_int *)(psxM + (addr & 0x1fffff));
6342 }
6343 else if (
6344 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6345 (0xbfc00000 <= addr && addr < 0xbfc80000))
6346 {
6347 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6348 // but timings in PCSX are too tied to the interpreter's 2-per-insn assumption
6349 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6350 cycle_multiplier_active = 200;
6351
6352 *limit = (addr & 0xfff00000) | 0x80000;
6353 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6354 }
6355 return NULL;
6356}
6357
6358static u_int scan_for_ret(u_int addr)
6359{
6360 u_int limit = 0;
6361 u_int *mem;
6362
6363 mem = get_source_start(addr, &limit);
6364 if (mem == NULL)
6365 return addr;
6366
6367 if (limit > addr + 0x1000)
6368 limit = addr + 0x1000;
6369 for (; addr < limit; addr += 4, mem++) {
6370 if (*mem == 0x03e00008) // jr $ra
6371 return addr + 8;
6372 }
6373 return addr;
6374}
6375
6376struct savestate_block {
6377 uint32_t addr;
6378 uint32_t regflags;
6379};
6380
6381static int addr_cmp(const void *p1_, const void *p2_)
6382{
6383 const struct savestate_block *p1 = p1_, *p2 = p2_;
6384 return p1->addr - p2->addr;
6385}
6386
6387int new_dynarec_save_blocks(void *save, int size)
6388{
6389 struct savestate_block *sblocks = save;
6390 int maxcount = size / sizeof(sblocks[0]);
6391 struct savestate_block tmp_blocks[1024];
6392 struct block_info *block;
6393 int p, s, d, o, bcnt;
6394 u_int addr;
6395
6396 o = 0;
6397 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6398 bcnt = 0;
6399 for (block = blocks[p]; block != NULL; block = block->next) {
6400 if (block->is_dirty)
6401 continue;
6402 tmp_blocks[bcnt].addr = block->start;
6403 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6404 bcnt++;
6405 }
6406 if (bcnt < 1)
6407 continue;
6408 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6409
6410 addr = tmp_blocks[0].addr;
6411 for (s = d = 0; s < bcnt; s++) {
6412 if (tmp_blocks[s].addr < addr)
6413 continue;
6414 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6415 tmp_blocks[d++] = tmp_blocks[s];
6416 addr = scan_for_ret(tmp_blocks[s].addr);
6417 }
6418
6419 if (o + d > maxcount)
6420 d = maxcount - o;
6421 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6422 o += d;
6423 }
6424
6425 return o * sizeof(sblocks[0]);
6426}
6427
6428void new_dynarec_load_blocks(const void *save, int size)
6429{
6430 const struct savestate_block *sblocks = save;
6431 int count = size / sizeof(sblocks[0]);
6432 struct block_info *block;
6433 u_int regs_save[32];
6434 u_int page;
6435 uint32_t f;
6436 int i, b;
6437
6438 // restore clean blocks, if any
6439 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6440 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6441 if (!block->is_dirty)
6442 continue;
6443 assert(block->source && block->copy);
6444 if (memcmp(block->source, block->copy, block->len))
6445 continue;
6446
6447 // see try_restore_block
6448 block->is_dirty = 0;
6449 mark_invalid_code(block->start, block->len, 0);
6450 i++;
6451 }
6452 }
6453 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6454
6455 // change GPRs for speculation to at least partially work..
6456 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6457 for (i = 1; i < 32; i++)
6458 psxRegs.GPR.r[i] = 0x80000000;
6459
6460 for (b = 0; b < count; b++) {
6461 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6462 if (f & 1)
6463 psxRegs.GPR.r[i] = 0x1f800000;
6464 }
6465
6466 ndrc_get_addr_ht(sblocks[b].addr);
6467
6468 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6469 if (f & 1)
6470 psxRegs.GPR.r[i] = 0x80000000;
6471 }
6472 }
6473
6474 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6475}
6476
6477void new_dynarec_print_stats(void)
6478{
6479#ifdef STAT_PRINT
6480 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6481 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6482 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6483 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6484 out - ndrc->translation_cache, stat_blocks, stat_links);
6485 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6486 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6487 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6488#endif
6489}
6490
6491static int apply_hacks(void)
6492{
6493 int i;
6494 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6495 return 0;
6496 /* special hack(s) */
6497 for (i = 0; i < slen - 4; i++)
6498 {
6499 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6500 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6501 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6502 && cinfo[i+3].imm == 0x6e40 && dops[i+3].rs1 == 2)
6503 {
6504 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6505 dops[i + 3].itype = NOP;
6506 }
6507 }
6508 i = slen;
6509 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6510 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6511 && dops[i-7].itype == STORE)
6512 {
6513 i = i-8;
6514 if (dops[i].itype == IMM16)
6515 i--;
6516 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6517 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6518 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6519 {
6520 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6521 f1_hack = 1;
6522 return 1;
6523 }
6524 }
6525 return 0;
6526}
6527
6528static int is_ld_use_hazard(int ld_rt, const struct decoded_insn *op)
6529{
6530 return ld_rt != 0 && (ld_rt == op->rs1 || ld_rt == op->rs2)
6531 && op->itype != LOADLR && op->itype != CJUMP && op->itype != SJUMP;
6532}
6533
6534static void force_intcall(int i)
6535{
6536 memset(&dops[i], 0, sizeof(dops[i]));
6537 dops[i].itype = INTCALL;
6538 dops[i].rs1 = CCREG;
6539 dops[i].is_exception = 1;
6540 cinfo[i].ba = -1;
6541}
6542
6543static void disassemble_one(int i, u_int src)
6544{
6545 unsigned int type, op, op2, op3;
6546 enum ls_width_type ls_type = LS_32;
6547 memset(&dops[i], 0, sizeof(dops[i]));
6548 memset(&cinfo[i], 0, sizeof(cinfo[i]));
6549 cinfo[i].ba = -1;
6550 cinfo[i].addr = -1;
6551 dops[i].opcode = op = src >> 26;
6552 op2 = 0;
6553 type = INTCALL;
6554 set_mnemonic(i, "???");
6555 switch(op)
6556 {
6557 case 0x00: set_mnemonic(i, "special");
6558 op2 = src & 0x3f;
6559 switch(op2)
6560 {
6561 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6562 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6563 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6564 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6565 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6566 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6567 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6568 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6569 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6570 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6571 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6572 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6573 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6574 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6575 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6576 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6577 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6578 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6579 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6580 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6581 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6582 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6583 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6584 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6585 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6586 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6587 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6588 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6589 }
6590 break;
6591 case 0x01: set_mnemonic(i, "regimm");
6592 type = SJUMP;
6593 op2 = (src >> 16) & 0x1f;
6594 switch(op2)
6595 {
6596 case 0x10: set_mnemonic(i, "BLTZAL"); break;
6597 case 0x11: set_mnemonic(i, "BGEZAL"); break;
6598 default:
6599 if (op2 & 1)
6600 set_mnemonic(i, "BGEZ");
6601 else
6602 set_mnemonic(i, "BLTZ");
6603 }
6604 break;
6605 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6606 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6607 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6608 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6609 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6610 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6611 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6612 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6613 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6614 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6615 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6616 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6617 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6618 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6619 case 0x10: set_mnemonic(i, "COP0");
6620 op2 = (src >> 21) & 0x1f;
6621 if (op2 & 0x10) {
6622 op3 = src & 0x1f;
6623 switch (op3)
6624 {
6625 case 0x01: case 0x02: case 0x06: case 0x08: type = INTCALL; break;
6626 case 0x10: set_mnemonic(i, "RFE"); type=RFE; break;
6627 default: type = OTHER; break;
6628 }
6629 break;
6630 }
6631 switch(op2)
6632 {
6633 u32 rd;
6634 case 0x00:
6635 set_mnemonic(i, "MFC0");
6636 rd = (src >> 11) & 0x1F;
6637 if (!(0x00000417u & (1u << rd)))
6638 type = COP0;
6639 break;
6640 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6641 case 0x02:
6642 case 0x06: type = INTCALL; break;
6643 default: type = OTHER; break;
6644 }
6645 break;
6646 case 0x11: set_mnemonic(i, "COP1");
6647 op2 = (src >> 21) & 0x1f;
6648 break;
6649 case 0x12: set_mnemonic(i, "COP2");
6650 op2 = (src >> 21) & 0x1f;
6651 if (op2 & 0x10) {
6652 type = OTHER;
6653 if (gte_handlers[src & 0x3f] != NULL) {
6654#ifdef DISASM
6655 if (gte_regnames[src & 0x3f] != NULL)
6656 strcpy(insn[i], gte_regnames[src & 0x3f]);
6657 else
6658 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", src & 0x3f);
6659#endif
6660 type = C2OP;
6661 }
6662 }
6663 else switch(op2)
6664 {
6665 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6666 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6667 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6668 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6669 }
6670 break;
6671 case 0x13: set_mnemonic(i, "COP3");
6672 op2 = (src >> 21) & 0x1f;
6673 break;
6674 case 0x20: set_mnemonic(i, "LB"); type=LOAD; ls_type = LS_8; break;
6675 case 0x21: set_mnemonic(i, "LH"); type=LOAD; ls_type = LS_16; break;
6676 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; ls_type = LS_LR; break;
6677 case 0x23: set_mnemonic(i, "LW"); type=LOAD; ls_type = LS_32; break;
6678 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; ls_type = LS_8; break;
6679 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; ls_type = LS_16; break;
6680 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; ls_type = LS_LR; break;
6681 case 0x28: set_mnemonic(i, "SB"); type=STORE; ls_type = LS_8; break;
6682 case 0x29: set_mnemonic(i, "SH"); type=STORE; ls_type = LS_16; break;
6683 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; ls_type = LS_LR; break;
6684 case 0x2B: set_mnemonic(i, "SW"); type=STORE; ls_type = LS_32; break;
6685 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; ls_type = LS_LR; break;
6686 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; ls_type = LS_32; break;
6687 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; ls_type = LS_32; break;
6688 case 0x3B:
6689 if (Config.HLE && (src & 0x03ffffff) < ARRAY_SIZE(psxHLEt)) {
6690 set_mnemonic(i, "HLECALL");
6691 type = HLECALL;
6692 }
6693 break;
6694 default:
6695 break;
6696 }
6697 if (type == INTCALL)
6698 SysPrintf("NI %08x @%08x (%08x)\n", src, start + i*4, start);
6699 dops[i].itype = type;
6700 dops[i].opcode2 = op2;
6701 dops[i].ls_type = ls_type;
6702 /* Get registers/immediates */
6703 dops[i].use_lt1=0;
6704 gte_rs[i]=gte_rt[i]=0;
6705 dops[i].rs1 = 0;
6706 dops[i].rs2 = 0;
6707 dops[i].rt1 = 0;
6708 dops[i].rt2 = 0;
6709 switch(type) {
6710 case LOAD:
6711 dops[i].rs1 = (src >> 21) & 0x1f;
6712 dops[i].rt1 = (src >> 16) & 0x1f;
6713 cinfo[i].imm = (short)src;
6714 break;
6715 case STORE:
6716 case STORELR:
6717 dops[i].rs1 = (src >> 21) & 0x1f;
6718 dops[i].rs2 = (src >> 16) & 0x1f;
6719 cinfo[i].imm = (short)src;
6720 break;
6721 case LOADLR:
6722 // LWL/LWR only load part of the register,
6723 // therefore the target register must be treated as a source too
6724 dops[i].rs1 = (src >> 21) & 0x1f;
6725 dops[i].rs2 = (src >> 16) & 0x1f;
6726 dops[i].rt1 = (src >> 16) & 0x1f;
6727 cinfo[i].imm = (short)src;
6728 break;
6729 case IMM16:
6730 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6731 else dops[i].rs1 = (src >> 21) & 0x1f;
6732 dops[i].rs2 = 0;
6733 dops[i].rt1 = (src >> 16) & 0x1f;
6734 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6735 cinfo[i].imm = (unsigned short)src;
6736 }else{
6737 cinfo[i].imm = (short)src;
6738 }
6739 break;
6740 case UJUMP:
6741 // The JAL instruction writes to r31.
6742 if (op&1) {
6743 dops[i].rt1=31;
6744 }
6745 dops[i].rs2=CCREG;
6746 break;
6747 case RJUMP:
6748 dops[i].rs1 = (src >> 21) & 0x1f;
6749 // The JALR instruction writes to rd.
6750 if (op2&1) {
6751 dops[i].rt1 = (src >> 11) & 0x1f;
6752 }
6753 dops[i].rs2=CCREG;
6754 break;
6755 case CJUMP:
6756 dops[i].rs1 = (src >> 21) & 0x1f;
6757 dops[i].rs2 = (src >> 16) & 0x1f;
6758 if(op&2) { // BGTZ/BLEZ
6759 dops[i].rs2=0;
6760 }
6761 break;
6762 case SJUMP:
6763 dops[i].rs1 = (src >> 21) & 0x1f;
6764 dops[i].rs2 = CCREG;
6765 if (op2 == 0x10 || op2 == 0x11) { // BxxAL
6766 dops[i].rt1 = 31;
6767 // NOTE: If the branch is not taken, r31 is still overwritten
6768 }
6769 break;
6770 case ALU:
6771 dops[i].rs1=(src>>21)&0x1f; // source
6772 dops[i].rs2=(src>>16)&0x1f; // subtract amount
6773 dops[i].rt1=(src>>11)&0x1f; // destination
6774 break;
6775 case MULTDIV:
6776 dops[i].rs1=(src>>21)&0x1f; // source
6777 dops[i].rs2=(src>>16)&0x1f; // divisor
6778 dops[i].rt1=HIREG;
6779 dops[i].rt2=LOREG;
6780 break;
6781 case MOV:
6782 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6783 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6784 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6785 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6786 if((op2&0x1d)==0x10) dops[i].rt1=(src>>11)&0x1f; // MFxx
6787 if((op2&0x1d)==0x11) dops[i].rs1=(src>>21)&0x1f; // MTxx
6788 break;
6789 case SHIFT:
6790 dops[i].rs1=(src>>16)&0x1f; // target of shift
6791 dops[i].rs2=(src>>21)&0x1f; // shift amount
6792 dops[i].rt1=(src>>11)&0x1f; // destination
6793 break;
6794 case SHIFTIMM:
6795 dops[i].rs1=(src>>16)&0x1f;
6796 dops[i].rs2=0;
6797 dops[i].rt1=(src>>11)&0x1f;
6798 cinfo[i].imm=(src>>6)&0x1f;
6799 break;
6800 case COP0:
6801 if(op2==0) dops[i].rt1=(src>>16)&0x1F; // MFC0
6802 if(op2==4) dops[i].rs1=(src>>16)&0x1F; // MTC0
6803 if(op2==4&&((src>>11)&0x1e)==12) dops[i].rs2=CCREG;
6804 break;
6805 case COP2:
6806 if(op2<3) dops[i].rt1=(src>>16)&0x1F; // MFC2/CFC2
6807 if(op2>3) dops[i].rs1=(src>>16)&0x1F; // MTC2/CTC2
6808 int gr=(src>>11)&0x1F;
6809 switch(op2)
6810 {
6811 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6812 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6813 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6814 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6815 }
6816 break;
6817 case C2LS:
6818 dops[i].rs1=(src>>21)&0x1F;
6819 cinfo[i].imm=(short)src;
6820 if(op==0x32) gte_rt[i]=1ll<<((src>>16)&0x1F); // LWC2
6821 else gte_rs[i]=1ll<<((src>>16)&0x1F); // SWC2
6822 break;
6823 case C2OP:
6824 gte_rs[i]=gte_reg_reads[src&0x3f];
6825 gte_rt[i]=gte_reg_writes[src&0x3f];
6826 gte_rt[i]|=1ll<<63; // every op changes flags
6827 if((src&0x3f)==GTE_MVMVA) {
6828 int v = (src >> 15) & 3;
6829 gte_rs[i]&=~0xe3fll;
6830 if(v==3) gte_rs[i]|=0xe00ll;
6831 else gte_rs[i]|=3ll<<(v*2);
6832 }
6833 break;
6834 case SYSCALL:
6835 case HLECALL:
6836 case INTCALL:
6837 dops[i].rs1=CCREG;
6838 break;
6839 default:
6840 break;
6841 }
6842}
6843
6844static noinline void pass1_disassemble(u_int pagelimit)
6845{
6846 int i, j, done = 0, ni_count = 0;
6847 int ds_next = 0;
6848
6849 for (i = 0; !done; i++)
6850 {
6851 int force_j_to_interpreter = 0;
6852 unsigned int type, op, op2;
6853
6854 disassemble_one(i, source[i]);
6855 dops[i].is_ds = ds_next; ds_next = 0;
6856 type = dops[i].itype;
6857 op = dops[i].opcode;
6858 op2 = dops[i].opcode2;
6859
6860 /* Calculate branch target addresses */
6861 if(type==UJUMP)
6862 cinfo[i].ba=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6863 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6864 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6865 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6866 cinfo[i].ba=start+i*4+8; // Ignore never taken branch
6867 else if(type==CJUMP||type==SJUMP)
6868 cinfo[i].ba=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6869
6870 /* simplify always (not)taken branches */
6871 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6872 dops[i].rs1 = dops[i].rs2 = 0;
6873 if (!(op & 1)) {
6874 dops[i].itype = type = UJUMP;
6875 dops[i].rs2 = CCREG;
6876 }
6877 }
6878 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6879 dops[i].itype = type = UJUMP;
6880
6881 dops[i].is_jump = type == RJUMP || type == UJUMP || type == CJUMP || type == SJUMP;
6882 dops[i].is_ujump = type == RJUMP || type == UJUMP;
6883 dops[i].is_load = type == LOAD || type == LOADLR || op == 0x32; // LWC2
6884 dops[i].is_delay_load = (dops[i].is_load || (source[i] & 0xf3d00000) == 0x40000000); // MFC/CFC
6885 dops[i].is_store = type == STORE || type == STORELR || op == 0x3a; // SWC2
6886 dops[i].is_exception = type == SYSCALL || type == HLECALL || type == INTCALL;
6887 dops[i].may_except = dops[i].is_exception || (type == ALU && (op2 == 0x20 || op2 == 0x22)) || op == 8;
6888 ds_next = dops[i].is_jump;
6889
6890 if (((op & 0x37) == 0x21 || op == 0x25) // LH/SH/LHU
6891 && ((cinfo[i].imm & 1) || Config.PreciseExceptions))
6892 dops[i].may_except = 1;
6893 if (((op & 0x37) == 0x23 || (op & 0x37) == 0x32) // LW/SW/LWC2/SWC2
6894 && ((cinfo[i].imm & 3) || Config.PreciseExceptions))
6895 dops[i].may_except = 1;
6896
6897 /* rare messy cases to just pass over to the interpreter */
6898 if (i > 0 && dops[i-1].is_jump) {
6899 j = i - 1;
6900 // branch in delay slot?
6901 if (dops[i].is_jump) {
6902 // don't handle first branch and call interpreter if it's hit
6903 SysPrintf("branch in DS @%08x (%08x)\n", start + i*4, start);
6904 force_j_to_interpreter = 1;
6905 }
6906 // load delay detection through a branch
6907 else if (dops[i].is_delay_load && dops[i].rt1 != 0) {
6908 const struct decoded_insn *dop = NULL;
6909 int t = -1;
6910 if (cinfo[i-1].ba != -1) {
6911 t = (cinfo[i-1].ba - start) / 4;
6912 if (t < 0 || t > i) {
6913 u_int limit = 0;
6914 u_int *mem = get_source_start(cinfo[i-1].ba, &limit);
6915 if (mem != NULL) {
6916 disassemble_one(MAXBLOCK - 1, mem[0]);
6917 dop = &dops[MAXBLOCK - 1];
6918 }
6919 }
6920 else
6921 dop = &dops[t];
6922 }
6923 if ((dop && is_ld_use_hazard(dops[i].rt1, dop))
6924 || (!dop && Config.PreciseExceptions)) {
6925 // jump target wants DS result - potential load delay effect
6926 SysPrintf("load delay in DS @%08x (%08x)\n", start + i*4, start);
6927 force_j_to_interpreter = 1;
6928 if (0 <= t && t < i)
6929 dops[t + 1].bt = 1; // expected return from interpreter
6930 }
6931 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6932 !(i>=3&&dops[i-3].is_jump)) {
6933 // v0 overwrite like this is a sign of trouble, bail out
6934 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6935 force_j_to_interpreter = 1;
6936 }
6937 }
6938 }
6939 else if (i > 0 && dops[i-1].is_delay_load
6940 && is_ld_use_hazard(dops[i-1].rt1, &dops[i])
6941 && (i < 2 || !dops[i-2].is_ujump)) {
6942 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6943 for (j = i - 1; j > 0 && dops[j-1].is_delay_load; j--)
6944 if (dops[j-1].rt1 != dops[i-1].rt1)
6945 break;
6946 force_j_to_interpreter = 1;
6947 }
6948 if (force_j_to_interpreter) {
6949 force_intcall(j);
6950 done = 2;
6951 i = j; // don't compile the problematic branch/load/etc
6952 }
6953 if (dops[i].is_exception && i > 0 && dops[i-1].is_jump) {
6954 SysPrintf("exception in DS @%08x (%08x)\n", start + i*4, start);
6955 i--;
6956 force_intcall(i);
6957 done = 2;
6958 }
6959 if (i >= 2 && (source[i-2] & 0xffe0f800) == 0x40806000) // MTC0 $12
6960 dops[i].bt = 1;
6961 if (i >= 1 && (source[i-1] & 0xffe0f800) == 0x40806800) // MTC0 $13
6962 dops[i].bt = 1;
6963
6964 /* Is this the end of the block? */
6965 if (i > 0 && dops[i-1].is_ujump) {
6966 if (dops[i-1].rt1 == 0) { // not jal
6967 int found_bbranch = 0, t = (cinfo[i-1].ba - start) / 4;
6968 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6969 // scan for a branch back to i+1
6970 for (j = t; j < t + 64; j++) {
6971 int tmpop = source[j] >> 26;
6972 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6973 int t2 = j + 1 + (int)(signed short)source[j];
6974 if (t2 == i + 1) {
6975 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6976 found_bbranch = 1;
6977 break;
6978 }
6979 }
6980 }
6981 }
6982 if (!found_bbranch)
6983 done = 2;
6984 }
6985 else {
6986 if(stop_after_jal) done=1;
6987 // Stop on BREAK
6988 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6989 }
6990 // Don't recompile stuff that's already compiled
6991 if(check_addr(start+i*4+4)) done=1;
6992 // Don't get too close to the limit
6993 if (i > MAXBLOCK - 64)
6994 done = 1;
6995 }
6996 if (dops[i].itype == HLECALL)
6997 done = 1;
6998 else if (dops[i].itype == INTCALL)
6999 done = 2;
7000 else if (dops[i].is_exception)
7001 done = stop_after_jal ? 1 : 2;
7002 if (done == 2) {
7003 // Does the block continue due to a branch?
7004 for(j=i-1;j>=0;j--)
7005 {
7006 if(cinfo[j].ba==start+i*4) done=j=0; // Branch into delay slot
7007 if(cinfo[j].ba==start+i*4+4) done=j=0;
7008 if(cinfo[j].ba==start+i*4+8) done=j=0;
7009 }
7010 }
7011 //assert(i<MAXBLOCK-1);
7012 if(start+i*4==pagelimit-4) done=1;
7013 assert(start+i*4<pagelimit);
7014 if (i == MAXBLOCK - 2)
7015 done = 1;
7016 // Stop if we're compiling junk
7017 if (dops[i].itype == INTCALL && (++ni_count > 8 || dops[i].opcode == 0x11)) {
7018 done=stop_after_jal=1;
7019 SysPrintf("Disabled speculative precompilation\n");
7020 }
7021 }
7022 while (i > 0 && dops[i-1].is_jump)
7023 i--;
7024 assert(i > 0);
7025 assert(!dops[i-1].is_jump);
7026 slen = i;
7027}
7028
7029// Basic liveness analysis for MIPS registers
7030static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7031{
7032 int i;
7033 uint64_t u,gte_u,b,gte_b;
7034 uint64_t temp_u,temp_gte_u=0;
7035 uint64_t gte_u_unknown=0;
7036 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7037 gte_u_unknown=~0ll;
7038 if(iend==slen-1) {
7039 u=1;
7040 gte_u=gte_u_unknown;
7041 }else{
7042 //u=unneeded_reg[iend+1];
7043 u=1;
7044 gte_u=gte_unneeded[iend+1];
7045 }
7046
7047 for (i=iend;i>=istart;i--)
7048 {
7049 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7050 if(dops[i].is_jump)
7051 {
7052 // If subroutine call, flag return address as a possible branch target
7053 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7054
7055 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7056 {
7057 // Branch out of this block, flush all regs
7058 u=1;
7059 gte_u=gte_u_unknown;
7060 branch_unneeded_reg[i]=u;
7061 // Merge in delay slot
7062 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7063 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7064 u|=1;
7065 gte_u|=gte_rt[i+1];
7066 gte_u&=~gte_rs[i+1];
7067 }
7068 else
7069 {
7070 // Internal branch, flag target
7071 dops[(cinfo[i].ba-start)>>2].bt=1;
7072 if(cinfo[i].ba<=start+i*4) {
7073 // Backward branch
7074 if(dops[i].is_ujump)
7075 {
7076 // Unconditional branch
7077 temp_u=1;
7078 temp_gte_u=0;
7079 } else {
7080 // Conditional branch (not taken case)
7081 temp_u=unneeded_reg[i+2];
7082 temp_gte_u&=gte_unneeded[i+2];
7083 }
7084 // Merge in delay slot
7085 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7086 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7087 temp_u|=1;
7088 temp_gte_u|=gte_rt[i+1];
7089 temp_gte_u&=~gte_rs[i+1];
7090 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7091 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7092 temp_u|=1;
7093 temp_gte_u|=gte_rt[i];
7094 temp_gte_u&=~gte_rs[i];
7095 unneeded_reg[i]=temp_u;
7096 gte_unneeded[i]=temp_gte_u;
7097 // Only go three levels deep. This recursion can take an
7098 // excessive amount of time if there are a lot of nested loops.
7099 if(r<2) {
7100 pass2_unneeded_regs((cinfo[i].ba-start)>>2,i-1,r+1);
7101 }else{
7102 unneeded_reg[(cinfo[i].ba-start)>>2]=1;
7103 gte_unneeded[(cinfo[i].ba-start)>>2]=gte_u_unknown;
7104 }
7105 } /*else*/ if(1) {
7106 if (dops[i].is_ujump)
7107 {
7108 // Unconditional branch
7109 u=unneeded_reg[(cinfo[i].ba-start)>>2];
7110 gte_u=gte_unneeded[(cinfo[i].ba-start)>>2];
7111 branch_unneeded_reg[i]=u;
7112 // Merge in delay slot
7113 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7114 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7115 u|=1;
7116 gte_u|=gte_rt[i+1];
7117 gte_u&=~gte_rs[i+1];
7118 } else {
7119 // Conditional branch
7120 b=unneeded_reg[(cinfo[i].ba-start)>>2];
7121 gte_b=gte_unneeded[(cinfo[i].ba-start)>>2];
7122 branch_unneeded_reg[i]=b;
7123 // Branch delay slot
7124 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7125 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7126 b|=1;
7127 gte_b|=gte_rt[i+1];
7128 gte_b&=~gte_rs[i+1];
7129 u&=b;
7130 gte_u&=gte_b;
7131 if(i<slen-1) {
7132 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7133 } else {
7134 branch_unneeded_reg[i]=1;
7135 }
7136 }
7137 }
7138 }
7139 }
7140 //u=1; // DEBUG
7141 // Written registers are unneeded
7142 u|=1LL<<dops[i].rt1;
7143 u|=1LL<<dops[i].rt2;
7144 gte_u|=gte_rt[i];
7145 // Accessed registers are needed
7146 u&=~(1LL<<dops[i].rs1);
7147 u&=~(1LL<<dops[i].rs2);
7148 gte_u&=~gte_rs[i];
7149 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7150 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7151 if (dops[i].may_except || dops[i].itype == RFE)
7152 {
7153 // SYSCALL instruction, etc or conditional exception
7154 u=1;
7155 }
7156 // Source-target dependencies
7157 // R0 is always unneeded
7158 u|=1;
7159 // Save it
7160 unneeded_reg[i]=u;
7161 gte_unneeded[i]=gte_u;
7162 /*
7163 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7164 printf("U:");
7165 int r;
7166 for(r=1;r<=CCREG;r++) {
7167 if((unneeded_reg[i]>>r)&1) {
7168 if(r==HIREG) printf(" HI");
7169 else if(r==LOREG) printf(" LO");
7170 else printf(" r%d",r);
7171 }
7172 }
7173 printf("\n");
7174 */
7175 }
7176}
7177
7178static noinline void pass2a_unneeded_other(void)
7179{
7180 int i, j;
7181 for (i = 0; i < slen; i++)
7182 {
7183 // remove redundant alignment checks
7184 if (dops[i].may_except && (dops[i].is_load || dops[i].is_store)
7185 && dops[i].rt1 != dops[i].rs1 && !dops[i].is_ds)
7186 {
7187 int base = dops[i].rs1, lsb = cinfo[i].imm, ls_type = dops[i].ls_type;
7188 int mask = ls_type == LS_32 ? 3 : 1;
7189 lsb &= mask;
7190 for (j = i + 1; j < slen; j++) {
7191 if (dops[j].bt || dops[j].is_jump)
7192 break;
7193 if ((dops[j].is_load || dops[j].is_store) && dops[j].rs1 == base
7194 && dops[j].ls_type == ls_type && (cinfo[j].imm & mask) == lsb)
7195 dops[j].may_except = 0;
7196 if (dops[j].rt1 == base)
7197 break;
7198 }
7199 }
7200 }
7201}
7202
7203static noinline void pass3_register_alloc(u_int addr)
7204{
7205 struct regstat current; // Current register allocations/status
7206 clear_all_regs(current.regmap_entry);
7207 clear_all_regs(current.regmap);
7208 current.wasdirty = current.dirty = 0;
7209 current.u = unneeded_reg[0];
7210 alloc_reg(&current, 0, CCREG);
7211 dirty_reg(&current, CCREG);
7212 current.wasconst = 0;
7213 current.isconst = 0;
7214 current.loadedconst = 0;
7215 current.noevict = 0;
7216 //current.waswritten = 0;
7217 int ds=0;
7218 int cc=0;
7219 int hr;
7220 int i, j;
7221
7222 if (addr & 1) {
7223 // First instruction is delay slot
7224 cc=-1;
7225 dops[1].bt=1;
7226 ds=1;
7227 unneeded_reg[0]=1;
7228 }
7229
7230 for(i=0;i<slen;i++)
7231 {
7232 if(dops[i].bt)
7233 {
7234 for(hr=0;hr<HOST_REGS;hr++)
7235 {
7236 // Is this really necessary?
7237 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7238 }
7239 current.isconst=0;
7240 //current.waswritten=0;
7241 }
7242
7243 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7244 regs[i].wasconst=current.isconst;
7245 regs[i].wasdirty=current.dirty;
7246 regs[i].dirty=0;
7247 regs[i].u=0;
7248 regs[i].isconst=0;
7249 regs[i].loadedconst=0;
7250 if (!dops[i].is_jump) {
7251 if(i+1<slen) {
7252 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7253 current.u|=1;
7254 } else {
7255 current.u=1;
7256 }
7257 } else {
7258 if(i+1<slen) {
7259 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7260 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7261 current.u|=1;
7262 } else {
7263 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7264 abort();
7265 }
7266 }
7267 assert(dops[i].is_ds == ds);
7268 if(ds) {
7269 ds=0; // Skip delay slot, already allocated as part of branch
7270 // ...but we need to alloc it in case something jumps here
7271 if(i+1<slen) {
7272 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7273 }else{
7274 current.u=branch_unneeded_reg[i-1];
7275 }
7276 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7277 current.u|=1;
7278 struct regstat temp;
7279 memcpy(&temp,&current,sizeof(current));
7280 temp.wasdirty=temp.dirty;
7281 // TODO: Take into account unconditional branches, as below
7282 delayslot_alloc(&temp,i);
7283 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7284 regs[i].wasdirty=temp.wasdirty;
7285 regs[i].dirty=temp.dirty;
7286 regs[i].isconst=0;
7287 regs[i].wasconst=0;
7288 current.isconst=0;
7289 // Create entry (branch target) regmap
7290 for(hr=0;hr<HOST_REGS;hr++)
7291 {
7292 int r=temp.regmap[hr];
7293 if(r>=0) {
7294 if(r!=regmap_pre[i][hr]) {
7295 regs[i].regmap_entry[hr]=-1;
7296 }
7297 else
7298 {
7299 assert(r < 64);
7300 if((current.u>>r)&1) {
7301 regs[i].regmap_entry[hr]=-1;
7302 regs[i].regmap[hr]=-1;
7303 //Don't clear regs in the delay slot as the branch might need them
7304 //current.regmap[hr]=-1;
7305 }else
7306 regs[i].regmap_entry[hr]=r;
7307 }
7308 } else {
7309 // First instruction expects CCREG to be allocated
7310 if(i==0&&hr==HOST_CCREG)
7311 regs[i].regmap_entry[hr]=CCREG;
7312 else
7313 regs[i].regmap_entry[hr]=-1;
7314 }
7315 }
7316 }
7317 else { // Not delay slot
7318 current.noevict = 0;
7319 switch(dops[i].itype) {
7320 case UJUMP:
7321 //current.isconst=0; // DEBUG
7322 //current.wasconst=0; // DEBUG
7323 //regs[i].wasconst=0; // DEBUG
7324 clear_const(&current,dops[i].rt1);
7325 alloc_cc(&current,i);
7326 dirty_reg(&current,CCREG);
7327 if (dops[i].rt1==31) {
7328 alloc_reg(&current,i,31);
7329 dirty_reg(&current,31);
7330 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7331 //assert(dops[i+1].rt1!=dops[i].rt1);
7332 #ifdef REG_PREFETCH
7333 alloc_reg(&current,i,PTEMP);
7334 #endif
7335 }
7336 dops[i].ooo=1;
7337 delayslot_alloc(&current,i+1);
7338 //current.isconst=0; // DEBUG
7339 ds=1;
7340 break;
7341 case RJUMP:
7342 //current.isconst=0;
7343 //current.wasconst=0;
7344 //regs[i].wasconst=0;
7345 clear_const(&current,dops[i].rs1);
7346 clear_const(&current,dops[i].rt1);
7347 alloc_cc(&current,i);
7348 dirty_reg(&current,CCREG);
7349 if (!ds_writes_rjump_rs(i)) {
7350 alloc_reg(&current,i,dops[i].rs1);
7351 if (dops[i].rt1!=0) {
7352 alloc_reg(&current,i,dops[i].rt1);
7353 dirty_reg(&current,dops[i].rt1);
7354 #ifdef REG_PREFETCH
7355 alloc_reg(&current,i,PTEMP);
7356 #endif
7357 }
7358 #ifdef USE_MINI_HT
7359 if(dops[i].rs1==31) { // JALR
7360 alloc_reg(&current,i,RHASH);
7361 alloc_reg(&current,i,RHTBL);
7362 }
7363 #endif
7364 delayslot_alloc(&current,i+1);
7365 } else {
7366 // The delay slot overwrites our source register,
7367 // allocate a temporary register to hold the old value.
7368 current.isconst=0;
7369 current.wasconst=0;
7370 regs[i].wasconst=0;
7371 delayslot_alloc(&current,i+1);
7372 current.isconst=0;
7373 alloc_reg(&current,i,RTEMP);
7374 }
7375 //current.isconst=0; // DEBUG
7376 dops[i].ooo=1;
7377 ds=1;
7378 break;
7379 case CJUMP:
7380 //current.isconst=0;
7381 //current.wasconst=0;
7382 //regs[i].wasconst=0;
7383 clear_const(&current,dops[i].rs1);
7384 clear_const(&current,dops[i].rs2);
7385 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7386 {
7387 alloc_cc(&current,i);
7388 dirty_reg(&current,CCREG);
7389 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7390 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7391 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7392 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7393 // The delay slot overwrites one of our conditions.
7394 // Allocate the branch condition registers instead.
7395 current.isconst=0;
7396 current.wasconst=0;
7397 regs[i].wasconst=0;
7398 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7399 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7400 }
7401 else
7402 {
7403 dops[i].ooo=1;
7404 delayslot_alloc(&current,i+1);
7405 }
7406 }
7407 else
7408 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7409 {
7410 alloc_cc(&current,i);
7411 dirty_reg(&current,CCREG);
7412 alloc_reg(&current,i,dops[i].rs1);
7413 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7414 // The delay slot overwrites one of our conditions.
7415 // Allocate the branch condition registers instead.
7416 current.isconst=0;
7417 current.wasconst=0;
7418 regs[i].wasconst=0;
7419 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7420 }
7421 else
7422 {
7423 dops[i].ooo=1;
7424 delayslot_alloc(&current,i+1);
7425 }
7426 }
7427 else
7428 // Don't alloc the delay slot yet because we might not execute it
7429 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7430 {
7431 current.isconst=0;
7432 current.wasconst=0;
7433 regs[i].wasconst=0;
7434 alloc_cc(&current,i);
7435 dirty_reg(&current,CCREG);
7436 alloc_reg(&current,i,dops[i].rs1);
7437 alloc_reg(&current,i,dops[i].rs2);
7438 }
7439 else
7440 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7441 {
7442 current.isconst=0;
7443 current.wasconst=0;
7444 regs[i].wasconst=0;
7445 alloc_cc(&current,i);
7446 dirty_reg(&current,CCREG);
7447 alloc_reg(&current,i,dops[i].rs1);
7448 }
7449 ds=1;
7450 //current.isconst=0;
7451 break;
7452 case SJUMP:
7453 clear_const(&current,dops[i].rs1);
7454 clear_const(&current,dops[i].rt1);
7455 {
7456 alloc_cc(&current,i);
7457 dirty_reg(&current,CCREG);
7458 alloc_reg(&current,i,dops[i].rs1);
7459 if (dops[i].rt1 == 31) { // BLTZAL/BGEZAL
7460 alloc_reg(&current,i,31);
7461 dirty_reg(&current,31);
7462 }
7463 if ((dops[i].rs1 &&
7464 (dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7465 ||(dops[i].rt1 == 31 && dops[i].rs1 == 31) // overwrites it's own condition
7466 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7467 // Allocate the branch condition registers instead.
7468 current.isconst=0;
7469 current.wasconst=0;
7470 regs[i].wasconst=0;
7471 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7472 }
7473 else
7474 {
7475 dops[i].ooo=1;
7476 delayslot_alloc(&current,i+1);
7477 }
7478 }
7479 ds=1;
7480 //current.isconst=0;
7481 break;
7482 case IMM16:
7483 imm16_alloc(&current,i);
7484 break;
7485 case LOAD:
7486 case LOADLR:
7487 load_alloc(&current,i);
7488 break;
7489 case STORE:
7490 case STORELR:
7491 store_alloc(&current,i);
7492 break;
7493 case ALU:
7494 alu_alloc(&current,i);
7495 break;
7496 case SHIFT:
7497 shift_alloc(&current,i);
7498 break;
7499 case MULTDIV:
7500 multdiv_alloc(&current,i);
7501 break;
7502 case SHIFTIMM:
7503 shiftimm_alloc(&current,i);
7504 break;
7505 case MOV:
7506 mov_alloc(&current,i);
7507 break;
7508 case COP0:
7509 cop0_alloc(&current,i);
7510 break;
7511 case RFE:
7512 rfe_alloc(&current,i);
7513 break;
7514 case COP2:
7515 cop2_alloc(&current,i);
7516 break;
7517 case C2LS:
7518 c2ls_alloc(&current,i);
7519 break;
7520 case C2OP:
7521 c2op_alloc(&current,i);
7522 break;
7523 case SYSCALL:
7524 case HLECALL:
7525 case INTCALL:
7526 syscall_alloc(&current,i);
7527 break;
7528 }
7529
7530 // Create entry (branch target) regmap
7531 for(hr=0;hr<HOST_REGS;hr++)
7532 {
7533 int r,or;
7534 r=current.regmap[hr];
7535 if(r>=0) {
7536 if(r!=regmap_pre[i][hr]) {
7537 // TODO: delay slot (?)
7538 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7539 if(or<0||r>=TEMPREG){
7540 regs[i].regmap_entry[hr]=-1;
7541 }
7542 else
7543 {
7544 // Just move it to a different register
7545 regs[i].regmap_entry[hr]=r;
7546 // If it was dirty before, it's still dirty
7547 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r);
7548 }
7549 }
7550 else
7551 {
7552 // Unneeded
7553 if(r==0){
7554 regs[i].regmap_entry[hr]=0;
7555 }
7556 else
7557 {
7558 assert(r<64);
7559 if((current.u>>r)&1) {
7560 regs[i].regmap_entry[hr]=-1;
7561 //regs[i].regmap[hr]=-1;
7562 current.regmap[hr]=-1;
7563 }else
7564 regs[i].regmap_entry[hr]=r;
7565 }
7566 }
7567 } else {
7568 // Branches expect CCREG to be allocated at the target
7569 if(regmap_pre[i][hr]==CCREG)
7570 regs[i].regmap_entry[hr]=CCREG;
7571 else
7572 regs[i].regmap_entry[hr]=-1;
7573 }
7574 }
7575 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7576 }
7577
7578#if 0 // see do_store_smc_check()
7579 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)cinfo[i-1].imm<0x800)
7580 current.waswritten|=1<<dops[i-1].rs1;
7581 current.waswritten&=~(1<<dops[i].rt1);
7582 current.waswritten&=~(1<<dops[i].rt2);
7583 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)cinfo[i].imm>=0x800)
7584 current.waswritten&=~(1<<dops[i].rs1);
7585#endif
7586
7587 /* Branch post-alloc */
7588 if(i>0)
7589 {
7590 current.wasdirty=current.dirty;
7591 switch(dops[i-1].itype) {
7592 case UJUMP:
7593 memcpy(&branch_regs[i-1],&current,sizeof(current));
7594 branch_regs[i-1].isconst=0;
7595 branch_regs[i-1].wasconst=0;
7596 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7597 alloc_cc(&branch_regs[i-1],i-1);
7598 dirty_reg(&branch_regs[i-1],CCREG);
7599 if(dops[i-1].rt1==31) { // JAL
7600 alloc_reg(&branch_regs[i-1],i-1,31);
7601 dirty_reg(&branch_regs[i-1],31);
7602 }
7603 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7604 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7605 break;
7606 case RJUMP:
7607 memcpy(&branch_regs[i-1],&current,sizeof(current));
7608 branch_regs[i-1].isconst=0;
7609 branch_regs[i-1].wasconst=0;
7610 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7611 alloc_cc(&branch_regs[i-1],i-1);
7612 dirty_reg(&branch_regs[i-1],CCREG);
7613 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7614 if(dops[i-1].rt1!=0) { // JALR
7615 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7616 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7617 }
7618 #ifdef USE_MINI_HT
7619 if(dops[i-1].rs1==31) { // JALR
7620 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7621 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7622 }
7623 #endif
7624 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7625 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7626 break;
7627 case CJUMP:
7628 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7629 {
7630 alloc_cc(&current,i-1);
7631 dirty_reg(&current,CCREG);
7632 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7633 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7634 // The delay slot overwrote one of our conditions
7635 // Delay slot goes after the test (in order)
7636 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7637 current.u|=1;
7638 delayslot_alloc(&current,i);
7639 current.isconst=0;
7640 }
7641 else
7642 {
7643 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7644 // Alloc the branch condition registers
7645 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
7646 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
7647 }
7648 memcpy(&branch_regs[i-1],&current,sizeof(current));
7649 branch_regs[i-1].isconst=0;
7650 branch_regs[i-1].wasconst=0;
7651 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7652 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7653 }
7654 else
7655 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7656 {
7657 alloc_cc(&current,i-1);
7658 dirty_reg(&current,CCREG);
7659 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7660 // The delay slot overwrote the branch condition
7661 // Delay slot goes after the test (in order)
7662 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7663 current.u|=1;
7664 delayslot_alloc(&current,i);
7665 current.isconst=0;
7666 }
7667 else
7668 {
7669 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7670 // Alloc the branch condition register
7671 alloc_reg(&current,i-1,dops[i-1].rs1);
7672 }
7673 memcpy(&branch_regs[i-1],&current,sizeof(current));
7674 branch_regs[i-1].isconst=0;
7675 branch_regs[i-1].wasconst=0;
7676 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7677 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7678 }
7679 break;
7680 case SJUMP:
7681 {
7682 alloc_cc(&current,i-1);
7683 dirty_reg(&current,CCREG);
7684 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7685 // The delay slot overwrote the branch condition
7686 // Delay slot goes after the test (in order)
7687 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7688 current.u|=1;
7689 delayslot_alloc(&current,i);
7690 current.isconst=0;
7691 }
7692 else
7693 {
7694 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7695 // Alloc the branch condition register
7696 alloc_reg(&current,i-1,dops[i-1].rs1);
7697 }
7698 memcpy(&branch_regs[i-1],&current,sizeof(current));
7699 branch_regs[i-1].isconst=0;
7700 branch_regs[i-1].wasconst=0;
7701 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
7702 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7703 }
7704 break;
7705 }
7706
7707 if (dops[i-1].is_ujump)
7708 {
7709 if(dops[i-1].rt1==31) // JAL/JALR
7710 {
7711 // Subroutine call will return here, don't alloc any registers
7712 current.dirty=0;
7713 clear_all_regs(current.regmap);
7714 alloc_reg(&current,i,CCREG);
7715 dirty_reg(&current,CCREG);
7716 }
7717 else if(i+1<slen)
7718 {
7719 // Internal branch will jump here, match registers to caller
7720 current.dirty=0;
7721 clear_all_regs(current.regmap);
7722 alloc_reg(&current,i,CCREG);
7723 dirty_reg(&current,CCREG);
7724 for(j=i-1;j>=0;j--)
7725 {
7726 if(cinfo[j].ba==start+i*4+4) {
7727 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7728 current.dirty=branch_regs[j].dirty;
7729 break;
7730 }
7731 }
7732 while(j>=0) {
7733 if(cinfo[j].ba==start+i*4+4) {
7734 for(hr=0;hr<HOST_REGS;hr++) {
7735 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7736 current.regmap[hr]=-1;
7737 }
7738 current.dirty&=branch_regs[j].dirty;
7739 }
7740 }
7741 j--;
7742 }
7743 }
7744 }
7745 }
7746
7747 // Count cycles in between branches
7748 cinfo[i].ccadj = CLOCK_ADJUST(cc);
7749 if (i > 0 && (dops[i-1].is_jump || dops[i].is_exception))
7750 {
7751 cc=0;
7752 }
7753#if !defined(DRC_DBG)
7754 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
7755 {
7756 // this should really be removed since the real stalls have been implemented,
7757 // but doing so causes sizeable perf regression against the older version
7758 u_int gtec = gte_cycletab[source[i] & 0x3f];
7759 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7760 }
7761 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7762 {
7763 cc+=4;
7764 }
7765 else if(dops[i].itype==C2LS)
7766 {
7767 // same as with C2OP
7768 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7769 }
7770#endif
7771 else
7772 {
7773 cc++;
7774 }
7775
7776 if(!dops[i].is_ds) {
7777 regs[i].dirty=current.dirty;
7778 regs[i].isconst=current.isconst;
7779 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7780 }
7781 for(hr=0;hr<HOST_REGS;hr++) {
7782 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
7783 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7784 regs[i].wasconst&=~(1<<hr);
7785 }
7786 }
7787 }
7788 //regs[i].waswritten=current.waswritten;
7789 }
7790}
7791
7792static noinline void pass4_cull_unused_regs(void)
7793{
7794 u_int last_needed_regs[4] = {0,0,0,0};
7795 u_int nr=0;
7796 int i;
7797
7798 for (i=slen-1;i>=0;i--)
7799 {
7800 int hr;
7801 __builtin_prefetch(regs[i-2].regmap);
7802 if(dops[i].is_jump)
7803 {
7804 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
7805 {
7806 // Branch out of this block, don't need anything
7807 nr=0;
7808 }
7809 else
7810 {
7811 // Internal branch
7812 // Need whatever matches the target
7813 nr=0;
7814 int t=(cinfo[i].ba-start)>>2;
7815 for(hr=0;hr<HOST_REGS;hr++)
7816 {
7817 if(regs[i].regmap_entry[hr]>=0) {
7818 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7819 }
7820 }
7821 }
7822 // Conditional branch may need registers for following instructions
7823 if (!dops[i].is_ujump)
7824 {
7825 if(i<slen-2) {
7826 nr |= last_needed_regs[(i+2) & 3];
7827 for(hr=0;hr<HOST_REGS;hr++)
7828 {
7829 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7830 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7831 }
7832 }
7833 }
7834 // Don't need stuff which is overwritten
7835 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7836 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7837 // Merge in delay slot
7838 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7839 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7840 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7841 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7842 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7843 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7844 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7845 nr |= get_regm(regmap_pre[i], ROREG);
7846 nr |= get_regm(regs[i].regmap_entry, ROREG);
7847 }
7848 if (dops[i+1].is_store) {
7849 nr |= get_regm(regmap_pre[i], INVCP);
7850 nr |= get_regm(regs[i].regmap_entry, INVCP);
7851 }
7852 }
7853 else if (dops[i].is_exception)
7854 {
7855 // SYSCALL instruction, etc
7856 nr=0;
7857 }
7858 else // Non-branch
7859 {
7860 if(i<slen-1) {
7861 for(hr=0;hr<HOST_REGS;hr++) {
7862 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7863 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7864 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7865 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7866 }
7867 }
7868 }
7869 // Overwritten registers are not needed
7870 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7871 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7872 nr &= ~get_regm(regs[i].regmap, FTEMP);
7873 // Source registers are needed
7874 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7875 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7876 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7877 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7878 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7879 nr |= get_regm(regmap_pre[i], ROREG);
7880 nr |= get_regm(regs[i].regmap_entry, ROREG);
7881 }
7882 if (dops[i].is_store) {
7883 nr |= get_regm(regmap_pre[i], INVCP);
7884 nr |= get_regm(regs[i].regmap_entry, INVCP);
7885 }
7886
7887 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7888 for(hr=0;hr<HOST_REGS;hr++)
7889 {
7890 // Don't store a register immediately after writing it,
7891 // may prevent dual-issue.
7892 // But do so if this is a branch target, otherwise we
7893 // might have to load the register before the branch.
7894 if((regs[i].wasdirty>>hr)&1) {
7895 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7896 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7897 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7898 }
7899 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7900 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7901 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7902 }
7903 }
7904 }
7905 // Cycle count is needed at branches. Assume it is needed at the target too.
7906 if (i == 0 || dops[i].bt || dops[i].may_except || dops[i].itype == CJUMP) {
7907 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7908 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7909 }
7910 // Save it
7911 last_needed_regs[i & 3] = nr;
7912
7913 // Deallocate unneeded registers
7914 for(hr=0;hr<HOST_REGS;hr++)
7915 {
7916 if(!((nr>>hr)&1)) {
7917 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7918 if(dops[i].is_jump)
7919 {
7920 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7921 if (dops[i+1].is_load || dops[i+1].is_store)
7922 map1 = ROREG;
7923 if (dops[i+1].is_store)
7924 map2 = INVCP;
7925 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7926 temp = FTEMP;
7927 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7928 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7929 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7930 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7931 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7932 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7933 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7934 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7935 {
7936 regs[i].regmap[hr]=-1;
7937 regs[i].isconst&=~(1<<hr);
7938 regs[i].dirty&=~(1<<hr);
7939 regs[i+1].wasdirty&=~(1<<hr);
7940 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7941 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7942 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7943 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7944 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7945 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7946 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7947 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7948 {
7949 branch_regs[i].regmap[hr]=-1;
7950 branch_regs[i].regmap_entry[hr]=-1;
7951 if (!dops[i].is_ujump)
7952 {
7953 if (i < slen-2) {
7954 regmap_pre[i+2][hr]=-1;
7955 regs[i+2].wasconst&=~(1<<hr);
7956 }
7957 }
7958 }
7959 }
7960 }
7961 else
7962 {
7963 // Non-branch
7964 if(i>0)
7965 {
7966 int map1 = -1, map2 = -1, temp=-1;
7967 if (dops[i].is_load || dops[i].is_store)
7968 map1 = ROREG;
7969 if (dops[i].is_store)
7970 map2 = INVCP;
7971 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
7972 temp = FTEMP;
7973 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7974 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7975 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
7976 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
7977 regs[i].regmap[hr] != CCREG)
7978 {
7979 if(i<slen-1&&!dops[i].is_ds) {
7980 assert(regs[i].regmap[hr]<64);
7981 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
7982 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
7983 {
7984 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
7985 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
7986 }
7987 regmap_pre[i+1][hr]=-1;
7988 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
7989 regs[i+1].wasconst&=~(1<<hr);
7990 }
7991 regs[i].regmap[hr]=-1;
7992 regs[i].isconst&=~(1<<hr);
7993 regs[i].dirty&=~(1<<hr);
7994 regs[i+1].wasdirty&=~(1<<hr);
7995 }
7996 }
7997 }
7998 } // if needed
7999 } // for hr
8000 }
8001}
8002
8003// If a register is allocated during a loop, try to allocate it for the
8004// entire loop, if possible. This avoids loading/storing registers
8005// inside of the loop.
8006static noinline void pass5a_preallocate1(void)
8007{
8008 int i, j, hr;
8009 signed char f_regmap[HOST_REGS];
8010 clear_all_regs(f_regmap);
8011 for(i=0;i<slen-1;i++)
8012 {
8013 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8014 {
8015 if(cinfo[i].ba>=start && cinfo[i].ba<(start+i*4))
8016 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8017 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8018 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8019 ||dops[i+1].itype==SHIFT
8020 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8021 {
8022 int t=(cinfo[i].ba-start)>>2;
8023 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8024 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8025 for(hr=0;hr<HOST_REGS;hr++)
8026 {
8027 if(regs[i].regmap[hr]>=0) {
8028 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8029 // dealloc old register
8030 int n;
8031 for(n=0;n<HOST_REGS;n++)
8032 {
8033 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8034 }
8035 // and alloc new one
8036 f_regmap[hr]=regs[i].regmap[hr];
8037 }
8038 }
8039 if(branch_regs[i].regmap[hr]>=0) {
8040 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8041 // dealloc old register
8042 int n;
8043 for(n=0;n<HOST_REGS;n++)
8044 {
8045 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8046 }
8047 // and alloc new one
8048 f_regmap[hr]=branch_regs[i].regmap[hr];
8049 }
8050 }
8051 if(dops[i].ooo) {
8052 if(count_free_regs(regs[i].regmap)<=cinfo[i+1].min_free_regs)
8053 f_regmap[hr]=branch_regs[i].regmap[hr];
8054 }else{
8055 if(count_free_regs(branch_regs[i].regmap)<=cinfo[i+1].min_free_regs)
8056 f_regmap[hr]=branch_regs[i].regmap[hr];
8057 }
8058 // Avoid dirty->clean transition
8059 #ifdef DESTRUCTIVE_WRITEBACK
8060 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8061 #endif
8062 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8063 // case above, however it's always a good idea. We can't hoist the
8064 // load if the register was already allocated, so there's no point
8065 // wasting time analyzing most of these cases. It only "succeeds"
8066 // when the mapping was different and the load can be replaced with
8067 // a mov, which is of negligible benefit. So such cases are
8068 // skipped below.
8069 if(f_regmap[hr]>0) {
8070 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8071 int r=f_regmap[hr];
8072 for(j=t;j<=i;j++)
8073 {
8074 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8075 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8076 assert(r < 64);
8077 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8078 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,cinfo[i].ba,start+j*4,hr,r);
8079 int k;
8080 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8081 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8082 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8083 k=i;
8084 while(k>1&&regs[k-1].regmap[hr]==-1) {
8085 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8086 //printf("no free regs for store %x\n",start+(k-1)*4);
8087 break;
8088 }
8089 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8090 //printf("no-match due to different register\n");
8091 break;
8092 }
8093 if (dops[k-2].is_jump) {
8094 //printf("no-match due to branch\n");
8095 break;
8096 }
8097 // call/ret fast path assumes no registers allocated
8098 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8099 break;
8100 }
8101 k--;
8102 }
8103 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8104 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8105 while(k<i) {
8106 regs[k].regmap_entry[hr]=f_regmap[hr];
8107 regs[k].regmap[hr]=f_regmap[hr];
8108 regmap_pre[k+1][hr]=f_regmap[hr];
8109 regs[k].wasdirty&=~(1<<hr);
8110 regs[k].dirty&=~(1<<hr);
8111 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8112 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8113 regs[k].wasconst&=~(1<<hr);
8114 regs[k].isconst&=~(1<<hr);
8115 k++;
8116 }
8117 }
8118 else {
8119 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8120 break;
8121 }
8122 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8123 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8124 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8125 regs[i].regmap_entry[hr]=f_regmap[hr];
8126 regs[i].regmap[hr]=f_regmap[hr];
8127 regs[i].wasdirty&=~(1<<hr);
8128 regs[i].dirty&=~(1<<hr);
8129 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8130 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8131 regs[i].wasconst&=~(1<<hr);
8132 regs[i].isconst&=~(1<<hr);
8133 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8134 branch_regs[i].wasdirty&=~(1<<hr);
8135 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8136 branch_regs[i].regmap[hr]=f_regmap[hr];
8137 branch_regs[i].dirty&=~(1<<hr);
8138 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8139 branch_regs[i].wasconst&=~(1<<hr);
8140 branch_regs[i].isconst&=~(1<<hr);
8141 if (!dops[i].is_ujump) {
8142 regmap_pre[i+2][hr]=f_regmap[hr];
8143 regs[i+2].wasdirty&=~(1<<hr);
8144 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
8145 }
8146 }
8147 }
8148 for(k=t;k<j;k++) {
8149 // Alloc register clean at beginning of loop,
8150 // but may dirty it in pass 6
8151 regs[k].regmap_entry[hr]=f_regmap[hr];
8152 regs[k].regmap[hr]=f_regmap[hr];
8153 regs[k].dirty&=~(1<<hr);
8154 regs[k].wasconst&=~(1<<hr);
8155 regs[k].isconst&=~(1<<hr);
8156 if (dops[k].is_jump) {
8157 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8158 branch_regs[k].regmap[hr]=f_regmap[hr];
8159 branch_regs[k].dirty&=~(1<<hr);
8160 branch_regs[k].wasconst&=~(1<<hr);
8161 branch_regs[k].isconst&=~(1<<hr);
8162 if (!dops[k].is_ujump) {
8163 regmap_pre[k+2][hr]=f_regmap[hr];
8164 regs[k+2].wasdirty&=~(1<<hr);
8165 }
8166 }
8167 else
8168 {
8169 regmap_pre[k+1][hr]=f_regmap[hr];
8170 regs[k+1].wasdirty&=~(1<<hr);
8171 }
8172 }
8173 if(regs[j].regmap[hr]==f_regmap[hr])
8174 regs[j].regmap_entry[hr]=f_regmap[hr];
8175 break;
8176 }
8177 if(j==i) break;
8178 if(regs[j].regmap[hr]>=0)
8179 break;
8180 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8181 //printf("no-match due to different register\n");
8182 break;
8183 }
8184 if (dops[j].is_ujump)
8185 {
8186 // Stop on unconditional branch
8187 break;
8188 }
8189 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8190 {
8191 if(dops[j].ooo) {
8192 if(count_free_regs(regs[j].regmap)<=cinfo[j+1].min_free_regs)
8193 break;
8194 }else{
8195 if(count_free_regs(branch_regs[j].regmap)<=cinfo[j+1].min_free_regs)
8196 break;
8197 }
8198 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8199 //printf("no-match due to different register (branch)\n");
8200 break;
8201 }
8202 }
8203 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8204 //printf("No free regs for store %x\n",start+j*4);
8205 break;
8206 }
8207 assert(f_regmap[hr]<64);
8208 }
8209 }
8210 }
8211 }
8212 }
8213 }else{
8214 // Non branch or undetermined branch target
8215 for(hr=0;hr<HOST_REGS;hr++)
8216 {
8217 if(hr!=EXCLUDE_REG) {
8218 if(regs[i].regmap[hr]>=0) {
8219 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8220 // dealloc old register
8221 int n;
8222 for(n=0;n<HOST_REGS;n++)
8223 {
8224 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8225 }
8226 // and alloc new one
8227 f_regmap[hr]=regs[i].regmap[hr];
8228 }
8229 }
8230 }
8231 }
8232 // Try to restore cycle count at branch targets
8233 if(dops[i].bt) {
8234 for(j=i;j<slen-1;j++) {
8235 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8236 if(count_free_regs(regs[j].regmap)<=cinfo[j].min_free_regs) {
8237 //printf("no free regs for store %x\n",start+j*4);
8238 break;
8239 }
8240 }
8241 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8242 int k=i;
8243 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8244 while(k<j) {
8245 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8246 regs[k].regmap[HOST_CCREG]=CCREG;
8247 regmap_pre[k+1][HOST_CCREG]=CCREG;
8248 regs[k+1].wasdirty|=1<<HOST_CCREG;
8249 regs[k].dirty|=1<<HOST_CCREG;
8250 regs[k].wasconst&=~(1<<HOST_CCREG);
8251 regs[k].isconst&=~(1<<HOST_CCREG);
8252 k++;
8253 }
8254 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8255 }
8256 // Work backwards from the branch target
8257 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8258 {
8259 //printf("Extend backwards\n");
8260 int k;
8261 k=i;
8262 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8263 if(count_free_regs(regs[k-1].regmap)<=cinfo[k-1].min_free_regs) {
8264 //printf("no free regs for store %x\n",start+(k-1)*4);
8265 break;
8266 }
8267 k--;
8268 }
8269 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8270 //printf("Extend CC, %x ->\n",start+k*4);
8271 while(k<=i) {
8272 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8273 regs[k].regmap[HOST_CCREG]=CCREG;
8274 regmap_pre[k+1][HOST_CCREG]=CCREG;
8275 regs[k+1].wasdirty|=1<<HOST_CCREG;
8276 regs[k].dirty|=1<<HOST_CCREG;
8277 regs[k].wasconst&=~(1<<HOST_CCREG);
8278 regs[k].isconst&=~(1<<HOST_CCREG);
8279 k++;
8280 }
8281 }
8282 else {
8283 //printf("Fail Extend CC, %x ->\n",start+k*4);
8284 }
8285 }
8286 }
8287 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=SHIFT&&
8288 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8289 dops[i].itype!=IMM16&&dops[i].itype!=LOAD)
8290 {
8291 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8292 }
8293 }
8294 }
8295}
8296
8297// This allocates registers (if possible) one instruction prior
8298// to use, which can avoid a load-use penalty on certain CPUs.
8299static noinline void pass5b_preallocate2(void)
8300{
8301 int i, hr;
8302 for(i=0;i<slen-1;i++)
8303 {
8304 if (!i || !dops[i-1].is_jump)
8305 {
8306 if(!dops[i+1].bt)
8307 {
8308 int j, can_steal = 1;
8309 for (j = i; j < i + 2; j++) {
8310 int free_regs = 0;
8311 if (cinfo[j].min_free_regs == 0)
8312 continue;
8313 for (hr = 0; hr < HOST_REGS; hr++)
8314 if (hr != EXCLUDE_REG && regs[j].regmap[hr] < 0)
8315 free_regs++;
8316 if (free_regs <= cinfo[j].min_free_regs) {
8317 can_steal = 0;
8318 break;
8319 }
8320 }
8321 if (!can_steal)
8322 continue;
8323 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8324 ||(dops[i].itype==COP2&&dops[i].opcode2<3))
8325 {
8326 if(dops[i+1].rs1) {
8327 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8328 {
8329 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8330 {
8331 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8332 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8333 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8334 regs[i].isconst&=~(1<<hr);
8335 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8336 constmap[i][hr]=constmap[i+1][hr];
8337 regs[i+1].wasdirty&=~(1<<hr);
8338 regs[i].dirty&=~(1<<hr);
8339 }
8340 }
8341 }
8342 if(dops[i+1].rs2) {
8343 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8344 {
8345 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8346 {
8347 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8348 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8349 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8350 regs[i].isconst&=~(1<<hr);
8351 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8352 constmap[i][hr]=constmap[i+1][hr];
8353 regs[i+1].wasdirty&=~(1<<hr);
8354 regs[i].dirty&=~(1<<hr);
8355 }
8356 }
8357 }
8358 // Preload target address for load instruction (non-constant)
8359 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8360 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8361 {
8362 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8363 {
8364 regs[i].regmap[hr]=dops[i+1].rs1;
8365 regmap_pre[i+1][hr]=dops[i+1].rs1;
8366 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8367 regs[i].isconst&=~(1<<hr);
8368 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8369 constmap[i][hr]=constmap[i+1][hr];
8370 regs[i+1].wasdirty&=~(1<<hr);
8371 regs[i].dirty&=~(1<<hr);
8372 }
8373 }
8374 }
8375 // Load source into target register
8376 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8377 if((hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1))>=0)
8378 {
8379 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8380 {
8381 regs[i].regmap[hr]=dops[i+1].rs1;
8382 regmap_pre[i+1][hr]=dops[i+1].rs1;
8383 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8384 regs[i].isconst&=~(1<<hr);
8385 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8386 constmap[i][hr]=constmap[i+1][hr];
8387 regs[i+1].wasdirty&=~(1<<hr);
8388 regs[i].dirty&=~(1<<hr);
8389 }
8390 }
8391 }
8392 // Address for store instruction (non-constant)
8393 if (dops[i+1].is_store) { // SB/SH/SW/SWC2
8394 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8395 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8396 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8397 else {
8398 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8399 regs[i+1].isconst&=~(1<<hr);
8400 regs[i+1].dirty&=~(1<<hr);
8401 regs[i+2].wasdirty&=~(1<<hr);
8402 }
8403 assert(hr>=0);
8404 #if 0 // what is this for? double allocs $0 in ps1_rom.bin
8405 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8406 {
8407 regs[i].regmap[hr]=dops[i+1].rs1;
8408 regmap_pre[i+1][hr]=dops[i+1].rs1;
8409 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8410 regs[i].isconst&=~(1<<hr);
8411 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8412 constmap[i][hr]=constmap[i+1][hr];
8413 regs[i+1].wasdirty&=~(1<<hr);
8414 regs[i].dirty&=~(1<<hr);
8415 }
8416 #endif
8417 }
8418 }
8419 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) { // LWC2
8420 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8421 int nr;
8422 hr=get_reg(regs[i+1].regmap,FTEMP);
8423 assert(hr>=0);
8424 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8425 {
8426 regs[i].regmap[hr]=dops[i+1].rs1;
8427 regmap_pre[i+1][hr]=dops[i+1].rs1;
8428 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8429 regs[i].isconst&=~(1<<hr);
8430 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8431 constmap[i][hr]=constmap[i+1][hr];
8432 regs[i+1].wasdirty&=~(1<<hr);
8433 regs[i].dirty&=~(1<<hr);
8434 }
8435 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8436 {
8437 // move it to another register
8438 regs[i+1].regmap[hr]=-1;
8439 regmap_pre[i+2][hr]=-1;
8440 regs[i+1].regmap[nr]=FTEMP;
8441 regmap_pre[i+2][nr]=FTEMP;
8442 regs[i].regmap[nr]=dops[i+1].rs1;
8443 regmap_pre[i+1][nr]=dops[i+1].rs1;
8444 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8445 regs[i].isconst&=~(1<<nr);
8446 regs[i+1].isconst&=~(1<<nr);
8447 regs[i].dirty&=~(1<<nr);
8448 regs[i+1].wasdirty&=~(1<<nr);
8449 regs[i+1].dirty&=~(1<<nr);
8450 regs[i+2].wasdirty&=~(1<<nr);
8451 }
8452 }
8453 }
8454 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C2LS*/) {
8455 hr = -1;
8456 if(dops[i+1].itype==LOAD)
8457 hr=get_reg_w(regs[i+1].regmap, dops[i+1].rt1);
8458 if (dops[i+1].itype == LOADLR || dops[i+1].opcode == 0x32) // LWC2
8459 hr=get_reg(regs[i+1].regmap,FTEMP);
8460 if (dops[i+1].is_store) {
8461 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8462 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8463 }
8464 if(hr>=0&&regs[i].regmap[hr]<0) {
8465 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8466 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8467 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8468 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8469 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8470 regs[i].isconst&=~(1<<hr);
8471 regs[i+1].wasdirty&=~(1<<hr);
8472 regs[i].dirty&=~(1<<hr);
8473 }
8474 }
8475 }
8476 }
8477 }
8478 }
8479 }
8480}
8481
8482// Write back dirty registers as soon as we will no longer modify them,
8483// so that we don't end up with lots of writes at the branches.
8484static noinline void pass6_clean_registers(int istart, int iend, int wr)
8485{
8486 static u_int wont_dirty[MAXBLOCK];
8487 static u_int will_dirty[MAXBLOCK];
8488 int i;
8489 int r;
8490 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8491 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8492 if(iend==slen-1) {
8493 will_dirty_i=will_dirty_next=0;
8494 wont_dirty_i=wont_dirty_next=0;
8495 }else{
8496 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8497 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8498 }
8499 for (i=iend;i>=istart;i--)
8500 {
8501 signed char rregmap_i[RRMAP_SIZE];
8502 u_int hr_candirty = 0;
8503 assert(HOST_REGS < 32);
8504 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8505 __builtin_prefetch(regs[i-1].regmap);
8506 if(dops[i].is_jump)
8507 {
8508 signed char branch_rregmap_i[RRMAP_SIZE];
8509 u_int branch_hr_candirty = 0;
8510 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8511 if(cinfo[i].ba<start || cinfo[i].ba>=(start+slen*4))
8512 {
8513 // Branch out of this block, flush all regs
8514 will_dirty_i = 0;
8515 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8516 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8517 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8518 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8519 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8520 will_dirty_i &= branch_hr_candirty;
8521 if (dops[i].is_ujump)
8522 {
8523 // Unconditional branch
8524 wont_dirty_i = 0;
8525 // Merge in delay slot (will dirty)
8526 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8527 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8528 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8529 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8530 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8531 will_dirty_i &= hr_candirty;
8532 }
8533 else
8534 {
8535 // Conditional branch
8536 wont_dirty_i = wont_dirty_next;
8537 // Merge in delay slot (will dirty)
8538 // (the original code had no explanation why these 2 are commented out)
8539 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8540 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8541 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8542 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8543 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8544 will_dirty_i &= hr_candirty;
8545 }
8546 // Merge in delay slot (wont dirty)
8547 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8548 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8549 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8550 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8551 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8552 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8553 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8554 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8555 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8556 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8557 wont_dirty_i &= ~(1u << 31);
8558 if(wr) {
8559 #ifndef DESTRUCTIVE_WRITEBACK
8560 branch_regs[i].dirty&=wont_dirty_i;
8561 #endif
8562 branch_regs[i].dirty|=will_dirty_i;
8563 }
8564 }
8565 else
8566 {
8567 // Internal branch
8568 if(cinfo[i].ba<=start+i*4) {
8569 // Backward branch
8570 if (dops[i].is_ujump)
8571 {
8572 // Unconditional branch
8573 temp_will_dirty=0;
8574 temp_wont_dirty=0;
8575 // Merge in delay slot (will dirty)
8576 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8577 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8578 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8579 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8580 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8581 temp_will_dirty &= branch_hr_candirty;
8582 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8583 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8584 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8585 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8586 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8587 temp_will_dirty &= hr_candirty;
8588 } else {
8589 // Conditional branch (not taken case)
8590 temp_will_dirty=will_dirty_next;
8591 temp_wont_dirty=wont_dirty_next;
8592 // Merge in delay slot (will dirty)
8593 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8594 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8595 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8596 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8597 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8598 temp_will_dirty &= branch_hr_candirty;
8599 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8600 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8601 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8602 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8603 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8604 temp_will_dirty &= hr_candirty;
8605 }
8606 // Merge in delay slot (wont dirty)
8607 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8608 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8609 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8610 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8611 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8612 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8613 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8614 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8615 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8616 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8617 temp_wont_dirty &= ~(1u << 31);
8618 // Deal with changed mappings
8619 if(i<iend) {
8620 for(r=0;r<HOST_REGS;r++) {
8621 if(r!=EXCLUDE_REG) {
8622 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8623 temp_will_dirty&=~(1<<r);
8624 temp_wont_dirty&=~(1<<r);
8625 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8626 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8627 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8628 } else {
8629 temp_will_dirty|=1<<r;
8630 temp_wont_dirty|=1<<r;
8631 }
8632 }
8633 }
8634 }
8635 }
8636 if(wr) {
8637 will_dirty[i]=temp_will_dirty;
8638 wont_dirty[i]=temp_wont_dirty;
8639 pass6_clean_registers((cinfo[i].ba-start)>>2,i-1,0);
8640 }else{
8641 // Limit recursion. It can take an excessive amount
8642 // of time if there are a lot of nested loops.
8643 will_dirty[(cinfo[i].ba-start)>>2]=0;
8644 wont_dirty[(cinfo[i].ba-start)>>2]=-1;
8645 }
8646 }
8647 /*else*/ if(1)
8648 {
8649 if (dops[i].is_ujump)
8650 {
8651 // Unconditional branch
8652 will_dirty_i=0;
8653 wont_dirty_i=0;
8654 //if(cinfo[i].ba>start+i*4) { // Disable recursion (for debugging)
8655 for(r=0;r<HOST_REGS;r++) {
8656 if(r!=EXCLUDE_REG) {
8657 if(branch_regs[i].regmap[r]==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8658 will_dirty_i|=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8659 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8660 }
8661 if(branch_regs[i].regmap[r]>=0) {
8662 will_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8663 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8664 }
8665 }
8666 }
8667 //}
8668 // Merge in delay slot
8669 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8670 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8671 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8672 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8673 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8674 will_dirty_i &= branch_hr_candirty;
8675 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8676 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8677 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8678 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8679 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8680 will_dirty_i &= hr_candirty;
8681 } else {
8682 // Conditional branch
8683 will_dirty_i=will_dirty_next;
8684 wont_dirty_i=wont_dirty_next;
8685 //if(cinfo[i].ba>start+i*4) // Disable recursion (for debugging)
8686 for(r=0;r<HOST_REGS;r++) {
8687 if(r!=EXCLUDE_REG) {
8688 signed char target_reg=branch_regs[i].regmap[r];
8689 if(target_reg==regs[(cinfo[i].ba-start)>>2].regmap_entry[r]) {
8690 will_dirty_i&=will_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8691 wont_dirty_i|=wont_dirty[(cinfo[i].ba-start)>>2]&(1<<r);
8692 }
8693 else if(target_reg>=0) {
8694 will_dirty_i&=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8695 wont_dirty_i|=((unneeded_reg[(cinfo[i].ba-start)>>2]>>target_reg)&1)<<r;
8696 }
8697 }
8698 }
8699 // Merge in delay slot
8700 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8701 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8702 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8703 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8704 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8705 will_dirty_i &= branch_hr_candirty;
8706 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8707 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8708 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8709 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8710 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8711 will_dirty_i &= hr_candirty;
8712 }
8713 // Merge in delay slot (won't dirty)
8714 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8715 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8716 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8717 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8718 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8719 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8720 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8721 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8722 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8723 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8724 wont_dirty_i &= ~(1u << 31);
8725 if(wr) {
8726 #ifndef DESTRUCTIVE_WRITEBACK
8727 branch_regs[i].dirty&=wont_dirty_i;
8728 #endif
8729 branch_regs[i].dirty|=will_dirty_i;
8730 }
8731 }
8732 }
8733 }
8734 else if (dops[i].is_exception)
8735 {
8736 // SYSCALL instruction, etc
8737 will_dirty_i=0;
8738 wont_dirty_i=0;
8739 }
8740 will_dirty_next=will_dirty_i;
8741 wont_dirty_next=wont_dirty_i;
8742 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8743 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8744 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8745 will_dirty_i &= hr_candirty;
8746 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8747 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8748 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8749 wont_dirty_i &= ~(1u << 31);
8750 if (i > istart && !dops[i].is_jump) {
8751 // Don't store a register immediately after writing it,
8752 // may prevent dual-issue.
8753 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8754 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8755 }
8756 // Save it
8757 will_dirty[i]=will_dirty_i;
8758 wont_dirty[i]=wont_dirty_i;
8759 // Mark registers that won't be dirtied as not dirty
8760 if(wr) {
8761 regs[i].dirty|=will_dirty_i;
8762 #ifndef DESTRUCTIVE_WRITEBACK
8763 regs[i].dirty&=wont_dirty_i;
8764 if(dops[i].is_jump)
8765 {
8766 if (i < iend-1 && !dops[i].is_ujump) {
8767 for(r=0;r<HOST_REGS;r++) {
8768 if(r!=EXCLUDE_REG) {
8769 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8770 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8771 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8772 }
8773 }
8774 }
8775 }
8776 else
8777 {
8778 if(i<iend) {
8779 for(r=0;r<HOST_REGS;r++) {
8780 if(r!=EXCLUDE_REG) {
8781 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8782 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8783 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8784 }
8785 }
8786 }
8787 }
8788 #endif
8789 }
8790 // Deal with changed mappings
8791 temp_will_dirty=will_dirty_i;
8792 temp_wont_dirty=wont_dirty_i;
8793 for(r=0;r<HOST_REGS;r++) {
8794 if(r!=EXCLUDE_REG) {
8795 int nr;
8796 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8797 if(wr) {
8798 #ifndef DESTRUCTIVE_WRITEBACK
8799 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8800 #endif
8801 regs[i].wasdirty|=will_dirty_i&(1<<r);
8802 }
8803 }
8804 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8805 // Register moved to a different register
8806 will_dirty_i&=~(1<<r);
8807 wont_dirty_i&=~(1<<r);
8808 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8809 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8810 if(wr) {
8811 #ifndef DESTRUCTIVE_WRITEBACK
8812 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8813 #endif
8814 regs[i].wasdirty|=will_dirty_i&(1<<r);
8815 }
8816 }
8817 else {
8818 will_dirty_i&=~(1<<r);
8819 wont_dirty_i&=~(1<<r);
8820 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8821 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8822 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8823 } else {
8824 wont_dirty_i|=1<<r;
8825 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8826 }
8827 }
8828 }
8829 }
8830 }
8831}
8832
8833static noinline void pass10_expire_blocks(void)
8834{
8835 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8836 // not sizeof(ndrc->translation_cache) due to vita hack
8837 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8838 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8839 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8840 int hit;
8841
8842 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8843 {
8844 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8845 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8846 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8847 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8848 inv_debug("EXP: base_offs %x/%lx phase %u\n", base_offs,
8849 (long)(out - ndrc->translation_cache), phase);
8850 }
8851
8852 if (!phase) {
8853 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8854 if (hit) {
8855 do_clear_cache();
8856 #ifdef USE_MINI_HT
8857 memset(mini_ht, -1, sizeof(mini_ht));
8858 #endif
8859 }
8860 }
8861 else
8862 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8863 }
8864}
8865
8866static struct block_info *new_block_info(u_int start, u_int len,
8867 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8868{
8869 struct block_info **b_pptr;
8870 struct block_info *block;
8871 u_int page = get_page(start);
8872
8873 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8874 assert(block);
8875 assert(jump_in_count > 0);
8876 block->source = source;
8877 block->copy = copy;
8878 block->start = start;
8879 block->len = len;
8880 block->reg_sv_flags = 0;
8881 block->tc_offs = beginning - ndrc->translation_cache;
8882 //block->tc_len = out - beginning;
8883 block->is_dirty = 0;
8884 block->inv_near_misses = 0;
8885 block->jump_in_cnt = jump_in_count;
8886
8887 // insert sorted by start mirror-unmasked vaddr
8888 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8889 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8890 block->next = *b_pptr;
8891 *b_pptr = block;
8892 break;
8893 }
8894 }
8895 stat_inc(stat_blocks);
8896 return block;
8897}
8898
8899static int new_recompile_block(u_int addr)
8900{
8901 u_int pagelimit = 0;
8902 u_int state_rflags = 0;
8903 int i;
8904
8905 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8906
8907 if (addr & 3) {
8908 if (addr != hack_addr) {
8909 SysPrintf("game crash @%08x, ra=%08x\n", addr, psxRegs.GPR.n.ra);
8910 hack_addr = addr;
8911 }
8912 return -1;
8913 }
8914
8915 // this is just for speculation
8916 for (i = 1; i < 32; i++) {
8917 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8918 state_rflags |= 1 << i;
8919 }
8920
8921 start = addr;
8922 new_dynarec_did_compile=1;
8923 if (Config.HLE && start == 0x80001000) // hlecall
8924 {
8925 void *beginning = start_block();
8926
8927 emit_movimm(start,0);
8928 emit_writeword(0,&pcaddr);
8929 emit_far_jump(new_dyna_leave);
8930 literal_pool(0);
8931 end_block(beginning);
8932 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8933 block->jump_in[0].vaddr = start;
8934 block->jump_in[0].addr = beginning;
8935 return 0;
8936 }
8937 else if (f1_hack && hack_addr == 0) {
8938 void *beginning = start_block();
8939 emit_movimm(start, 0);
8940 emit_writeword(0, &hack_addr);
8941 emit_readword(&psxRegs.GPR.n.sp, 0);
8942 emit_readptr(&mem_rtab, 1);
8943 emit_shrimm(0, 12, 2);
8944 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8945 emit_addimm(0, 0x18, 0);
8946 emit_adds_ptr(1, 1, 1);
8947 emit_ldr_dualindexed(1, 0, 0);
8948 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8949 emit_far_call(ndrc_get_addr_ht);
8950 emit_jmpreg(0); // jr k0
8951 literal_pool(0);
8952 end_block(beginning);
8953
8954 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8955 block->jump_in[0].vaddr = start;
8956 block->jump_in[0].addr = beginning;
8957 SysPrintf("F1 hack to %08x\n", start);
8958 return 0;
8959 }
8960
8961 cycle_multiplier_active = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
8962 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
8963
8964 source = get_source_start(start, &pagelimit);
8965 if (source == NULL) {
8966 if (addr != hack_addr) {
8967 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8968 hack_addr = addr;
8969 }
8970 //abort();
8971 return -1;
8972 }
8973
8974 /* Pass 1: disassemble */
8975 /* Pass 2: register dependencies, branch targets */
8976 /* Pass 3: register allocation */
8977 /* Pass 4: branch dependencies */
8978 /* Pass 5: pre-alloc */
8979 /* Pass 6: optimize clean/dirty state */
8980 /* Pass 7: flag 32-bit registers */
8981 /* Pass 8: assembly */
8982 /* Pass 9: linker */
8983 /* Pass 10: garbage collection / free memory */
8984
8985 /* Pass 1 disassembly */
8986
8987 pass1_disassemble(pagelimit);
8988
8989 int clear_hack_addr = apply_hacks();
8990
8991 /* Pass 2 - Register dependencies and branch targets */
8992
8993 pass2_unneeded_regs(0,slen-1,0);
8994
8995 pass2a_unneeded_other();
8996
8997 /* Pass 3 - Register allocation */
8998
8999 pass3_register_alloc(addr);
9000
9001 /* Pass 4 - Cull unused host registers */
9002
9003 pass4_cull_unused_regs();
9004
9005 /* Pass 5 - Pre-allocate registers */
9006
9007 pass5a_preallocate1();
9008 pass5b_preallocate2();
9009
9010 /* Pass 6 - Optimize clean/dirty state */
9011 pass6_clean_registers(0, slen-1, 1);
9012
9013 /* Pass 7 */
9014 for (i=slen-1;i>=0;i--)
9015 {
9016 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9017 {
9018 // Conditional branch
9019 if((source[i]>>16)!=0x1000&&i<slen-2) {
9020 // Mark this address as a branch target since it may be called
9021 // upon return from interrupt
9022 dops[i+2].bt=1;
9023 }
9024 }
9025 }
9026
9027 /* Pass 8 - Assembly */
9028 linkcount=0;stubcount=0;
9029 is_delayslot=0;
9030 u_int dirty_pre=0;
9031 void *beginning=start_block();
9032 void *instr_addr0_override = NULL;
9033 int ds = 0;
9034
9035 if (start == 0x80030000) {
9036 // nasty hack for the fastbios thing
9037 // override block entry to this code
9038 instr_addr0_override = out;
9039 emit_movimm(start,0);
9040 // abuse io address var as a flag that we
9041 // have already returned here once
9042 emit_readword(&address,1);
9043 emit_writeword(0,&pcaddr);
9044 emit_writeword(0,&address);
9045 emit_cmp(0,1);
9046 #ifdef __aarch64__
9047 emit_jeq(out + 4*2);
9048 emit_far_jump(new_dyna_leave);
9049 #else
9050 emit_jne(new_dyna_leave);
9051 #endif
9052 }
9053 for(i=0;i<slen;i++)
9054 {
9055 __builtin_prefetch(regs[i+1].regmap);
9056 check_regmap(regmap_pre[i]);
9057 check_regmap(regs[i].regmap_entry);
9058 check_regmap(regs[i].regmap);
9059 //if(ds) printf("ds: ");
9060 disassemble_inst(i);
9061 if(ds) {
9062 ds=0; // Skip delay slot
9063 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9064 instr_addr[i] = NULL;
9065 } else {
9066 speculate_register_values(i);
9067 #ifndef DESTRUCTIVE_WRITEBACK
9068 if (i < 2 || !dops[i-2].is_ujump)
9069 {
9070 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9071 }
9072 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9073 dirty_pre=branch_regs[i].dirty;
9074 }else{
9075 dirty_pre=regs[i].dirty;
9076 }
9077 #endif
9078 // write back
9079 if (i < 2 || !dops[i-2].is_ujump)
9080 {
9081 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9082 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9083 }
9084 // branch target entry point
9085 instr_addr[i] = out;
9086 assem_debug("<->\n");
9087 drc_dbg_emit_do_cmp(i, cinfo[i].ccadj);
9088 if (clear_hack_addr) {
9089 emit_movimm(0, 0);
9090 emit_writeword(0, &hack_addr);
9091 clear_hack_addr = 0;
9092 }
9093
9094 // load regs
9095 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9096 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9097 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9098 address_generation(i,&regs[i],regs[i].regmap_entry);
9099 load_consts(regmap_pre[i],regs[i].regmap,i);
9100 if(dops[i].is_jump)
9101 {
9102 // Load the delay slot registers if necessary
9103 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9104 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9105 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9106 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9107 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9108 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9109 if (dops[i+1].is_store)
9110 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9111 }
9112 else if(i+1<slen)
9113 {
9114 // Preload registers for following instruction
9115 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9116 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9117 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9118 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9119 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9120 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9121 }
9122 // TODO: if(is_ooo(i)) address_generation(i+1);
9123 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9124 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9125 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9126 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9127 if (dops[i].is_store)
9128 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9129
9130 ds = assemble(i, &regs[i], cinfo[i].ccadj);
9131
9132 drc_dbg_emit_wb_dirtys(i, &regs[i]);
9133 if (dops[i].is_ujump)
9134 literal_pool(1024);
9135 else
9136 literal_pool_jumpover(256);
9137 }
9138 }
9139
9140 assert(slen > 0);
9141 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9142 // no ending needed for this block since INTCALL never returns
9143 }
9144 // If the block did not end with an unconditional branch,
9145 // add a jump to the next instruction.
9146 else if (i > 1) {
9147 if (!dops[i-2].is_ujump) {
9148 assert(!dops[i-1].is_jump);
9149 assert(i==slen);
9150 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9151 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9152 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9153 emit_loadreg(CCREG,HOST_CCREG);
9154 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9155 }
9156 else
9157 {
9158 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9159 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9160 }
9161 add_to_linker(out,start+i*4,0);
9162 emit_jmp(0);
9163 }
9164 }
9165 else
9166 {
9167 assert(i>0);
9168 assert(!dops[i-1].is_jump);
9169 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9170 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9171 emit_loadreg(CCREG,HOST_CCREG);
9172 emit_addimm(HOST_CCREG, cinfo[i-1].ccadj + CLOCK_ADJUST(1), HOST_CCREG);
9173 add_to_linker(out,start+i*4,0);
9174 emit_jmp(0);
9175 }
9176
9177 // Stubs
9178 for(i = 0; i < stubcount; i++)
9179 {
9180 switch(stubs[i].type)
9181 {
9182 case LOADB_STUB:
9183 case LOADH_STUB:
9184 case LOADW_STUB:
9185 case LOADBU_STUB:
9186 case LOADHU_STUB:
9187 do_readstub(i);break;
9188 case STOREB_STUB:
9189 case STOREH_STUB:
9190 case STOREW_STUB:
9191 do_writestub(i);break;
9192 case CC_STUB:
9193 do_ccstub(i);break;
9194 case INVCODE_STUB:
9195 do_invstub(i);break;
9196 case STORELR_STUB:
9197 do_unalignedwritestub(i);break;
9198 case OVERFLOW_STUB:
9199 do_overflowstub(i); break;
9200 case ALIGNMENT_STUB:
9201 do_alignmentstub(i); break;
9202 default:
9203 assert(0);
9204 }
9205 }
9206
9207 if (instr_addr0_override)
9208 instr_addr[0] = instr_addr0_override;
9209
9210#if 0
9211 /* check for improper expiration */
9212 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9213 int j;
9214 if (!jumps[i])
9215 continue;
9216 for (j = 0; j < jumps[i]->count; j++)
9217 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9218 }
9219#endif
9220
9221 /* Pass 9 - Linker */
9222 for(i=0;i<linkcount;i++)
9223 {
9224 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9225 literal_pool(64);
9226 if (!link_addr[i].internal)
9227 {
9228 void *stub = out;
9229 void *addr = check_addr(link_addr[i].target);
9230 emit_extjump(link_addr[i].addr, link_addr[i].target);
9231 if (addr) {
9232 set_jump_target(link_addr[i].addr, addr);
9233 ndrc_add_jump_out(link_addr[i].target,stub);
9234 }
9235 else
9236 set_jump_target(link_addr[i].addr, stub);
9237 }
9238 else
9239 {
9240 // Internal branch
9241 int target=(link_addr[i].target-start)>>2;
9242 assert(target>=0&&target<slen);
9243 assert(instr_addr[target]);
9244 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9245 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9246 //#else
9247 set_jump_target(link_addr[i].addr, instr_addr[target]);
9248 //#endif
9249 }
9250 }
9251
9252 u_int source_len = slen*4;
9253 if (dops[slen-1].itype == INTCALL && source_len > 4)
9254 // no need to treat the last instruction as compiled
9255 // as interpreter fully handles it
9256 source_len -= 4;
9257
9258 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9259 copy = shadow;
9260
9261 // External Branch Targets (jump_in)
9262 int jump_in_count = 1;
9263 assert(instr_addr[0]);
9264 for (i = 1; i < slen; i++)
9265 {
9266 if (dops[i].bt && instr_addr[i])
9267 jump_in_count++;
9268 }
9269
9270 struct block_info *block =
9271 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9272 block->reg_sv_flags = state_rflags;
9273
9274 int jump_in_i = 0;
9275 for (i = 0; i < slen; i++)
9276 {
9277 if ((i == 0 || dops[i].bt) && instr_addr[i])
9278 {
9279 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9280 u_int vaddr = start + i*4;
9281
9282 literal_pool(256);
9283 void *entry = out;
9284 load_regs_entry(i);
9285 if (entry == out)
9286 entry = instr_addr[i];
9287 else
9288 emit_jmp(instr_addr[i]);
9289
9290 block->jump_in[jump_in_i].vaddr = vaddr;
9291 block->jump_in[jump_in_i].addr = entry;
9292 jump_in_i++;
9293 }
9294 }
9295 assert(jump_in_i == jump_in_count);
9296 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9297 // Write out the literal pool if necessary
9298 literal_pool(0);
9299 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9300 // Align code
9301 if(((u_int)out)&7) emit_addnop(13);
9302 #endif
9303 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9304 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9305 memcpy(copy, source, source_len);
9306 copy += source_len;
9307
9308 end_block(beginning);
9309
9310 // If we're within 256K of the end of the buffer,
9311 // start over from the beginning. (Is 256K enough?)
9312 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9313 out = ndrc->translation_cache;
9314
9315 // Trap writes to any of the pages we compiled
9316 mark_invalid_code(start, slen*4, 0);
9317
9318 /* Pass 10 - Free memory by expiring oldest blocks */
9319
9320 pass10_expire_blocks();
9321
9322#ifdef ASSEM_PRINT
9323 fflush(stdout);
9324#endif
9325 stat_inc(stat_bc_direct);
9326 return 0;
9327}
9328
9329// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork