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drc: prefer callee-saved regs on alloc
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / new_dynarec.c
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1/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
20
21#include <stdlib.h>
22#include <stdint.h> //include for uint64_t
23#include <assert.h>
24#include <errno.h>
25#include <sys/mman.h>
26#ifdef __MACH__
27#include <libkern/OSCacheControl.h>
28#endif
29#ifdef _3DS
30#include <3ds_utils.h>
31#endif
32#ifdef VITA
33#include <psp2/kernel/sysmem.h>
34static int sceBlock;
35#endif
36
37#include "new_dynarec_config.h"
38#include "../psxhle.h"
39#include "../psxinterpreter.h"
40#include "../gte.h"
41#include "emu_if.h" // emulator interface
42
43#define noinline __attribute__((noinline,noclone))
44#ifndef ARRAY_SIZE
45#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
46#endif
47#ifndef min
48#define min(a, b) ((b) < (a) ? (b) : (a))
49#endif
50#ifndef max
51#define max(a, b) ((b) > (a) ? (b) : (a))
52#endif
53
54//#define DISASM
55//#define ASSEM_PRINT
56
57#ifdef ASSEM_PRINT
58#define assem_debug printf
59#else
60#define assem_debug(...)
61#endif
62//#define inv_debug printf
63#define inv_debug(...)
64
65#ifdef __i386__
66#include "assem_x86.h"
67#endif
68#ifdef __x86_64__
69#include "assem_x64.h"
70#endif
71#ifdef __arm__
72#include "assem_arm.h"
73#endif
74#ifdef __aarch64__
75#include "assem_arm64.h"
76#endif
77
78#define RAM_SIZE 0x200000
79#define MAXBLOCK 4096
80#define MAX_OUTPUT_BLOCK_SIZE 262144
81
82struct ndrc_mem
83{
84 u_char translation_cache[1 << TARGET_SIZE_2];
85 struct
86 {
87 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
88 const void *f[2048 / sizeof(void *)];
89 } tramp;
90};
91
92#ifdef BASE_ADDR_DYNAMIC
93static struct ndrc_mem *ndrc;
94#else
95static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
96static struct ndrc_mem *ndrc = &ndrc_;
97#endif
98
99// stubs
100enum stub_type {
101 CC_STUB = 1,
102 FP_STUB = 2,
103 LOADB_STUB = 3,
104 LOADH_STUB = 4,
105 LOADW_STUB = 5,
106 LOADD_STUB = 6,
107 LOADBU_STUB = 7,
108 LOADHU_STUB = 8,
109 STOREB_STUB = 9,
110 STOREH_STUB = 10,
111 STOREW_STUB = 11,
112 STORED_STUB = 12,
113 STORELR_STUB = 13,
114 INVCODE_STUB = 14,
115};
116
117struct regstat
118{
119 signed char regmap_entry[HOST_REGS];
120 signed char regmap[HOST_REGS];
121 uint64_t wasdirty;
122 uint64_t dirty;
123 uint64_t u;
124 u_int wasconst;
125 u_int isconst;
126 u_int loadedconst; // host regs that have constants loaded
127 u_int waswritten; // MIPS regs that were used as store base before
128};
129
130// note: asm depends on this layout
131struct ll_entry
132{
133 u_int vaddr;
134 u_int reg_sv_flags;
135 void *addr;
136 struct ll_entry *next;
137};
138
139struct ht_entry
140{
141 u_int vaddr[2];
142 void *tcaddr[2];
143};
144
145struct code_stub
146{
147 enum stub_type type;
148 void *addr;
149 void *retaddr;
150 u_int a;
151 uintptr_t b;
152 uintptr_t c;
153 u_int d;
154 u_int e;
155};
156
157struct link_entry
158{
159 void *addr;
160 u_int target;
161 u_int ext;
162};
163
164static struct decoded_insn
165{
166 u_char itype;
167 u_char opcode;
168 u_char opcode2;
169 u_char rs1;
170 u_char rs2;
171 u_char rt1;
172 u_char rt2;
173 u_char lt1;
174 u_char bt:1;
175 u_char ooo:1;
176 u_char is_ds:1;
177 u_char is_jump:1;
178 u_char is_ujump:1;
179 u_char is_load:1;
180 u_char is_store:1;
181} dops[MAXBLOCK];
182
183 // used by asm:
184 u_char *out;
185 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
186 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
187 struct ll_entry *jump_dirty[4096];
188
189 static struct ll_entry *jump_out[4096];
190 static u_int start;
191 static u_int *source;
192 static char insn[MAXBLOCK][10];
193 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
194 static uint64_t gte_rt[MAXBLOCK];
195 static uint64_t gte_unneeded[MAXBLOCK];
196 static u_int smrv[32]; // speculated MIPS register values
197 static u_int smrv_strong; // mask or regs that are likely to have correct values
198 static u_int smrv_weak; // same, but somewhat less likely
199 static u_int smrv_strong_next; // same, but after current insn executes
200 static u_int smrv_weak_next;
201 static int imm[MAXBLOCK];
202 static u_int ba[MAXBLOCK];
203 static uint64_t unneeded_reg[MAXBLOCK];
204 static uint64_t branch_unneeded_reg[MAXBLOCK];
205 static signed char regmap_pre[MAXBLOCK][HOST_REGS]; // pre-instruction i?
206 // contains 'real' consts at [i] insn, but may differ from what's actually
207 // loaded in host reg as 'final' value is always loaded, see get_final_value()
208 static uint32_t current_constmap[HOST_REGS];
209 static uint32_t constmap[MAXBLOCK][HOST_REGS];
210 static struct regstat regs[MAXBLOCK];
211 static struct regstat branch_regs[MAXBLOCK];
212 static signed char minimum_free_regs[MAXBLOCK];
213 static u_int needed_reg[MAXBLOCK];
214 static u_int wont_dirty[MAXBLOCK];
215 static u_int will_dirty[MAXBLOCK];
216 static int ccadj[MAXBLOCK];
217 static int slen;
218 static void *instr_addr[MAXBLOCK];
219 static struct link_entry link_addr[MAXBLOCK];
220 static int linkcount;
221 static struct code_stub stubs[MAXBLOCK*3];
222 static int stubcount;
223 static u_int literals[1024][2];
224 static int literalcount;
225 static int is_delayslot;
226 static char shadow[1048576] __attribute__((aligned(16)));
227 static void *copy;
228 static int expirep;
229 static u_int stop_after_jal;
230 static u_int f1_hack; // 0 - off, ~0 - capture address, else addr
231
232 int new_dynarec_hacks;
233 int new_dynarec_hacks_pergame;
234 int new_dynarec_hacks_old;
235 int new_dynarec_did_compile;
236
237 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
238
239 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
240 extern int last_count; // last absolute target, often = next_interupt
241 extern int pcaddr;
242 extern int pending_exception;
243 extern int branch_target;
244 extern uintptr_t ram_offset;
245 extern uintptr_t mini_ht[32][2];
246 extern u_char restore_candidate[512];
247
248 /* registers that may be allocated */
249 /* 1-31 gpr */
250#define LOREG 32 // lo
251#define HIREG 33 // hi
252//#define FSREG 34 // FPU status (FCSR)
253#define CSREG 35 // Coprocessor status
254#define CCREG 36 // Cycle count
255#define INVCP 37 // Pointer to invalid_code
256//#define MMREG 38 // Pointer to memory_map
257#define ROREG 39 // ram offset (if rdram!=0x80000000)
258#define TEMPREG 40
259#define FTEMP 40 // FPU temporary register
260#define PTEMP 41 // Prefetch temporary register
261//#define TLREG 42 // TLB mapping offset
262#define RHASH 43 // Return address hash
263#define RHTBL 44 // Return address hash table address
264#define RTEMP 45 // JR/JALR address register
265#define MAXREG 45
266#define AGEN1 46 // Address generation temporary register
267//#define AGEN2 47 // Address generation temporary register
268//#define MGEN1 48 // Maptable address generation temporary register
269//#define MGEN2 49 // Maptable address generation temporary register
270#define BTREG 50 // Branch target temporary register
271
272 /* instruction types */
273#define NOP 0 // No operation
274#define LOAD 1 // Load
275#define STORE 2 // Store
276#define LOADLR 3 // Unaligned load
277#define STORELR 4 // Unaligned store
278#define MOV 5 // Move
279#define ALU 6 // Arithmetic/logic
280#define MULTDIV 7 // Multiply/divide
281#define SHIFT 8 // Shift by register
282#define SHIFTIMM 9// Shift by immediate
283#define IMM16 10 // 16-bit immediate
284#define RJUMP 11 // Unconditional jump to register
285#define UJUMP 12 // Unconditional jump
286#define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
287#define SJUMP 14 // Conditional branch (regimm format)
288#define COP0 15 // Coprocessor 0
289#define COP1 16 // Coprocessor 1
290#define C1LS 17 // Coprocessor 1 load/store
291//#define FJUMP 18 // Conditional branch (floating point)
292//#define FLOAT 19 // Floating point unit
293//#define FCONV 20 // Convert integer to float
294//#define FCOMP 21 // Floating point compare (sets FSREG)
295#define SYSCALL 22// SYSCALL
296#define OTHER 23 // Other
297#define SPAN 24 // Branch/delay slot spans 2 pages
298#define NI 25 // Not implemented
299#define HLECALL 26// PCSX fake opcodes for HLE
300#define COP2 27 // Coprocessor 2 move
301#define C2LS 28 // Coprocessor 2 load/store
302#define C2OP 29 // Coprocessor 2 operation
303#define INTCALL 30// Call interpreter to handle rare corner cases
304
305 /* branch codes */
306#define TAKEN 1
307#define NOTTAKEN 2
308#define NULLDS 3
309
310#define DJT_1 (void *)1l // no function, just a label in assem_debug log
311#define DJT_2 (void *)2l
312
313// asm linkage
314int new_recompile_block(u_int addr);
315void *get_addr_ht(u_int vaddr);
316void invalidate_block(u_int block);
317void invalidate_addr(u_int addr);
318void remove_hash(int vaddr);
319void dyna_linker();
320void dyna_linker_ds();
321void verify_code();
322void verify_code_ds();
323void cc_interrupt();
324void fp_exception();
325void fp_exception_ds();
326void jump_to_new_pc();
327void call_gteStall();
328void new_dyna_leave();
329
330// Needed by assembler
331static void wb_register(signed char r,signed char regmap[],uint64_t dirty);
332static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty);
333static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr);
334static void load_all_regs(signed char i_regmap[]);
335static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
336static void load_regs_entry(int t);
337static void load_all_consts(signed char regmap[],u_int dirty,int i);
338static u_int get_host_reglist(const signed char *regmap);
339
340static int verify_dirty(const u_int *ptr);
341static int get_final_value(int hr, int i, int *value);
342static void add_stub(enum stub_type type, void *addr, void *retaddr,
343 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
344static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
345 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
346static void add_to_linker(void *addr, u_int target, int ext);
347static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
348 int addr, int *offset_reg, int *addr_reg_override);
349static void *get_direct_memhandler(void *table, u_int addr,
350 enum stub_type type, uintptr_t *addr_host);
351static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
352static void pass_args(int a0, int a1);
353static void emit_far_jump(const void *f);
354static void emit_far_call(const void *f);
355
356static void mprotect_w_x(void *start, void *end, int is_x)
357{
358#ifdef NO_WRITE_EXEC
359 #if defined(VITA)
360 // *Open* enables write on all memory that was
361 // allocated by sceKernelAllocMemBlockForVM()?
362 if (is_x)
363 sceKernelCloseVMDomain();
364 else
365 sceKernelOpenVMDomain();
366 #else
367 u_long mstart = (u_long)start & ~4095ul;
368 u_long mend = (u_long)end;
369 if (mprotect((void *)mstart, mend - mstart,
370 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
371 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
372 #endif
373#endif
374}
375
376static void start_tcache_write(void *start, void *end)
377{
378 mprotect_w_x(start, end, 0);
379}
380
381static void end_tcache_write(void *start, void *end)
382{
383#if defined(__arm__) || defined(__aarch64__)
384 size_t len = (char *)end - (char *)start;
385 #if defined(__BLACKBERRY_QNX__)
386 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
387 #elif defined(__MACH__)
388 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
389 #elif defined(VITA)
390 sceKernelSyncVMDomain(sceBlock, start, len);
391 #elif defined(_3DS)
392 ctr_flush_invalidate_cache();
393 #elif defined(__aarch64__)
394 // as of 2021, __clear_cache() is still broken on arm64
395 // so here is a custom one :(
396 clear_cache_arm64(start, end);
397 #else
398 __clear_cache(start, end);
399 #endif
400 (void)len;
401#endif
402
403 mprotect_w_x(start, end, 1);
404}
405
406static void *start_block(void)
407{
408 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
409 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
410 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
411 start_tcache_write(out, end);
412 return out;
413}
414
415static void end_block(void *start)
416{
417 end_tcache_write(start, out);
418}
419
420// also takes care of w^x mappings when patching code
421static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
422
423static void mark_clear_cache(void *target)
424{
425 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
426 u_int mask = 1u << ((offset >> 12) & 31);
427 if (!(needs_clear_cache[offset >> 17] & mask)) {
428 char *start = (char *)((uintptr_t)target & ~4095l);
429 start_tcache_write(start, start + 4095);
430 needs_clear_cache[offset >> 17] |= mask;
431 }
432}
433
434// Clearing the cache is rather slow on ARM Linux, so mark the areas
435// that need to be cleared, and then only clear these areas once.
436static void do_clear_cache(void)
437{
438 int i, j;
439 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
440 {
441 u_int bitmap = needs_clear_cache[i];
442 if (!bitmap)
443 continue;
444 for (j = 0; j < 32; j++)
445 {
446 u_char *start, *end;
447 if (!(bitmap & (1<<j)))
448 continue;
449
450 start = ndrc->translation_cache + i*131072 + j*4096;
451 end = start + 4095;
452 for (j++; j < 32; j++) {
453 if (!(bitmap & (1<<j)))
454 break;
455 end += 4096;
456 }
457 end_tcache_write(start, end);
458 }
459 needs_clear_cache[i] = 0;
460 }
461}
462
463//#define DEBUG_CYCLE_COUNT 1
464
465#define NO_CYCLE_PENALTY_THR 12
466
467int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
468int cycle_multiplier_override;
469int cycle_multiplier_old;
470
471static int CLOCK_ADJUST(int x)
472{
473 int m = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
474 ? cycle_multiplier_override : cycle_multiplier;
475 int s=(x>>31)|1;
476 return (x * m + s * 50) / 100;
477}
478
479static int ds_writes_rjump_rs(int i)
480{
481 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
482}
483
484static u_int get_page(u_int vaddr)
485{
486 u_int page=vaddr&~0xe0000000;
487 if (page < 0x1000000)
488 page &= ~0x0e00000; // RAM mirrors
489 page>>=12;
490 if(page>2048) page=2048+(page&2047);
491 return page;
492}
493
494// no virtual mem in PCSX
495static u_int get_vpage(u_int vaddr)
496{
497 return get_page(vaddr);
498}
499
500static struct ht_entry *hash_table_get(u_int vaddr)
501{
502 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
503}
504
505static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
506{
507 ht_bin->vaddr[1] = ht_bin->vaddr[0];
508 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
509 ht_bin->vaddr[0] = vaddr;
510 ht_bin->tcaddr[0] = tcaddr;
511}
512
513// some messy ari64's code, seems to rely on unsigned 32bit overflow
514static int doesnt_expire_soon(void *tcaddr)
515{
516 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
517 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
518}
519
520// Get address from virtual address
521// This is called from the recompiled JR/JALR instructions
522void noinline *get_addr(u_int vaddr)
523{
524 u_int page=get_page(vaddr);
525 u_int vpage=get_vpage(vaddr);
526 struct ll_entry *head;
527 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
528 head=jump_in[page];
529 while(head!=NULL) {
530 if(head->vaddr==vaddr) {
531 //printf("TRACE: count=%d next=%d (get_addr match %x: %p)\n",Count,next_interupt,vaddr,head->addr);
532 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
533 return head->addr;
534 }
535 head=head->next;
536 }
537 head=jump_dirty[vpage];
538 while(head!=NULL) {
539 if(head->vaddr==vaddr) {
540 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %p)\n",Count,next_interupt,vaddr,head->addr);
541 // Don't restore blocks which are about to expire from the cache
542 if (doesnt_expire_soon(head->addr))
543 if (verify_dirty(head->addr)) {
544 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
545 invalid_code[vaddr>>12]=0;
546 inv_code_start=inv_code_end=~0;
547 if(vpage<2048) {
548 restore_candidate[vpage>>3]|=1<<(vpage&7);
549 }
550 else restore_candidate[page>>3]|=1<<(page&7);
551 struct ht_entry *ht_bin = hash_table_get(vaddr);
552 if (ht_bin->vaddr[0] == vaddr)
553 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
554 else
555 hash_table_add(ht_bin, vaddr, head->addr);
556
557 return head->addr;
558 }
559 }
560 head=head->next;
561 }
562 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
563 int r=new_recompile_block(vaddr);
564 if(r==0) return get_addr(vaddr);
565 // Execute in unmapped page, generate pagefault execption
566 Status|=2;
567 Cause=(vaddr<<31)|0x8;
568 EPC=(vaddr&1)?vaddr-5:vaddr;
569 BadVAddr=(vaddr&~1);
570 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
571 EntryHi=BadVAddr&0xFFFFE000;
572 return get_addr_ht(0x80000000);
573}
574// Look up address in hash table first
575void *get_addr_ht(u_int vaddr)
576{
577 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
578 const struct ht_entry *ht_bin = hash_table_get(vaddr);
579 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
580 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
581 return get_addr(vaddr);
582}
583
584void clear_all_regs(signed char regmap[])
585{
586 int hr;
587 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
588}
589
590static signed char get_reg(const signed char regmap[],int r)
591{
592 int hr;
593 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
594 return -1;
595}
596
597// Find a register that is available for two consecutive cycles
598static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
599{
600 int hr;
601 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
602 return -1;
603}
604
605int count_free_regs(signed char regmap[])
606{
607 int count=0;
608 int hr;
609 for(hr=0;hr<HOST_REGS;hr++)
610 {
611 if(hr!=EXCLUDE_REG) {
612 if(regmap[hr]<0) count++;
613 }
614 }
615 return count;
616}
617
618void dirty_reg(struct regstat *cur,signed char reg)
619{
620 int hr;
621 if(!reg) return;
622 for (hr=0;hr<HOST_REGS;hr++) {
623 if((cur->regmap[hr]&63)==reg) {
624 cur->dirty|=1<<hr;
625 }
626 }
627}
628
629static void set_const(struct regstat *cur, signed char reg, uint32_t value)
630{
631 int hr;
632 if(!reg) return;
633 for (hr=0;hr<HOST_REGS;hr++) {
634 if(cur->regmap[hr]==reg) {
635 cur->isconst|=1<<hr;
636 current_constmap[hr]=value;
637 }
638 }
639}
640
641static void clear_const(struct regstat *cur, signed char reg)
642{
643 int hr;
644 if(!reg) return;
645 for (hr=0;hr<HOST_REGS;hr++) {
646 if((cur->regmap[hr]&63)==reg) {
647 cur->isconst&=~(1<<hr);
648 }
649 }
650}
651
652static int is_const(struct regstat *cur, signed char reg)
653{
654 int hr;
655 if(reg<0) return 0;
656 if(!reg) return 1;
657 for (hr=0;hr<HOST_REGS;hr++) {
658 if((cur->regmap[hr]&63)==reg) {
659 return (cur->isconst>>hr)&1;
660 }
661 }
662 return 0;
663}
664
665static uint32_t get_const(struct regstat *cur, signed char reg)
666{
667 int hr;
668 if(!reg) return 0;
669 for (hr=0;hr<HOST_REGS;hr++) {
670 if(cur->regmap[hr]==reg) {
671 return current_constmap[hr];
672 }
673 }
674 SysPrintf("Unknown constant in r%d\n",reg);
675 abort();
676}
677
678// Least soon needed registers
679// Look at the next ten instructions and see which registers
680// will be used. Try not to reallocate these.
681void lsn(u_char hsn[], int i, int *preferred_reg)
682{
683 int j;
684 int b=-1;
685 for(j=0;j<9;j++)
686 {
687 if(i+j>=slen) {
688 j=slen-i-1;
689 break;
690 }
691 if (dops[i+j].is_ujump)
692 {
693 // Don't go past an unconditonal jump
694 j++;
695 break;
696 }
697 }
698 for(;j>=0;j--)
699 {
700 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
701 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
702 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
703 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
704 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
705 // Stores can allocate zero
706 hsn[dops[i+j].rs1]=j;
707 hsn[dops[i+j].rs2]=j;
708 }
709 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
710 hsn[ROREG] = j;
711 // On some architectures stores need invc_ptr
712 #if defined(HOST_IMM8)
713 if (dops[i+j].is_store)
714 hsn[INVCP] = j;
715 #endif
716 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
717 {
718 hsn[CCREG]=j;
719 b=j;
720 }
721 }
722 if(b>=0)
723 {
724 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
725 {
726 // Follow first branch
727 int t=(ba[i+b]-start)>>2;
728 j=7-b;if(t+j>=slen) j=slen-t-1;
729 for(;j>=0;j--)
730 {
731 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
732 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
733 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
734 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
735 }
736 }
737 // TODO: preferred register based on backward branch
738 }
739 // Delay slot should preferably not overwrite branch conditions or cycle count
740 if (i > 0 && dops[i-1].is_jump) {
741 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
742 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
743 hsn[CCREG]=1;
744 // ...or hash tables
745 hsn[RHASH]=1;
746 hsn[RHTBL]=1;
747 }
748 // Coprocessor load/store needs FTEMP, even if not declared
749 if(dops[i].itype==C2LS) {
750 hsn[FTEMP]=0;
751 }
752 // Load L/R also uses FTEMP as a temporary register
753 if(dops[i].itype==LOADLR) {
754 hsn[FTEMP]=0;
755 }
756 // Also SWL/SWR/SDL/SDR
757 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
758 hsn[FTEMP]=0;
759 }
760 // Don't remove the miniht registers
761 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
762 {
763 hsn[RHASH]=0;
764 hsn[RHTBL]=0;
765 }
766}
767
768// We only want to allocate registers if we're going to use them again soon
769int needed_again(int r, int i)
770{
771 int j;
772 int b=-1;
773 int rn=10;
774
775 if (i > 0 && dops[i-1].is_ujump)
776 {
777 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
778 return 0; // Don't need any registers if exiting the block
779 }
780 for(j=0;j<9;j++)
781 {
782 if(i+j>=slen) {
783 j=slen-i-1;
784 break;
785 }
786 if (dops[i+j].is_ujump)
787 {
788 // Don't go past an unconditonal jump
789 j++;
790 break;
791 }
792 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
793 {
794 break;
795 }
796 }
797 for(;j>=1;j--)
798 {
799 if(dops[i+j].rs1==r) rn=j;
800 if(dops[i+j].rs2==r) rn=j;
801 if((unneeded_reg[i+j]>>r)&1) rn=10;
802 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
803 {
804 b=j;
805 }
806 }
807 if(rn<10) return 1;
808 (void)b;
809 return 0;
810}
811
812// Try to match register allocations at the end of a loop with those
813// at the beginning
814int loop_reg(int i, int r, int hr)
815{
816 int j,k;
817 for(j=0;j<9;j++)
818 {
819 if(i+j>=slen) {
820 j=slen-i-1;
821 break;
822 }
823 if (dops[i+j].is_ujump)
824 {
825 // Don't go past an unconditonal jump
826 j++;
827 break;
828 }
829 }
830 k=0;
831 if(i>0){
832 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
833 k--;
834 }
835 for(;k<j;k++)
836 {
837 assert(r < 64);
838 if((unneeded_reg[i+k]>>r)&1) return hr;
839 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
840 {
841 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
842 {
843 int t=(ba[i+k]-start)>>2;
844 int reg=get_reg(regs[t].regmap_entry,r);
845 if(reg>=0) return reg;
846 //reg=get_reg(regs[t+1].regmap_entry,r);
847 //if(reg>=0) return reg;
848 }
849 }
850 }
851 return hr;
852}
853
854
855// Allocate every register, preserving source/target regs
856void alloc_all(struct regstat *cur,int i)
857{
858 int hr;
859
860 for(hr=0;hr<HOST_REGS;hr++) {
861 if(hr!=EXCLUDE_REG) {
862 if(((cur->regmap[hr]&63)!=dops[i].rs1)&&((cur->regmap[hr]&63)!=dops[i].rs2)&&
863 ((cur->regmap[hr]&63)!=dops[i].rt1)&&((cur->regmap[hr]&63)!=dops[i].rt2))
864 {
865 cur->regmap[hr]=-1;
866 cur->dirty&=~(1<<hr);
867 }
868 // Don't need zeros
869 if((cur->regmap[hr]&63)==0)
870 {
871 cur->regmap[hr]=-1;
872 cur->dirty&=~(1<<hr);
873 }
874 }
875 }
876}
877
878#ifndef NDEBUG
879static int host_tempreg_in_use;
880
881static void host_tempreg_acquire(void)
882{
883 assert(!host_tempreg_in_use);
884 host_tempreg_in_use = 1;
885}
886
887static void host_tempreg_release(void)
888{
889 host_tempreg_in_use = 0;
890}
891#else
892static void host_tempreg_acquire(void) {}
893static void host_tempreg_release(void) {}
894#endif
895
896#ifdef ASSEM_PRINT
897extern void gen_interupt();
898extern void do_insn_cmp();
899#define FUNCNAME(f) { f, " " #f }
900static const struct {
901 void *addr;
902 const char *name;
903} function_names[] = {
904 FUNCNAME(cc_interrupt),
905 FUNCNAME(gen_interupt),
906 FUNCNAME(get_addr_ht),
907 FUNCNAME(get_addr),
908 FUNCNAME(jump_handler_read8),
909 FUNCNAME(jump_handler_read16),
910 FUNCNAME(jump_handler_read32),
911 FUNCNAME(jump_handler_write8),
912 FUNCNAME(jump_handler_write16),
913 FUNCNAME(jump_handler_write32),
914 FUNCNAME(invalidate_addr),
915 FUNCNAME(jump_to_new_pc),
916 FUNCNAME(call_gteStall),
917 FUNCNAME(new_dyna_leave),
918 FUNCNAME(pcsx_mtc0),
919 FUNCNAME(pcsx_mtc0_ds),
920#ifdef DRC_DBG
921 FUNCNAME(do_insn_cmp),
922#endif
923#ifdef __arm__
924 FUNCNAME(verify_code),
925#endif
926};
927
928static const char *func_name(const void *a)
929{
930 int i;
931 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
932 if (function_names[i].addr == a)
933 return function_names[i].name;
934 return "";
935}
936#else
937#define func_name(x) ""
938#endif
939
940#ifdef __i386__
941#include "assem_x86.c"
942#endif
943#ifdef __x86_64__
944#include "assem_x64.c"
945#endif
946#ifdef __arm__
947#include "assem_arm.c"
948#endif
949#ifdef __aarch64__
950#include "assem_arm64.c"
951#endif
952
953static void *get_trampoline(const void *f)
954{
955 size_t i;
956
957 for (i = 0; i < ARRAY_SIZE(ndrc->tramp.f); i++) {
958 if (ndrc->tramp.f[i] == f || ndrc->tramp.f[i] == NULL)
959 break;
960 }
961 if (i == ARRAY_SIZE(ndrc->tramp.f)) {
962 SysPrintf("trampoline table is full, last func %p\n", f);
963 abort();
964 }
965 if (ndrc->tramp.f[i] == NULL) {
966 start_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
967 ndrc->tramp.f[i] = f;
968 end_tcache_write(&ndrc->tramp.f[i], &ndrc->tramp.f[i + 1]);
969 }
970 return &ndrc->tramp.ops[i];
971}
972
973static void emit_far_jump(const void *f)
974{
975 if (can_jump_or_call(f)) {
976 emit_jmp(f);
977 return;
978 }
979
980 f = get_trampoline(f);
981 emit_jmp(f);
982}
983
984static void emit_far_call(const void *f)
985{
986 if (can_jump_or_call(f)) {
987 emit_call(f);
988 return;
989 }
990
991 f = get_trampoline(f);
992 emit_call(f);
993}
994
995// Add virtual address mapping to linked list
996void ll_add(struct ll_entry **head,int vaddr,void *addr)
997{
998 struct ll_entry *new_entry;
999 new_entry=malloc(sizeof(struct ll_entry));
1000 assert(new_entry!=NULL);
1001 new_entry->vaddr=vaddr;
1002 new_entry->reg_sv_flags=0;
1003 new_entry->addr=addr;
1004 new_entry->next=*head;
1005 *head=new_entry;
1006}
1007
1008void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
1009{
1010 ll_add(head,vaddr,addr);
1011 (*head)->reg_sv_flags=reg_sv_flags;
1012}
1013
1014// Check if an address is already compiled
1015// but don't return addresses which are about to expire from the cache
1016void *check_addr(u_int vaddr)
1017{
1018 struct ht_entry *ht_bin = hash_table_get(vaddr);
1019 size_t i;
1020 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1021 if (ht_bin->vaddr[i] == vaddr)
1022 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
1023 if (isclean(ht_bin->tcaddr[i]))
1024 return ht_bin->tcaddr[i];
1025 }
1026 u_int page=get_page(vaddr);
1027 struct ll_entry *head;
1028 head=jump_in[page];
1029 while (head != NULL) {
1030 if (head->vaddr == vaddr) {
1031 if (doesnt_expire_soon(head->addr)) {
1032 // Update existing entry with current address
1033 if (ht_bin->vaddr[0] == vaddr) {
1034 ht_bin->tcaddr[0] = head->addr;
1035 return head->addr;
1036 }
1037 if (ht_bin->vaddr[1] == vaddr) {
1038 ht_bin->tcaddr[1] = head->addr;
1039 return head->addr;
1040 }
1041 // Insert into hash table with low priority.
1042 // Don't evict existing entries, as they are probably
1043 // addresses that are being accessed frequently.
1044 if (ht_bin->vaddr[0] == -1) {
1045 ht_bin->vaddr[0] = vaddr;
1046 ht_bin->tcaddr[0] = head->addr;
1047 }
1048 else if (ht_bin->vaddr[1] == -1) {
1049 ht_bin->vaddr[1] = vaddr;
1050 ht_bin->tcaddr[1] = head->addr;
1051 }
1052 return head->addr;
1053 }
1054 }
1055 head=head->next;
1056 }
1057 return 0;
1058}
1059
1060void remove_hash(int vaddr)
1061{
1062 //printf("remove hash: %x\n",vaddr);
1063 struct ht_entry *ht_bin = hash_table_get(vaddr);
1064 if (ht_bin->vaddr[1] == vaddr) {
1065 ht_bin->vaddr[1] = -1;
1066 ht_bin->tcaddr[1] = NULL;
1067 }
1068 if (ht_bin->vaddr[0] == vaddr) {
1069 ht_bin->vaddr[0] = ht_bin->vaddr[1];
1070 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
1071 ht_bin->vaddr[1] = -1;
1072 ht_bin->tcaddr[1] = NULL;
1073 }
1074}
1075
1076static void ll_remove_matching_addrs(struct ll_entry **head,
1077 uintptr_t base_offs_s, int shift)
1078{
1079 struct ll_entry *next;
1080 while(*head) {
1081 uintptr_t o1 = (u_char *)(*head)->addr - ndrc->translation_cache;
1082 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1083 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1084 {
1085 inv_debug("EXP: Remove pointer to %p (%x)\n",(*head)->addr,(*head)->vaddr);
1086 remove_hash((*head)->vaddr);
1087 next=(*head)->next;
1088 free(*head);
1089 *head=next;
1090 }
1091 else
1092 {
1093 head=&((*head)->next);
1094 }
1095 }
1096}
1097
1098// Remove all entries from linked list
1099void ll_clear(struct ll_entry **head)
1100{
1101 struct ll_entry *cur;
1102 struct ll_entry *next;
1103 if((cur=*head)) {
1104 *head=0;
1105 while(cur) {
1106 next=cur->next;
1107 free(cur);
1108 cur=next;
1109 }
1110 }
1111}
1112
1113// Dereference the pointers and remove if it matches
1114static void ll_kill_pointers(struct ll_entry *head,
1115 uintptr_t base_offs_s, int shift)
1116{
1117 while(head) {
1118 u_char *ptr = get_pointer(head->addr);
1119 uintptr_t o1 = ptr - ndrc->translation_cache;
1120 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
1121 inv_debug("EXP: Lookup pointer to %p at %p (%x)\n",ptr,head->addr,head->vaddr);
1122 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s)
1123 {
1124 inv_debug("EXP: Kill pointer at %p (%x)\n",head->addr,head->vaddr);
1125 void *host_addr=find_extjump_insn(head->addr);
1126 mark_clear_cache(host_addr);
1127 set_jump_target(host_addr, head->addr);
1128 }
1129 head=head->next;
1130 }
1131}
1132
1133// This is called when we write to a compiled block (see do_invstub)
1134static void invalidate_page(u_int page)
1135{
1136 struct ll_entry *head;
1137 struct ll_entry *next;
1138 head=jump_in[page];
1139 jump_in[page]=0;
1140 while(head!=NULL) {
1141 inv_debug("INVALIDATE: %x\n",head->vaddr);
1142 remove_hash(head->vaddr);
1143 next=head->next;
1144 free(head);
1145 head=next;
1146 }
1147 head=jump_out[page];
1148 jump_out[page]=0;
1149 while(head!=NULL) {
1150 inv_debug("INVALIDATE: kill pointer to %x (%p)\n",head->vaddr,head->addr);
1151 void *host_addr=find_extjump_insn(head->addr);
1152 mark_clear_cache(host_addr);
1153 set_jump_target(host_addr, head->addr); // point back to dyna_linker
1154 next=head->next;
1155 free(head);
1156 head=next;
1157 }
1158}
1159
1160static void invalidate_block_range(u_int block, u_int first, u_int last)
1161{
1162 u_int page=get_page(block<<12);
1163 //printf("first=%d last=%d\n",first,last);
1164 invalidate_page(page);
1165 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1166 assert(last<page+5);
1167 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 while(first<page) {
1169 invalidate_page(first);
1170 first++;
1171 }
1172 for(first=page+1;first<last;first++) {
1173 invalidate_page(first);
1174 }
1175 do_clear_cache();
1176
1177 // Don't trap writes
1178 invalid_code[block]=1;
1179
1180 #ifdef USE_MINI_HT
1181 memset(mini_ht,-1,sizeof(mini_ht));
1182 #endif
1183}
1184
1185void invalidate_block(u_int block)
1186{
1187 u_int page=get_page(block<<12);
1188 u_int vpage=get_vpage(block<<12);
1189 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1190 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1191 u_int first,last;
1192 first=last=page;
1193 struct ll_entry *head;
1194 head=jump_dirty[vpage];
1195 //printf("page=%d vpage=%d\n",page,vpage);
1196 while(head!=NULL) {
1197 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1198 u_char *start, *end;
1199 get_bounds(head->addr, &start, &end);
1200 //printf("start: %p end: %p\n", start, end);
1201 if (page < 2048 && start >= rdram && end < rdram+RAM_SIZE) {
1202 if (((start-rdram)>>12) <= page && ((end-1-rdram)>>12) >= page) {
1203 if ((((start-rdram)>>12)&2047) < first) first = ((start-rdram)>>12)&2047;
1204 if ((((end-1-rdram)>>12)&2047) > last) last = ((end-1-rdram)>>12)&2047;
1205 }
1206 }
1207 }
1208 head=head->next;
1209 }
1210 invalidate_block_range(block,first,last);
1211}
1212
1213void invalidate_addr(u_int addr)
1214{
1215 //static int rhits;
1216 // this check is done by the caller
1217 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1218 u_int page=get_vpage(addr);
1219 if(page<2048) { // RAM
1220 struct ll_entry *head;
1221 u_int addr_min=~0, addr_max=0;
1222 u_int mask=RAM_SIZE-1;
1223 u_int addr_main=0x80000000|(addr&mask);
1224 int pg1;
1225 inv_code_start=addr_main&~0xfff;
1226 inv_code_end=addr_main|0xfff;
1227 pg1=page;
1228 if (pg1>0) {
1229 // must check previous page too because of spans..
1230 pg1--;
1231 inv_code_start-=0x1000;
1232 }
1233 for(;pg1<=page;pg1++) {
1234 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1235 u_char *start_h, *end_h;
1236 u_int start, end;
1237 get_bounds(head->addr, &start_h, &end_h);
1238 start = (uintptr_t)start_h - ram_offset;
1239 end = (uintptr_t)end_h - ram_offset;
1240 if(start<=addr_main&&addr_main<end) {
1241 if(start<addr_min) addr_min=start;
1242 if(end>addr_max) addr_max=end;
1243 }
1244 else if(addr_main<start) {
1245 if(start<inv_code_end)
1246 inv_code_end=start-1;
1247 }
1248 else {
1249 if(end>inv_code_start)
1250 inv_code_start=end;
1251 }
1252 }
1253 }
1254 if (addr_min!=~0) {
1255 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1256 inv_code_start=inv_code_end=~0;
1257 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1258 return;
1259 }
1260 else {
1261 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1262 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1263 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1264 return;
1265 }
1266 }
1267 invalidate_block(addr>>12);
1268}
1269
1270// This is called when loading a save state.
1271// Anything could have changed, so invalidate everything.
1272void invalidate_all_pages(void)
1273{
1274 u_int page;
1275 for(page=0;page<4096;page++)
1276 invalidate_page(page);
1277 for(page=0;page<1048576;page++)
1278 if(!invalid_code[page]) {
1279 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1280 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1281 }
1282 #ifdef USE_MINI_HT
1283 memset(mini_ht,-1,sizeof(mini_ht));
1284 #endif
1285 do_clear_cache();
1286}
1287
1288static void do_invstub(int n)
1289{
1290 literal_pool(20);
1291 u_int reglist=stubs[n].a;
1292 set_jump_target(stubs[n].addr, out);
1293 save_regs(reglist);
1294 if(stubs[n].b!=0) emit_mov(stubs[n].b,0);
1295 emit_far_call(invalidate_addr);
1296 restore_regs(reglist);
1297 emit_jmp(stubs[n].retaddr); // return address
1298}
1299
1300// Add an entry to jump_out after making a link
1301// src should point to code by emit_extjump2()
1302void add_jump_out(u_int vaddr,void *src)
1303{
1304 u_int page=get_page(vaddr);
1305 inv_debug("add_jump_out: %p -> %x (%d)\n",src,vaddr,page);
1306 check_extjump2(src);
1307 ll_add(jump_out+page,vaddr,src);
1308 //inv_debug("add_jump_out: to %p\n",get_pointer(src));
1309}
1310
1311// If a code block was found to be unmodified (bit was set in
1312// restore_candidate) and it remains unmodified (bit is clear
1313// in invalid_code) then move the entries for that 4K page from
1314// the dirty list to the clean list.
1315void clean_blocks(u_int page)
1316{
1317 struct ll_entry *head;
1318 inv_debug("INV: clean_blocks page=%d\n",page);
1319 head=jump_dirty[page];
1320 while(head!=NULL) {
1321 if(!invalid_code[head->vaddr>>12]) {
1322 // Don't restore blocks which are about to expire from the cache
1323 if (doesnt_expire_soon(head->addr)) {
1324 if(verify_dirty(head->addr)) {
1325 u_char *start, *end;
1326 //printf("Possibly Restore %x (%p)\n",head->vaddr, head->addr);
1327 u_int i;
1328 u_int inv=0;
1329 get_bounds(head->addr, &start, &end);
1330 if (start - rdram < RAM_SIZE) {
1331 for (i = (start-rdram+0x80000000)>>12; i <= (end-1-rdram+0x80000000)>>12; i++) {
1332 inv|=invalid_code[i];
1333 }
1334 }
1335 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1336 inv=1;
1337 }
1338 if(!inv) {
1339 void *clean_addr = get_clean_addr(head->addr);
1340 if (doesnt_expire_soon(clean_addr)) {
1341 u_int ppage=page;
1342 inv_debug("INV: Restored %x (%p/%p)\n",head->vaddr, head->addr, clean_addr);
1343 //printf("page=%x, addr=%x\n",page,head->vaddr);
1344 //assert(head->vaddr>>12==(page|0x80000));
1345 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1346 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1347 if (ht_bin->vaddr[0] == head->vaddr)
1348 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1349 if (ht_bin->vaddr[1] == head->vaddr)
1350 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1351 }
1352 }
1353 }
1354 }
1355 }
1356 head=head->next;
1357 }
1358}
1359
1360/* Register allocation */
1361
1362// Note: registers are allocated clean (unmodified state)
1363// if you intend to modify the register, you must call dirty_reg().
1364static void alloc_reg(struct regstat *cur,int i,signed char reg)
1365{
1366 int r,hr;
1367 int preferred_reg = PREFERRED_REG_FIRST
1368 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1369 if (reg == CCREG) preferred_reg = HOST_CCREG;
1370 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1371 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1372
1373 // Don't allocate unused registers
1374 if((cur->u>>reg)&1) return;
1375
1376 // see if it's already allocated
1377 for(hr=0;hr<HOST_REGS;hr++)
1378 {
1379 if(cur->regmap[hr]==reg) return;
1380 }
1381
1382 // Keep the same mapping if the register was already allocated in a loop
1383 preferred_reg = loop_reg(i,reg,preferred_reg);
1384
1385 // Try to allocate the preferred register
1386 if(cur->regmap[preferred_reg]==-1) {
1387 cur->regmap[preferred_reg]=reg;
1388 cur->dirty&=~(1<<preferred_reg);
1389 cur->isconst&=~(1<<preferred_reg);
1390 return;
1391 }
1392 r=cur->regmap[preferred_reg];
1393 assert(r < 64);
1394 if((cur->u>>r)&1) {
1395 cur->regmap[preferred_reg]=reg;
1396 cur->dirty&=~(1<<preferred_reg);
1397 cur->isconst&=~(1<<preferred_reg);
1398 return;
1399 }
1400
1401 // Clear any unneeded registers
1402 // We try to keep the mapping consistent, if possible, because it
1403 // makes branches easier (especially loops). So we try to allocate
1404 // first (see above) before removing old mappings. If this is not
1405 // possible then go ahead and clear out the registers that are no
1406 // longer needed.
1407 for(hr=0;hr<HOST_REGS;hr++)
1408 {
1409 r=cur->regmap[hr];
1410 if(r>=0) {
1411 assert(r < 64);
1412 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1413 }
1414 }
1415
1416 // Try to allocate any available register, but prefer
1417 // registers that have not been used recently.
1418 if (i > 0) {
1419 for (hr = PREFERRED_REG_FIRST; ; ) {
1420 if (cur->regmap[hr] < 0) {
1421 int oldreg = regs[i-1].regmap[hr];
1422 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1423 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1424 {
1425 cur->regmap[hr]=reg;
1426 cur->dirty&=~(1<<hr);
1427 cur->isconst&=~(1<<hr);
1428 return;
1429 }
1430 }
1431 hr++;
1432 if (hr == EXCLUDE_REG)
1433 hr++;
1434 if (hr == HOST_REGS)
1435 hr = 0;
1436 if (hr == PREFERRED_REG_FIRST)
1437 break;
1438 }
1439 }
1440
1441 // Try to allocate any available register
1442 for (hr = PREFERRED_REG_FIRST; ; ) {
1443 if (cur->regmap[hr] < 0) {
1444 cur->regmap[hr]=reg;
1445 cur->dirty&=~(1<<hr);
1446 cur->isconst&=~(1<<hr);
1447 return;
1448 }
1449 hr++;
1450 if (hr == EXCLUDE_REG)
1451 hr++;
1452 if (hr == HOST_REGS)
1453 hr = 0;
1454 if (hr == PREFERRED_REG_FIRST)
1455 break;
1456 }
1457
1458 // Ok, now we have to evict someone
1459 // Pick a register we hopefully won't need soon
1460 u_char hsn[MAXREG+1];
1461 memset(hsn,10,sizeof(hsn));
1462 int j;
1463 lsn(hsn,i,&preferred_reg);
1464 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1465 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1466 if(i>0) {
1467 // Don't evict the cycle count at entry points, otherwise the entry
1468 // stub will have to write it.
1469 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1470 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1471 for(j=10;j>=3;j--)
1472 {
1473 // Alloc preferred register if available
1474 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1475 for(hr=0;hr<HOST_REGS;hr++) {
1476 // Evict both parts of a 64-bit register
1477 if((cur->regmap[hr]&63)==r) {
1478 cur->regmap[hr]=-1;
1479 cur->dirty&=~(1<<hr);
1480 cur->isconst&=~(1<<hr);
1481 }
1482 }
1483 cur->regmap[preferred_reg]=reg;
1484 return;
1485 }
1486 for(r=1;r<=MAXREG;r++)
1487 {
1488 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1489 for(hr=0;hr<HOST_REGS;hr++) {
1490 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1491 if(cur->regmap[hr]==r) {
1492 cur->regmap[hr]=reg;
1493 cur->dirty&=~(1<<hr);
1494 cur->isconst&=~(1<<hr);
1495 return;
1496 }
1497 }
1498 }
1499 }
1500 }
1501 }
1502 }
1503 for(j=10;j>=0;j--)
1504 {
1505 for(r=1;r<=MAXREG;r++)
1506 {
1507 if(hsn[r]==j) {
1508 for(hr=0;hr<HOST_REGS;hr++) {
1509 if(cur->regmap[hr]==r) {
1510 cur->regmap[hr]=reg;
1511 cur->dirty&=~(1<<hr);
1512 cur->isconst&=~(1<<hr);
1513 return;
1514 }
1515 }
1516 }
1517 }
1518 }
1519 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1520}
1521
1522// Allocate a temporary register. This is done without regard to
1523// dirty status or whether the register we request is on the unneeded list
1524// Note: This will only allocate one register, even if called multiple times
1525static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1526{
1527 int r,hr;
1528 int preferred_reg = -1;
1529
1530 // see if it's already allocated
1531 for(hr=0;hr<HOST_REGS;hr++)
1532 {
1533 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1534 }
1535
1536 // Try to allocate any available register
1537 for(hr=HOST_REGS-1;hr>=0;hr--) {
1538 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1539 cur->regmap[hr]=reg;
1540 cur->dirty&=~(1<<hr);
1541 cur->isconst&=~(1<<hr);
1542 return;
1543 }
1544 }
1545
1546 // Find an unneeded register
1547 for(hr=HOST_REGS-1;hr>=0;hr--)
1548 {
1549 r=cur->regmap[hr];
1550 if(r>=0) {
1551 assert(r < 64);
1552 if((cur->u>>r)&1) {
1553 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1554 cur->regmap[hr]=reg;
1555 cur->dirty&=~(1<<hr);
1556 cur->isconst&=~(1<<hr);
1557 return;
1558 }
1559 }
1560 }
1561 }
1562
1563 // Ok, now we have to evict someone
1564 // Pick a register we hopefully won't need soon
1565 // TODO: we might want to follow unconditional jumps here
1566 // TODO: get rid of dupe code and make this into a function
1567 u_char hsn[MAXREG+1];
1568 memset(hsn,10,sizeof(hsn));
1569 int j;
1570 lsn(hsn,i,&preferred_reg);
1571 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1572 if(i>0) {
1573 // Don't evict the cycle count at entry points, otherwise the entry
1574 // stub will have to write it.
1575 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1576 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1577 for(j=10;j>=3;j--)
1578 {
1579 for(r=1;r<=MAXREG;r++)
1580 {
1581 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1582 for(hr=0;hr<HOST_REGS;hr++) {
1583 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1584 if(cur->regmap[hr]==r) {
1585 cur->regmap[hr]=reg;
1586 cur->dirty&=~(1<<hr);
1587 cur->isconst&=~(1<<hr);
1588 return;
1589 }
1590 }
1591 }
1592 }
1593 }
1594 }
1595 }
1596 for(j=10;j>=0;j--)
1597 {
1598 for(r=1;r<=MAXREG;r++)
1599 {
1600 if(hsn[r]==j) {
1601 for(hr=0;hr<HOST_REGS;hr++) {
1602 if(cur->regmap[hr]==r) {
1603 cur->regmap[hr]=reg;
1604 cur->dirty&=~(1<<hr);
1605 cur->isconst&=~(1<<hr);
1606 return;
1607 }
1608 }
1609 }
1610 }
1611 }
1612 SysPrintf("This shouldn't happen");abort();
1613}
1614
1615static void mov_alloc(struct regstat *current,int i)
1616{
1617 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1618 // logically this is needed but just won't work, no idea why
1619 //alloc_cc(current,i); // for stalls
1620 //dirty_reg(current,CCREG);
1621 }
1622
1623 // Note: Don't need to actually alloc the source registers
1624 //alloc_reg(current,i,dops[i].rs1);
1625 alloc_reg(current,i,dops[i].rt1);
1626
1627 clear_const(current,dops[i].rs1);
1628 clear_const(current,dops[i].rt1);
1629 dirty_reg(current,dops[i].rt1);
1630}
1631
1632static void shiftimm_alloc(struct regstat *current,int i)
1633{
1634 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1635 {
1636 if(dops[i].rt1) {
1637 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1638 else dops[i].lt1=dops[i].rs1;
1639 alloc_reg(current,i,dops[i].rt1);
1640 dirty_reg(current,dops[i].rt1);
1641 if(is_const(current,dops[i].rs1)) {
1642 int v=get_const(current,dops[i].rs1);
1643 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1644 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1645 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1646 }
1647 else clear_const(current,dops[i].rt1);
1648 }
1649 }
1650 else
1651 {
1652 clear_const(current,dops[i].rs1);
1653 clear_const(current,dops[i].rt1);
1654 }
1655
1656 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1657 {
1658 assert(0);
1659 }
1660 if(dops[i].opcode2==0x3c) // DSLL32
1661 {
1662 assert(0);
1663 }
1664 if(dops[i].opcode2==0x3e) // DSRL32
1665 {
1666 assert(0);
1667 }
1668 if(dops[i].opcode2==0x3f) // DSRA32
1669 {
1670 assert(0);
1671 }
1672}
1673
1674static void shift_alloc(struct regstat *current,int i)
1675{
1676 if(dops[i].rt1) {
1677 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1678 {
1679 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1680 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1681 alloc_reg(current,i,dops[i].rt1);
1682 if(dops[i].rt1==dops[i].rs2) {
1683 alloc_reg_temp(current,i,-1);
1684 minimum_free_regs[i]=1;
1685 }
1686 } else { // DSLLV/DSRLV/DSRAV
1687 assert(0);
1688 }
1689 clear_const(current,dops[i].rs1);
1690 clear_const(current,dops[i].rs2);
1691 clear_const(current,dops[i].rt1);
1692 dirty_reg(current,dops[i].rt1);
1693 }
1694}
1695
1696static void alu_alloc(struct regstat *current,int i)
1697{
1698 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1699 if(dops[i].rt1) {
1700 if(dops[i].rs1&&dops[i].rs2) {
1701 alloc_reg(current,i,dops[i].rs1);
1702 alloc_reg(current,i,dops[i].rs2);
1703 }
1704 else {
1705 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1706 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1707 }
1708 alloc_reg(current,i,dops[i].rt1);
1709 }
1710 }
1711 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1712 if(dops[i].rt1) {
1713 alloc_reg(current,i,dops[i].rs1);
1714 alloc_reg(current,i,dops[i].rs2);
1715 alloc_reg(current,i,dops[i].rt1);
1716 }
1717 }
1718 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1719 if(dops[i].rt1) {
1720 if(dops[i].rs1&&dops[i].rs2) {
1721 alloc_reg(current,i,dops[i].rs1);
1722 alloc_reg(current,i,dops[i].rs2);
1723 }
1724 else
1725 {
1726 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1727 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1728 }
1729 alloc_reg(current,i,dops[i].rt1);
1730 }
1731 }
1732 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1733 assert(0);
1734 }
1735 clear_const(current,dops[i].rs1);
1736 clear_const(current,dops[i].rs2);
1737 clear_const(current,dops[i].rt1);
1738 dirty_reg(current,dops[i].rt1);
1739}
1740
1741static void imm16_alloc(struct regstat *current,int i)
1742{
1743 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1744 else dops[i].lt1=dops[i].rs1;
1745 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1746 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1747 assert(0);
1748 }
1749 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1750 clear_const(current,dops[i].rs1);
1751 clear_const(current,dops[i].rt1);
1752 }
1753 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1754 if(is_const(current,dops[i].rs1)) {
1755 int v=get_const(current,dops[i].rs1);
1756 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1757 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1758 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1759 }
1760 else clear_const(current,dops[i].rt1);
1761 }
1762 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1763 if(is_const(current,dops[i].rs1)) {
1764 int v=get_const(current,dops[i].rs1);
1765 set_const(current,dops[i].rt1,v+imm[i]);
1766 }
1767 else clear_const(current,dops[i].rt1);
1768 }
1769 else {
1770 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1771 }
1772 dirty_reg(current,dops[i].rt1);
1773}
1774
1775static void load_alloc(struct regstat *current,int i)
1776{
1777 clear_const(current,dops[i].rt1);
1778 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1779 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1780 if (needed_again(dops[i].rs1, i))
1781 alloc_reg(current, i, dops[i].rs1);
1782 if (ram_offset)
1783 alloc_reg(current, i, ROREG);
1784 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1785 alloc_reg(current,i,dops[i].rt1);
1786 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1787 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1788 {
1789 assert(0);
1790 }
1791 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1792 {
1793 assert(0);
1794 }
1795 dirty_reg(current,dops[i].rt1);
1796 // LWL/LWR need a temporary register for the old value
1797 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1798 {
1799 alloc_reg(current,i,FTEMP);
1800 alloc_reg_temp(current,i,-1);
1801 minimum_free_regs[i]=1;
1802 }
1803 }
1804 else
1805 {
1806 // Load to r0 or unneeded register (dummy load)
1807 // but we still need a register to calculate the address
1808 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
1809 {
1810 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1811 }
1812 alloc_reg_temp(current,i,-1);
1813 minimum_free_regs[i]=1;
1814 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
1815 {
1816 assert(0);
1817 }
1818 }
1819}
1820
1821void store_alloc(struct regstat *current,int i)
1822{
1823 clear_const(current,dops[i].rs2);
1824 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
1825 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1826 alloc_reg(current,i,dops[i].rs2);
1827 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
1828 assert(0);
1829 }
1830 if (ram_offset)
1831 alloc_reg(current, i, ROREG);
1832 #if defined(HOST_IMM8)
1833 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1834 alloc_reg(current, i, INVCP);
1835 #endif
1836 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
1837 alloc_reg(current,i,FTEMP);
1838 }
1839 // We need a temporary register for address generation
1840 alloc_reg_temp(current,i,-1);
1841 minimum_free_regs[i]=1;
1842}
1843
1844void c1ls_alloc(struct regstat *current,int i)
1845{
1846 clear_const(current,dops[i].rt1);
1847 alloc_reg(current,i,CSREG); // Status
1848}
1849
1850void c2ls_alloc(struct regstat *current,int i)
1851{
1852 clear_const(current,dops[i].rt1);
1853 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1854 alloc_reg(current,i,FTEMP);
1855 if (ram_offset)
1856 alloc_reg(current, i, ROREG);
1857 #if defined(HOST_IMM8)
1858 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1859 if (dops[i].opcode == 0x3a) // SWC2
1860 alloc_reg(current,i,INVCP);
1861 #endif
1862 // We need a temporary register for address generation
1863 alloc_reg_temp(current,i,-1);
1864 minimum_free_regs[i]=1;
1865}
1866
1867#ifndef multdiv_alloc
1868void multdiv_alloc(struct regstat *current,int i)
1869{
1870 // case 0x18: MULT
1871 // case 0x19: MULTU
1872 // case 0x1A: DIV
1873 // case 0x1B: DIVU
1874 // case 0x1C: DMULT
1875 // case 0x1D: DMULTU
1876 // case 0x1E: DDIV
1877 // case 0x1F: DDIVU
1878 clear_const(current,dops[i].rs1);
1879 clear_const(current,dops[i].rs2);
1880 alloc_cc(current,i); // for stalls
1881 if(dops[i].rs1&&dops[i].rs2)
1882 {
1883 if((dops[i].opcode2&4)==0) // 32-bit
1884 {
1885 current->u&=~(1LL<<HIREG);
1886 current->u&=~(1LL<<LOREG);
1887 alloc_reg(current,i,HIREG);
1888 alloc_reg(current,i,LOREG);
1889 alloc_reg(current,i,dops[i].rs1);
1890 alloc_reg(current,i,dops[i].rs2);
1891 dirty_reg(current,HIREG);
1892 dirty_reg(current,LOREG);
1893 }
1894 else // 64-bit
1895 {
1896 assert(0);
1897 }
1898 }
1899 else
1900 {
1901 // Multiply by zero is zero.
1902 // MIPS does not have a divide by zero exception.
1903 // The result is undefined, we return zero.
1904 alloc_reg(current,i,HIREG);
1905 alloc_reg(current,i,LOREG);
1906 dirty_reg(current,HIREG);
1907 dirty_reg(current,LOREG);
1908 }
1909}
1910#endif
1911
1912void cop0_alloc(struct regstat *current,int i)
1913{
1914 if(dops[i].opcode2==0) // MFC0
1915 {
1916 if(dops[i].rt1) {
1917 clear_const(current,dops[i].rt1);
1918 alloc_all(current,i);
1919 alloc_reg(current,i,dops[i].rt1);
1920 dirty_reg(current,dops[i].rt1);
1921 }
1922 }
1923 else if(dops[i].opcode2==4) // MTC0
1924 {
1925 if(dops[i].rs1){
1926 clear_const(current,dops[i].rs1);
1927 alloc_reg(current,i,dops[i].rs1);
1928 alloc_all(current,i);
1929 }
1930 else {
1931 alloc_all(current,i); // FIXME: Keep r0
1932 current->u&=~1LL;
1933 alloc_reg(current,i,0);
1934 }
1935 }
1936 else
1937 {
1938 // TLBR/TLBWI/TLBWR/TLBP/ERET
1939 assert(dops[i].opcode2==0x10);
1940 alloc_all(current,i);
1941 }
1942 minimum_free_regs[i]=HOST_REGS;
1943}
1944
1945static void cop2_alloc(struct regstat *current,int i)
1946{
1947 if (dops[i].opcode2 < 3) // MFC2/CFC2
1948 {
1949 alloc_cc(current,i); // for stalls
1950 dirty_reg(current,CCREG);
1951 if(dops[i].rt1){
1952 clear_const(current,dops[i].rt1);
1953 alloc_reg(current,i,dops[i].rt1);
1954 dirty_reg(current,dops[i].rt1);
1955 }
1956 }
1957 else if (dops[i].opcode2 > 3) // MTC2/CTC2
1958 {
1959 if(dops[i].rs1){
1960 clear_const(current,dops[i].rs1);
1961 alloc_reg(current,i,dops[i].rs1);
1962 }
1963 else {
1964 current->u&=~1LL;
1965 alloc_reg(current,i,0);
1966 }
1967 }
1968 alloc_reg_temp(current,i,-1);
1969 minimum_free_regs[i]=1;
1970}
1971
1972void c2op_alloc(struct regstat *current,int i)
1973{
1974 alloc_cc(current,i); // for stalls
1975 dirty_reg(current,CCREG);
1976 alloc_reg_temp(current,i,-1);
1977}
1978
1979void syscall_alloc(struct regstat *current,int i)
1980{
1981 alloc_cc(current,i);
1982 dirty_reg(current,CCREG);
1983 alloc_all(current,i);
1984 minimum_free_regs[i]=HOST_REGS;
1985 current->isconst=0;
1986}
1987
1988void delayslot_alloc(struct regstat *current,int i)
1989{
1990 switch(dops[i].itype) {
1991 case UJUMP:
1992 case CJUMP:
1993 case SJUMP:
1994 case RJUMP:
1995 case SYSCALL:
1996 case HLECALL:
1997 case SPAN:
1998 assem_debug("jump in the delay slot. this shouldn't happen.\n");//abort();
1999 SysPrintf("Disabled speculative precompilation\n");
2000 stop_after_jal=1;
2001 break;
2002 case IMM16:
2003 imm16_alloc(current,i);
2004 break;
2005 case LOAD:
2006 case LOADLR:
2007 load_alloc(current,i);
2008 break;
2009 case STORE:
2010 case STORELR:
2011 store_alloc(current,i);
2012 break;
2013 case ALU:
2014 alu_alloc(current,i);
2015 break;
2016 case SHIFT:
2017 shift_alloc(current,i);
2018 break;
2019 case MULTDIV:
2020 multdiv_alloc(current,i);
2021 break;
2022 case SHIFTIMM:
2023 shiftimm_alloc(current,i);
2024 break;
2025 case MOV:
2026 mov_alloc(current,i);
2027 break;
2028 case COP0:
2029 cop0_alloc(current,i);
2030 break;
2031 case COP1:
2032 break;
2033 case COP2:
2034 cop2_alloc(current,i);
2035 break;
2036 case C1LS:
2037 c1ls_alloc(current,i);
2038 break;
2039 case C2LS:
2040 c2ls_alloc(current,i);
2041 break;
2042 case C2OP:
2043 c2op_alloc(current,i);
2044 break;
2045 }
2046}
2047
2048// Special case where a branch and delay slot span two pages in virtual memory
2049static void pagespan_alloc(struct regstat *current,int i)
2050{
2051 current->isconst=0;
2052 current->wasconst=0;
2053 regs[i].wasconst=0;
2054 minimum_free_regs[i]=HOST_REGS;
2055 alloc_all(current,i);
2056 alloc_cc(current,i);
2057 dirty_reg(current,CCREG);
2058 if(dops[i].opcode==3) // JAL
2059 {
2060 alloc_reg(current,i,31);
2061 dirty_reg(current,31);
2062 }
2063 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
2064 {
2065 alloc_reg(current,i,dops[i].rs1);
2066 if (dops[i].rt1!=0) {
2067 alloc_reg(current,i,dops[i].rt1);
2068 dirty_reg(current,dops[i].rt1);
2069 }
2070 }
2071 if((dops[i].opcode&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2072 {
2073 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2074 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
2075 }
2076 else
2077 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2078 {
2079 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
2080 }
2081 //else ...
2082}
2083
2084static void add_stub(enum stub_type type, void *addr, void *retaddr,
2085 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2086{
2087 assert(stubcount < ARRAY_SIZE(stubs));
2088 stubs[stubcount].type = type;
2089 stubs[stubcount].addr = addr;
2090 stubs[stubcount].retaddr = retaddr;
2091 stubs[stubcount].a = a;
2092 stubs[stubcount].b = b;
2093 stubs[stubcount].c = c;
2094 stubs[stubcount].d = d;
2095 stubs[stubcount].e = e;
2096 stubcount++;
2097}
2098
2099static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2100 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2101{
2102 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2103}
2104
2105// Write out a single register
2106static void wb_register(signed char r,signed char regmap[],uint64_t dirty)
2107{
2108 int hr;
2109 for(hr=0;hr<HOST_REGS;hr++) {
2110 if(hr!=EXCLUDE_REG) {
2111 if((regmap[hr]&63)==r) {
2112 if((dirty>>hr)&1) {
2113 assert(regmap[hr]<64);
2114 emit_storereg(r,hr);
2115 }
2116 }
2117 }
2118 }
2119}
2120
2121static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2122{
2123 //if(dirty_pre==dirty) return;
2124 int hr,reg;
2125 for(hr=0;hr<HOST_REGS;hr++) {
2126 if(hr!=EXCLUDE_REG) {
2127 reg=pre[hr];
2128 if(((~u)>>(reg&63))&1) {
2129 if(reg>0) {
2130 if(((dirty_pre&~dirty)>>hr)&1) {
2131 if(reg>0&&reg<34) {
2132 emit_storereg(reg,hr);
2133 }
2134 else if(reg>=64) {
2135 assert(0);
2136 }
2137 }
2138 }
2139 }
2140 }
2141 }
2142}
2143
2144// trashes r2
2145static void pass_args(int a0, int a1)
2146{
2147 if(a0==1&&a1==0) {
2148 // must swap
2149 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2150 }
2151 else if(a0!=0&&a1==0) {
2152 emit_mov(a1,1);
2153 if (a0>=0) emit_mov(a0,0);
2154 }
2155 else {
2156 if(a0>=0&&a0!=0) emit_mov(a0,0);
2157 if(a1>=0&&a1!=1) emit_mov(a1,1);
2158 }
2159}
2160
2161static void alu_assemble(int i,struct regstat *i_regs)
2162{
2163 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2164 if(dops[i].rt1) {
2165 signed char s1,s2,t;
2166 t=get_reg(i_regs->regmap,dops[i].rt1);
2167 if(t>=0) {
2168 s1=get_reg(i_regs->regmap,dops[i].rs1);
2169 s2=get_reg(i_regs->regmap,dops[i].rs2);
2170 if(dops[i].rs1&&dops[i].rs2) {
2171 assert(s1>=0);
2172 assert(s2>=0);
2173 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2174 else emit_add(s1,s2,t);
2175 }
2176 else if(dops[i].rs1) {
2177 if(s1>=0) emit_mov(s1,t);
2178 else emit_loadreg(dops[i].rs1,t);
2179 }
2180 else if(dops[i].rs2) {
2181 if(s2>=0) {
2182 if(dops[i].opcode2&2) emit_neg(s2,t);
2183 else emit_mov(s2,t);
2184 }
2185 else {
2186 emit_loadreg(dops[i].rs2,t);
2187 if(dops[i].opcode2&2) emit_neg(t,t);
2188 }
2189 }
2190 else emit_zeroreg(t);
2191 }
2192 }
2193 }
2194 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2195 assert(0);
2196 }
2197 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2198 if(dops[i].rt1) {
2199 signed char s1l,s2l,t;
2200 {
2201 t=get_reg(i_regs->regmap,dops[i].rt1);
2202 //assert(t>=0);
2203 if(t>=0) {
2204 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2205 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2206 if(dops[i].rs2==0) // rx<r0
2207 {
2208 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2209 assert(s1l>=0);
2210 emit_shrimm(s1l,31,t);
2211 }
2212 else // SLTU (unsigned can not be less than zero, 0<0)
2213 emit_zeroreg(t);
2214 }
2215 else if(dops[i].rs1==0) // r0<rx
2216 {
2217 assert(s2l>=0);
2218 if(dops[i].opcode2==0x2a) // SLT
2219 emit_set_gz32(s2l,t);
2220 else // SLTU (set if not zero)
2221 emit_set_nz32(s2l,t);
2222 }
2223 else{
2224 assert(s1l>=0);assert(s2l>=0);
2225 if(dops[i].opcode2==0x2a) // SLT
2226 emit_set_if_less32(s1l,s2l,t);
2227 else // SLTU
2228 emit_set_if_carry32(s1l,s2l,t);
2229 }
2230 }
2231 }
2232 }
2233 }
2234 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2235 if(dops[i].rt1) {
2236 signed char s1l,s2l,tl;
2237 tl=get_reg(i_regs->regmap,dops[i].rt1);
2238 {
2239 if(tl>=0) {
2240 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2241 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2242 if(dops[i].rs1&&dops[i].rs2) {
2243 assert(s1l>=0);
2244 assert(s2l>=0);
2245 if(dops[i].opcode2==0x24) { // AND
2246 emit_and(s1l,s2l,tl);
2247 } else
2248 if(dops[i].opcode2==0x25) { // OR
2249 emit_or(s1l,s2l,tl);
2250 } else
2251 if(dops[i].opcode2==0x26) { // XOR
2252 emit_xor(s1l,s2l,tl);
2253 } else
2254 if(dops[i].opcode2==0x27) { // NOR
2255 emit_or(s1l,s2l,tl);
2256 emit_not(tl,tl);
2257 }
2258 }
2259 else
2260 {
2261 if(dops[i].opcode2==0x24) { // AND
2262 emit_zeroreg(tl);
2263 } else
2264 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2265 if(dops[i].rs1){
2266 if(s1l>=0) emit_mov(s1l,tl);
2267 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2268 }
2269 else
2270 if(dops[i].rs2){
2271 if(s2l>=0) emit_mov(s2l,tl);
2272 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2273 }
2274 else emit_zeroreg(tl);
2275 } else
2276 if(dops[i].opcode2==0x27) { // NOR
2277 if(dops[i].rs1){
2278 if(s1l>=0) emit_not(s1l,tl);
2279 else {
2280 emit_loadreg(dops[i].rs1,tl);
2281 emit_not(tl,tl);
2282 }
2283 }
2284 else
2285 if(dops[i].rs2){
2286 if(s2l>=0) emit_not(s2l,tl);
2287 else {
2288 emit_loadreg(dops[i].rs2,tl);
2289 emit_not(tl,tl);
2290 }
2291 }
2292 else emit_movimm(-1,tl);
2293 }
2294 }
2295 }
2296 }
2297 }
2298 }
2299}
2300
2301void imm16_assemble(int i,struct regstat *i_regs)
2302{
2303 if (dops[i].opcode==0x0f) { // LUI
2304 if(dops[i].rt1) {
2305 signed char t;
2306 t=get_reg(i_regs->regmap,dops[i].rt1);
2307 //assert(t>=0);
2308 if(t>=0) {
2309 if(!((i_regs->isconst>>t)&1))
2310 emit_movimm(imm[i]<<16,t);
2311 }
2312 }
2313 }
2314 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2315 if(dops[i].rt1) {
2316 signed char s,t;
2317 t=get_reg(i_regs->regmap,dops[i].rt1);
2318 s=get_reg(i_regs->regmap,dops[i].rs1);
2319 if(dops[i].rs1) {
2320 //assert(t>=0);
2321 //assert(s>=0);
2322 if(t>=0) {
2323 if(!((i_regs->isconst>>t)&1)) {
2324 if(s<0) {
2325 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2326 emit_addimm(t,imm[i],t);
2327 }else{
2328 if(!((i_regs->wasconst>>s)&1))
2329 emit_addimm(s,imm[i],t);
2330 else
2331 emit_movimm(constmap[i][s]+imm[i],t);
2332 }
2333 }
2334 }
2335 } else {
2336 if(t>=0) {
2337 if(!((i_regs->isconst>>t)&1))
2338 emit_movimm(imm[i],t);
2339 }
2340 }
2341 }
2342 }
2343 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2344 if(dops[i].rt1) {
2345 signed char sl,tl;
2346 tl=get_reg(i_regs->regmap,dops[i].rt1);
2347 sl=get_reg(i_regs->regmap,dops[i].rs1);
2348 if(tl>=0) {
2349 if(dops[i].rs1) {
2350 assert(sl>=0);
2351 emit_addimm(sl,imm[i],tl);
2352 } else {
2353 emit_movimm(imm[i],tl);
2354 }
2355 }
2356 }
2357 }
2358 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2359 if(dops[i].rt1) {
2360 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2361 signed char sl,t;
2362 t=get_reg(i_regs->regmap,dops[i].rt1);
2363 sl=get_reg(i_regs->regmap,dops[i].rs1);
2364 //assert(t>=0);
2365 if(t>=0) {
2366 if(dops[i].rs1>0) {
2367 if(dops[i].opcode==0x0a) { // SLTI
2368 if(sl<0) {
2369 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2370 emit_slti32(t,imm[i],t);
2371 }else{
2372 emit_slti32(sl,imm[i],t);
2373 }
2374 }
2375 else { // SLTIU
2376 if(sl<0) {
2377 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2378 emit_sltiu32(t,imm[i],t);
2379 }else{
2380 emit_sltiu32(sl,imm[i],t);
2381 }
2382 }
2383 }else{
2384 // SLTI(U) with r0 is just stupid,
2385 // nonetheless examples can be found
2386 if(dops[i].opcode==0x0a) // SLTI
2387 if(0<imm[i]) emit_movimm(1,t);
2388 else emit_zeroreg(t);
2389 else // SLTIU
2390 {
2391 if(imm[i]) emit_movimm(1,t);
2392 else emit_zeroreg(t);
2393 }
2394 }
2395 }
2396 }
2397 }
2398 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2399 if(dops[i].rt1) {
2400 signed char sl,tl;
2401 tl=get_reg(i_regs->regmap,dops[i].rt1);
2402 sl=get_reg(i_regs->regmap,dops[i].rs1);
2403 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2404 if(dops[i].opcode==0x0c) //ANDI
2405 {
2406 if(dops[i].rs1) {
2407 if(sl<0) {
2408 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2409 emit_andimm(tl,imm[i],tl);
2410 }else{
2411 if(!((i_regs->wasconst>>sl)&1))
2412 emit_andimm(sl,imm[i],tl);
2413 else
2414 emit_movimm(constmap[i][sl]&imm[i],tl);
2415 }
2416 }
2417 else
2418 emit_zeroreg(tl);
2419 }
2420 else
2421 {
2422 if(dops[i].rs1) {
2423 if(sl<0) {
2424 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2425 }
2426 if(dops[i].opcode==0x0d) { // ORI
2427 if(sl<0) {
2428 emit_orimm(tl,imm[i],tl);
2429 }else{
2430 if(!((i_regs->wasconst>>sl)&1))
2431 emit_orimm(sl,imm[i],tl);
2432 else
2433 emit_movimm(constmap[i][sl]|imm[i],tl);
2434 }
2435 }
2436 if(dops[i].opcode==0x0e) { // XORI
2437 if(sl<0) {
2438 emit_xorimm(tl,imm[i],tl);
2439 }else{
2440 if(!((i_regs->wasconst>>sl)&1))
2441 emit_xorimm(sl,imm[i],tl);
2442 else
2443 emit_movimm(constmap[i][sl]^imm[i],tl);
2444 }
2445 }
2446 }
2447 else {
2448 emit_movimm(imm[i],tl);
2449 }
2450 }
2451 }
2452 }
2453 }
2454}
2455
2456void shiftimm_assemble(int i,struct regstat *i_regs)
2457{
2458 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2459 {
2460 if(dops[i].rt1) {
2461 signed char s,t;
2462 t=get_reg(i_regs->regmap,dops[i].rt1);
2463 s=get_reg(i_regs->regmap,dops[i].rs1);
2464 //assert(t>=0);
2465 if(t>=0&&!((i_regs->isconst>>t)&1)){
2466 if(dops[i].rs1==0)
2467 {
2468 emit_zeroreg(t);
2469 }
2470 else
2471 {
2472 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2473 if(imm[i]) {
2474 if(dops[i].opcode2==0) // SLL
2475 {
2476 emit_shlimm(s<0?t:s,imm[i],t);
2477 }
2478 if(dops[i].opcode2==2) // SRL
2479 {
2480 emit_shrimm(s<0?t:s,imm[i],t);
2481 }
2482 if(dops[i].opcode2==3) // SRA
2483 {
2484 emit_sarimm(s<0?t:s,imm[i],t);
2485 }
2486 }else{
2487 // Shift by zero
2488 if(s>=0 && s!=t) emit_mov(s,t);
2489 }
2490 }
2491 }
2492 //emit_storereg(dops[i].rt1,t); //DEBUG
2493 }
2494 }
2495 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2496 {
2497 assert(0);
2498 }
2499 if(dops[i].opcode2==0x3c) // DSLL32
2500 {
2501 assert(0);
2502 }
2503 if(dops[i].opcode2==0x3e) // DSRL32
2504 {
2505 assert(0);
2506 }
2507 if(dops[i].opcode2==0x3f) // DSRA32
2508 {
2509 assert(0);
2510 }
2511}
2512
2513#ifndef shift_assemble
2514static void shift_assemble(int i,struct regstat *i_regs)
2515{
2516 signed char s,t,shift;
2517 if (dops[i].rt1 == 0)
2518 return;
2519 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2520 t = get_reg(i_regs->regmap, dops[i].rt1);
2521 s = get_reg(i_regs->regmap, dops[i].rs1);
2522 shift = get_reg(i_regs->regmap, dops[i].rs2);
2523 if (t < 0)
2524 return;
2525
2526 if(dops[i].rs1==0)
2527 emit_zeroreg(t);
2528 else if(dops[i].rs2==0) {
2529 assert(s>=0);
2530 if(s!=t) emit_mov(s,t);
2531 }
2532 else {
2533 host_tempreg_acquire();
2534 emit_andimm(shift,31,HOST_TEMPREG);
2535 switch(dops[i].opcode2) {
2536 case 4: // SLLV
2537 emit_shl(s,HOST_TEMPREG,t);
2538 break;
2539 case 6: // SRLV
2540 emit_shr(s,HOST_TEMPREG,t);
2541 break;
2542 case 7: // SRAV
2543 emit_sar(s,HOST_TEMPREG,t);
2544 break;
2545 default:
2546 assert(0);
2547 }
2548 host_tempreg_release();
2549 }
2550}
2551
2552#endif
2553
2554enum {
2555 MTYPE_8000 = 0,
2556 MTYPE_8020,
2557 MTYPE_0000,
2558 MTYPE_A000,
2559 MTYPE_1F80,
2560};
2561
2562static int get_ptr_mem_type(u_int a)
2563{
2564 if(a < 0x00200000) {
2565 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2566 // return wrong, must use memhandler for BIOS self-test to pass
2567 // 007 does similar stuff from a00 mirror, weird stuff
2568 return MTYPE_8000;
2569 return MTYPE_0000;
2570 }
2571 if(0x1f800000 <= a && a < 0x1f801000)
2572 return MTYPE_1F80;
2573 if(0x80200000 <= a && a < 0x80800000)
2574 return MTYPE_8020;
2575 if(0xa0000000 <= a && a < 0xa0200000)
2576 return MTYPE_A000;
2577 return MTYPE_8000;
2578}
2579
2580static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2581{
2582 int r = get_reg(i_regs->regmap, ROREG);
2583 if (r < 0 && host_tempreg_free) {
2584 host_tempreg_acquire();
2585 emit_loadreg(ROREG, r = HOST_TEMPREG);
2586 }
2587 if (r < 0)
2588 abort();
2589 return r;
2590}
2591
2592static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2593 int addr, int *offset_reg, int *addr_reg_override)
2594{
2595 void *jaddr = NULL;
2596 int type = 0;
2597 int mr = dops[i].rs1;
2598 *offset_reg = -1;
2599 if(((smrv_strong|smrv_weak)>>mr)&1) {
2600 type=get_ptr_mem_type(smrv[mr]);
2601 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2602 }
2603 else {
2604 // use the mirror we are running on
2605 type=get_ptr_mem_type(start);
2606 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2607 }
2608
2609 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2610 host_tempreg_acquire();
2611 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2612 addr=*addr_reg_override=HOST_TEMPREG;
2613 type=0;
2614 }
2615 else if(type==MTYPE_0000) { // RAM 0 mirror
2616 host_tempreg_acquire();
2617 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2618 addr=*addr_reg_override=HOST_TEMPREG;
2619 type=0;
2620 }
2621 else if(type==MTYPE_A000) { // RAM A mirror
2622 host_tempreg_acquire();
2623 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2624 addr=*addr_reg_override=HOST_TEMPREG;
2625 type=0;
2626 }
2627 else if(type==MTYPE_1F80) { // scratchpad
2628 if (psxH == (void *)0x1f800000) {
2629 host_tempreg_acquire();
2630 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2631 emit_cmpimm(HOST_TEMPREG,0x1000);
2632 host_tempreg_release();
2633 jaddr=out;
2634 emit_jc(0);
2635 }
2636 else {
2637 // do the usual RAM check, jump will go to the right handler
2638 type=0;
2639 }
2640 }
2641
2642 if (type == 0) // need ram check
2643 {
2644 emit_cmpimm(addr,RAM_SIZE);
2645 jaddr = out;
2646 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2647 // Hint to branch predictor that the branch is unlikely to be taken
2648 if (dops[i].rs1 >= 28)
2649 emit_jno_unlikely(0);
2650 else
2651 #endif
2652 emit_jno(0);
2653 if (ram_offset != 0)
2654 *offset_reg = get_ro_reg(i_regs, 0);
2655 }
2656
2657 return jaddr;
2658}
2659
2660// return memhandler, or get directly accessable address and return 0
2661static void *get_direct_memhandler(void *table, u_int addr,
2662 enum stub_type type, uintptr_t *addr_host)
2663{
2664 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2665 uintptr_t l1, l2 = 0;
2666 l1 = ((uintptr_t *)table)[addr>>12];
2667 if (!(l1 & msb)) {
2668 uintptr_t v = l1 << 1;
2669 *addr_host = v + addr;
2670 return NULL;
2671 }
2672 else {
2673 l1 <<= 1;
2674 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2675 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2676 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2677 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2678 else
2679 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2680 if (!(l2 & msb)) {
2681 uintptr_t v = l2 << 1;
2682 *addr_host = v + (addr&0xfff);
2683 return NULL;
2684 }
2685 return (void *)(l2 << 1);
2686 }
2687}
2688
2689static u_int get_host_reglist(const signed char *regmap)
2690{
2691 u_int reglist = 0, hr;
2692 for (hr = 0; hr < HOST_REGS; hr++) {
2693 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2694 reglist |= 1 << hr;
2695 }
2696 return reglist;
2697}
2698
2699static u_int reglist_exclude(u_int reglist, int r1, int r2)
2700{
2701 if (r1 >= 0)
2702 reglist &= ~(1u << r1);
2703 if (r2 >= 0)
2704 reglist &= ~(1u << r2);
2705 return reglist;
2706}
2707
2708// find a temp caller-saved register not in reglist (so assumed to be free)
2709static int reglist_find_free(u_int reglist)
2710{
2711 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2712 if (free_regs == 0)
2713 return -1;
2714 return __builtin_ctz(free_regs);
2715}
2716
2717static void do_load_word(int a, int rt, int offset_reg)
2718{
2719 if (offset_reg >= 0)
2720 emit_ldr_dualindexed(offset_reg, a, rt);
2721 else
2722 emit_readword_indexed(0, a, rt);
2723}
2724
2725static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2726{
2727 if (offset_reg < 0) {
2728 emit_writeword_indexed(rt, ofs, a);
2729 return;
2730 }
2731 if (ofs != 0)
2732 emit_addimm(a, ofs, a);
2733 emit_str_dualindexed(offset_reg, a, rt);
2734 if (ofs != 0 && preseve_a)
2735 emit_addimm(a, -ofs, a);
2736}
2737
2738static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2739{
2740 if (offset_reg < 0) {
2741 emit_writehword_indexed(rt, ofs, a);
2742 return;
2743 }
2744 if (ofs != 0)
2745 emit_addimm(a, ofs, a);
2746 emit_strh_dualindexed(offset_reg, a, rt);
2747 if (ofs != 0 && preseve_a)
2748 emit_addimm(a, -ofs, a);
2749}
2750
2751static void do_store_byte(int a, int rt, int offset_reg)
2752{
2753 if (offset_reg >= 0)
2754 emit_strb_dualindexed(offset_reg, a, rt);
2755 else
2756 emit_writebyte_indexed(rt, 0, a);
2757}
2758
2759static void load_assemble(int i, const struct regstat *i_regs)
2760{
2761 int s,tl,addr;
2762 int offset;
2763 void *jaddr=0;
2764 int memtarget=0,c=0;
2765 int offset_reg = -1;
2766 int fastio_reg_override = -1;
2767 u_int reglist=get_host_reglist(i_regs->regmap);
2768 tl=get_reg(i_regs->regmap,dops[i].rt1);
2769 s=get_reg(i_regs->regmap,dops[i].rs1);
2770 offset=imm[i];
2771 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2772 if(s>=0) {
2773 c=(i_regs->wasconst>>s)&1;
2774 if (c) {
2775 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2776 }
2777 }
2778 //printf("load_assemble: c=%d\n",c);
2779 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2780 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2781 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2782 ||dops[i].rt1==0) {
2783 // could be FIFO, must perform the read
2784 // ||dummy read
2785 assem_debug("(forced read)\n");
2786 tl=get_reg(i_regs->regmap,-1);
2787 assert(tl>=0);
2788 }
2789 if(offset||s<0||c) addr=tl;
2790 else addr=s;
2791 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2792 if(tl>=0) {
2793 //printf("load_assemble: c=%d\n",c);
2794 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2795 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2796 reglist&=~(1<<tl);
2797 if(!c) {
2798 #ifdef R29_HACK
2799 // Strmnnrmn's speed hack
2800 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2801 #endif
2802 {
2803 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2804 &offset_reg, &fastio_reg_override);
2805 }
2806 }
2807 else if (ram_offset && memtarget) {
2808 offset_reg = get_ro_reg(i_regs, 0);
2809 }
2810 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2811 switch (dops[i].opcode) {
2812 case 0x20: // LB
2813 if(!c||memtarget) {
2814 if(!dummy) {
2815 int a = tl;
2816 if (!c) a = addr;
2817 if (fastio_reg_override >= 0)
2818 a = fastio_reg_override;
2819
2820 if (offset_reg >= 0)
2821 emit_ldrsb_dualindexed(offset_reg, a, tl);
2822 else
2823 emit_movsbl_indexed(0, a, tl);
2824 }
2825 if(jaddr)
2826 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2827 }
2828 else
2829 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2830 break;
2831 case 0x21: // LH
2832 if(!c||memtarget) {
2833 if(!dummy) {
2834 int a = tl;
2835 if (!c) a = addr;
2836 if (fastio_reg_override >= 0)
2837 a = fastio_reg_override;
2838 if (offset_reg >= 0)
2839 emit_ldrsh_dualindexed(offset_reg, a, tl);
2840 else
2841 emit_movswl_indexed(0, a, tl);
2842 }
2843 if(jaddr)
2844 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2845 }
2846 else
2847 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2848 break;
2849 case 0x23: // LW
2850 if(!c||memtarget) {
2851 if(!dummy) {
2852 int a = addr;
2853 if (fastio_reg_override >= 0)
2854 a = fastio_reg_override;
2855 do_load_word(a, tl, offset_reg);
2856 }
2857 if(jaddr)
2858 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2859 }
2860 else
2861 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2862 break;
2863 case 0x24: // LBU
2864 if(!c||memtarget) {
2865 if(!dummy) {
2866 int a = tl;
2867 if (!c) a = addr;
2868 if (fastio_reg_override >= 0)
2869 a = fastio_reg_override;
2870
2871 if (offset_reg >= 0)
2872 emit_ldrb_dualindexed(offset_reg, a, tl);
2873 else
2874 emit_movzbl_indexed(0, a, tl);
2875 }
2876 if(jaddr)
2877 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2878 }
2879 else
2880 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2881 break;
2882 case 0x25: // LHU
2883 if(!c||memtarget) {
2884 if(!dummy) {
2885 int a = tl;
2886 if(!c) a = addr;
2887 if (fastio_reg_override >= 0)
2888 a = fastio_reg_override;
2889 if (offset_reg >= 0)
2890 emit_ldrh_dualindexed(offset_reg, a, tl);
2891 else
2892 emit_movzwl_indexed(0, a, tl);
2893 }
2894 if(jaddr)
2895 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2896 }
2897 else
2898 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj[i],reglist);
2899 break;
2900 case 0x27: // LWU
2901 case 0x37: // LD
2902 default:
2903 assert(0);
2904 }
2905 }
2906 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2907 host_tempreg_release();
2908}
2909
2910#ifndef loadlr_assemble
2911static void loadlr_assemble(int i, const struct regstat *i_regs)
2912{
2913 int s,tl,temp,temp2,addr;
2914 int offset;
2915 void *jaddr=0;
2916 int memtarget=0,c=0;
2917 int offset_reg = -1;
2918 int fastio_reg_override = -1;
2919 u_int reglist=get_host_reglist(i_regs->regmap);
2920 tl=get_reg(i_regs->regmap,dops[i].rt1);
2921 s=get_reg(i_regs->regmap,dops[i].rs1);
2922 temp=get_reg(i_regs->regmap,-1);
2923 temp2=get_reg(i_regs->regmap,FTEMP);
2924 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
2925 assert(addr<0);
2926 offset=imm[i];
2927 reglist|=1<<temp;
2928 if(offset||s<0||c) addr=temp2;
2929 else addr=s;
2930 if(s>=0) {
2931 c=(i_regs->wasconst>>s)&1;
2932 if(c) {
2933 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2934 }
2935 }
2936 if(!c) {
2937 emit_shlimm(addr,3,temp);
2938 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2939 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
2940 }else{
2941 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
2942 }
2943 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
2944 &offset_reg, &fastio_reg_override);
2945 }
2946 else {
2947 if (ram_offset && memtarget) {
2948 offset_reg = get_ro_reg(i_regs, 0);
2949 }
2950 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
2951 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
2952 }else{
2953 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
2954 }
2955 }
2956 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
2957 if(!c||memtarget) {
2958 int a = temp2;
2959 if (fastio_reg_override >= 0)
2960 a = fastio_reg_override;
2961 do_load_word(a, temp2, offset_reg);
2962 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
2963 host_tempreg_release();
2964 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj[i],reglist);
2965 }
2966 else
2967 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
2968 if(dops[i].rt1) {
2969 assert(tl>=0);
2970 emit_andimm(temp,24,temp);
2971 if (dops[i].opcode==0x22) // LWL
2972 emit_xorimm(temp,24,temp);
2973 host_tempreg_acquire();
2974 emit_movimm(-1,HOST_TEMPREG);
2975 if (dops[i].opcode==0x26) {
2976 emit_shr(temp2,temp,temp2);
2977 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
2978 }else{
2979 emit_shl(temp2,temp,temp2);
2980 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
2981 }
2982 host_tempreg_release();
2983 emit_or(temp2,tl,tl);
2984 }
2985 //emit_storereg(dops[i].rt1,tl); // DEBUG
2986 }
2987 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
2988 assert(0);
2989 }
2990}
2991#endif
2992
2993static void store_assemble(int i, const struct regstat *i_regs)
2994{
2995 int s,tl;
2996 int addr,temp;
2997 int offset;
2998 void *jaddr=0;
2999 enum stub_type type=0;
3000 int memtarget=0,c=0;
3001 int agr=AGEN1+(i&1);
3002 int offset_reg = -1;
3003 int fastio_reg_override = -1;
3004 u_int reglist=get_host_reglist(i_regs->regmap);
3005 tl=get_reg(i_regs->regmap,dops[i].rs2);
3006 s=get_reg(i_regs->regmap,dops[i].rs1);
3007 temp=get_reg(i_regs->regmap,agr);
3008 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3009 offset=imm[i];
3010 if(s>=0) {
3011 c=(i_regs->wasconst>>s)&1;
3012 if(c) {
3013 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3014 }
3015 }
3016 assert(tl>=0);
3017 assert(temp>=0);
3018 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3019 if(offset||s<0||c) addr=temp;
3020 else addr=s;
3021 if (!c) {
3022 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3023 &offset_reg, &fastio_reg_override);
3024 }
3025 else if (ram_offset && memtarget) {
3026 offset_reg = get_ro_reg(i_regs, 0);
3027 }
3028
3029 switch (dops[i].opcode) {
3030 case 0x28: // SB
3031 if(!c||memtarget) {
3032 int a = temp;
3033 if (!c) a = addr;
3034 if (fastio_reg_override >= 0)
3035 a = fastio_reg_override;
3036 do_store_byte(a, tl, offset_reg);
3037 }
3038 type = STOREB_STUB;
3039 break;
3040 case 0x29: // SH
3041 if(!c||memtarget) {
3042 int a = temp;
3043 if (!c) a = addr;
3044 if (fastio_reg_override >= 0)
3045 a = fastio_reg_override;
3046 do_store_hword(a, 0, tl, offset_reg, 1);
3047 }
3048 type = STOREH_STUB;
3049 break;
3050 case 0x2B: // SW
3051 if(!c||memtarget) {
3052 int a = addr;
3053 if (fastio_reg_override >= 0)
3054 a = fastio_reg_override;
3055 do_store_word(a, 0, tl, offset_reg, 1);
3056 }
3057 type = STOREW_STUB;
3058 break;
3059 case 0x3F: // SD
3060 default:
3061 assert(0);
3062 }
3063 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3064 host_tempreg_release();
3065 if(jaddr) {
3066 // PCSX store handlers don't check invcode again
3067 reglist|=1<<addr;
3068 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
3069 jaddr=0;
3070 }
3071 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3072 if(!c||memtarget) {
3073 #ifdef DESTRUCTIVE_SHIFT
3074 // The x86 shift operation is 'destructive'; it overwrites the
3075 // source register, so we need to make a copy first and use that.
3076 addr=temp;
3077 #endif
3078 #if defined(HOST_IMM8)
3079 int ir=get_reg(i_regs->regmap,INVCP);
3080 assert(ir>=0);
3081 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3082 #else
3083 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3084 #endif
3085 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3086 emit_callne(invalidate_addr_reg[addr]);
3087 #else
3088 void *jaddr2 = out;
3089 emit_jne(0);
3090 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3091 #endif
3092 }
3093 }
3094 u_int addr_val=constmap[i][s]+offset;
3095 if(jaddr) {
3096 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
3097 } else if(c&&!memtarget) {
3098 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj[i],reglist);
3099 }
3100 // basic current block modification detection..
3101 // not looking back as that should be in mips cache already
3102 // (see Spyro2 title->attract mode)
3103 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3104 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3105 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3106 if(i_regs->regmap==regs[i].regmap) {
3107 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3108 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3109 emit_movimm(start+i*4+4,0);
3110 emit_writeword(0,&pcaddr);
3111 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3112 emit_far_call(get_addr_ht);
3113 emit_jmpreg(0);
3114 }
3115 }
3116}
3117
3118static void storelr_assemble(int i, const struct regstat *i_regs)
3119{
3120 int s,tl;
3121 int temp;
3122 int offset;
3123 void *jaddr=0;
3124 void *case1, *case23, *case3;
3125 void *done0, *done1, *done2;
3126 int memtarget=0,c=0;
3127 int agr=AGEN1+(i&1);
3128 int offset_reg = -1;
3129 u_int reglist=get_host_reglist(i_regs->regmap);
3130 tl=get_reg(i_regs->regmap,dops[i].rs2);
3131 s=get_reg(i_regs->regmap,dops[i].rs1);
3132 temp=get_reg(i_regs->regmap,agr);
3133 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3134 offset=imm[i];
3135 if(s>=0) {
3136 c=(i_regs->isconst>>s)&1;
3137 if(c) {
3138 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3139 }
3140 }
3141 assert(tl>=0);
3142 assert(temp>=0);
3143 if(!c) {
3144 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3145 if(!offset&&s!=temp) emit_mov(s,temp);
3146 jaddr=out;
3147 emit_jno(0);
3148 }
3149 else
3150 {
3151 if(!memtarget||!dops[i].rs1) {
3152 jaddr=out;
3153 emit_jmp(0);
3154 }
3155 }
3156 if (ram_offset)
3157 offset_reg = get_ro_reg(i_regs, 0);
3158
3159 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3160 assert(0);
3161 }
3162
3163 emit_testimm(temp,2);
3164 case23=out;
3165 emit_jne(0);
3166 emit_testimm(temp,1);
3167 case1=out;
3168 emit_jne(0);
3169 // 0
3170 if (dops[i].opcode == 0x2A) { // SWL
3171 // Write msb into least significant byte
3172 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3173 do_store_byte(temp, tl, offset_reg);
3174 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3175 }
3176 else if (dops[i].opcode == 0x2E) { // SWR
3177 // Write entire word
3178 do_store_word(temp, 0, tl, offset_reg, 1);
3179 }
3180 done0 = out;
3181 emit_jmp(0);
3182 // 1
3183 set_jump_target(case1, out);
3184 if (dops[i].opcode == 0x2A) { // SWL
3185 // Write two msb into two least significant bytes
3186 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3187 do_store_hword(temp, -1, tl, offset_reg, 0);
3188 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3189 }
3190 else if (dops[i].opcode == 0x2E) { // SWR
3191 // Write 3 lsb into three most significant bytes
3192 do_store_byte(temp, tl, offset_reg);
3193 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3194 do_store_hword(temp, 1, tl, offset_reg, 0);
3195 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3196 }
3197 done1=out;
3198 emit_jmp(0);
3199 // 2,3
3200 set_jump_target(case23, out);
3201 emit_testimm(temp,1);
3202 case3 = out;
3203 emit_jne(0);
3204 // 2
3205 if (dops[i].opcode==0x2A) { // SWL
3206 // Write 3 msb into three least significant bytes
3207 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3208 do_store_hword(temp, -2, tl, offset_reg, 1);
3209 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3210 do_store_byte(temp, tl, offset_reg);
3211 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3212 }
3213 else if (dops[i].opcode == 0x2E) { // SWR
3214 // Write two lsb into two most significant bytes
3215 do_store_hword(temp, 0, tl, offset_reg, 1);
3216 }
3217 done2 = out;
3218 emit_jmp(0);
3219 // 3
3220 set_jump_target(case3, out);
3221 if (dops[i].opcode == 0x2A) { // SWL
3222 do_store_word(temp, -3, tl, offset_reg, 0);
3223 }
3224 else if (dops[i].opcode == 0x2E) { // SWR
3225 do_store_byte(temp, tl, offset_reg);
3226 }
3227 set_jump_target(done0, out);
3228 set_jump_target(done1, out);
3229 set_jump_target(done2, out);
3230 if (offset_reg == HOST_TEMPREG)
3231 host_tempreg_release();
3232 if(!c||!memtarget)
3233 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
3234 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3235 #if defined(HOST_IMM8)
3236 int ir=get_reg(i_regs->regmap,INVCP);
3237 assert(ir>=0);
3238 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3239 #else
3240 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3241 #endif
3242 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3243 emit_callne(invalidate_addr_reg[temp]);
3244 #else
3245 void *jaddr2 = out;
3246 emit_jne(0);
3247 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3248 #endif
3249 }
3250}
3251
3252static void cop0_assemble(int i,struct regstat *i_regs)
3253{
3254 if(dops[i].opcode2==0) // MFC0
3255 {
3256 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3257 u_int copr=(source[i]>>11)&0x1f;
3258 //assert(t>=0); // Why does this happen? OOT is weird
3259 if(t>=0&&dops[i].rt1!=0) {
3260 emit_readword(&reg_cop0[copr],t);
3261 }
3262 }
3263 else if(dops[i].opcode2==4) // MTC0
3264 {
3265 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3266 char copr=(source[i]>>11)&0x1f;
3267 assert(s>=0);
3268 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3269 if(copr==9||copr==11||copr==12||copr==13) {
3270 emit_readword(&last_count,HOST_TEMPREG);
3271 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3272 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3273 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3274 emit_writeword(HOST_CCREG,&Count);
3275 }
3276 // What a mess. The status register (12) can enable interrupts,
3277 // so needs a special case to handle a pending interrupt.
3278 // The interrupt must be taken immediately, because a subsequent
3279 // instruction might disable interrupts again.
3280 if(copr==12||copr==13) {
3281 if (is_delayslot) {
3282 // burn cycles to cause cc_interrupt, which will
3283 // reschedule next_interupt. Relies on CCREG from above.
3284 assem_debug("MTC0 DS %d\n", copr);
3285 emit_writeword(HOST_CCREG,&last_count);
3286 emit_movimm(0,HOST_CCREG);
3287 emit_storereg(CCREG,HOST_CCREG);
3288 emit_loadreg(dops[i].rs1,1);
3289 emit_movimm(copr,0);
3290 emit_far_call(pcsx_mtc0_ds);
3291 emit_loadreg(dops[i].rs1,s);
3292 return;
3293 }
3294 emit_movimm(start+i*4+4,HOST_TEMPREG);
3295 emit_writeword(HOST_TEMPREG,&pcaddr);
3296 emit_movimm(0,HOST_TEMPREG);
3297 emit_writeword(HOST_TEMPREG,&pending_exception);
3298 }
3299 if(s==HOST_CCREG)
3300 emit_loadreg(dops[i].rs1,1);
3301 else if(s!=1)
3302 emit_mov(s,1);
3303 emit_movimm(copr,0);
3304 emit_far_call(pcsx_mtc0);
3305 if(copr==9||copr==11||copr==12||copr==13) {
3306 emit_readword(&Count,HOST_CCREG);
3307 emit_readword(&next_interupt,HOST_TEMPREG);
3308 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3309 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3310 emit_writeword(HOST_TEMPREG,&last_count);
3311 emit_storereg(CCREG,HOST_CCREG);
3312 }
3313 if(copr==12||copr==13) {
3314 assert(!is_delayslot);
3315 emit_readword(&pending_exception,14);
3316 emit_test(14,14);
3317 void *jaddr = out;
3318 emit_jeq(0);
3319 emit_readword(&pcaddr, 0);
3320 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3321 emit_far_call(get_addr_ht);
3322 emit_jmpreg(0);
3323 set_jump_target(jaddr, out);
3324 }
3325 emit_loadreg(dops[i].rs1,s);
3326 }
3327 else
3328 {
3329 assert(dops[i].opcode2==0x10);
3330 //if((source[i]&0x3f)==0x10) // RFE
3331 {
3332 emit_readword(&Status,0);
3333 emit_andimm(0,0x3c,1);
3334 emit_andimm(0,~0xf,0);
3335 emit_orrshr_imm(1,2,0);
3336 emit_writeword(0,&Status);
3337 }
3338 }
3339}
3340
3341static void cop1_unusable(int i,struct regstat *i_regs)
3342{
3343 // XXX: should just just do the exception instead
3344 //if(!cop1_usable)
3345 {
3346 void *jaddr=out;
3347 emit_jmp(0);
3348 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3349 }
3350}
3351
3352static void cop1_assemble(int i,struct regstat *i_regs)
3353{
3354 cop1_unusable(i, i_regs);
3355}
3356
3357static void c1ls_assemble(int i,struct regstat *i_regs)
3358{
3359 cop1_unusable(i, i_regs);
3360}
3361
3362// FP_STUB
3363static void do_cop1stub(int n)
3364{
3365 literal_pool(256);
3366 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3367 set_jump_target(stubs[n].addr, out);
3368 int i=stubs[n].a;
3369// int rs=stubs[n].b;
3370 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3371 int ds=stubs[n].d;
3372 if(!ds) {
3373 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3374 //if(i_regs!=&regs[i]) printf("oops: regs[i]=%x i_regs=%x",(int)&regs[i],(int)i_regs);
3375 }
3376 //else {printf("fp exception in delay slot\n");}
3377 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3378 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3379 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3380 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3381 emit_far_jump(ds?fp_exception_ds:fp_exception);
3382}
3383
3384static int cop2_is_stalling_op(int i, int *cycles)
3385{
3386 if (dops[i].opcode == 0x3a) { // SWC2
3387 *cycles = 0;
3388 return 1;
3389 }
3390 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3391 *cycles = 0;
3392 return 1;
3393 }
3394 if (dops[i].itype == C2OP) {
3395 *cycles = gte_cycletab[source[i] & 0x3f];
3396 return 1;
3397 }
3398 // ... what about MTC2/CTC2/LWC2?
3399 return 0;
3400}
3401
3402#if 0
3403static void log_gte_stall(int stall, u_int cycle)
3404{
3405 if ((u_int)stall <= 44)
3406 printf("x stall %2d %u\n", stall, cycle + last_count);
3407}
3408
3409static void emit_log_gte_stall(int i, int stall, u_int reglist)
3410{
3411 save_regs(reglist);
3412 if (stall > 0)
3413 emit_movimm(stall, 0);
3414 else
3415 emit_mov(HOST_TEMPREG, 0);
3416 emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
3417 emit_far_call(log_gte_stall);
3418 restore_regs(reglist);
3419}
3420#endif
3421
3422static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3423{
3424 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3425 int rtmp = reglist_find_free(reglist);
3426
3427 if (HACK_ENABLED(NDHACK_NO_STALLS))
3428 return;
3429 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3430 // happens occasionally... cc evicted? Don't bother then
3431 //printf("no cc %08x\n", start + i*4);
3432 return;
3433 }
3434 if (!dops[i].bt) {
3435 for (j = i - 1; j >= 0; j--) {
3436 //if (dops[j].is_ds) break;
3437 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3438 break;
3439 }
3440 j = max(j, 0);
3441 }
3442 cycles_passed = CLOCK_ADJUST(ccadj[i] - ccadj[j]);
3443 if (other_gte_op_cycles >= 0)
3444 stall = other_gte_op_cycles - cycles_passed;
3445 else if (cycles_passed >= 44)
3446 stall = 0; // can't stall
3447 if (stall == -MAXBLOCK && rtmp >= 0) {
3448 // unknown stall, do the expensive runtime check
3449 assem_debug("; cop2_do_stall_check\n");
3450#if 0 // too slow
3451 save_regs(reglist);
3452 emit_movimm(gte_cycletab[op], 0);
3453 emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]), 1);
3454 emit_far_call(call_gteStall);
3455 restore_regs(reglist);
3456#else
3457 host_tempreg_acquire();
3458 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3459 emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp);
3460 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3461 emit_cmpimm(HOST_TEMPREG, 44);
3462 emit_cmovb_reg(rtmp, HOST_CCREG);
3463 //emit_log_gte_stall(i, 0, reglist);
3464 host_tempreg_release();
3465#endif
3466 }
3467 else if (stall > 0) {
3468 //emit_log_gte_stall(i, stall, reglist);
3469 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3470 }
3471
3472 // save gteBusyCycle, if needed
3473 if (gte_cycletab[op] == 0)
3474 return;
3475 other_gte_op_cycles = -1;
3476 for (j = i + 1; j < slen; j++) {
3477 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3478 break;
3479 if (dops[j].is_jump) {
3480 // check ds
3481 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3482 j++;
3483 break;
3484 }
3485 }
3486 if (other_gte_op_cycles >= 0)
3487 // will handle stall when assembling that op
3488 return;
3489 cycles_passed = CLOCK_ADJUST(ccadj[min(j, slen -1)] - ccadj[i]);
3490 if (cycles_passed >= 44)
3491 return;
3492 assem_debug("; save gteBusyCycle\n");
3493 host_tempreg_acquire();
3494#if 0
3495 emit_readword(&last_count, HOST_TEMPREG);
3496 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3497 emit_addimm(HOST_TEMPREG, CLOCK_ADJUST(ccadj[i]), HOST_TEMPREG);
3498 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3499 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3500#else
3501 emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + gte_cycletab[op], HOST_TEMPREG);
3502 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3503#endif
3504 host_tempreg_release();
3505}
3506
3507static int is_mflohi(int i)
3508{
3509 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3510}
3511
3512static int check_multdiv(int i, int *cycles)
3513{
3514 if (dops[i].itype != MULTDIV)
3515 return 0;
3516 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3517 *cycles = 11; // approx from 7 11 14
3518 else
3519 *cycles = 37;
3520 return 1;
3521}
3522
3523static void multdiv_prepare_stall(int i, const struct regstat *i_regs)
3524{
3525 int j, found = 0, c = 0;
3526 if (HACK_ENABLED(NDHACK_NO_STALLS))
3527 return;
3528 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3529 // happens occasionally... cc evicted? Don't bother then
3530 return;
3531 }
3532 for (j = i + 1; j < slen; j++) {
3533 if (dops[j].bt)
3534 break;
3535 if ((found = is_mflohi(j)))
3536 break;
3537 if (dops[j].is_jump) {
3538 // check ds
3539 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3540 j++;
3541 break;
3542 }
3543 }
3544 if (found)
3545 // handle all in multdiv_do_stall()
3546 return;
3547 check_multdiv(i, &c);
3548 assert(c > 0);
3549 assem_debug("; muldiv prepare stall %d\n", c);
3550 host_tempreg_acquire();
3551 emit_addimm(HOST_CCREG, CLOCK_ADJUST(ccadj[i]) + c, HOST_TEMPREG);
3552 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3553 host_tempreg_release();
3554}
3555
3556static void multdiv_do_stall(int i, const struct regstat *i_regs)
3557{
3558 int j, known_cycles = 0;
3559 u_int reglist = get_host_reglist(i_regs->regmap);
3560 int rtmp = get_reg(i_regs->regmap, -1);
3561 if (rtmp < 0)
3562 rtmp = reglist_find_free(reglist);
3563 if (HACK_ENABLED(NDHACK_NO_STALLS))
3564 return;
3565 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3566 // happens occasionally... cc evicted? Don't bother then
3567 //printf("no cc/rtmp %08x\n", start + i*4);
3568 return;
3569 }
3570 if (!dops[i].bt) {
3571 for (j = i - 1; j >= 0; j--) {
3572 if (dops[j].is_ds) break;
3573 if (check_multdiv(j, &known_cycles) || dops[j].bt)
3574 break;
3575 if (is_mflohi(j))
3576 // already handled by this op
3577 return;
3578 }
3579 j = max(j, 0);
3580 }
3581 if (known_cycles > 0) {
3582 known_cycles -= CLOCK_ADJUST(ccadj[i] - ccadj[j]);
3583 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3584 if (known_cycles > 0)
3585 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3586 return;
3587 }
3588 assem_debug("; muldiv stall unresolved\n");
3589 host_tempreg_acquire();
3590 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3591 emit_addimm(rtmp, -CLOCK_ADJUST(ccadj[i]), rtmp);
3592 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3593 emit_cmpimm(HOST_TEMPREG, 37);
3594 emit_cmovb_reg(rtmp, HOST_CCREG);
3595 //emit_log_gte_stall(i, 0, reglist);
3596 host_tempreg_release();
3597}
3598
3599static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3600{
3601 switch (copr) {
3602 case 1:
3603 case 3:
3604 case 5:
3605 case 8:
3606 case 9:
3607 case 10:
3608 case 11:
3609 emit_readword(&reg_cop2d[copr],tl);
3610 emit_signextend16(tl,tl);
3611 emit_writeword(tl,&reg_cop2d[copr]); // hmh
3612 break;
3613 case 7:
3614 case 16:
3615 case 17:
3616 case 18:
3617 case 19:
3618 emit_readword(&reg_cop2d[copr],tl);
3619 emit_andimm(tl,0xffff,tl);
3620 emit_writeword(tl,&reg_cop2d[copr]);
3621 break;
3622 case 15:
3623 emit_readword(&reg_cop2d[14],tl); // SXY2
3624 emit_writeword(tl,&reg_cop2d[copr]);
3625 break;
3626 case 28:
3627 case 29:
3628 c2op_mfc2_29_assemble(tl,temp);
3629 break;
3630 default:
3631 emit_readword(&reg_cop2d[copr],tl);
3632 break;
3633 }
3634}
3635
3636static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3637{
3638 switch (copr) {
3639 case 15:
3640 emit_readword(&reg_cop2d[13],temp); // SXY1
3641 emit_writeword(sl,&reg_cop2d[copr]);
3642 emit_writeword(temp,&reg_cop2d[12]); // SXY0
3643 emit_readword(&reg_cop2d[14],temp); // SXY2
3644 emit_writeword(sl,&reg_cop2d[14]);
3645 emit_writeword(temp,&reg_cop2d[13]); // SXY1
3646 break;
3647 case 28:
3648 emit_andimm(sl,0x001f,temp);
3649 emit_shlimm(temp,7,temp);
3650 emit_writeword(temp,&reg_cop2d[9]);
3651 emit_andimm(sl,0x03e0,temp);
3652 emit_shlimm(temp,2,temp);
3653 emit_writeword(temp,&reg_cop2d[10]);
3654 emit_andimm(sl,0x7c00,temp);
3655 emit_shrimm(temp,3,temp);
3656 emit_writeword(temp,&reg_cop2d[11]);
3657 emit_writeword(sl,&reg_cop2d[28]);
3658 break;
3659 case 30:
3660 emit_xorsar_imm(sl,sl,31,temp);
3661#if defined(HAVE_ARMV5) || defined(__aarch64__)
3662 emit_clz(temp,temp);
3663#else
3664 emit_movs(temp,HOST_TEMPREG);
3665 emit_movimm(0,temp);
3666 emit_jeq((int)out+4*4);
3667 emit_addpl_imm(temp,1,temp);
3668 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3669 emit_jns((int)out-2*4);
3670#endif
3671 emit_writeword(sl,&reg_cop2d[30]);
3672 emit_writeword(temp,&reg_cop2d[31]);
3673 break;
3674 case 31:
3675 break;
3676 default:
3677 emit_writeword(sl,&reg_cop2d[copr]);
3678 break;
3679 }
3680}
3681
3682static void c2ls_assemble(int i, const struct regstat *i_regs)
3683{
3684 int s,tl;
3685 int ar;
3686 int offset;
3687 int memtarget=0,c=0;
3688 void *jaddr2=NULL;
3689 enum stub_type type;
3690 int agr=AGEN1+(i&1);
3691 int offset_reg = -1;
3692 int fastio_reg_override = -1;
3693 u_int reglist=get_host_reglist(i_regs->regmap);
3694 u_int copr=(source[i]>>16)&0x1f;
3695 s=get_reg(i_regs->regmap,dops[i].rs1);
3696 tl=get_reg(i_regs->regmap,FTEMP);
3697 offset=imm[i];
3698 assert(dops[i].rs1>0);
3699 assert(tl>=0);
3700
3701 if(i_regs->regmap[HOST_CCREG]==CCREG)
3702 reglist&=~(1<<HOST_CCREG);
3703
3704 // get the address
3705 if (dops[i].opcode==0x3a) { // SWC2
3706 ar=get_reg(i_regs->regmap,agr);
3707 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3708 reglist|=1<<ar;
3709 } else { // LWC2
3710 ar=tl;
3711 }
3712 if(s>=0) c=(i_regs->wasconst>>s)&1;
3713 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3714 if (!offset&&!c&&s>=0) ar=s;
3715 assert(ar>=0);
3716
3717 cop2_do_stall_check(0, i, i_regs, reglist);
3718
3719 if (dops[i].opcode==0x3a) { // SWC2
3720 cop2_get_dreg(copr,tl,-1);
3721 type=STOREW_STUB;
3722 }
3723 else
3724 type=LOADW_STUB;
3725
3726 if(c&&!memtarget) {
3727 jaddr2=out;
3728 emit_jmp(0); // inline_readstub/inline_writestub?
3729 }
3730 else {
3731 if(!c) {
3732 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3733 &offset_reg, &fastio_reg_override);
3734 }
3735 else if (ram_offset && memtarget) {
3736 offset_reg = get_ro_reg(i_regs, 0);
3737 }
3738 switch (dops[i].opcode) {
3739 case 0x32: { // LWC2
3740 int a = ar;
3741 if (fastio_reg_override >= 0)
3742 a = fastio_reg_override;
3743 do_load_word(a, tl, offset_reg);
3744 break;
3745 }
3746 case 0x3a: { // SWC2
3747 #ifdef DESTRUCTIVE_SHIFT
3748 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3749 #endif
3750 int a = ar;
3751 if (fastio_reg_override >= 0)
3752 a = fastio_reg_override;
3753 do_store_word(a, 0, tl, offset_reg, 1);
3754 break;
3755 }
3756 default:
3757 assert(0);
3758 }
3759 }
3760 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3761 host_tempreg_release();
3762 if(jaddr2)
3763 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
3764 if(dops[i].opcode==0x3a) // SWC2
3765 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3766#if defined(HOST_IMM8)
3767 int ir=get_reg(i_regs->regmap,INVCP);
3768 assert(ir>=0);
3769 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3770#else
3771 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3772#endif
3773 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3774 emit_callne(invalidate_addr_reg[ar]);
3775 #else
3776 void *jaddr3 = out;
3777 emit_jne(0);
3778 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3779 #endif
3780 }
3781 if (dops[i].opcode==0x32) { // LWC2
3782 host_tempreg_acquire();
3783 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3784 host_tempreg_release();
3785 }
3786}
3787
3788static void cop2_assemble(int i, const struct regstat *i_regs)
3789{
3790 u_int copr = (source[i]>>11) & 0x1f;
3791 signed char temp = get_reg(i_regs->regmap, -1);
3792
3793 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3794 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3795 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3796 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3797 reglist = reglist_exclude(reglist, tl, -1);
3798 }
3799 cop2_do_stall_check(0, i, i_regs, reglist);
3800 }
3801 if (dops[i].opcode2==0) { // MFC2
3802 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3803 if(tl>=0&&dops[i].rt1!=0)
3804 cop2_get_dreg(copr,tl,temp);
3805 }
3806 else if (dops[i].opcode2==4) { // MTC2
3807 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3808 cop2_put_dreg(copr,sl,temp);
3809 }
3810 else if (dops[i].opcode2==2) // CFC2
3811 {
3812 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3813 if(tl>=0&&dops[i].rt1!=0)
3814 emit_readword(&reg_cop2c[copr],tl);
3815 }
3816 else if (dops[i].opcode2==6) // CTC2
3817 {
3818 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3819 switch(copr) {
3820 case 4:
3821 case 12:
3822 case 20:
3823 case 26:
3824 case 27:
3825 case 29:
3826 case 30:
3827 emit_signextend16(sl,temp);
3828 break;
3829 case 31:
3830 c2op_ctc2_31_assemble(sl,temp);
3831 break;
3832 default:
3833 temp=sl;
3834 break;
3835 }
3836 emit_writeword(temp,&reg_cop2c[copr]);
3837 assert(sl>=0);
3838 }
3839}
3840
3841static void do_unalignedwritestub(int n)
3842{
3843 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
3844 literal_pool(256);
3845 set_jump_target(stubs[n].addr, out);
3846
3847 int i=stubs[n].a;
3848 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3849 int addr=stubs[n].b;
3850 u_int reglist=stubs[n].e;
3851 signed char *i_regmap=i_regs->regmap;
3852 int temp2=get_reg(i_regmap,FTEMP);
3853 int rt;
3854 rt=get_reg(i_regmap,dops[i].rs2);
3855 assert(rt>=0);
3856 assert(addr>=0);
3857 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
3858 reglist|=(1<<addr);
3859 reglist&=~(1<<temp2);
3860
3861 // don't bother with it and call write handler
3862 save_regs(reglist);
3863 pass_args(addr,rt);
3864 int cc=get_reg(i_regmap,CCREG);
3865 if(cc<0)
3866 emit_loadreg(CCREG,2);
3867 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n].d+1),2);
3868 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
3869 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n].d+1),cc<0?2:cc);
3870 if(cc<0)
3871 emit_storereg(CCREG,2);
3872 restore_regs(reglist);
3873 emit_jmp(stubs[n].retaddr); // return address
3874}
3875
3876#ifndef multdiv_assemble
3877void multdiv_assemble(int i,struct regstat *i_regs)
3878{
3879 printf("Need multdiv_assemble for this architecture.\n");
3880 abort();
3881}
3882#endif
3883
3884static void mov_assemble(int i,struct regstat *i_regs)
3885{
3886 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
3887 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
3888 if(dops[i].rt1) {
3889 signed char sl,tl;
3890 tl=get_reg(i_regs->regmap,dops[i].rt1);
3891 //assert(tl>=0);
3892 if(tl>=0) {
3893 sl=get_reg(i_regs->regmap,dops[i].rs1);
3894 if(sl>=0) emit_mov(sl,tl);
3895 else emit_loadreg(dops[i].rs1,tl);
3896 }
3897 }
3898 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
3899 multdiv_do_stall(i, i_regs);
3900}
3901
3902// call interpreter, exception handler, things that change pc/regs/cycles ...
3903static void call_c_cpu_handler(int i, const struct regstat *i_regs, u_int pc, void *func)
3904{
3905 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3906 assert(ccreg==HOST_CCREG);
3907 assert(!is_delayslot);
3908 (void)ccreg;
3909
3910 emit_movimm(pc,3); // Get PC
3911 emit_readword(&last_count,2);
3912 emit_writeword(3,&psxRegs.pc);
3913 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3914 emit_add(2,HOST_CCREG,2);
3915 emit_writeword(2,&psxRegs.cycle);
3916 emit_far_call(func);
3917 emit_far_jump(jump_to_new_pc);
3918}
3919
3920static void syscall_assemble(int i,struct regstat *i_regs)
3921{
3922 emit_movimm(0x20,0); // cause code
3923 emit_movimm(0,1); // not in delay slot
3924 call_c_cpu_handler(i,i_regs,start+i*4,psxException);
3925}
3926
3927static void hlecall_assemble(int i,struct regstat *i_regs)
3928{
3929 void *hlefunc = psxNULL;
3930 uint32_t hleCode = source[i] & 0x03ffffff;
3931 if (hleCode < ARRAY_SIZE(psxHLEt))
3932 hlefunc = psxHLEt[hleCode];
3933
3934 call_c_cpu_handler(i,i_regs,start+i*4+4,hlefunc);
3935}
3936
3937static void intcall_assemble(int i,struct regstat *i_regs)
3938{
3939 call_c_cpu_handler(i,i_regs,start+i*4,execI);
3940}
3941
3942static void speculate_mov(int rs,int rt)
3943{
3944 if(rt!=0) {
3945 smrv_strong_next|=1<<rt;
3946 smrv[rt]=smrv[rs];
3947 }
3948}
3949
3950static void speculate_mov_weak(int rs,int rt)
3951{
3952 if(rt!=0) {
3953 smrv_weak_next|=1<<rt;
3954 smrv[rt]=smrv[rs];
3955 }
3956}
3957
3958static void speculate_register_values(int i)
3959{
3960 if(i==0) {
3961 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3962 // gp,sp are likely to stay the same throughout the block
3963 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3964 smrv_weak_next=~smrv_strong_next;
3965 //printf(" llr %08x\n", smrv[4]);
3966 }
3967 smrv_strong=smrv_strong_next;
3968 smrv_weak=smrv_weak_next;
3969 switch(dops[i].itype) {
3970 case ALU:
3971 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3972 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
3973 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3974 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
3975 else {
3976 smrv_strong_next&=~(1<<dops[i].rt1);
3977 smrv_weak_next&=~(1<<dops[i].rt1);
3978 }
3979 break;
3980 case SHIFTIMM:
3981 smrv_strong_next&=~(1<<dops[i].rt1);
3982 smrv_weak_next&=~(1<<dops[i].rt1);
3983 // fallthrough
3984 case IMM16:
3985 if(dops[i].rt1&&is_const(&regs[i],dops[i].rt1)) {
3986 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
3987 if(hr>=0) {
3988 if(get_final_value(hr,i,&value))
3989 smrv[dops[i].rt1]=value;
3990 else smrv[dops[i].rt1]=constmap[i][hr];
3991 smrv_strong_next|=1<<dops[i].rt1;
3992 }
3993 }
3994 else {
3995 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
3996 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
3997 }
3998 break;
3999 case LOAD:
4000 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4001 // special case for BIOS
4002 smrv[dops[i].rt1]=0xa0000000;
4003 smrv_strong_next|=1<<dops[i].rt1;
4004 break;
4005 }
4006 // fallthrough
4007 case SHIFT:
4008 case LOADLR:
4009 case MOV:
4010 smrv_strong_next&=~(1<<dops[i].rt1);
4011 smrv_weak_next&=~(1<<dops[i].rt1);
4012 break;
4013 case COP0:
4014 case COP2:
4015 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4016 smrv_strong_next&=~(1<<dops[i].rt1);
4017 smrv_weak_next&=~(1<<dops[i].rt1);
4018 }
4019 break;
4020 case C2LS:
4021 if (dops[i].opcode==0x32) { // LWC2
4022 smrv_strong_next&=~(1<<dops[i].rt1);
4023 smrv_weak_next&=~(1<<dops[i].rt1);
4024 }
4025 break;
4026 }
4027#if 0
4028 int r=4;
4029 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4030 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4031#endif
4032}
4033
4034static void ds_assemble(int i,struct regstat *i_regs)
4035{
4036 speculate_register_values(i);
4037 is_delayslot=1;
4038 switch(dops[i].itype) {
4039 case ALU:
4040 alu_assemble(i,i_regs);break;
4041 case IMM16:
4042 imm16_assemble(i,i_regs);break;
4043 case SHIFT:
4044 shift_assemble(i,i_regs);break;
4045 case SHIFTIMM:
4046 shiftimm_assemble(i,i_regs);break;
4047 case LOAD:
4048 load_assemble(i,i_regs);break;
4049 case LOADLR:
4050 loadlr_assemble(i,i_regs);break;
4051 case STORE:
4052 store_assemble(i,i_regs);break;
4053 case STORELR:
4054 storelr_assemble(i,i_regs);break;
4055 case COP0:
4056 cop0_assemble(i,i_regs);break;
4057 case COP1:
4058 cop1_assemble(i,i_regs);break;
4059 case C1LS:
4060 c1ls_assemble(i,i_regs);break;
4061 case COP2:
4062 cop2_assemble(i,i_regs);break;
4063 case C2LS:
4064 c2ls_assemble(i,i_regs);break;
4065 case C2OP:
4066 c2op_assemble(i,i_regs);break;
4067 case MULTDIV:
4068 multdiv_assemble(i,i_regs);
4069 multdiv_prepare_stall(i,i_regs);
4070 break;
4071 case MOV:
4072 mov_assemble(i,i_regs);break;
4073 case SYSCALL:
4074 case HLECALL:
4075 case INTCALL:
4076 case SPAN:
4077 case UJUMP:
4078 case RJUMP:
4079 case CJUMP:
4080 case SJUMP:
4081 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4082 }
4083 is_delayslot=0;
4084}
4085
4086// Is the branch target a valid internal jump?
4087static int internal_branch(int addr)
4088{
4089 if(addr&1) return 0; // Indirect (register) jump
4090 if(addr>=start && addr<start+slen*4-4)
4091 {
4092 return 1;
4093 }
4094 return 0;
4095}
4096
4097static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4098{
4099 int hr;
4100 for(hr=0;hr<HOST_REGS;hr++) {
4101 if(hr!=EXCLUDE_REG) {
4102 if(pre[hr]!=entry[hr]) {
4103 if(pre[hr]>=0) {
4104 if((dirty>>hr)&1) {
4105 if(get_reg(entry,pre[hr])<0) {
4106 assert(pre[hr]<64);
4107 if(!((u>>pre[hr])&1))
4108 emit_storereg(pre[hr],hr);
4109 }
4110 }
4111 }
4112 }
4113 }
4114 }
4115 // Move from one register to another (no writeback)
4116 for(hr=0;hr<HOST_REGS;hr++) {
4117 if(hr!=EXCLUDE_REG) {
4118 if(pre[hr]!=entry[hr]) {
4119 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4120 int nr;
4121 if((nr=get_reg(entry,pre[hr]))>=0) {
4122 emit_mov(hr,nr);
4123 }
4124 }
4125 }
4126 }
4127 }
4128}
4129
4130// Load the specified registers
4131// This only loads the registers given as arguments because
4132// we don't want to load things that will be overwritten
4133static void load_regs(signed char entry[],signed char regmap[],int rs1,int rs2)
4134{
4135 int hr;
4136 // Load 32-bit regs
4137 for(hr=0;hr<HOST_REGS;hr++) {
4138 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4139 if(entry[hr]!=regmap[hr]) {
4140 if(regmap[hr]==rs1||regmap[hr]==rs2)
4141 {
4142 if(regmap[hr]==0) {
4143 emit_zeroreg(hr);
4144 }
4145 else
4146 {
4147 emit_loadreg(regmap[hr],hr);
4148 }
4149 }
4150 }
4151 }
4152 }
4153}
4154
4155// Load registers prior to the start of a loop
4156// so that they are not loaded within the loop
4157static void loop_preload(signed char pre[],signed char entry[])
4158{
4159 int hr;
4160 for(hr=0;hr<HOST_REGS;hr++) {
4161 if(hr!=EXCLUDE_REG) {
4162 if(pre[hr]!=entry[hr]) {
4163 if(entry[hr]>=0) {
4164 if(get_reg(pre,entry[hr])<0) {
4165 assem_debug("loop preload:\n");
4166 //printf("loop preload: %d\n",hr);
4167 if(entry[hr]==0) {
4168 emit_zeroreg(hr);
4169 }
4170 else if(entry[hr]<TEMPREG)
4171 {
4172 emit_loadreg(entry[hr],hr);
4173 }
4174 else if(entry[hr]-64<TEMPREG)
4175 {
4176 emit_loadreg(entry[hr],hr);
4177 }
4178 }
4179 }
4180 }
4181 }
4182 }
4183}
4184
4185// Generate address for load/store instruction
4186// goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4187void address_generation(int i,struct regstat *i_regs,signed char entry[])
4188{
4189 if (dops[i].is_load || dops[i].is_store) {
4190 int ra=-1;
4191 int agr=AGEN1+(i&1);
4192 if(dops[i].itype==LOAD) {
4193 ra=get_reg(i_regs->regmap,dops[i].rt1);
4194 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4195 assert(ra>=0);
4196 }
4197 if(dops[i].itype==LOADLR) {
4198 ra=get_reg(i_regs->regmap,FTEMP);
4199 }
4200 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4201 ra=get_reg(i_regs->regmap,agr);
4202 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4203 }
4204 if(dops[i].itype==C2LS) {
4205 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4206 ra=get_reg(i_regs->regmap,FTEMP);
4207 else { // SWC1/SDC1/SWC2/SDC2
4208 ra=get_reg(i_regs->regmap,agr);
4209 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4210 }
4211 }
4212 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4213 if(ra>=0) {
4214 int offset=imm[i];
4215 int c=(i_regs->wasconst>>rs)&1;
4216 if(dops[i].rs1==0) {
4217 // Using r0 as a base address
4218 if(!entry||entry[ra]!=agr) {
4219 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4220 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4221 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4222 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4223 }else{
4224 emit_movimm(offset,ra);
4225 }
4226 } // else did it in the previous cycle
4227 }
4228 else if(rs<0) {
4229 if(!entry||entry[ra]!=dops[i].rs1)
4230 emit_loadreg(dops[i].rs1,ra);
4231 //if(!entry||entry[ra]!=dops[i].rs1)
4232 // printf("poor load scheduling!\n");
4233 }
4234 else if(c) {
4235 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4236 if(!entry||entry[ra]!=agr) {
4237 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4238 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4239 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4240 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4241 }else{
4242 emit_movimm(constmap[i][rs]+offset,ra);
4243 regs[i].loadedconst|=1<<ra;
4244 }
4245 } // else did it in the previous cycle
4246 } // else load_consts already did it
4247 }
4248 if(offset&&!c&&dops[i].rs1) {
4249 if(rs>=0) {
4250 emit_addimm(rs,offset,ra);
4251 }else{
4252 emit_addimm(ra,offset,ra);
4253 }
4254 }
4255 }
4256 }
4257 // Preload constants for next instruction
4258 if (dops[i+1].is_load || dops[i+1].is_store) {
4259 int agr,ra;
4260 // Actual address
4261 agr=AGEN1+((i+1)&1);
4262 ra=get_reg(i_regs->regmap,agr);
4263 if(ra>=0) {
4264 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4265 int offset=imm[i+1];
4266 int c=(regs[i+1].wasconst>>rs)&1;
4267 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4268 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4269 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4270 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4271 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4272 }else{
4273 emit_movimm(constmap[i+1][rs]+offset,ra);
4274 regs[i+1].loadedconst|=1<<ra;
4275 }
4276 }
4277 else if(dops[i+1].rs1==0) {
4278 // Using r0 as a base address
4279 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4280 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4281 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4282 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4283 }else{
4284 emit_movimm(offset,ra);
4285 }
4286 }
4287 }
4288 }
4289}
4290
4291static int get_final_value(int hr, int i, int *value)
4292{
4293 int reg=regs[i].regmap[hr];
4294 while(i<slen-1) {
4295 if(regs[i+1].regmap[hr]!=reg) break;
4296 if(!((regs[i+1].isconst>>hr)&1)) break;
4297 if(dops[i+1].bt) break;
4298 i++;
4299 }
4300 if(i<slen-1) {
4301 if (dops[i].is_jump) {
4302 *value=constmap[i][hr];
4303 return 1;
4304 }
4305 if(!dops[i+1].bt) {
4306 if (dops[i+1].is_jump) {
4307 // Load in delay slot, out-of-order execution
4308 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4309 {
4310 // Precompute load address
4311 *value=constmap[i][hr]+imm[i+2];
4312 return 1;
4313 }
4314 }
4315 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4316 {
4317 // Precompute load address
4318 *value=constmap[i][hr]+imm[i+1];
4319 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4320 return 1;
4321 }
4322 }
4323 }
4324 *value=constmap[i][hr];
4325 //printf("c=%lx\n",(long)constmap[i][hr]);
4326 if(i==slen-1) return 1;
4327 assert(reg < 64);
4328 return !((unneeded_reg[i+1]>>reg)&1);
4329}
4330
4331// Load registers with known constants
4332static void load_consts(signed char pre[],signed char regmap[],int i)
4333{
4334 int hr,hr2;
4335 // propagate loaded constant flags
4336 if(i==0||dops[i].bt)
4337 regs[i].loadedconst=0;
4338 else {
4339 for(hr=0;hr<HOST_REGS;hr++) {
4340 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4341 &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4342 {
4343 regs[i].loadedconst|=1<<hr;
4344 }
4345 }
4346 }
4347 // Load 32-bit regs
4348 for(hr=0;hr<HOST_REGS;hr++) {
4349 if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4350 //if(entry[hr]!=regmap[hr]) {
4351 if(!((regs[i].loadedconst>>hr)&1)) {
4352 assert(regmap[hr]<64);
4353 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4354 int value,similar=0;
4355 if(get_final_value(hr,i,&value)) {
4356 // see if some other register has similar value
4357 for(hr2=0;hr2<HOST_REGS;hr2++) {
4358 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4359 if(is_similar_value(value,constmap[i][hr2])) {
4360 similar=1;
4361 break;
4362 }
4363 }
4364 }
4365 if(similar) {
4366 int value2;
4367 if(get_final_value(hr2,i,&value2)) // is this needed?
4368 emit_movimm_from(value2,hr2,value,hr);
4369 else
4370 emit_movimm(value,hr);
4371 }
4372 else if(value==0) {
4373 emit_zeroreg(hr);
4374 }
4375 else {
4376 emit_movimm(value,hr);
4377 }
4378 }
4379 regs[i].loadedconst|=1<<hr;
4380 }
4381 }
4382 }
4383 }
4384}
4385
4386void load_all_consts(signed char regmap[], u_int dirty, int i)
4387{
4388 int hr;
4389 // Load 32-bit regs
4390 for(hr=0;hr<HOST_REGS;hr++) {
4391 if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4392 assert(regmap[hr] < 64);
4393 if(((regs[i].isconst>>hr)&1)&&regmap[hr]>0) {
4394 int value=constmap[i][hr];
4395 if(value==0) {
4396 emit_zeroreg(hr);
4397 }
4398 else {
4399 emit_movimm(value,hr);
4400 }
4401 }
4402 }
4403 }
4404}
4405
4406// Write out all dirty registers (except cycle count)
4407static void wb_dirtys(signed char i_regmap[],uint64_t i_dirty)
4408{
4409 int hr;
4410 for(hr=0;hr<HOST_REGS;hr++) {
4411 if(hr!=EXCLUDE_REG) {
4412 if(i_regmap[hr]>0) {
4413 if(i_regmap[hr]!=CCREG) {
4414 if((i_dirty>>hr)&1) {
4415 assert(i_regmap[hr]<64);
4416 emit_storereg(i_regmap[hr],hr);
4417 }
4418 }
4419 }
4420 }
4421 }
4422}
4423
4424// Write out dirty registers that we need to reload (pair with load_needed_regs)
4425// This writes the registers not written by store_regs_bt
4426void wb_needed_dirtys(signed char i_regmap[],uint64_t i_dirty,int addr)
4427{
4428 int hr;
4429 int t=(addr-start)>>2;
4430 for(hr=0;hr<HOST_REGS;hr++) {
4431 if(hr!=EXCLUDE_REG) {
4432 if(i_regmap[hr]>0) {
4433 if(i_regmap[hr]!=CCREG) {
4434 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4435 if((i_dirty>>hr)&1) {
4436 assert(i_regmap[hr]<64);
4437 emit_storereg(i_regmap[hr],hr);
4438 }
4439 }
4440 }
4441 }
4442 }
4443 }
4444}
4445
4446// Load all registers (except cycle count)
4447void load_all_regs(signed char i_regmap[])
4448{
4449 int hr;
4450 for(hr=0;hr<HOST_REGS;hr++) {
4451 if(hr!=EXCLUDE_REG) {
4452 if(i_regmap[hr]==0) {
4453 emit_zeroreg(hr);
4454 }
4455 else
4456 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4457 {
4458 emit_loadreg(i_regmap[hr],hr);
4459 }
4460 }
4461 }
4462}
4463
4464// Load all current registers also needed by next instruction
4465void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4466{
4467 int hr;
4468 for(hr=0;hr<HOST_REGS;hr++) {
4469 if(hr!=EXCLUDE_REG) {
4470 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4471 if(i_regmap[hr]==0) {
4472 emit_zeroreg(hr);
4473 }
4474 else
4475 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4476 {
4477 emit_loadreg(i_regmap[hr],hr);
4478 }
4479 }
4480 }
4481 }
4482}
4483
4484// Load all regs, storing cycle count if necessary
4485void load_regs_entry(int t)
4486{
4487 int hr;
4488 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4489 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4490 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4491 emit_storereg(CCREG,HOST_CCREG);
4492 }
4493 // Load 32-bit regs
4494 for(hr=0;hr<HOST_REGS;hr++) {
4495 if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4496 if(regs[t].regmap_entry[hr]==0) {
4497 emit_zeroreg(hr);
4498 }
4499 else if(regs[t].regmap_entry[hr]!=CCREG)
4500 {
4501 emit_loadreg(regs[t].regmap_entry[hr],hr);
4502 }
4503 }
4504 }
4505}
4506
4507// Store dirty registers prior to branch
4508void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4509{
4510 if(internal_branch(addr))
4511 {
4512 int t=(addr-start)>>2;
4513 int hr;
4514 for(hr=0;hr<HOST_REGS;hr++) {
4515 if(hr!=EXCLUDE_REG) {
4516 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4517 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4518 if((i_dirty>>hr)&1) {
4519 assert(i_regmap[hr]<64);
4520 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4521 emit_storereg(i_regmap[hr],hr);
4522 }
4523 }
4524 }
4525 }
4526 }
4527 }
4528 else
4529 {
4530 // Branch out of this block, write out all dirty regs
4531 wb_dirtys(i_regmap,i_dirty);
4532 }
4533}
4534
4535// Load all needed registers for branch target
4536static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4537{
4538 //if(addr>=start && addr<(start+slen*4))
4539 if(internal_branch(addr))
4540 {
4541 int t=(addr-start)>>2;
4542 int hr;
4543 // Store the cycle count before loading something else
4544 if(i_regmap[HOST_CCREG]!=CCREG) {
4545 assert(i_regmap[HOST_CCREG]==-1);
4546 }
4547 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4548 emit_storereg(CCREG,HOST_CCREG);
4549 }
4550 // Load 32-bit regs
4551 for(hr=0;hr<HOST_REGS;hr++) {
4552 if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4553 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4554 if(regs[t].regmap_entry[hr]==0) {
4555 emit_zeroreg(hr);
4556 }
4557 else if(regs[t].regmap_entry[hr]!=CCREG)
4558 {
4559 emit_loadreg(regs[t].regmap_entry[hr],hr);
4560 }
4561 }
4562 }
4563 }
4564 }
4565}
4566
4567static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4568{
4569 if(addr>=start && addr<start+slen*4-4)
4570 {
4571 int t=(addr-start)>>2;
4572 int hr;
4573 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4574 for(hr=0;hr<HOST_REGS;hr++)
4575 {
4576 if(hr!=EXCLUDE_REG)
4577 {
4578 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4579 {
4580 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4581 {
4582 return 0;
4583 }
4584 else
4585 if((i_dirty>>hr)&1)
4586 {
4587 if(i_regmap[hr]<TEMPREG)
4588 {
4589 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4590 return 0;
4591 }
4592 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4593 {
4594 assert(0);
4595 }
4596 }
4597 }
4598 else // Same register but is it 32-bit or dirty?
4599 if(i_regmap[hr]>=0)
4600 {
4601 if(!((regs[t].dirty>>hr)&1))
4602 {
4603 if((i_dirty>>hr)&1)
4604 {
4605 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4606 {
4607 //printf("%x: dirty no match\n",addr);
4608 return 0;
4609 }
4610 }
4611 }
4612 }
4613 }
4614 }
4615 // Delay slots are not valid branch targets
4616 //if(t>0&&(dops[t-1].is_jump) return 0;
4617 // Delay slots require additional processing, so do not match
4618 if(dops[t].is_ds) return 0;
4619 }
4620 else
4621 {
4622 int hr;
4623 for(hr=0;hr<HOST_REGS;hr++)
4624 {
4625 if(hr!=EXCLUDE_REG)
4626 {
4627 if(i_regmap[hr]>=0)
4628 {
4629 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4630 {
4631 if((i_dirty>>hr)&1)
4632 {
4633 return 0;
4634 }
4635 }
4636 }
4637 }
4638 }
4639 }
4640 return 1;
4641}
4642
4643#ifdef DRC_DBG
4644static void drc_dbg_emit_do_cmp(int i)
4645{
4646 extern void do_insn_cmp();
4647 //extern int cycle;
4648 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4649
4650 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4651 save_regs(reglist);
4652 // write out changed consts to match the interpreter
4653 if (i > 0 && !dops[i].bt) {
4654 for (hr = 0; hr < HOST_REGS; hr++) {
4655 int reg = regs[i-1].regmap[hr];
4656 if (hr == EXCLUDE_REG || reg < 0)
4657 continue;
4658 if (!((regs[i-1].isconst >> hr) & 1))
4659 continue;
4660 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4661 continue;
4662 emit_movimm(constmap[i-1][hr],0);
4663 emit_storereg(reg, 0);
4664 }
4665 }
4666 emit_movimm(start+i*4,0);
4667 emit_writeword(0,&pcaddr);
4668 emit_far_call(do_insn_cmp);
4669 //emit_readword(&cycle,0);
4670 //emit_addimm(0,2,0);
4671 //emit_writeword(0,&cycle);
4672 (void)get_reg2;
4673 restore_regs(reglist);
4674 assem_debug("\\\\do_insn_cmp\n");
4675}
4676#else
4677#define drc_dbg_emit_do_cmp(x)
4678#endif
4679
4680// Used when a branch jumps into the delay slot of another branch
4681static void ds_assemble_entry(int i)
4682{
4683 int t=(ba[i]-start)>>2;
4684 if (!instr_addr[t])
4685 instr_addr[t] = out;
4686 assem_debug("Assemble delay slot at %x\n",ba[i]);
4687 assem_debug("<->\n");
4688 drc_dbg_emit_do_cmp(t);
4689 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4690 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4691 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4692 address_generation(t,&regs[t],regs[t].regmap_entry);
4693 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4694 load_regs(regs[t].regmap_entry,regs[t].regmap,ROREG,ROREG);
4695 if (dops[t].is_store)
4696 load_regs(regs[t].regmap_entry,regs[t].regmap,INVCP,INVCP);
4697 is_delayslot=0;
4698 switch(dops[t].itype) {
4699 case ALU:
4700 alu_assemble(t,&regs[t]);break;
4701 case IMM16:
4702 imm16_assemble(t,&regs[t]);break;
4703 case SHIFT:
4704 shift_assemble(t,&regs[t]);break;
4705 case SHIFTIMM:
4706 shiftimm_assemble(t,&regs[t]);break;
4707 case LOAD:
4708 load_assemble(t,&regs[t]);break;
4709 case LOADLR:
4710 loadlr_assemble(t,&regs[t]);break;
4711 case STORE:
4712 store_assemble(t,&regs[t]);break;
4713 case STORELR:
4714 storelr_assemble(t,&regs[t]);break;
4715 case COP0:
4716 cop0_assemble(t,&regs[t]);break;
4717 case COP1:
4718 cop1_assemble(t,&regs[t]);break;
4719 case C1LS:
4720 c1ls_assemble(t,&regs[t]);break;
4721 case COP2:
4722 cop2_assemble(t,&regs[t]);break;
4723 case C2LS:
4724 c2ls_assemble(t,&regs[t]);break;
4725 case C2OP:
4726 c2op_assemble(t,&regs[t]);break;
4727 case MULTDIV:
4728 multdiv_assemble(t,&regs[t]);
4729 multdiv_prepare_stall(i,&regs[t]);
4730 break;
4731 case MOV:
4732 mov_assemble(t,&regs[t]);break;
4733 case SYSCALL:
4734 case HLECALL:
4735 case INTCALL:
4736 case SPAN:
4737 case UJUMP:
4738 case RJUMP:
4739 case CJUMP:
4740 case SJUMP:
4741 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4742 }
4743 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4744 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4745 if(internal_branch(ba[i]+4))
4746 assem_debug("branch: internal\n");
4747 else
4748 assem_debug("branch: external\n");
4749 assert(internal_branch(ba[i]+4));
4750 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4751 emit_jmp(0);
4752}
4753
4754static void emit_extjump(void *addr, u_int target)
4755{
4756 emit_extjump2(addr, target, dyna_linker);
4757}
4758
4759static void emit_extjump_ds(void *addr, u_int target)
4760{
4761 emit_extjump2(addr, target, dyna_linker_ds);
4762}
4763
4764// Load 2 immediates optimizing for small code size
4765static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4766{
4767 emit_movimm(imm1,rt1);
4768 emit_movimm_from(imm1,rt1,imm2,rt2);
4769}
4770
4771void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4772{
4773 int count;
4774 void *jaddr;
4775 void *idle=NULL;
4776 int t=0;
4777 if(dops[i].itype==RJUMP)
4778 {
4779 *adj=0;
4780 }
4781 //if(ba[i]>=start && ba[i]<(start+slen*4))
4782 if(internal_branch(ba[i]))
4783 {
4784 t=(ba[i]-start)>>2;
4785 if(dops[t].is_ds) *adj=-1; // Branch into delay slot adds an extra cycle
4786 else *adj=ccadj[t];
4787 }
4788 else
4789 {
4790 *adj=0;
4791 }
4792 count=ccadj[i];
4793 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4794 // Idle loop
4795 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4796 idle=out;
4797 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4798 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4799 jaddr=out;
4800 emit_jmp(0);
4801 }
4802 else if(*adj==0||invert) {
4803 int cycles=CLOCK_ADJUST(count+2);
4804 // faster loop HACK
4805#if 0
4806 if (t&&*adj) {
4807 int rel=t-i;
4808 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4809 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4810 }
4811#endif
4812 emit_addimm_and_set_flags(cycles,HOST_CCREG);
4813 jaddr=out;
4814 emit_jns(0);
4815 }
4816 else
4817 {
4818 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4819 jaddr=out;
4820 emit_jns(0);
4821 }
4822 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4823}
4824
4825static void do_ccstub(int n)
4826{
4827 literal_pool(256);
4828 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4829 set_jump_target(stubs[n].addr, out);
4830 int i=stubs[n].b;
4831 if(stubs[n].d==NULLDS) {
4832 // Delay slot instruction is nullified ("likely" branch)
4833 wb_dirtys(regs[i].regmap,regs[i].dirty);
4834 }
4835 else if(stubs[n].d!=TAKEN) {
4836 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
4837 }
4838 else {
4839 if(internal_branch(ba[i]))
4840 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
4841 }
4842 if(stubs[n].c!=-1)
4843 {
4844 // Save PC as return address
4845 emit_movimm(stubs[n].c,EAX);
4846 emit_writeword(EAX,&pcaddr);
4847 }
4848 else
4849 {
4850 // Return address depends on which way the branch goes
4851 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
4852 {
4853 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
4854 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
4855 if(dops[i].rs1==0)
4856 {
4857 s1l=s2l;
4858 s2l=-1;
4859 }
4860 else if(dops[i].rs2==0)
4861 {
4862 s2l=-1;
4863 }
4864 assert(s1l>=0);
4865 #ifdef DESTRUCTIVE_WRITEBACK
4866 if(dops[i].rs1) {
4867 if((branch_regs[i].dirty>>s1l)&&1)
4868 emit_loadreg(dops[i].rs1,s1l);
4869 }
4870 else {
4871 if((branch_regs[i].dirty>>s1l)&1)
4872 emit_loadreg(dops[i].rs2,s1l);
4873 }
4874 if(s2l>=0)
4875 if((branch_regs[i].dirty>>s2l)&1)
4876 emit_loadreg(dops[i].rs2,s2l);
4877 #endif
4878 int hr=0;
4879 int addr=-1,alt=-1,ntaddr=-1;
4880 while(hr<HOST_REGS)
4881 {
4882 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4883 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4884 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4885 {
4886 addr=hr++;break;
4887 }
4888 hr++;
4889 }
4890 while(hr<HOST_REGS)
4891 {
4892 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4893 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4894 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4895 {
4896 alt=hr++;break;
4897 }
4898 hr++;
4899 }
4900 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
4901 {
4902 while(hr<HOST_REGS)
4903 {
4904 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4905 (branch_regs[i].regmap[hr]&63)!=dops[i].rs1 &&
4906 (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 )
4907 {
4908 ntaddr=hr;break;
4909 }
4910 hr++;
4911 }
4912 assert(hr<HOST_REGS);
4913 }
4914 if((dops[i].opcode&0x2f)==4) // BEQ
4915 {
4916 #ifdef HAVE_CMOV_IMM
4917 if(s2l>=0) emit_cmp(s1l,s2l);
4918 else emit_test(s1l,s1l);
4919 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4920 #else
4921 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4922 if(s2l>=0) emit_cmp(s1l,s2l);
4923 else emit_test(s1l,s1l);
4924 emit_cmovne_reg(alt,addr);
4925 #endif
4926 }
4927 if((dops[i].opcode&0x2f)==5) // BNE
4928 {
4929 #ifdef HAVE_CMOV_IMM
4930 if(s2l>=0) emit_cmp(s1l,s2l);
4931 else emit_test(s1l,s1l);
4932 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4933 #else
4934 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4935 if(s2l>=0) emit_cmp(s1l,s2l);
4936 else emit_test(s1l,s1l);
4937 emit_cmovne_reg(alt,addr);
4938 #endif
4939 }
4940 if((dops[i].opcode&0x2f)==6) // BLEZ
4941 {
4942 //emit_movimm(ba[i],alt);
4943 //emit_movimm(start+i*4+8,addr);
4944 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4945 emit_cmpimm(s1l,1);
4946 emit_cmovl_reg(alt,addr);
4947 }
4948 if((dops[i].opcode&0x2f)==7) // BGTZ
4949 {
4950 //emit_movimm(ba[i],addr);
4951 //emit_movimm(start+i*4+8,ntaddr);
4952 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4953 emit_cmpimm(s1l,1);
4954 emit_cmovl_reg(ntaddr,addr);
4955 }
4956 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
4957 {
4958 //emit_movimm(ba[i],alt);
4959 //emit_movimm(start+i*4+8,addr);
4960 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4961 emit_test(s1l,s1l);
4962 emit_cmovs_reg(alt,addr);
4963 }
4964 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
4965 {
4966 //emit_movimm(ba[i],addr);
4967 //emit_movimm(start+i*4+8,alt);
4968 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4969 emit_test(s1l,s1l);
4970 emit_cmovs_reg(alt,addr);
4971 }
4972 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
4973 if(source[i]&0x10000) // BC1T
4974 {
4975 //emit_movimm(ba[i],alt);
4976 //emit_movimm(start+i*4+8,addr);
4977 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4978 emit_testimm(s1l,0x800000);
4979 emit_cmovne_reg(alt,addr);
4980 }
4981 else // BC1F
4982 {
4983 //emit_movimm(ba[i],addr);
4984 //emit_movimm(start+i*4+8,alt);
4985 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4986 emit_testimm(s1l,0x800000);
4987 emit_cmovne_reg(alt,addr);
4988 }
4989 }
4990 emit_writeword(addr,&pcaddr);
4991 }
4992 else
4993 if(dops[i].itype==RJUMP)
4994 {
4995 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
4996 if (ds_writes_rjump_rs(i)) {
4997 r=get_reg(branch_regs[i].regmap,RTEMP);
4998 }
4999 emit_writeword(r,&pcaddr);
5000 }
5001 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5002 }
5003 // Update cycle count
5004 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5005 if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
5006 emit_far_call(cc_interrupt);
5007 if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((signed int)stubs[n].a),HOST_CCREG);
5008 if(stubs[n].d==TAKEN) {
5009 if(internal_branch(ba[i]))
5010 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5011 else if(dops[i].itype==RJUMP) {
5012 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5013 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5014 else
5015 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5016 }
5017 }else if(stubs[n].d==NOTTAKEN) {
5018 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5019 else load_all_regs(branch_regs[i].regmap);
5020 }else if(stubs[n].d==NULLDS) {
5021 // Delay slot instruction is nullified ("likely" branch)
5022 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5023 else load_all_regs(regs[i].regmap);
5024 }else{
5025 load_all_regs(branch_regs[i].regmap);
5026 }
5027 if (stubs[n].retaddr)
5028 emit_jmp(stubs[n].retaddr);
5029 else
5030 do_jump_vaddr(stubs[n].e);
5031}
5032
5033static void add_to_linker(void *addr, u_int target, int ext)
5034{
5035 assert(linkcount < ARRAY_SIZE(link_addr));
5036 link_addr[linkcount].addr = addr;
5037 link_addr[linkcount].target = target;
5038 link_addr[linkcount].ext = ext;
5039 linkcount++;
5040}
5041
5042static void ujump_assemble_write_ra(int i)
5043{
5044 int rt;
5045 unsigned int return_address;
5046 rt=get_reg(branch_regs[i].regmap,31);
5047 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5048 //assert(rt>=0);
5049 return_address=start+i*4+8;
5050 if(rt>=0) {
5051 #ifdef USE_MINI_HT
5052 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5053 int temp=-1; // note: must be ds-safe
5054 #ifdef HOST_TEMPREG
5055 temp=HOST_TEMPREG;
5056 #endif
5057 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5058 else emit_movimm(return_address,rt);
5059 }
5060 else
5061 #endif
5062 {
5063 #ifdef REG_PREFETCH
5064 if(temp>=0)
5065 {
5066 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5067 }
5068 #endif
5069 emit_movimm(return_address,rt); // PC into link register
5070 #ifdef IMM_PREFETCH
5071 emit_prefetch(hash_table_get(return_address));
5072 #endif
5073 }
5074 }
5075}
5076
5077static void ujump_assemble(int i,struct regstat *i_regs)
5078{
5079 int ra_done=0;
5080 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5081 address_generation(i+1,i_regs,regs[i].regmap_entry);
5082 #ifdef REG_PREFETCH
5083 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5084 if(dops[i].rt1==31&&temp>=0)
5085 {
5086 signed char *i_regmap=i_regs->regmap;
5087 int return_address=start+i*4+8;
5088 if(get_reg(branch_regs[i].regmap,31)>0)
5089 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5090 }
5091 #endif
5092 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5093 ujump_assemble_write_ra(i); // writeback ra for DS
5094 ra_done=1;
5095 }
5096 ds_assemble(i+1,i_regs);
5097 uint64_t bc_unneeded=branch_regs[i].u;
5098 bc_unneeded|=1|(1LL<<dops[i].rt1);
5099 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5100 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5101 if(!ra_done&&dops[i].rt1==31)
5102 ujump_assemble_write_ra(i);
5103 int cc,adj;
5104 cc=get_reg(branch_regs[i].regmap,CCREG);
5105 assert(cc==HOST_CCREG);
5106 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5107 #ifdef REG_PREFETCH
5108 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5109 #endif
5110 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5111 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5112 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5113 if(internal_branch(ba[i]))
5114 assem_debug("branch: internal\n");
5115 else
5116 assem_debug("branch: external\n");
5117 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5118 ds_assemble_entry(i);
5119 }
5120 else {
5121 add_to_linker(out,ba[i],internal_branch(ba[i]));
5122 emit_jmp(0);
5123 }
5124}
5125
5126static void rjump_assemble_write_ra(int i)
5127{
5128 int rt,return_address;
5129 assert(dops[i+1].rt1!=dops[i].rt1);
5130 assert(dops[i+1].rt2!=dops[i].rt1);
5131 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5132 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5133 assert(rt>=0);
5134 return_address=start+i*4+8;
5135 #ifdef REG_PREFETCH
5136 if(temp>=0)
5137 {
5138 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5139 }
5140 #endif
5141 emit_movimm(return_address,rt); // PC into link register
5142 #ifdef IMM_PREFETCH
5143 emit_prefetch(hash_table_get(return_address));
5144 #endif
5145}
5146
5147static void rjump_assemble(int i,struct regstat *i_regs)
5148{
5149 int temp;
5150 int rs,cc;
5151 int ra_done=0;
5152 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5153 assert(rs>=0);
5154 if (ds_writes_rjump_rs(i)) {
5155 // Delay slot abuse, make a copy of the branch address register
5156 temp=get_reg(branch_regs[i].regmap,RTEMP);
5157 assert(temp>=0);
5158 assert(regs[i].regmap[temp]==RTEMP);
5159 emit_mov(rs,temp);
5160 rs=temp;
5161 }
5162 address_generation(i+1,i_regs,regs[i].regmap_entry);
5163 #ifdef REG_PREFETCH
5164 if(dops[i].rt1==31)
5165 {
5166 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5167 signed char *i_regmap=i_regs->regmap;
5168 int return_address=start+i*4+8;
5169 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5170 }
5171 }
5172 #endif
5173 #ifdef USE_MINI_HT
5174 if(dops[i].rs1==31) {
5175 int rh=get_reg(regs[i].regmap,RHASH);
5176 if(rh>=0) do_preload_rhash(rh);
5177 }
5178 #endif
5179 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5180 rjump_assemble_write_ra(i);
5181 ra_done=1;
5182 }
5183 ds_assemble(i+1,i_regs);
5184 uint64_t bc_unneeded=branch_regs[i].u;
5185 bc_unneeded|=1|(1LL<<dops[i].rt1);
5186 bc_unneeded&=~(1LL<<dops[i].rs1);
5187 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5188 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5189 if(!ra_done&&dops[i].rt1!=0)
5190 rjump_assemble_write_ra(i);
5191 cc=get_reg(branch_regs[i].regmap,CCREG);
5192 assert(cc==HOST_CCREG);
5193 (void)cc;
5194 #ifdef USE_MINI_HT
5195 int rh=get_reg(branch_regs[i].regmap,RHASH);
5196 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5197 if(dops[i].rs1==31) {
5198 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5199 do_preload_rhtbl(ht);
5200 do_rhash(rs,rh);
5201 }
5202 #endif
5203 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5204 #ifdef DESTRUCTIVE_WRITEBACK
5205 if((branch_regs[i].dirty>>rs)&1) {
5206 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5207 emit_loadreg(dops[i].rs1,rs);
5208 }
5209 }
5210 #endif
5211 #ifdef REG_PREFETCH
5212 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5213 #endif
5214 #ifdef USE_MINI_HT
5215 if(dops[i].rs1==31) {
5216 do_miniht_load(ht,rh);
5217 }
5218 #endif
5219 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5220 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5221 //assert(adj==0);
5222 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5223 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5224 if(dops[i+1].itype==COP0&&(source[i+1]&0x3f)==0x10)
5225 // special case for RFE
5226 emit_jmp(0);
5227 else
5228 emit_jns(0);
5229 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5230 #ifdef USE_MINI_HT
5231 if(dops[i].rs1==31) {
5232 do_miniht_jump(rs,rh,ht);
5233 }
5234 else
5235 #endif
5236 {
5237 do_jump_vaddr(rs);
5238 }
5239 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5240 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5241 #endif
5242}
5243
5244static void cjump_assemble(int i,struct regstat *i_regs)
5245{
5246 signed char *i_regmap=i_regs->regmap;
5247 int cc;
5248 int match;
5249 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5250 assem_debug("match=%d\n",match);
5251 int s1l,s2l;
5252 int unconditional=0,nop=0;
5253 int invert=0;
5254 int internal=internal_branch(ba[i]);
5255 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5256 if(!match) invert=1;
5257 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5258 if(i>(ba[i]-start)>>2) invert=1;
5259 #endif
5260 #ifdef __aarch64__
5261 invert=1; // because of near cond. branches
5262 #endif
5263
5264 if(dops[i].ooo) {
5265 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5266 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5267 }
5268 else {
5269 s1l=get_reg(i_regmap,dops[i].rs1);
5270 s2l=get_reg(i_regmap,dops[i].rs2);
5271 }
5272 if(dops[i].rs1==0&&dops[i].rs2==0)
5273 {
5274 if(dops[i].opcode&1) nop=1;
5275 else unconditional=1;
5276 //assert(dops[i].opcode!=5);
5277 //assert(dops[i].opcode!=7);
5278 //assert(dops[i].opcode!=0x15);
5279 //assert(dops[i].opcode!=0x17);
5280 }
5281 else if(dops[i].rs1==0)
5282 {
5283 s1l=s2l;
5284 s2l=-1;
5285 }
5286 else if(dops[i].rs2==0)
5287 {
5288 s2l=-1;
5289 }
5290
5291 if(dops[i].ooo) {
5292 // Out of order execution (delay slot first)
5293 //printf("OOOE\n");
5294 address_generation(i+1,i_regs,regs[i].regmap_entry);
5295 ds_assemble(i+1,i_regs);
5296 int adj;
5297 uint64_t bc_unneeded=branch_regs[i].u;
5298 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5299 bc_unneeded|=1;
5300 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5301 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5302 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5303 cc=get_reg(branch_regs[i].regmap,CCREG);
5304 assert(cc==HOST_CCREG);
5305 if(unconditional)
5306 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5307 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5308 //assem_debug("cycle count (adj)\n");
5309 if(unconditional) {
5310 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5311 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5312 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5313 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5314 if(internal)
5315 assem_debug("branch: internal\n");
5316 else
5317 assem_debug("branch: external\n");
5318 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5319 ds_assemble_entry(i);
5320 }
5321 else {
5322 add_to_linker(out,ba[i],internal);
5323 emit_jmp(0);
5324 }
5325 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5326 if(((u_int)out)&7) emit_addnop(0);
5327 #endif
5328 }
5329 }
5330 else if(nop) {
5331 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5332 void *jaddr=out;
5333 emit_jns(0);
5334 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5335 }
5336 else {
5337 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5338 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5339 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5340
5341 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5342 assert(s1l>=0);
5343 if(dops[i].opcode==4) // BEQ
5344 {
5345 if(s2l>=0) emit_cmp(s1l,s2l);
5346 else emit_test(s1l,s1l);
5347 if(invert){
5348 nottaken=out;
5349 emit_jne(DJT_1);
5350 }else{
5351 add_to_linker(out,ba[i],internal);
5352 emit_jeq(0);
5353 }
5354 }
5355 if(dops[i].opcode==5) // BNE
5356 {
5357 if(s2l>=0) emit_cmp(s1l,s2l);
5358 else emit_test(s1l,s1l);
5359 if(invert){
5360 nottaken=out;
5361 emit_jeq(DJT_1);
5362 }else{
5363 add_to_linker(out,ba[i],internal);
5364 emit_jne(0);
5365 }
5366 }
5367 if(dops[i].opcode==6) // BLEZ
5368 {
5369 emit_cmpimm(s1l,1);
5370 if(invert){
5371 nottaken=out;
5372 emit_jge(DJT_1);
5373 }else{
5374 add_to_linker(out,ba[i],internal);
5375 emit_jl(0);
5376 }
5377 }
5378 if(dops[i].opcode==7) // BGTZ
5379 {
5380 emit_cmpimm(s1l,1);
5381 if(invert){
5382 nottaken=out;
5383 emit_jl(DJT_1);
5384 }else{
5385 add_to_linker(out,ba[i],internal);
5386 emit_jge(0);
5387 }
5388 }
5389 if(invert) {
5390 if(taken) set_jump_target(taken, out);
5391 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5392 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5393 if(adj) {
5394 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5395 add_to_linker(out,ba[i],internal);
5396 }else{
5397 emit_addnop(13);
5398 add_to_linker(out,ba[i],internal*2);
5399 }
5400 emit_jmp(0);
5401 }else
5402 #endif
5403 {
5404 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5405 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5406 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5407 if(internal)
5408 assem_debug("branch: internal\n");
5409 else
5410 assem_debug("branch: external\n");
5411 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5412 ds_assemble_entry(i);
5413 }
5414 else {
5415 add_to_linker(out,ba[i],internal);
5416 emit_jmp(0);
5417 }
5418 }
5419 set_jump_target(nottaken, out);
5420 }
5421
5422 if(nottaken1) set_jump_target(nottaken1, out);
5423 if(adj) {
5424 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5425 }
5426 } // (!unconditional)
5427 } // if(ooo)
5428 else
5429 {
5430 // In-order execution (branch first)
5431 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5432 if(!unconditional&&!nop) {
5433 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5434 assert(s1l>=0);
5435 if((dops[i].opcode&0x2f)==4) // BEQ
5436 {
5437 if(s2l>=0) emit_cmp(s1l,s2l);
5438 else emit_test(s1l,s1l);
5439 nottaken=out;
5440 emit_jne(DJT_2);
5441 }
5442 if((dops[i].opcode&0x2f)==5) // BNE
5443 {
5444 if(s2l>=0) emit_cmp(s1l,s2l);
5445 else emit_test(s1l,s1l);
5446 nottaken=out;
5447 emit_jeq(DJT_2);
5448 }
5449 if((dops[i].opcode&0x2f)==6) // BLEZ
5450 {
5451 emit_cmpimm(s1l,1);
5452 nottaken=out;
5453 emit_jge(DJT_2);
5454 }
5455 if((dops[i].opcode&0x2f)==7) // BGTZ
5456 {
5457 emit_cmpimm(s1l,1);
5458 nottaken=out;
5459 emit_jl(DJT_2);
5460 }
5461 } // if(!unconditional)
5462 int adj;
5463 uint64_t ds_unneeded=branch_regs[i].u;
5464 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5465 ds_unneeded|=1;
5466 // branch taken
5467 if(!nop) {
5468 if(taken) set_jump_target(taken, out);
5469 assem_debug("1:\n");
5470 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5471 // load regs
5472 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5473 address_generation(i+1,&branch_regs[i],0);
5474 if (ram_offset)
5475 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5476 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5477 ds_assemble(i+1,&branch_regs[i]);
5478 cc=get_reg(branch_regs[i].regmap,CCREG);
5479 if(cc==-1) {
5480 emit_loadreg(CCREG,cc=HOST_CCREG);
5481 // CHECK: Is the following instruction (fall thru) allocated ok?
5482 }
5483 assert(cc==HOST_CCREG);
5484 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5485 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5486 assem_debug("cycle count (adj)\n");
5487 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5488 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5489 if(internal)
5490 assem_debug("branch: internal\n");
5491 else
5492 assem_debug("branch: external\n");
5493 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5494 ds_assemble_entry(i);
5495 }
5496 else {
5497 add_to_linker(out,ba[i],internal);
5498 emit_jmp(0);
5499 }
5500 }
5501 // branch not taken
5502 if(!unconditional) {
5503 if(nottaken1) set_jump_target(nottaken1, out);
5504 set_jump_target(nottaken, out);
5505 assem_debug("2:\n");
5506 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5507 // load regs
5508 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5509 address_generation(i+1,&branch_regs[i],0);
5510 if (ram_offset)
5511 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5512 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5513 ds_assemble(i+1,&branch_regs[i]);
5514 cc=get_reg(branch_regs[i].regmap,CCREG);
5515 if (cc == -1) {
5516 // Cycle count isn't in a register, temporarily load it then write it out
5517 emit_loadreg(CCREG,HOST_CCREG);
5518 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5519 void *jaddr=out;
5520 emit_jns(0);
5521 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5522 emit_storereg(CCREG,HOST_CCREG);
5523 }
5524 else{
5525 cc=get_reg(i_regmap,CCREG);
5526 assert(cc==HOST_CCREG);
5527 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5528 void *jaddr=out;
5529 emit_jns(0);
5530 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5531 }
5532 }
5533 }
5534}
5535
5536static void sjump_assemble(int i,struct regstat *i_regs)
5537{
5538 signed char *i_regmap=i_regs->regmap;
5539 int cc;
5540 int match;
5541 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5542 assem_debug("smatch=%d\n",match);
5543 int s1l;
5544 int unconditional=0,nevertaken=0;
5545 int invert=0;
5546 int internal=internal_branch(ba[i]);
5547 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5548 if(!match) invert=1;
5549 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5550 if(i>(ba[i]-start)>>2) invert=1;
5551 #endif
5552 #ifdef __aarch64__
5553 invert=1; // because of near cond. branches
5554 #endif
5555
5556 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5557 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5558
5559 if(dops[i].ooo) {
5560 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5561 }
5562 else {
5563 s1l=get_reg(i_regmap,dops[i].rs1);
5564 }
5565 if(dops[i].rs1==0)
5566 {
5567 if(dops[i].opcode2&1) unconditional=1;
5568 else nevertaken=1;
5569 // These are never taken (r0 is never less than zero)
5570 //assert(dops[i].opcode2!=0);
5571 //assert(dops[i].opcode2!=2);
5572 //assert(dops[i].opcode2!=0x10);
5573 //assert(dops[i].opcode2!=0x12);
5574 }
5575
5576 if(dops[i].ooo) {
5577 // Out of order execution (delay slot first)
5578 //printf("OOOE\n");
5579 address_generation(i+1,i_regs,regs[i].regmap_entry);
5580 ds_assemble(i+1,i_regs);
5581 int adj;
5582 uint64_t bc_unneeded=branch_regs[i].u;
5583 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5584 bc_unneeded|=1;
5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5586 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5587 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5588 if(dops[i].rt1==31) {
5589 int rt,return_address;
5590 rt=get_reg(branch_regs[i].regmap,31);
5591 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5592 if(rt>=0) {
5593 // Save the PC even if the branch is not taken
5594 return_address=start+i*4+8;
5595 emit_movimm(return_address,rt); // PC into link register
5596 #ifdef IMM_PREFETCH
5597 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5598 #endif
5599 }
5600 }
5601 cc=get_reg(branch_regs[i].regmap,CCREG);
5602 assert(cc==HOST_CCREG);
5603 if(unconditional)
5604 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5605 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5606 assem_debug("cycle count (adj)\n");
5607 if(unconditional) {
5608 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5609 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5610 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5611 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5612 if(internal)
5613 assem_debug("branch: internal\n");
5614 else
5615 assem_debug("branch: external\n");
5616 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5617 ds_assemble_entry(i);
5618 }
5619 else {
5620 add_to_linker(out,ba[i],internal);
5621 emit_jmp(0);
5622 }
5623 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5624 if(((u_int)out)&7) emit_addnop(0);
5625 #endif
5626 }
5627 }
5628 else if(nevertaken) {
5629 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5630 void *jaddr=out;
5631 emit_jns(0);
5632 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5633 }
5634 else {
5635 void *nottaken = NULL;
5636 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5637 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5638 {
5639 assert(s1l>=0);
5640 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5641 {
5642 emit_test(s1l,s1l);
5643 if(invert){
5644 nottaken=out;
5645 emit_jns(DJT_1);
5646 }else{
5647 add_to_linker(out,ba[i],internal);
5648 emit_js(0);
5649 }
5650 }
5651 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5652 {
5653 emit_test(s1l,s1l);
5654 if(invert){
5655 nottaken=out;
5656 emit_js(DJT_1);
5657 }else{
5658 add_to_linker(out,ba[i],internal);
5659 emit_jns(0);
5660 }
5661 }
5662 }
5663
5664 if(invert) {
5665 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5666 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5667 if(adj) {
5668 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5669 add_to_linker(out,ba[i],internal);
5670 }else{
5671 emit_addnop(13);
5672 add_to_linker(out,ba[i],internal*2);
5673 }
5674 emit_jmp(0);
5675 }else
5676 #endif
5677 {
5678 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5679 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5680 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5681 if(internal)
5682 assem_debug("branch: internal\n");
5683 else
5684 assem_debug("branch: external\n");
5685 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5686 ds_assemble_entry(i);
5687 }
5688 else {
5689 add_to_linker(out,ba[i],internal);
5690 emit_jmp(0);
5691 }
5692 }
5693 set_jump_target(nottaken, out);
5694 }
5695
5696 if(adj) {
5697 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5698 }
5699 } // (!unconditional)
5700 } // if(ooo)
5701 else
5702 {
5703 // In-order execution (branch first)
5704 //printf("IOE\n");
5705 void *nottaken = NULL;
5706 if(dops[i].rt1==31) {
5707 int rt,return_address;
5708 rt=get_reg(branch_regs[i].regmap,31);
5709 if(rt>=0) {
5710 // Save the PC even if the branch is not taken
5711 return_address=start+i*4+8;
5712 emit_movimm(return_address,rt); // PC into link register
5713 #ifdef IMM_PREFETCH
5714 emit_prefetch(hash_table_get(return_address));
5715 #endif
5716 }
5717 }
5718 if(!unconditional) {
5719 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5720 assert(s1l>=0);
5721 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5722 {
5723 emit_test(s1l,s1l);
5724 nottaken=out;
5725 emit_jns(DJT_1);
5726 }
5727 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5728 {
5729 emit_test(s1l,s1l);
5730 nottaken=out;
5731 emit_js(DJT_1);
5732 }
5733 } // if(!unconditional)
5734 int adj;
5735 uint64_t ds_unneeded=branch_regs[i].u;
5736 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5737 ds_unneeded|=1;
5738 // branch taken
5739 if(!nevertaken) {
5740 //assem_debug("1:\n");
5741 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5742 // load regs
5743 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5744 address_generation(i+1,&branch_regs[i],0);
5745 if (ram_offset)
5746 load_regs(regs[i].regmap,branch_regs[i].regmap,ROREG,ROREG);
5747 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5748 ds_assemble(i+1,&branch_regs[i]);
5749 cc=get_reg(branch_regs[i].regmap,CCREG);
5750 if(cc==-1) {
5751 emit_loadreg(CCREG,cc=HOST_CCREG);
5752 // CHECK: Is the following instruction (fall thru) allocated ok?
5753 }
5754 assert(cc==HOST_CCREG);
5755 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5756 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5757 assem_debug("cycle count (adj)\n");
5758 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5759 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5760 if(internal)
5761 assem_debug("branch: internal\n");
5762 else
5763 assem_debug("branch: external\n");
5764 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5765 ds_assemble_entry(i);
5766 }
5767 else {
5768 add_to_linker(out,ba[i],internal);
5769 emit_jmp(0);
5770 }
5771 }
5772 // branch not taken
5773 if(!unconditional) {
5774 set_jump_target(nottaken, out);
5775 assem_debug("1:\n");
5776 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5777 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5778 address_generation(i+1,&branch_regs[i],0);
5779 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,CCREG);
5780 ds_assemble(i+1,&branch_regs[i]);
5781 cc=get_reg(branch_regs[i].regmap,CCREG);
5782 if (cc == -1) {
5783 // Cycle count isn't in a register, temporarily load it then write it out
5784 emit_loadreg(CCREG,HOST_CCREG);
5785 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5786 void *jaddr=out;
5787 emit_jns(0);
5788 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5789 emit_storereg(CCREG,HOST_CCREG);
5790 }
5791 else{
5792 cc=get_reg(i_regmap,CCREG);
5793 assert(cc==HOST_CCREG);
5794 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5795 void *jaddr=out;
5796 emit_jns(0);
5797 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5798 }
5799 }
5800 }
5801}
5802
5803static void pagespan_assemble(int i,struct regstat *i_regs)
5804{
5805 int s1l=get_reg(i_regs->regmap,dops[i].rs1);
5806 int s2l=get_reg(i_regs->regmap,dops[i].rs2);
5807 void *taken = NULL;
5808 void *nottaken = NULL;
5809 int unconditional=0;
5810 if(dops[i].rs1==0)
5811 {
5812 s1l=s2l;
5813 s2l=-1;
5814 }
5815 else if(dops[i].rs2==0)
5816 {
5817 s2l=-1;
5818 }
5819 int hr=0;
5820 int addr=-1,alt=-1,ntaddr=-1;
5821 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5822 else {
5823 while(hr<HOST_REGS)
5824 {
5825 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5826 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5827 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5828 {
5829 addr=hr++;break;
5830 }
5831 hr++;
5832 }
5833 }
5834 while(hr<HOST_REGS)
5835 {
5836 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5837 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5838 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5839 {
5840 alt=hr++;break;
5841 }
5842 hr++;
5843 }
5844 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5845 {
5846 while(hr<HOST_REGS)
5847 {
5848 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5849 (i_regs->regmap[hr]&63)!=dops[i].rs1 &&
5850 (i_regs->regmap[hr]&63)!=dops[i].rs2 )
5851 {
5852 ntaddr=hr;break;
5853 }
5854 hr++;
5855 }
5856 }
5857 assert(hr<HOST_REGS);
5858 if((dops[i].opcode&0x2e)==4||dops[i].opcode==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5859 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
5860 }
5861 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5862 if(dops[i].opcode==2) // J
5863 {
5864 unconditional=1;
5865 }
5866 if(dops[i].opcode==3) // JAL
5867 {
5868 // TODO: mini_ht
5869 int rt=get_reg(i_regs->regmap,31);
5870 emit_movimm(start+i*4+8,rt);
5871 unconditional=1;
5872 }
5873 if(dops[i].opcode==0&&(dops[i].opcode2&0x3E)==8) // JR/JALR
5874 {
5875 emit_mov(s1l,addr);
5876 if(dops[i].opcode2==9) // JALR
5877 {
5878 int rt=get_reg(i_regs->regmap,dops[i].rt1);
5879 emit_movimm(start+i*4+8,rt);
5880 }
5881 }
5882 if((dops[i].opcode&0x3f)==4) // BEQ
5883 {
5884 if(dops[i].rs1==dops[i].rs2)
5885 {
5886 unconditional=1;
5887 }
5888 else
5889 #ifdef HAVE_CMOV_IMM
5890 if(1) {
5891 if(s2l>=0) emit_cmp(s1l,s2l);
5892 else emit_test(s1l,s1l);
5893 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5894 }
5895 else
5896 #endif
5897 {
5898 assert(s1l>=0);
5899 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5900 if(s2l>=0) emit_cmp(s1l,s2l);
5901 else emit_test(s1l,s1l);
5902 emit_cmovne_reg(alt,addr);
5903 }
5904 }
5905 if((dops[i].opcode&0x3f)==5) // BNE
5906 {
5907 #ifdef HAVE_CMOV_IMM
5908 if(s2l>=0) emit_cmp(s1l,s2l);
5909 else emit_test(s1l,s1l);
5910 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5911 #else
5912 assert(s1l>=0);
5913 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5914 if(s2l>=0) emit_cmp(s1l,s2l);
5915 else emit_test(s1l,s1l);
5916 emit_cmovne_reg(alt,addr);
5917 #endif
5918 }
5919 if((dops[i].opcode&0x3f)==0x14) // BEQL
5920 {
5921 if(s2l>=0) emit_cmp(s1l,s2l);
5922 else emit_test(s1l,s1l);
5923 if(nottaken) set_jump_target(nottaken, out);
5924 nottaken=out;
5925 emit_jne(0);
5926 }
5927 if((dops[i].opcode&0x3f)==0x15) // BNEL
5928 {
5929 if(s2l>=0) emit_cmp(s1l,s2l);
5930 else emit_test(s1l,s1l);
5931 nottaken=out;
5932 emit_jeq(0);
5933 if(taken) set_jump_target(taken, out);
5934 }
5935 if((dops[i].opcode&0x3f)==6) // BLEZ
5936 {
5937 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5938 emit_cmpimm(s1l,1);
5939 emit_cmovl_reg(alt,addr);
5940 }
5941 if((dops[i].opcode&0x3f)==7) // BGTZ
5942 {
5943 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5944 emit_cmpimm(s1l,1);
5945 emit_cmovl_reg(ntaddr,addr);
5946 }
5947 if((dops[i].opcode&0x3f)==0x16) // BLEZL
5948 {
5949 assert((dops[i].opcode&0x3f)!=0x16);
5950 }
5951 if((dops[i].opcode&0x3f)==0x17) // BGTZL
5952 {
5953 assert((dops[i].opcode&0x3f)!=0x17);
5954 }
5955 assert(dops[i].opcode!=1); // BLTZ/BGEZ
5956
5957 //FIXME: Check CSREG
5958 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5959 if((source[i]&0x30000)==0) // BC1F
5960 {
5961 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5962 emit_testimm(s1l,0x800000);
5963 emit_cmovne_reg(alt,addr);
5964 }
5965 if((source[i]&0x30000)==0x10000) // BC1T
5966 {
5967 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5968 emit_testimm(s1l,0x800000);
5969 emit_cmovne_reg(alt,addr);
5970 }
5971 if((source[i]&0x30000)==0x20000) // BC1FL
5972 {
5973 emit_testimm(s1l,0x800000);
5974 nottaken=out;
5975 emit_jne(0);
5976 }
5977 if((source[i]&0x30000)==0x30000) // BC1TL
5978 {
5979 emit_testimm(s1l,0x800000);
5980 nottaken=out;
5981 emit_jeq(0);
5982 }
5983 }
5984
5985 assert(i_regs->regmap[HOST_CCREG]==CCREG);
5986 wb_dirtys(regs[i].regmap,regs[i].dirty);
5987 if(unconditional)
5988 {
5989 emit_movimm(ba[i],HOST_BTREG);
5990 }
5991 else if(addr!=HOST_BTREG)
5992 {
5993 emit_mov(addr,HOST_BTREG);
5994 }
5995 void *branch_addr=out;
5996 emit_jmp(0);
5997 int target_addr=start+i*4+5;
5998 void *stub=out;
5999 void *compiled_target_addr=check_addr(target_addr);
6000 emit_extjump_ds(branch_addr, target_addr);
6001 if(compiled_target_addr) {
6002 set_jump_target(branch_addr, compiled_target_addr);
6003 add_jump_out(target_addr,stub);
6004 }
6005 else set_jump_target(branch_addr, stub);
6006}
6007
6008// Assemble the delay slot for the above
6009static void pagespan_ds()
6010{
6011 assem_debug("initial delay slot:\n");
6012 u_int vaddr=start+1;
6013 u_int page=get_page(vaddr);
6014 u_int vpage=get_vpage(vaddr);
6015 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6016 do_dirty_stub_ds(slen*4);
6017 ll_add(jump_in+page,vaddr,(void *)out);
6018 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6019 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6020 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty);
6021 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6022 emit_writeword(HOST_BTREG,&branch_target);
6023 load_regs(regs[0].regmap_entry,regs[0].regmap,dops[0].rs1,dops[0].rs2);
6024 address_generation(0,&regs[0],regs[0].regmap_entry);
6025 if (ram_offset && (dops[0].is_load || dops[0].is_store))
6026 load_regs(regs[0].regmap_entry,regs[0].regmap,ROREG,ROREG);
6027 if (dops[0].is_store)
6028 load_regs(regs[0].regmap_entry,regs[0].regmap,INVCP,INVCP);
6029 is_delayslot=0;
6030 switch(dops[0].itype) {
6031 case ALU:
6032 alu_assemble(0,&regs[0]);break;
6033 case IMM16:
6034 imm16_assemble(0,&regs[0]);break;
6035 case SHIFT:
6036 shift_assemble(0,&regs[0]);break;
6037 case SHIFTIMM:
6038 shiftimm_assemble(0,&regs[0]);break;
6039 case LOAD:
6040 load_assemble(0,&regs[0]);break;
6041 case LOADLR:
6042 loadlr_assemble(0,&regs[0]);break;
6043 case STORE:
6044 store_assemble(0,&regs[0]);break;
6045 case STORELR:
6046 storelr_assemble(0,&regs[0]);break;
6047 case COP0:
6048 cop0_assemble(0,&regs[0]);break;
6049 case COP1:
6050 cop1_assemble(0,&regs[0]);break;
6051 case C1LS:
6052 c1ls_assemble(0,&regs[0]);break;
6053 case COP2:
6054 cop2_assemble(0,&regs[0]);break;
6055 case C2LS:
6056 c2ls_assemble(0,&regs[0]);break;
6057 case C2OP:
6058 c2op_assemble(0,&regs[0]);break;
6059 case MULTDIV:
6060 multdiv_assemble(0,&regs[0]);
6061 multdiv_prepare_stall(0,&regs[0]);
6062 break;
6063 case MOV:
6064 mov_assemble(0,&regs[0]);break;
6065 case SYSCALL:
6066 case HLECALL:
6067 case INTCALL:
6068 case SPAN:
6069 case UJUMP:
6070 case RJUMP:
6071 case CJUMP:
6072 case SJUMP:
6073 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6074 }
6075 int btaddr=get_reg(regs[0].regmap,BTREG);
6076 if(btaddr<0) {
6077 btaddr=get_reg(regs[0].regmap,-1);
6078 emit_readword(&branch_target,btaddr);
6079 }
6080 assert(btaddr!=HOST_CCREG);
6081 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6082#ifdef HOST_IMM8
6083 host_tempreg_acquire();
6084 emit_movimm(start+4,HOST_TEMPREG);
6085 emit_cmp(btaddr,HOST_TEMPREG);
6086 host_tempreg_release();
6087#else
6088 emit_cmpimm(btaddr,start+4);
6089#endif
6090 void *branch = out;
6091 emit_jeq(0);
6092 store_regs_bt(regs[0].regmap,regs[0].dirty,-1);
6093 do_jump_vaddr(btaddr);
6094 set_jump_target(branch, out);
6095 store_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6096 load_regs_bt(regs[0].regmap,regs[0].dirty,start+4);
6097}
6098
6099// Basic liveness analysis for MIPS registers
6100void unneeded_registers(int istart,int iend,int r)
6101{
6102 int i;
6103 uint64_t u,gte_u,b,gte_b;
6104 uint64_t temp_u,temp_gte_u=0;
6105 uint64_t gte_u_unknown=0;
6106 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
6107 gte_u_unknown=~0ll;
6108 if(iend==slen-1) {
6109 u=1;
6110 gte_u=gte_u_unknown;
6111 }else{
6112 //u=unneeded_reg[iend+1];
6113 u=1;
6114 gte_u=gte_unneeded[iend+1];
6115 }
6116
6117 for (i=iend;i>=istart;i--)
6118 {
6119 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6120 if(dops[i].is_jump)
6121 {
6122 // If subroutine call, flag return address as a possible branch target
6123 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
6124
6125 if(ba[i]<start || ba[i]>=(start+slen*4))
6126 {
6127 // Branch out of this block, flush all regs
6128 u=1;
6129 gte_u=gte_u_unknown;
6130 branch_unneeded_reg[i]=u;
6131 // Merge in delay slot
6132 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6133 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6134 u|=1;
6135 gte_u|=gte_rt[i+1];
6136 gte_u&=~gte_rs[i+1];
6137 }
6138 else
6139 {
6140 // Internal branch, flag target
6141 dops[(ba[i]-start)>>2].bt=1;
6142 if(ba[i]<=start+i*4) {
6143 // Backward branch
6144 if(dops[i].is_ujump)
6145 {
6146 // Unconditional branch
6147 temp_u=1;
6148 temp_gte_u=0;
6149 } else {
6150 // Conditional branch (not taken case)
6151 temp_u=unneeded_reg[i+2];
6152 temp_gte_u&=gte_unneeded[i+2];
6153 }
6154 // Merge in delay slot
6155 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6156 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6157 temp_u|=1;
6158 temp_gte_u|=gte_rt[i+1];
6159 temp_gte_u&=~gte_rs[i+1];
6160 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
6161 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
6162 temp_u|=1;
6163 temp_gte_u|=gte_rt[i];
6164 temp_gte_u&=~gte_rs[i];
6165 unneeded_reg[i]=temp_u;
6166 gte_unneeded[i]=temp_gte_u;
6167 // Only go three levels deep. This recursion can take an
6168 // excessive amount of time if there are a lot of nested loops.
6169 if(r<2) {
6170 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6171 }else{
6172 unneeded_reg[(ba[i]-start)>>2]=1;
6173 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6174 }
6175 } /*else*/ if(1) {
6176 if (dops[i].is_ujump)
6177 {
6178 // Unconditional branch
6179 u=unneeded_reg[(ba[i]-start)>>2];
6180 gte_u=gte_unneeded[(ba[i]-start)>>2];
6181 branch_unneeded_reg[i]=u;
6182 // Merge in delay slot
6183 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6184 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6185 u|=1;
6186 gte_u|=gte_rt[i+1];
6187 gte_u&=~gte_rs[i+1];
6188 } else {
6189 // Conditional branch
6190 b=unneeded_reg[(ba[i]-start)>>2];
6191 gte_b=gte_unneeded[(ba[i]-start)>>2];
6192 branch_unneeded_reg[i]=b;
6193 // Branch delay slot
6194 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
6195 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
6196 b|=1;
6197 gte_b|=gte_rt[i+1];
6198 gte_b&=~gte_rs[i+1];
6199 u&=b;
6200 gte_u&=gte_b;
6201 if(i<slen-1) {
6202 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6203 } else {
6204 branch_unneeded_reg[i]=1;
6205 }
6206 }
6207 }
6208 }
6209 }
6210 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6211 {
6212 // SYSCALL instruction (software interrupt)
6213 u=1;
6214 }
6215 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6216 {
6217 // ERET instruction (return from interrupt)
6218 u=1;
6219 }
6220 //u=1; // DEBUG
6221 // Written registers are unneeded
6222 u|=1LL<<dops[i].rt1;
6223 u|=1LL<<dops[i].rt2;
6224 gte_u|=gte_rt[i];
6225 // Accessed registers are needed
6226 u&=~(1LL<<dops[i].rs1);
6227 u&=~(1LL<<dops[i].rs2);
6228 gte_u&=~gte_rs[i];
6229 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
6230 gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6231 // Source-target dependencies
6232 // R0 is always unneeded
6233 u|=1;
6234 // Save it
6235 unneeded_reg[i]=u;
6236 gte_unneeded[i]=gte_u;
6237 /*
6238 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6239 printf("U:");
6240 int r;
6241 for(r=1;r<=CCREG;r++) {
6242 if((unneeded_reg[i]>>r)&1) {
6243 if(r==HIREG) printf(" HI");
6244 else if(r==LOREG) printf(" LO");
6245 else printf(" r%d",r);
6246 }
6247 }
6248 printf("\n");
6249 */
6250 }
6251}
6252
6253// Write back dirty registers as soon as we will no longer modify them,
6254// so that we don't end up with lots of writes at the branches.
6255void clean_registers(int istart,int iend,int wr)
6256{
6257 int i;
6258 int r;
6259 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6260 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6261 if(iend==slen-1) {
6262 will_dirty_i=will_dirty_next=0;
6263 wont_dirty_i=wont_dirty_next=0;
6264 }else{
6265 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6266 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6267 }
6268 for (i=iend;i>=istart;i--)
6269 {
6270 if(dops[i].is_jump)
6271 {
6272 if(ba[i]<start || ba[i]>=(start+slen*4))
6273 {
6274 // Branch out of this block, flush all regs
6275 if (dops[i].is_ujump)
6276 {
6277 // Unconditional branch
6278 will_dirty_i=0;
6279 wont_dirty_i=0;
6280 // Merge in delay slot (will dirty)
6281 for(r=0;r<HOST_REGS;r++) {
6282 if(r!=EXCLUDE_REG) {
6283 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6284 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6285 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6286 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6287 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6288 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6289 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6290 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6291 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6292 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6293 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6294 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6295 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6296 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6297 }
6298 }
6299 }
6300 else
6301 {
6302 // Conditional branch
6303 will_dirty_i=0;
6304 wont_dirty_i=wont_dirty_next;
6305 // Merge in delay slot (will dirty)
6306 for(r=0;r<HOST_REGS;r++) {
6307 if(r!=EXCLUDE_REG) {
6308 if (1) { // !dops[i].likely) {
6309 // Might not dirty if likely branch is not taken
6310 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6311 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6312 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6313 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6314 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6315 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6316 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6317 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6318 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6319 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6320 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6321 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6322 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6323 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6324 }
6325 }
6326 }
6327 }
6328 // Merge in delay slot (wont dirty)
6329 for(r=0;r<HOST_REGS;r++) {
6330 if(r!=EXCLUDE_REG) {
6331 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6332 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6333 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6334 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6335 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6336 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6337 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6338 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6339 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6340 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6341 }
6342 }
6343 if(wr) {
6344 #ifndef DESTRUCTIVE_WRITEBACK
6345 branch_regs[i].dirty&=wont_dirty_i;
6346 #endif
6347 branch_regs[i].dirty|=will_dirty_i;
6348 }
6349 }
6350 else
6351 {
6352 // Internal branch
6353 if(ba[i]<=start+i*4) {
6354 // Backward branch
6355 if (dops[i].is_ujump)
6356 {
6357 // Unconditional branch
6358 temp_will_dirty=0;
6359 temp_wont_dirty=0;
6360 // Merge in delay slot (will dirty)
6361 for(r=0;r<HOST_REGS;r++) {
6362 if(r!=EXCLUDE_REG) {
6363 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6364 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6365 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6366 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6367 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6368 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6369 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6370 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6371 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6372 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6373 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6374 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6375 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6376 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6377 }
6378 }
6379 } else {
6380 // Conditional branch (not taken case)
6381 temp_will_dirty=will_dirty_next;
6382 temp_wont_dirty=wont_dirty_next;
6383 // Merge in delay slot (will dirty)
6384 for(r=0;r<HOST_REGS;r++) {
6385 if(r!=EXCLUDE_REG) {
6386 if (1) { // !dops[i].likely) {
6387 // Will not dirty if likely branch is not taken
6388 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6389 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6390 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6391 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6392 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6393 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6394 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6395 //if((regs[i].regmap[r]&63)==dops[i].rt1) temp_will_dirty|=1<<r;
6396 //if((regs[i].regmap[r]&63)==dops[i].rt2) temp_will_dirty|=1<<r;
6397 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_will_dirty|=1<<r;
6398 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_will_dirty|=1<<r;
6399 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6400 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6401 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6402 }
6403 }
6404 }
6405 }
6406 // Merge in delay slot (wont dirty)
6407 for(r=0;r<HOST_REGS;r++) {
6408 if(r!=EXCLUDE_REG) {
6409 if((regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6410 if((regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6411 if((regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6412 if((regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6413 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6414 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) temp_wont_dirty|=1<<r;
6415 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) temp_wont_dirty|=1<<r;
6416 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) temp_wont_dirty|=1<<r;
6417 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) temp_wont_dirty|=1<<r;
6418 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6419 }
6420 }
6421 // Deal with changed mappings
6422 if(i<iend) {
6423 for(r=0;r<HOST_REGS;r++) {
6424 if(r!=EXCLUDE_REG) {
6425 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6426 temp_will_dirty&=~(1<<r);
6427 temp_wont_dirty&=~(1<<r);
6428 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6429 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6430 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6431 } else {
6432 temp_will_dirty|=1<<r;
6433 temp_wont_dirty|=1<<r;
6434 }
6435 }
6436 }
6437 }
6438 }
6439 if(wr) {
6440 will_dirty[i]=temp_will_dirty;
6441 wont_dirty[i]=temp_wont_dirty;
6442 clean_registers((ba[i]-start)>>2,i-1,0);
6443 }else{
6444 // Limit recursion. It can take an excessive amount
6445 // of time if there are a lot of nested loops.
6446 will_dirty[(ba[i]-start)>>2]=0;
6447 wont_dirty[(ba[i]-start)>>2]=-1;
6448 }
6449 }
6450 /*else*/ if(1)
6451 {
6452 if (dops[i].is_ujump)
6453 {
6454 // Unconditional branch
6455 will_dirty_i=0;
6456 wont_dirty_i=0;
6457 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6458 for(r=0;r<HOST_REGS;r++) {
6459 if(r!=EXCLUDE_REG) {
6460 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6461 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6462 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6463 }
6464 if(branch_regs[i].regmap[r]>=0) {
6465 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6466 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6467 }
6468 }
6469 }
6470 //}
6471 // Merge in delay slot
6472 for(r=0;r<HOST_REGS;r++) {
6473 if(r!=EXCLUDE_REG) {
6474 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6475 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6476 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6477 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6478 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6479 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6480 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6481 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6482 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6483 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6484 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6485 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6486 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6487 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6488 }
6489 }
6490 } else {
6491 // Conditional branch
6492 will_dirty_i=will_dirty_next;
6493 wont_dirty_i=wont_dirty_next;
6494 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6495 for(r=0;r<HOST_REGS;r++) {
6496 if(r!=EXCLUDE_REG) {
6497 signed char target_reg=branch_regs[i].regmap[r];
6498 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6499 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6500 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6501 }
6502 else if(target_reg>=0) {
6503 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6504 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6505 }
6506 }
6507 }
6508 //}
6509 // Merge in delay slot
6510 for(r=0;r<HOST_REGS;r++) {
6511 if(r!=EXCLUDE_REG) {
6512 if (1) { // !dops[i].likely) {
6513 // Might not dirty if likely branch is not taken
6514 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6515 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6516 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6517 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6518 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6519 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6520 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6521 //if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6522 //if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6523 if((regs[i].regmap[r]&63)==dops[i+1].rt1) will_dirty_i|=1<<r;
6524 if((regs[i].regmap[r]&63)==dops[i+1].rt2) will_dirty_i|=1<<r;
6525 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6526 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6527 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6528 }
6529 }
6530 }
6531 }
6532 // Merge in delay slot (won't dirty)
6533 for(r=0;r<HOST_REGS;r++) {
6534 if(r!=EXCLUDE_REG) {
6535 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6536 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6537 if((regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6538 if((regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6539 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6540 if((branch_regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6541 if((branch_regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6542 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt1) wont_dirty_i|=1<<r;
6543 if((branch_regs[i].regmap[r]&63)==dops[i+1].rt2) wont_dirty_i|=1<<r;
6544 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6545 }
6546 }
6547 if(wr) {
6548 #ifndef DESTRUCTIVE_WRITEBACK
6549 branch_regs[i].dirty&=wont_dirty_i;
6550 #endif
6551 branch_regs[i].dirty|=will_dirty_i;
6552 }
6553 }
6554 }
6555 }
6556 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
6557 {
6558 // SYSCALL instruction (software interrupt)
6559 will_dirty_i=0;
6560 wont_dirty_i=0;
6561 }
6562 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
6563 {
6564 // ERET instruction (return from interrupt)
6565 will_dirty_i=0;
6566 wont_dirty_i=0;
6567 }
6568 will_dirty_next=will_dirty_i;
6569 wont_dirty_next=wont_dirty_i;
6570 for(r=0;r<HOST_REGS;r++) {
6571 if(r!=EXCLUDE_REG) {
6572 if((regs[i].regmap[r]&63)==dops[i].rt1) will_dirty_i|=1<<r;
6573 if((regs[i].regmap[r]&63)==dops[i].rt2) will_dirty_i|=1<<r;
6574 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6575 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6576 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6577 if((regs[i].regmap[r]&63)==dops[i].rt1) wont_dirty_i|=1<<r;
6578 if((regs[i].regmap[r]&63)==dops[i].rt2) wont_dirty_i|=1<<r;
6579 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6580 if(i>istart) {
6581 if (!dops[i].is_jump)
6582 {
6583 // Don't store a register immediately after writing it,
6584 // may prevent dual-issue.
6585 if((regs[i].regmap[r]&63)==dops[i-1].rt1) wont_dirty_i|=1<<r;
6586 if((regs[i].regmap[r]&63)==dops[i-1].rt2) wont_dirty_i|=1<<r;
6587 }
6588 }
6589 }
6590 }
6591 // Save it
6592 will_dirty[i]=will_dirty_i;
6593 wont_dirty[i]=wont_dirty_i;
6594 // Mark registers that won't be dirtied as not dirty
6595 if(wr) {
6596 regs[i].dirty|=will_dirty_i;
6597 #ifndef DESTRUCTIVE_WRITEBACK
6598 regs[i].dirty&=wont_dirty_i;
6599 if(dops[i].is_jump)
6600 {
6601 if (i < iend-1 && !dops[i].is_ujump) {
6602 for(r=0;r<HOST_REGS;r++) {
6603 if(r!=EXCLUDE_REG) {
6604 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6605 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6606 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6607 }
6608 }
6609 }
6610 }
6611 else
6612 {
6613 if(i<iend) {
6614 for(r=0;r<HOST_REGS;r++) {
6615 if(r!=EXCLUDE_REG) {
6616 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6617 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6618 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6619 }
6620 }
6621 }
6622 }
6623 #endif
6624 //}
6625 }
6626 // Deal with changed mappings
6627 temp_will_dirty=will_dirty_i;
6628 temp_wont_dirty=wont_dirty_i;
6629 for(r=0;r<HOST_REGS;r++) {
6630 if(r!=EXCLUDE_REG) {
6631 int nr;
6632 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6633 if(wr) {
6634 #ifndef DESTRUCTIVE_WRITEBACK
6635 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6636 #endif
6637 regs[i].wasdirty|=will_dirty_i&(1<<r);
6638 }
6639 }
6640 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6641 // Register moved to a different register
6642 will_dirty_i&=~(1<<r);
6643 wont_dirty_i&=~(1<<r);
6644 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6645 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6646 if(wr) {
6647 #ifndef DESTRUCTIVE_WRITEBACK
6648 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6649 #endif
6650 regs[i].wasdirty|=will_dirty_i&(1<<r);
6651 }
6652 }
6653 else {
6654 will_dirty_i&=~(1<<r);
6655 wont_dirty_i&=~(1<<r);
6656 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6657 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6658 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6659 } else {
6660 wont_dirty_i|=1<<r;
6661 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6662 }
6663 }
6664 }
6665 }
6666 }
6667}
6668
6669#ifdef DISASM
6670 /* disassembly */
6671void disassemble_inst(int i)
6672{
6673 if (dops[i].bt) printf("*"); else printf(" ");
6674 switch(dops[i].itype) {
6675 case UJUMP:
6676 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6677 case CJUMP:
6678 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6679 case SJUMP:
6680 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6681 case RJUMP:
6682 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6683 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6684 else
6685 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6686 break;
6687 case SPAN:
6688 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,ba[i]);break;
6689 case IMM16:
6690 if(dops[i].opcode==0xf) //LUI
6691 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6692 else
6693 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6694 break;
6695 case LOAD:
6696 case LOADLR:
6697 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6698 break;
6699 case STORE:
6700 case STORELR:
6701 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6702 break;
6703 case ALU:
6704 case SHIFT:
6705 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6706 break;
6707 case MULTDIV:
6708 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6709 break;
6710 case SHIFTIMM:
6711 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6712 break;
6713 case MOV:
6714 if((dops[i].opcode2&0x1d)==0x10)
6715 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6716 else if((dops[i].opcode2&0x1d)==0x11)
6717 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6718 else
6719 printf (" %x: %s\n",start+i*4,insn[i]);
6720 break;
6721 case COP0:
6722 if(dops[i].opcode2==0)
6723 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6724 else if(dops[i].opcode2==4)
6725 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6726 else printf (" %x: %s\n",start+i*4,insn[i]);
6727 break;
6728 case COP1:
6729 if(dops[i].opcode2<3)
6730 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6731 else if(dops[i].opcode2>3)
6732 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6733 else printf (" %x: %s\n",start+i*4,insn[i]);
6734 break;
6735 case COP2:
6736 if(dops[i].opcode2<3)
6737 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6738 else if(dops[i].opcode2>3)
6739 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6740 else printf (" %x: %s\n",start+i*4,insn[i]);
6741 break;
6742 case C1LS:
6743 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6744 break;
6745 case C2LS:
6746 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6747 break;
6748 case INTCALL:
6749 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6750 break;
6751 default:
6752 //printf (" %s %8x\n",insn[i],source[i]);
6753 printf (" %x: %s\n",start+i*4,insn[i]);
6754 }
6755}
6756#else
6757static void disassemble_inst(int i) {}
6758#endif // DISASM
6759
6760#define DRC_TEST_VAL 0x74657374
6761
6762static void new_dynarec_test(void)
6763{
6764 int (*testfunc)(void);
6765 void *beginning;
6766 int ret[2];
6767 size_t i;
6768
6769 // check structure linkage
6770 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6771 {
6772 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6773 }
6774
6775 SysPrintf("testing if we can run recompiled code...\n");
6776 ((volatile u_int *)out)[0]++; // make cache dirty
6777
6778 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6779 out = ndrc->translation_cache;
6780 beginning = start_block();
6781 emit_movimm(DRC_TEST_VAL + i, 0); // test
6782 emit_ret();
6783 literal_pool(0);
6784 end_block(beginning);
6785 testfunc = beginning;
6786 ret[i] = testfunc();
6787 }
6788
6789 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6790 SysPrintf("test passed.\n");
6791 else
6792 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6793 out = ndrc->translation_cache;
6794}
6795
6796// clear the state completely, instead of just marking
6797// things invalid like invalidate_all_pages() does
6798void new_dynarec_clear_full(void)
6799{
6800 int n;
6801 out = ndrc->translation_cache;
6802 memset(invalid_code,1,sizeof(invalid_code));
6803 memset(hash_table,0xff,sizeof(hash_table));
6804 memset(mini_ht,-1,sizeof(mini_ht));
6805 memset(restore_candidate,0,sizeof(restore_candidate));
6806 memset(shadow,0,sizeof(shadow));
6807 copy=shadow;
6808 expirep=16384; // Expiry pointer, +2 blocks
6809 pending_exception=0;
6810 literalcount=0;
6811 stop_after_jal=0;
6812 inv_code_start=inv_code_end=~0;
6813 f1_hack=0;
6814 // TLB
6815 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6816 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6817 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6818
6819 cycle_multiplier_old = cycle_multiplier;
6820 new_dynarec_hacks_old = new_dynarec_hacks;
6821}
6822
6823void new_dynarec_init(void)
6824{
6825 SysPrintf("Init new dynarec\n");
6826
6827#ifdef BASE_ADDR_DYNAMIC
6828 #ifdef VITA
6829 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6830 if (sceBlock < 0)
6831 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6832 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6833 if (ret < 0)
6834 SysPrintf("sceKernelGetMemBlockBase failed\n");
6835 #else
6836 uintptr_t desired_addr = 0;
6837 #ifdef __ELF__
6838 extern char _end;
6839 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6840 #endif
6841 ndrc = mmap((void *)desired_addr, sizeof(*ndrc),
6842 PROT_READ | PROT_WRITE | PROT_EXEC,
6843 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6844 if (ndrc == MAP_FAILED) {
6845 SysPrintf("mmap() failed: %s\n", strerror(errno));
6846 abort();
6847 }
6848 #endif
6849#else
6850 #ifndef NO_WRITE_EXEC
6851 // not all systems allow execute in data segment by default
6852 if (mprotect(ndrc, sizeof(ndrc->translation_cache) + sizeof(ndrc->tramp.ops),
6853 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6854 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6855 #endif
6856#endif
6857 out = ndrc->translation_cache;
6858 cycle_multiplier=200;
6859 new_dynarec_clear_full();
6860#ifdef HOST_IMM8
6861 // Copy this into local area so we don't have to put it in every literal pool
6862 invc_ptr=invalid_code;
6863#endif
6864 arch_init();
6865 new_dynarec_test();
6866 ram_offset=(uintptr_t)rdram-0x80000000;
6867 if (ram_offset!=0)
6868 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6869}
6870
6871void new_dynarec_cleanup(void)
6872{
6873 int n;
6874#ifdef BASE_ADDR_DYNAMIC
6875 #ifdef VITA
6876 sceKernelFreeMemBlock(sceBlock);
6877 sceBlock = -1;
6878 #else
6879 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6880 SysPrintf("munmap() failed\n");
6881 #endif
6882#endif
6883 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6884 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6885 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6886 #ifdef ROM_COPY
6887 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
6888 #endif
6889}
6890
6891static u_int *get_source_start(u_int addr, u_int *limit)
6892{
6893 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6894 cycle_multiplier_override = 0;
6895
6896 if (addr < 0x00200000 ||
6897 (0xa0000000 <= addr && addr < 0xa0200000))
6898 {
6899 // used for BIOS calls mostly?
6900 *limit = (addr&0xa0000000)|0x00200000;
6901 return (u_int *)(rdram + (addr&0x1fffff));
6902 }
6903 else if (!Config.HLE && (
6904 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6905 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6906 {
6907 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6908 // but timings in PCSX are too tied to the interpreter's BIAS
6909 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6910 cycle_multiplier_override = 200;
6911
6912 *limit = (addr & 0xfff00000) | 0x80000;
6913 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6914 }
6915 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6916 *limit = (addr & 0x80600000) + 0x00200000;
6917 return (u_int *)(rdram + (addr&0x1fffff));
6918 }
6919 return NULL;
6920}
6921
6922static u_int scan_for_ret(u_int addr)
6923{
6924 u_int limit = 0;
6925 u_int *mem;
6926
6927 mem = get_source_start(addr, &limit);
6928 if (mem == NULL)
6929 return addr;
6930
6931 if (limit > addr + 0x1000)
6932 limit = addr + 0x1000;
6933 for (; addr < limit; addr += 4, mem++) {
6934 if (*mem == 0x03e00008) // jr $ra
6935 return addr + 8;
6936 }
6937 return addr;
6938}
6939
6940struct savestate_block {
6941 uint32_t addr;
6942 uint32_t regflags;
6943};
6944
6945static int addr_cmp(const void *p1_, const void *p2_)
6946{
6947 const struct savestate_block *p1 = p1_, *p2 = p2_;
6948 return p1->addr - p2->addr;
6949}
6950
6951int new_dynarec_save_blocks(void *save, int size)
6952{
6953 struct savestate_block *blocks = save;
6954 int maxcount = size / sizeof(blocks[0]);
6955 struct savestate_block tmp_blocks[1024];
6956 struct ll_entry *head;
6957 int p, s, d, o, bcnt;
6958 u_int addr;
6959
6960 o = 0;
6961 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
6962 bcnt = 0;
6963 for (head = jump_in[p]; head != NULL; head = head->next) {
6964 tmp_blocks[bcnt].addr = head->vaddr;
6965 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
6966 bcnt++;
6967 }
6968 if (bcnt < 1)
6969 continue;
6970 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6971
6972 addr = tmp_blocks[0].addr;
6973 for (s = d = 0; s < bcnt; s++) {
6974 if (tmp_blocks[s].addr < addr)
6975 continue;
6976 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6977 tmp_blocks[d++] = tmp_blocks[s];
6978 addr = scan_for_ret(tmp_blocks[s].addr);
6979 }
6980
6981 if (o + d > maxcount)
6982 d = maxcount - o;
6983 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
6984 o += d;
6985 }
6986
6987 return o * sizeof(blocks[0]);
6988}
6989
6990void new_dynarec_load_blocks(const void *save, int size)
6991{
6992 const struct savestate_block *blocks = save;
6993 int count = size / sizeof(blocks[0]);
6994 u_int regs_save[32];
6995 uint32_t f;
6996 int i, b;
6997
6998 get_addr(psxRegs.pc);
6999
7000 // change GPRs for speculation to at least partially work..
7001 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7002 for (i = 1; i < 32; i++)
7003 psxRegs.GPR.r[i] = 0x80000000;
7004
7005 for (b = 0; b < count; b++) {
7006 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7007 if (f & 1)
7008 psxRegs.GPR.r[i] = 0x1f800000;
7009 }
7010
7011 get_addr(blocks[b].addr);
7012
7013 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7014 if (f & 1)
7015 psxRegs.GPR.r[i] = 0x80000000;
7016 }
7017 }
7018
7019 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7020}
7021
7022int new_recompile_block(u_int addr)
7023{
7024 u_int pagelimit = 0;
7025 u_int state_rflags = 0;
7026 int i;
7027
7028 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7029 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7030 //if(debug)
7031 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7032
7033 // this is just for speculation
7034 for (i = 1; i < 32; i++) {
7035 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7036 state_rflags |= 1 << i;
7037 }
7038
7039 start = (u_int)addr&~3;
7040 //assert(((u_int)addr&1)==0); // start-in-delay-slot flag
7041 new_dynarec_did_compile=1;
7042 if (Config.HLE && start == 0x80001000) // hlecall
7043 {
7044 // XXX: is this enough? Maybe check hleSoftCall?
7045 void *beginning=start_block();
7046 u_int page=get_page(start);
7047
7048 invalid_code[start>>12]=0;
7049 emit_movimm(start,0);
7050 emit_writeword(0,&pcaddr);
7051 emit_far_jump(new_dyna_leave);
7052 literal_pool(0);
7053 end_block(beginning);
7054 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7055 return 0;
7056 }
7057 else if (f1_hack == ~0u || (f1_hack != 0 && start == f1_hack)) {
7058 void *beginning = start_block();
7059 u_int page = get_page(start);
7060 emit_readword(&psxRegs.GPR.n.sp, 0);
7061 emit_readptr(&mem_rtab, 1);
7062 emit_shrimm(0, 12, 2);
7063 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
7064 emit_addimm(0, 0x18, 0);
7065 emit_adds_ptr(1, 1, 1);
7066 emit_ldr_dualindexed(1, 0, 0);
7067 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
7068 emit_far_call(get_addr_ht);
7069 emit_jmpreg(0); // jr k0
7070 literal_pool(0);
7071 end_block(beginning);
7072
7073 ll_add_flags(jump_in + page, start, state_rflags, beginning);
7074 SysPrintf("F1 hack to %08x\n", start);
7075 f1_hack = start;
7076 return 0;
7077 }
7078
7079 source = get_source_start(start, &pagelimit);
7080 if (source == NULL) {
7081 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7082 abort();
7083 }
7084
7085 /* Pass 1: disassemble */
7086 /* Pass 2: register dependencies, branch targets */
7087 /* Pass 3: register allocation */
7088 /* Pass 4: branch dependencies */
7089 /* Pass 5: pre-alloc */
7090 /* Pass 6: optimize clean/dirty state */
7091 /* Pass 7: flag 32-bit registers */
7092 /* Pass 8: assembly */
7093 /* Pass 9: linker */
7094 /* Pass 10: garbage collection / free memory */
7095
7096 int j;
7097 int done=0;
7098 unsigned int type,op,op2;
7099
7100 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7101
7102 /* Pass 1 disassembly */
7103
7104 for(i=0;!done;i++) {
7105 dops[i].bt=0;
7106 dops[i].ooo=0;
7107 op2=0;
7108 minimum_free_regs[i]=0;
7109 dops[i].opcode=op=source[i]>>26;
7110 switch(op)
7111 {
7112 case 0x00: strcpy(insn[i],"special"); type=NI;
7113 op2=source[i]&0x3f;
7114 switch(op2)
7115 {
7116 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7117 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7118 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7119 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7120 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7121 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7122 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7123 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7124 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7125 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7126 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7127 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7128 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7129 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7130 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7131 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7132 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7133 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7134 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7135 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7136 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7137 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7138 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7139 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7140 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7141 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7142 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7143 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7144 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7145 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7146 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7147 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7148 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7149 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7150 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7151#if 0
7152 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7153 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7154 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7155 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7156 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7157 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7158 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7159 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7160 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7161 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7162 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7163 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7164 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7165 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7166 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7167 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7168 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7169#endif
7170 }
7171 break;
7172 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7173 op2=(source[i]>>16)&0x1f;
7174 switch(op2)
7175 {
7176 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7177 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7178 //case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7179 //case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7180 //case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7181 //case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7182 //case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7183 //case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7184 //case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7185 //case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7186 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7187 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7188 //case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7189 //case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7190 }
7191 break;
7192 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7193 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7194 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7195 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7196 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7197 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7198 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7199 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7200 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7201 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7202 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7203 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7204 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7205 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7206 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7207 op2=(source[i]>>21)&0x1f;
7208 switch(op2)
7209 {
7210 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7211 case 0x02: strcpy(insn[i],"CFC0"); type=COP0; break;
7212 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7213 case 0x06: strcpy(insn[i],"CTC0"); type=COP0; break;
7214 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7215 }
7216 break;
7217 case 0x11: strcpy(insn[i],"cop1"); type=COP1;
7218 op2=(source[i]>>21)&0x1f;
7219 break;
7220#if 0
7221 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7222 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7223 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7224 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7225 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7226 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7227 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7228 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7229#endif
7230 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7231 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7232 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7233 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7234 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7235 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7236 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7237#if 0
7238 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7239#endif
7240 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7241 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7242 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7243 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7244#if 0
7245 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7246 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7247#endif
7248 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7249 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7250 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7251 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7252#if 0
7253 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7254 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7255 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7256#endif
7257 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7258 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7259#if 0
7260 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7261 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7262 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7263#endif
7264 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7265 op2=(source[i]>>21)&0x1f;
7266 //if (op2 & 0x10)
7267 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7268 if (gte_handlers[source[i]&0x3f]!=NULL) {
7269 if (gte_regnames[source[i]&0x3f]!=NULL)
7270 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7271 else
7272 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7273 type=C2OP;
7274 }
7275 }
7276 else switch(op2)
7277 {
7278 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7279 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7280 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7281 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7282 }
7283 break;
7284 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7285 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7286 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7287 default: strcpy(insn[i],"???"); type=NI;
7288 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7289 break;
7290 }
7291 dops[i].itype=type;
7292 dops[i].opcode2=op2;
7293 /* Get registers/immediates */
7294 dops[i].lt1=0;
7295 gte_rs[i]=gte_rt[i]=0;
7296 switch(type) {
7297 case LOAD:
7298 dops[i].rs1=(source[i]>>21)&0x1f;
7299 dops[i].rs2=0;
7300 dops[i].rt1=(source[i]>>16)&0x1f;
7301 dops[i].rt2=0;
7302 imm[i]=(short)source[i];
7303 break;
7304 case STORE:
7305 case STORELR:
7306 dops[i].rs1=(source[i]>>21)&0x1f;
7307 dops[i].rs2=(source[i]>>16)&0x1f;
7308 dops[i].rt1=0;
7309 dops[i].rt2=0;
7310 imm[i]=(short)source[i];
7311 break;
7312 case LOADLR:
7313 // LWL/LWR only load part of the register,
7314 // therefore the target register must be treated as a source too
7315 dops[i].rs1=(source[i]>>21)&0x1f;
7316 dops[i].rs2=(source[i]>>16)&0x1f;
7317 dops[i].rt1=(source[i]>>16)&0x1f;
7318 dops[i].rt2=0;
7319 imm[i]=(short)source[i];
7320 break;
7321 case IMM16:
7322 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
7323 else dops[i].rs1=(source[i]>>21)&0x1f;
7324 dops[i].rs2=0;
7325 dops[i].rt1=(source[i]>>16)&0x1f;
7326 dops[i].rt2=0;
7327 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7328 imm[i]=(unsigned short)source[i];
7329 }else{
7330 imm[i]=(short)source[i];
7331 }
7332 break;
7333 case UJUMP:
7334 dops[i].rs1=0;
7335 dops[i].rs2=0;
7336 dops[i].rt1=0;
7337 dops[i].rt2=0;
7338 // The JAL instruction writes to r31.
7339 if (op&1) {
7340 dops[i].rt1=31;
7341 }
7342 dops[i].rs2=CCREG;
7343 break;
7344 case RJUMP:
7345 dops[i].rs1=(source[i]>>21)&0x1f;
7346 dops[i].rs2=0;
7347 dops[i].rt1=0;
7348 dops[i].rt2=0;
7349 // The JALR instruction writes to rd.
7350 if (op2&1) {
7351 dops[i].rt1=(source[i]>>11)&0x1f;
7352 }
7353 dops[i].rs2=CCREG;
7354 break;
7355 case CJUMP:
7356 dops[i].rs1=(source[i]>>21)&0x1f;
7357 dops[i].rs2=(source[i]>>16)&0x1f;
7358 dops[i].rt1=0;
7359 dops[i].rt2=0;
7360 if(op&2) { // BGTZ/BLEZ
7361 dops[i].rs2=0;
7362 }
7363 break;
7364 case SJUMP:
7365 dops[i].rs1=(source[i]>>21)&0x1f;
7366 dops[i].rs2=CCREG;
7367 dops[i].rt1=0;
7368 dops[i].rt2=0;
7369 if(op2&0x10) { // BxxAL
7370 dops[i].rt1=31;
7371 // NOTE: If the branch is not taken, r31 is still overwritten
7372 }
7373 break;
7374 case ALU:
7375 dops[i].rs1=(source[i]>>21)&0x1f; // source
7376 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
7377 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7378 dops[i].rt2=0;
7379 break;
7380 case MULTDIV:
7381 dops[i].rs1=(source[i]>>21)&0x1f; // source
7382 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
7383 dops[i].rt1=HIREG;
7384 dops[i].rt2=LOREG;
7385 break;
7386 case MOV:
7387 dops[i].rs1=0;
7388 dops[i].rs2=0;
7389 dops[i].rt1=0;
7390 dops[i].rt2=0;
7391 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
7392 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
7393 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
7394 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
7395 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
7396 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
7397 break;
7398 case SHIFT:
7399 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
7400 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
7401 dops[i].rt1=(source[i]>>11)&0x1f; // destination
7402 dops[i].rt2=0;
7403 break;
7404 case SHIFTIMM:
7405 dops[i].rs1=(source[i]>>16)&0x1f;
7406 dops[i].rs2=0;
7407 dops[i].rt1=(source[i]>>11)&0x1f;
7408 dops[i].rt2=0;
7409 imm[i]=(source[i]>>6)&0x1f;
7410 // DSxx32 instructions
7411 if(op2>=0x3c) imm[i]|=0x20;
7412 break;
7413 case COP0:
7414 dops[i].rs1=0;
7415 dops[i].rs2=0;
7416 dops[i].rt1=0;
7417 dops[i].rt2=0;
7418 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
7419 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
7420 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
7421 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
7422 break;
7423 case COP1:
7424 dops[i].rs1=0;
7425 dops[i].rs2=0;
7426 dops[i].rt1=0;
7427 dops[i].rt2=0;
7428 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7429 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7430 dops[i].rs2=CSREG;
7431 break;
7432 case COP2:
7433 dops[i].rs1=0;
7434 dops[i].rs2=0;
7435 dops[i].rt1=0;
7436 dops[i].rt2=0;
7437 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
7438 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
7439 dops[i].rs2=CSREG;
7440 int gr=(source[i]>>11)&0x1F;
7441 switch(op2)
7442 {
7443 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7444 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7445 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7446 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7447 }
7448 break;
7449 case C1LS:
7450 dops[i].rs1=(source[i]>>21)&0x1F;
7451 dops[i].rs2=CSREG;
7452 dops[i].rt1=0;
7453 dops[i].rt2=0;
7454 imm[i]=(short)source[i];
7455 break;
7456 case C2LS:
7457 dops[i].rs1=(source[i]>>21)&0x1F;
7458 dops[i].rs2=0;
7459 dops[i].rt1=0;
7460 dops[i].rt2=0;
7461 imm[i]=(short)source[i];
7462 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7463 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7464 break;
7465 case C2OP:
7466 dops[i].rs1=0;
7467 dops[i].rs2=0;
7468 dops[i].rt1=0;
7469 dops[i].rt2=0;
7470 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7471 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7472 gte_rt[i]|=1ll<<63; // every op changes flags
7473 if((source[i]&0x3f)==GTE_MVMVA) {
7474 int v = (source[i] >> 15) & 3;
7475 gte_rs[i]&=~0xe3fll;
7476 if(v==3) gte_rs[i]|=0xe00ll;
7477 else gte_rs[i]|=3ll<<(v*2);
7478 }
7479 break;
7480 case SYSCALL:
7481 case HLECALL:
7482 case INTCALL:
7483 dops[i].rs1=CCREG;
7484 dops[i].rs2=0;
7485 dops[i].rt1=0;
7486 dops[i].rt2=0;
7487 break;
7488 default:
7489 dops[i].rs1=0;
7490 dops[i].rs2=0;
7491 dops[i].rt1=0;
7492 dops[i].rt2=0;
7493 }
7494 /* Calculate branch target addresses */
7495 if(type==UJUMP)
7496 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7497 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
7498 ba[i]=start+i*4+8; // Ignore never taken branch
7499 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
7500 ba[i]=start+i*4+8; // Ignore never taken branch
7501 else if(type==CJUMP||type==SJUMP)
7502 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7503 else ba[i]=-1;
7504
7505 /* simplify always (not)taken branches */
7506 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
7507 dops[i].rs1 = dops[i].rs2 = 0;
7508 if (!(op & 1)) {
7509 dops[i].itype = type = UJUMP;
7510 dops[i].rs2 = CCREG;
7511 }
7512 }
7513 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
7514 dops[i].itype = type = UJUMP;
7515
7516 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
7517 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
7518 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
7519 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
7520
7521 /* messy cases to just pass over to the interpreter */
7522 if (i > 0 && dops[i-1].is_jump) {
7523 int do_in_intrp=0;
7524 // branch in delay slot?
7525 if (dops[i].is_jump) {
7526 // don't handle first branch and call interpreter if it's hit
7527 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7528 do_in_intrp=1;
7529 }
7530 // basic load delay detection
7531 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
7532 int t=(ba[i-1]-start)/4;
7533 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
7534 // jump target wants DS result - potential load delay effect
7535 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7536 do_in_intrp=1;
7537 dops[t+1].bt=1; // expected return from interpreter
7538 }
7539 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
7540 !(i>=3&&dops[i-3].is_jump)) {
7541 // v0 overwrite like this is a sign of trouble, bail out
7542 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7543 do_in_intrp=1;
7544 }
7545 }
7546 if(do_in_intrp) {
7547 dops[i-1].rs1=CCREG;
7548 dops[i-1].rs2=dops[i-1].rt1=dops[i-1].rt2=0;
7549 ba[i-1]=-1;
7550 dops[i-1].itype=INTCALL;
7551 done=2;
7552 i--; // don't compile the DS
7553 }
7554 }
7555
7556 /* Is this the end of the block? */
7557 if (i > 0 && dops[i-1].is_ujump) {
7558 if(dops[i-1].rt1==0) { // Continue past subroutine call (JAL)
7559 done=2;
7560 }
7561 else {
7562 if(stop_after_jal) done=1;
7563 // Stop on BREAK
7564 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7565 }
7566 // Don't recompile stuff that's already compiled
7567 if(check_addr(start+i*4+4)) done=1;
7568 // Don't get too close to the limit
7569 if(i>MAXBLOCK/2) done=1;
7570 }
7571 if(dops[i].itype==SYSCALL&&stop_after_jal) done=1;
7572 if(dops[i].itype==HLECALL||dops[i].itype==INTCALL) done=2;
7573 if(done==2) {
7574 // Does the block continue due to a branch?
7575 for(j=i-1;j>=0;j--)
7576 {
7577 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7578 if(ba[j]==start+i*4+4) done=j=0;
7579 if(ba[j]==start+i*4+8) done=j=0;
7580 }
7581 }
7582 //assert(i<MAXBLOCK-1);
7583 if(start+i*4==pagelimit-4) done=1;
7584 assert(start+i*4<pagelimit);
7585 if (i==MAXBLOCK-1) done=1;
7586 // Stop if we're compiling junk
7587 if(dops[i].itype==NI&&dops[i].opcode==0x11) {
7588 done=stop_after_jal=1;
7589 SysPrintf("Disabled speculative precompilation\n");
7590 }
7591 }
7592 slen=i;
7593 if (dops[i-1].is_jump) {
7594 if(start+i*4==pagelimit) {
7595 dops[i-1].itype=SPAN;
7596 }
7597 }
7598 assert(slen>0);
7599
7600 /* spacial hack(s) */
7601 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
7602 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
7603 && dops[i-7].itype == STORE)
7604 {
7605 i = i-8;
7606 if (dops[i].itype == IMM16)
7607 i--;
7608 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
7609 if (dops[i].itype == STORELR && dops[i].rs1 == 6
7610 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
7611 {
7612 SysPrintf("F1 hack from %08x\n", start);
7613 if (f1_hack == 0)
7614 f1_hack = ~0u;
7615 }
7616 }
7617
7618 /* Pass 2 - Register dependencies and branch targets */
7619
7620 unneeded_registers(0,slen-1,0);
7621
7622 /* Pass 3 - Register allocation */
7623
7624 struct regstat current; // Current register allocations/status
7625 current.dirty=0;
7626 current.u=unneeded_reg[0];
7627 clear_all_regs(current.regmap);
7628 alloc_reg(&current,0,CCREG);
7629 dirty_reg(&current,CCREG);
7630 current.isconst=0;
7631 current.wasconst=0;
7632 current.waswritten=0;
7633 int ds=0;
7634 int cc=0;
7635 int hr=-1;
7636
7637 if((u_int)addr&1) {
7638 // First instruction is delay slot
7639 cc=-1;
7640 dops[1].bt=1;
7641 ds=1;
7642 unneeded_reg[0]=1;
7643 current.regmap[HOST_BTREG]=BTREG;
7644 }
7645
7646 for(i=0;i<slen;i++)
7647 {
7648 if(dops[i].bt)
7649 {
7650 int hr;
7651 for(hr=0;hr<HOST_REGS;hr++)
7652 {
7653 // Is this really necessary?
7654 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7655 }
7656 current.isconst=0;
7657 current.waswritten=0;
7658 }
7659
7660 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7661 regs[i].wasconst=current.isconst;
7662 regs[i].wasdirty=current.dirty;
7663 regs[i].loadedconst=0;
7664 if (!dops[i].is_jump) {
7665 if(i+1<slen) {
7666 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7667 current.u|=1;
7668 } else {
7669 current.u=1;
7670 }
7671 } else {
7672 if(i+1<slen) {
7673 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7674 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7675 current.u|=1;
7676 } else { SysPrintf("oops, branch at end of block with no delay slot\n");abort(); }
7677 }
7678 dops[i].is_ds=ds;
7679 if(ds) {
7680 ds=0; // Skip delay slot, already allocated as part of branch
7681 // ...but we need to alloc it in case something jumps here
7682 if(i+1<slen) {
7683 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7684 }else{
7685 current.u=branch_unneeded_reg[i-1];
7686 }
7687 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7688 current.u|=1;
7689 struct regstat temp;
7690 memcpy(&temp,&current,sizeof(current));
7691 temp.wasdirty=temp.dirty;
7692 // TODO: Take into account unconditional branches, as below
7693 delayslot_alloc(&temp,i);
7694 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7695 regs[i].wasdirty=temp.wasdirty;
7696 regs[i].dirty=temp.dirty;
7697 regs[i].isconst=0;
7698 regs[i].wasconst=0;
7699 current.isconst=0;
7700 // Create entry (branch target) regmap
7701 for(hr=0;hr<HOST_REGS;hr++)
7702 {
7703 int r=temp.regmap[hr];
7704 if(r>=0) {
7705 if(r!=regmap_pre[i][hr]) {
7706 regs[i].regmap_entry[hr]=-1;
7707 }
7708 else
7709 {
7710 assert(r < 64);
7711 if((current.u>>r)&1) {
7712 regs[i].regmap_entry[hr]=-1;
7713 regs[i].regmap[hr]=-1;
7714 //Don't clear regs in the delay slot as the branch might need them
7715 //current.regmap[hr]=-1;
7716 }else
7717 regs[i].regmap_entry[hr]=r;
7718 }
7719 } else {
7720 // First instruction expects CCREG to be allocated
7721 if(i==0&&hr==HOST_CCREG)
7722 regs[i].regmap_entry[hr]=CCREG;
7723 else
7724 regs[i].regmap_entry[hr]=-1;
7725 }
7726 }
7727 }
7728 else { // Not delay slot
7729 switch(dops[i].itype) {
7730 case UJUMP:
7731 //current.isconst=0; // DEBUG
7732 //current.wasconst=0; // DEBUG
7733 //regs[i].wasconst=0; // DEBUG
7734 clear_const(&current,dops[i].rt1);
7735 alloc_cc(&current,i);
7736 dirty_reg(&current,CCREG);
7737 if (dops[i].rt1==31) {
7738 alloc_reg(&current,i,31);
7739 dirty_reg(&current,31);
7740 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7741 //assert(dops[i+1].rt1!=dops[i].rt1);
7742 #ifdef REG_PREFETCH
7743 alloc_reg(&current,i,PTEMP);
7744 #endif
7745 }
7746 dops[i].ooo=1;
7747 delayslot_alloc(&current,i+1);
7748 //current.isconst=0; // DEBUG
7749 ds=1;
7750 //printf("i=%d, isconst=%x\n",i,current.isconst);
7751 break;
7752 case RJUMP:
7753 //current.isconst=0;
7754 //current.wasconst=0;
7755 //regs[i].wasconst=0;
7756 clear_const(&current,dops[i].rs1);
7757 clear_const(&current,dops[i].rt1);
7758 alloc_cc(&current,i);
7759 dirty_reg(&current,CCREG);
7760 if (!ds_writes_rjump_rs(i)) {
7761 alloc_reg(&current,i,dops[i].rs1);
7762 if (dops[i].rt1!=0) {
7763 alloc_reg(&current,i,dops[i].rt1);
7764 dirty_reg(&current,dops[i].rt1);
7765 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7766 assert(dops[i+1].rt1!=dops[i].rt1);
7767 #ifdef REG_PREFETCH
7768 alloc_reg(&current,i,PTEMP);
7769 #endif
7770 }
7771 #ifdef USE_MINI_HT
7772 if(dops[i].rs1==31) { // JALR
7773 alloc_reg(&current,i,RHASH);
7774 alloc_reg(&current,i,RHTBL);
7775 }
7776 #endif
7777 delayslot_alloc(&current,i+1);
7778 } else {
7779 // The delay slot overwrites our source register,
7780 // allocate a temporary register to hold the old value.
7781 current.isconst=0;
7782 current.wasconst=0;
7783 regs[i].wasconst=0;
7784 delayslot_alloc(&current,i+1);
7785 current.isconst=0;
7786 alloc_reg(&current,i,RTEMP);
7787 }
7788 //current.isconst=0; // DEBUG
7789 dops[i].ooo=1;
7790 ds=1;
7791 break;
7792 case CJUMP:
7793 //current.isconst=0;
7794 //current.wasconst=0;
7795 //regs[i].wasconst=0;
7796 clear_const(&current,dops[i].rs1);
7797 clear_const(&current,dops[i].rs2);
7798 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7799 {
7800 alloc_cc(&current,i);
7801 dirty_reg(&current,CCREG);
7802 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7803 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7804 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7805 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7806 // The delay slot overwrites one of our conditions.
7807 // Allocate the branch condition registers instead.
7808 current.isconst=0;
7809 current.wasconst=0;
7810 regs[i].wasconst=0;
7811 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7812 if(dops[i].rs2) alloc_reg(&current,i,dops[i].rs2);
7813 }
7814 else
7815 {
7816 dops[i].ooo=1;
7817 delayslot_alloc(&current,i+1);
7818 }
7819 }
7820 else
7821 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7822 {
7823 alloc_cc(&current,i);
7824 dirty_reg(&current,CCREG);
7825 alloc_reg(&current,i,dops[i].rs1);
7826 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7827 // The delay slot overwrites one of our conditions.
7828 // Allocate the branch condition registers instead.
7829 current.isconst=0;
7830 current.wasconst=0;
7831 regs[i].wasconst=0;
7832 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7833 }
7834 else
7835 {
7836 dops[i].ooo=1;
7837 delayslot_alloc(&current,i+1);
7838 }
7839 }
7840 else
7841 // Don't alloc the delay slot yet because we might not execute it
7842 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7843 {
7844 current.isconst=0;
7845 current.wasconst=0;
7846 regs[i].wasconst=0;
7847 alloc_cc(&current,i);
7848 dirty_reg(&current,CCREG);
7849 alloc_reg(&current,i,dops[i].rs1);
7850 alloc_reg(&current,i,dops[i].rs2);
7851 }
7852 else
7853 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7854 {
7855 current.isconst=0;
7856 current.wasconst=0;
7857 regs[i].wasconst=0;
7858 alloc_cc(&current,i);
7859 dirty_reg(&current,CCREG);
7860 alloc_reg(&current,i,dops[i].rs1);
7861 }
7862 ds=1;
7863 //current.isconst=0;
7864 break;
7865 case SJUMP:
7866 //current.isconst=0;
7867 //current.wasconst=0;
7868 //regs[i].wasconst=0;
7869 clear_const(&current,dops[i].rs1);
7870 clear_const(&current,dops[i].rt1);
7871 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7872 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7873 {
7874 alloc_cc(&current,i);
7875 dirty_reg(&current,CCREG);
7876 alloc_reg(&current,i,dops[i].rs1);
7877 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7878 alloc_reg(&current,i,31);
7879 dirty_reg(&current,31);
7880 //#ifdef REG_PREFETCH
7881 //alloc_reg(&current,i,PTEMP);
7882 //#endif
7883 }
7884 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7885 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7886 // Allocate the branch condition registers instead.
7887 current.isconst=0;
7888 current.wasconst=0;
7889 regs[i].wasconst=0;
7890 if(dops[i].rs1) alloc_reg(&current,i,dops[i].rs1);
7891 }
7892 else
7893 {
7894 dops[i].ooo=1;
7895 delayslot_alloc(&current,i+1);
7896 }
7897 }
7898 else
7899 // Don't alloc the delay slot yet because we might not execute it
7900 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7901 {
7902 current.isconst=0;
7903 current.wasconst=0;
7904 regs[i].wasconst=0;
7905 alloc_cc(&current,i);
7906 dirty_reg(&current,CCREG);
7907 alloc_reg(&current,i,dops[i].rs1);
7908 }
7909 ds=1;
7910 //current.isconst=0;
7911 break;
7912 case IMM16:
7913 imm16_alloc(&current,i);
7914 break;
7915 case LOAD:
7916 case LOADLR:
7917 load_alloc(&current,i);
7918 break;
7919 case STORE:
7920 case STORELR:
7921 store_alloc(&current,i);
7922 break;
7923 case ALU:
7924 alu_alloc(&current,i);
7925 break;
7926 case SHIFT:
7927 shift_alloc(&current,i);
7928 break;
7929 case MULTDIV:
7930 multdiv_alloc(&current,i);
7931 break;
7932 case SHIFTIMM:
7933 shiftimm_alloc(&current,i);
7934 break;
7935 case MOV:
7936 mov_alloc(&current,i);
7937 break;
7938 case COP0:
7939 cop0_alloc(&current,i);
7940 break;
7941 case COP1:
7942 break;
7943 case COP2:
7944 cop2_alloc(&current,i);
7945 break;
7946 case C1LS:
7947 c1ls_alloc(&current,i);
7948 break;
7949 case C2LS:
7950 c2ls_alloc(&current,i);
7951 break;
7952 case C2OP:
7953 c2op_alloc(&current,i);
7954 break;
7955 case SYSCALL:
7956 case HLECALL:
7957 case INTCALL:
7958 syscall_alloc(&current,i);
7959 break;
7960 case SPAN:
7961 pagespan_alloc(&current,i);
7962 break;
7963 }
7964
7965 // Create entry (branch target) regmap
7966 for(hr=0;hr<HOST_REGS;hr++)
7967 {
7968 int r,or;
7969 r=current.regmap[hr];
7970 if(r>=0) {
7971 if(r!=regmap_pre[i][hr]) {
7972 // TODO: delay slot (?)
7973 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7974 if(or<0||(r&63)>=TEMPREG){
7975 regs[i].regmap_entry[hr]=-1;
7976 }
7977 else
7978 {
7979 // Just move it to a different register
7980 regs[i].regmap_entry[hr]=r;
7981 // If it was dirty before, it's still dirty
7982 if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
7983 }
7984 }
7985 else
7986 {
7987 // Unneeded
7988 if(r==0){
7989 regs[i].regmap_entry[hr]=0;
7990 }
7991 else
7992 {
7993 assert(r<64);
7994 if((current.u>>r)&1) {
7995 regs[i].regmap_entry[hr]=-1;
7996 //regs[i].regmap[hr]=-1;
7997 current.regmap[hr]=-1;
7998 }else
7999 regs[i].regmap_entry[hr]=r;
8000 }
8001 }
8002 } else {
8003 // Branches expect CCREG to be allocated at the target
8004 if(regmap_pre[i][hr]==CCREG)
8005 regs[i].regmap_entry[hr]=CCREG;
8006 else
8007 regs[i].regmap_entry[hr]=-1;
8008 }
8009 }
8010 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8011 }
8012
8013 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
8014 current.waswritten|=1<<dops[i-1].rs1;
8015 current.waswritten&=~(1<<dops[i].rt1);
8016 current.waswritten&=~(1<<dops[i].rt2);
8017 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
8018 current.waswritten&=~(1<<dops[i].rs1);
8019
8020 /* Branch post-alloc */
8021 if(i>0)
8022 {
8023 current.wasdirty=current.dirty;
8024 switch(dops[i-1].itype) {
8025 case UJUMP:
8026 memcpy(&branch_regs[i-1],&current,sizeof(current));
8027 branch_regs[i-1].isconst=0;
8028 branch_regs[i-1].wasconst=0;
8029 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8030 alloc_cc(&branch_regs[i-1],i-1);
8031 dirty_reg(&branch_regs[i-1],CCREG);
8032 if(dops[i-1].rt1==31) { // JAL
8033 alloc_reg(&branch_regs[i-1],i-1,31);
8034 dirty_reg(&branch_regs[i-1],31);
8035 }
8036 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8037 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8038 break;
8039 case RJUMP:
8040 memcpy(&branch_regs[i-1],&current,sizeof(current));
8041 branch_regs[i-1].isconst=0;
8042 branch_regs[i-1].wasconst=0;
8043 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8044 alloc_cc(&branch_regs[i-1],i-1);
8045 dirty_reg(&branch_regs[i-1],CCREG);
8046 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
8047 if(dops[i-1].rt1!=0) { // JALR
8048 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
8049 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
8050 }
8051 #ifdef USE_MINI_HT
8052 if(dops[i-1].rs1==31) { // JALR
8053 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8054 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8055 }
8056 #endif
8057 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8058 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8059 break;
8060 case CJUMP:
8061 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
8062 {
8063 alloc_cc(&current,i-1);
8064 dirty_reg(&current,CCREG);
8065 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
8066 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
8067 // The delay slot overwrote one of our conditions
8068 // Delay slot goes after the test (in order)
8069 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8070 current.u|=1;
8071 delayslot_alloc(&current,i);
8072 current.isconst=0;
8073 }
8074 else
8075 {
8076 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
8077 // Alloc the branch condition registers
8078 if(dops[i-1].rs1) alloc_reg(&current,i-1,dops[i-1].rs1);
8079 if(dops[i-1].rs2) alloc_reg(&current,i-1,dops[i-1].rs2);
8080 }
8081 memcpy(&branch_regs[i-1],&current,sizeof(current));
8082 branch_regs[i-1].isconst=0;
8083 branch_regs[i-1].wasconst=0;
8084 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8085 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8086 }
8087 else
8088 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
8089 {
8090 alloc_cc(&current,i-1);
8091 dirty_reg(&current,CCREG);
8092 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8093 // The delay slot overwrote the branch condition
8094 // Delay slot goes after the test (in order)
8095 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8096 current.u|=1;
8097 delayslot_alloc(&current,i);
8098 current.isconst=0;
8099 }
8100 else
8101 {
8102 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8103 // Alloc the branch condition register
8104 alloc_reg(&current,i-1,dops[i-1].rs1);
8105 }
8106 memcpy(&branch_regs[i-1],&current,sizeof(current));
8107 branch_regs[i-1].isconst=0;
8108 branch_regs[i-1].wasconst=0;
8109 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8110 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8111 }
8112 else
8113 // Alloc the delay slot in case the branch is taken
8114 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
8115 {
8116 memcpy(&branch_regs[i-1],&current,sizeof(current));
8117 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8118 alloc_cc(&branch_regs[i-1],i);
8119 dirty_reg(&branch_regs[i-1],CCREG);
8120 delayslot_alloc(&branch_regs[i-1],i);
8121 branch_regs[i-1].isconst=0;
8122 alloc_reg(&current,i,CCREG); // Not taken path
8123 dirty_reg(&current,CCREG);
8124 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8125 }
8126 else
8127 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
8128 {
8129 memcpy(&branch_regs[i-1],&current,sizeof(current));
8130 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8131 alloc_cc(&branch_regs[i-1],i);
8132 dirty_reg(&branch_regs[i-1],CCREG);
8133 delayslot_alloc(&branch_regs[i-1],i);
8134 branch_regs[i-1].isconst=0;
8135 alloc_reg(&current,i,CCREG); // Not taken path
8136 dirty_reg(&current,CCREG);
8137 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8138 }
8139 break;
8140 case SJUMP:
8141 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
8142 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
8143 {
8144 alloc_cc(&current,i-1);
8145 dirty_reg(&current,CCREG);
8146 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
8147 // The delay slot overwrote the branch condition
8148 // Delay slot goes after the test (in order)
8149 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
8150 current.u|=1;
8151 delayslot_alloc(&current,i);
8152 current.isconst=0;
8153 }
8154 else
8155 {
8156 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
8157 // Alloc the branch condition register
8158 alloc_reg(&current,i-1,dops[i-1].rs1);
8159 }
8160 memcpy(&branch_regs[i-1],&current,sizeof(current));
8161 branch_regs[i-1].isconst=0;
8162 branch_regs[i-1].wasconst=0;
8163 memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
8164 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
8165 }
8166 else
8167 // Alloc the delay slot in case the branch is taken
8168 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
8169 {
8170 memcpy(&branch_regs[i-1],&current,sizeof(current));
8171 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
8172 alloc_cc(&branch_regs[i-1],i);
8173 dirty_reg(&branch_regs[i-1],CCREG);
8174 delayslot_alloc(&branch_regs[i-1],i);
8175 branch_regs[i-1].isconst=0;
8176 alloc_reg(&current,i,CCREG); // Not taken path
8177 dirty_reg(&current,CCREG);
8178 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8179 }
8180 // FIXME: BLTZAL/BGEZAL
8181 if(dops[i-1].opcode2&0x10) { // BxxZAL
8182 alloc_reg(&branch_regs[i-1],i-1,31);
8183 dirty_reg(&branch_regs[i-1],31);
8184 }
8185 break;
8186 }
8187
8188 if (dops[i-1].is_ujump)
8189 {
8190 if(dops[i-1].rt1==31) // JAL/JALR
8191 {
8192 // Subroutine call will return here, don't alloc any registers
8193 current.dirty=0;
8194 clear_all_regs(current.regmap);
8195 alloc_reg(&current,i,CCREG);
8196 dirty_reg(&current,CCREG);
8197 }
8198 else if(i+1<slen)
8199 {
8200 // Internal branch will jump here, match registers to caller
8201 current.dirty=0;
8202 clear_all_regs(current.regmap);
8203 alloc_reg(&current,i,CCREG);
8204 dirty_reg(&current,CCREG);
8205 for(j=i-1;j>=0;j--)
8206 {
8207 if(ba[j]==start+i*4+4) {
8208 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8209 current.dirty=branch_regs[j].dirty;
8210 break;
8211 }
8212 }
8213 while(j>=0) {
8214 if(ba[j]==start+i*4+4) {
8215 for(hr=0;hr<HOST_REGS;hr++) {
8216 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8217 current.regmap[hr]=-1;
8218 }
8219 current.dirty&=branch_regs[j].dirty;
8220 }
8221 }
8222 j--;
8223 }
8224 }
8225 }
8226 }
8227
8228 // Count cycles in between branches
8229 ccadj[i]=cc;
8230 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
8231 {
8232 cc=0;
8233 }
8234#if !defined(DRC_DBG)
8235 else if(dops[i].itype==C2OP&&gte_cycletab[source[i]&0x3f]>2)
8236 {
8237 // this should really be removed since the real stalls have been implemented,
8238 // but doing so causes sizeable perf regression against the older version
8239 u_int gtec = gte_cycletab[source[i] & 0x3f];
8240 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
8241 }
8242 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
8243 {
8244 cc+=4;
8245 }
8246 else if(dops[i].itype==C2LS)
8247 {
8248 // same as with C2OP
8249 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
8250 }
8251#endif
8252 else
8253 {
8254 cc++;
8255 }
8256
8257 if(!dops[i].is_ds) {
8258 regs[i].dirty=current.dirty;
8259 regs[i].isconst=current.isconst;
8260 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
8261 }
8262 for(hr=0;hr<HOST_REGS;hr++) {
8263 if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
8264 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8265 regs[i].wasconst&=~(1<<hr);
8266 }
8267 }
8268 }
8269 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8270 regs[i].waswritten=current.waswritten;
8271 }
8272
8273 /* Pass 4 - Cull unused host registers */
8274
8275 uint64_t nr=0;
8276
8277 for (i=slen-1;i>=0;i--)
8278 {
8279 int hr;
8280 if(dops[i].is_jump)
8281 {
8282 if(ba[i]<start || ba[i]>=(start+slen*4))
8283 {
8284 // Branch out of this block, don't need anything
8285 nr=0;
8286 }
8287 else
8288 {
8289 // Internal branch
8290 // Need whatever matches the target
8291 nr=0;
8292 int t=(ba[i]-start)>>2;
8293 for(hr=0;hr<HOST_REGS;hr++)
8294 {
8295 if(regs[i].regmap_entry[hr]>=0) {
8296 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8297 }
8298 }
8299 }
8300 // Conditional branch may need registers for following instructions
8301 if (!dops[i].is_ujump)
8302 {
8303 if(i<slen-2) {
8304 nr|=needed_reg[i+2];
8305 for(hr=0;hr<HOST_REGS;hr++)
8306 {
8307 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8308 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8309 }
8310 }
8311 }
8312 // Don't need stuff which is overwritten
8313 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8314 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8315 // Merge in delay slot
8316 for(hr=0;hr<HOST_REGS;hr++)
8317 {
8318 if(dops[i+1].rt1&&dops[i+1].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8319 if(dops[i+1].rt2&&dops[i+1].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8320 if(dops[i+1].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8321 if(dops[i+1].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8322 if(dops[i+1].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8323 if(dops[i+1].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8324 if(ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
8325 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8326 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8327 }
8328 if(dops[i+1].is_store) {
8329 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8330 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8331 }
8332 }
8333 }
8334 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8335 {
8336 // SYSCALL instruction (software interrupt)
8337 nr=0;
8338 }
8339 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8340 {
8341 // ERET instruction (return from interrupt)
8342 nr=0;
8343 }
8344 else // Non-branch
8345 {
8346 if(i<slen-1) {
8347 for(hr=0;hr<HOST_REGS;hr++) {
8348 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8349 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8350 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8351 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8352 }
8353 }
8354 }
8355 for(hr=0;hr<HOST_REGS;hr++)
8356 {
8357 // Overwritten registers are not needed
8358 if(dops[i].rt1&&dops[i].rt1==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8359 if(dops[i].rt2&&dops[i].rt2==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8360 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8361 // Source registers are needed
8362 if(dops[i].rs1==regmap_pre[i][hr]) nr|=1<<hr;
8363 if(dops[i].rs2==regmap_pre[i][hr]) nr|=1<<hr;
8364 if(dops[i].rs1==regs[i].regmap_entry[hr]) nr|=1<<hr;
8365 if(dops[i].rs2==regs[i].regmap_entry[hr]) nr|=1<<hr;
8366 if(ram_offset && (dops[i].is_load || dops[i].is_store)) {
8367 if(regmap_pre[i][hr]==ROREG) nr|=1<<hr;
8368 if(regs[i].regmap_entry[hr]==ROREG) nr|=1<<hr;
8369 }
8370 if(dops[i].is_store) {
8371 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8372 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8373 }
8374 // Don't store a register immediately after writing it,
8375 // may prevent dual-issue.
8376 // But do so if this is a branch target, otherwise we
8377 // might have to load the register before the branch.
8378 if(i>0&&!dops[i].bt&&((regs[i].wasdirty>>hr)&1)) {
8379 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
8380 if(dops[i-1].rt1==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8381 if(dops[i-1].rt2==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8382 }
8383 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
8384 if(dops[i-1].rt1==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8385 if(dops[i-1].rt2==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8386 }
8387 }
8388 }
8389 // Cycle count is needed at branches. Assume it is needed at the target too.
8390 if(i==0||dops[i].bt||dops[i].itype==CJUMP||dops[i].itype==SPAN) {
8391 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8392 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8393 }
8394 // Save it
8395 needed_reg[i]=nr;
8396
8397 // Deallocate unneeded registers
8398 for(hr=0;hr<HOST_REGS;hr++)
8399 {
8400 if(!((nr>>hr)&1)) {
8401 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8402 if(dops[i].is_jump)
8403 {
8404 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
8405 if (dops[i+1].is_load || dops[i+1].is_store)
8406 map1 = ROREG;
8407 if (dops[i+1].is_store)
8408 map2 = INVCP;
8409 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
8410 temp = FTEMP;
8411 if((regs[i].regmap[hr]&63)!=dops[i].rs1 && (regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8412 (regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8413 (regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8414 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
8415 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8416 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8417 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8418 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
8419 {
8420 regs[i].regmap[hr]=-1;
8421 regs[i].isconst&=~(1<<hr);
8422 if((branch_regs[i].regmap[hr]&63)!=dops[i].rs1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rs2 &&
8423 (branch_regs[i].regmap[hr]&63)!=dops[i].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8424 (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt1 && (branch_regs[i].regmap[hr]&63)!=dops[i+1].rt2 &&
8425 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
8426 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8427 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8428 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8429 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
8430 {
8431 branch_regs[i].regmap[hr]=-1;
8432 branch_regs[i].regmap_entry[hr]=-1;
8433 if (!dops[i].is_ujump)
8434 {
8435 if (i < slen-2) {
8436 regmap_pre[i+2][hr]=-1;
8437 regs[i+2].wasconst&=~(1<<hr);
8438 }
8439 }
8440 }
8441 }
8442 }
8443 else
8444 {
8445 // Non-branch
8446 if(i>0)
8447 {
8448 int map1 = -1, map2 = -1, temp=-1;
8449 if (dops[i].is_load || dops[i].is_store)
8450 map1 = ROREG;
8451 if (dops[i].is_store)
8452 map2 = INVCP;
8453 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8454 temp = FTEMP;
8455 if((regs[i].regmap[hr]&63)!=dops[i].rt1 && (regs[i].regmap[hr]&63)!=dops[i].rt2 &&
8456 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8457 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8458 (dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG))
8459 {
8460 if(i<slen-1&&!dops[i].is_ds) {
8461 assert(regs[i].regmap[hr]<64);
8462 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8463 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8464 {
8465 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8466 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8467 }
8468 regmap_pre[i+1][hr]=-1;
8469 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8470 regs[i+1].wasconst&=~(1<<hr);
8471 }
8472 regs[i].regmap[hr]=-1;
8473 regs[i].isconst&=~(1<<hr);
8474 }
8475 }
8476 }
8477 } // if needed
8478 } // for hr
8479 }
8480
8481 /* Pass 5 - Pre-allocate registers */
8482
8483 // If a register is allocated during a loop, try to allocate it for the
8484 // entire loop, if possible. This avoids loading/storing registers
8485 // inside of the loop.
8486
8487 signed char f_regmap[HOST_REGS];
8488 clear_all_regs(f_regmap);
8489 for(i=0;i<slen-1;i++)
8490 {
8491 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8492 {
8493 if(ba[i]>=start && ba[i]<(start+i*4))
8494 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8495 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8496 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8497 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8498 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8499 {
8500 int t=(ba[i]-start)>>2;
8501 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8502 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8503 for(hr=0;hr<HOST_REGS;hr++)
8504 {
8505 if(regs[i].regmap[hr]>=0) {
8506 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8507 // dealloc old register
8508 int n;
8509 for(n=0;n<HOST_REGS;n++)
8510 {
8511 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8512 }
8513 // and alloc new one
8514 f_regmap[hr]=regs[i].regmap[hr];
8515 }
8516 }
8517 if(branch_regs[i].regmap[hr]>=0) {
8518 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8519 // dealloc old register
8520 int n;
8521 for(n=0;n<HOST_REGS;n++)
8522 {
8523 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8524 }
8525 // and alloc new one
8526 f_regmap[hr]=branch_regs[i].regmap[hr];
8527 }
8528 }
8529 if(dops[i].ooo) {
8530 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8531 f_regmap[hr]=branch_regs[i].regmap[hr];
8532 }else{
8533 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8534 f_regmap[hr]=branch_regs[i].regmap[hr];
8535 }
8536 // Avoid dirty->clean transition
8537 #ifdef DESTRUCTIVE_WRITEBACK
8538 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8539 #endif
8540 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8541 // case above, however it's always a good idea. We can't hoist the
8542 // load if the register was already allocated, so there's no point
8543 // wasting time analyzing most of these cases. It only "succeeds"
8544 // when the mapping was different and the load can be replaced with
8545 // a mov, which is of negligible benefit. So such cases are
8546 // skipped below.
8547 if(f_regmap[hr]>0) {
8548 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8549 int r=f_regmap[hr];
8550 for(j=t;j<=i;j++)
8551 {
8552 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8553 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8554 assert(r < 64);
8555 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
8556 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8557 int k;
8558 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8559 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8560 if(r>63) {
8561 if(get_reg(regs[i].regmap,r&63)<0) break;
8562 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
8563 }
8564 k=i;
8565 while(k>1&&regs[k-1].regmap[hr]==-1) {
8566 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8567 //printf("no free regs for store %x\n",start+(k-1)*4);
8568 break;
8569 }
8570 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8571 //printf("no-match due to different register\n");
8572 break;
8573 }
8574 if (dops[k-2].is_jump) {
8575 //printf("no-match due to branch\n");
8576 break;
8577 }
8578 // call/ret fast path assumes no registers allocated
8579 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8580 break;
8581 }
8582 assert(r < 64);
8583 k--;
8584 }
8585 if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
8586 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8587 while(k<i) {
8588 regs[k].regmap_entry[hr]=f_regmap[hr];
8589 regs[k].regmap[hr]=f_regmap[hr];
8590 regmap_pre[k+1][hr]=f_regmap[hr];
8591 regs[k].wasdirty&=~(1<<hr);
8592 regs[k].dirty&=~(1<<hr);
8593 regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
8594 regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
8595 regs[k].wasconst&=~(1<<hr);
8596 regs[k].isconst&=~(1<<hr);
8597 k++;
8598 }
8599 }
8600 else {
8601 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8602 break;
8603 }
8604 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8605 if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
8606 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8607 regs[i].regmap_entry[hr]=f_regmap[hr];
8608 regs[i].regmap[hr]=f_regmap[hr];
8609 regs[i].wasdirty&=~(1<<hr);
8610 regs[i].dirty&=~(1<<hr);
8611 regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
8612 regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
8613 regs[i].wasconst&=~(1<<hr);
8614 regs[i].isconst&=~(1<<hr);
8615 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8616 branch_regs[i].wasdirty&=~(1<<hr);
8617 branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
8618 branch_regs[i].regmap[hr]=f_regmap[hr];
8619 branch_regs[i].dirty&=~(1<<hr);
8620 branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
8621 branch_regs[i].wasconst&=~(1<<hr);
8622 branch_regs[i].isconst&=~(1<<hr);
8623 if (!dops[i].is_ujump) {
8624 regmap_pre[i+2][hr]=f_regmap[hr];
8625 regs[i+2].wasdirty&=~(1<<hr);
8626 regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
8627 }
8628 }
8629 }
8630 for(k=t;k<j;k++) {
8631 // Alloc register clean at beginning of loop,
8632 // but may dirty it in pass 6
8633 regs[k].regmap_entry[hr]=f_regmap[hr];
8634 regs[k].regmap[hr]=f_regmap[hr];
8635 regs[k].dirty&=~(1<<hr);
8636 regs[k].wasconst&=~(1<<hr);
8637 regs[k].isconst&=~(1<<hr);
8638 if (dops[k].is_jump) {
8639 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8640 branch_regs[k].regmap[hr]=f_regmap[hr];
8641 branch_regs[k].dirty&=~(1<<hr);
8642 branch_regs[k].wasconst&=~(1<<hr);
8643 branch_regs[k].isconst&=~(1<<hr);
8644 if (!dops[k].is_ujump) {
8645 regmap_pre[k+2][hr]=f_regmap[hr];
8646 regs[k+2].wasdirty&=~(1<<hr);
8647 }
8648 }
8649 else
8650 {
8651 regmap_pre[k+1][hr]=f_regmap[hr];
8652 regs[k+1].wasdirty&=~(1<<hr);
8653 }
8654 }
8655 if(regs[j].regmap[hr]==f_regmap[hr])
8656 regs[j].regmap_entry[hr]=f_regmap[hr];
8657 break;
8658 }
8659 if(j==i) break;
8660 if(regs[j].regmap[hr]>=0)
8661 break;
8662 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8663 //printf("no-match due to different register\n");
8664 break;
8665 }
8666 if (dops[j].is_ujump)
8667 {
8668 // Stop on unconditional branch
8669 break;
8670 }
8671 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8672 {
8673 if(dops[j].ooo) {
8674 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8675 break;
8676 }else{
8677 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8678 break;
8679 }
8680 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8681 //printf("no-match due to different register (branch)\n");
8682 break;
8683 }
8684 }
8685 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8686 //printf("No free regs for store %x\n",start+j*4);
8687 break;
8688 }
8689 assert(f_regmap[hr]<64);
8690 }
8691 }
8692 }
8693 }
8694 }
8695 }else{
8696 // Non branch or undetermined branch target
8697 for(hr=0;hr<HOST_REGS;hr++)
8698 {
8699 if(hr!=EXCLUDE_REG) {
8700 if(regs[i].regmap[hr]>=0) {
8701 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8702 // dealloc old register
8703 int n;
8704 for(n=0;n<HOST_REGS;n++)
8705 {
8706 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8707 }
8708 // and alloc new one
8709 f_regmap[hr]=regs[i].regmap[hr];
8710 }
8711 }
8712 }
8713 }
8714 // Try to restore cycle count at branch targets
8715 if(dops[i].bt) {
8716 for(j=i;j<slen-1;j++) {
8717 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8718 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8719 //printf("no free regs for store %x\n",start+j*4);
8720 break;
8721 }
8722 }
8723 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8724 int k=i;
8725 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8726 while(k<j) {
8727 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8728 regs[k].regmap[HOST_CCREG]=CCREG;
8729 regmap_pre[k+1][HOST_CCREG]=CCREG;
8730 regs[k+1].wasdirty|=1<<HOST_CCREG;
8731 regs[k].dirty|=1<<HOST_CCREG;
8732 regs[k].wasconst&=~(1<<HOST_CCREG);
8733 regs[k].isconst&=~(1<<HOST_CCREG);
8734 k++;
8735 }
8736 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8737 }
8738 // Work backwards from the branch target
8739 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8740 {
8741 //printf("Extend backwards\n");
8742 int k;
8743 k=i;
8744 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8745 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8746 //printf("no free regs for store %x\n",start+(k-1)*4);
8747 break;
8748 }
8749 k--;
8750 }
8751 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8752 //printf("Extend CC, %x ->\n",start+k*4);
8753 while(k<=i) {
8754 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8755 regs[k].regmap[HOST_CCREG]=CCREG;
8756 regmap_pre[k+1][HOST_CCREG]=CCREG;
8757 regs[k+1].wasdirty|=1<<HOST_CCREG;
8758 regs[k].dirty|=1<<HOST_CCREG;
8759 regs[k].wasconst&=~(1<<HOST_CCREG);
8760 regs[k].isconst&=~(1<<HOST_CCREG);
8761 k++;
8762 }
8763 }
8764 else {
8765 //printf("Fail Extend CC, %x ->\n",start+k*4);
8766 }
8767 }
8768 }
8769 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8770 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8771 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8772 {
8773 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8774 }
8775 }
8776 }
8777
8778 // This allocates registers (if possible) one instruction prior
8779 // to use, which can avoid a load-use penalty on certain CPUs.
8780 for(i=0;i<slen-1;i++)
8781 {
8782 if (!i || !dops[i-1].is_jump)
8783 {
8784 if(!dops[i+1].bt)
8785 {
8786 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8787 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8788 {
8789 if(dops[i+1].rs1) {
8790 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8791 {
8792 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8793 {
8794 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8795 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8796 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8797 regs[i].isconst&=~(1<<hr);
8798 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8799 constmap[i][hr]=constmap[i+1][hr];
8800 regs[i+1].wasdirty&=~(1<<hr);
8801 regs[i].dirty&=~(1<<hr);
8802 }
8803 }
8804 }
8805 if(dops[i+1].rs2) {
8806 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8807 {
8808 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8809 {
8810 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8811 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8812 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8813 regs[i].isconst&=~(1<<hr);
8814 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8815 constmap[i][hr]=constmap[i+1][hr];
8816 regs[i+1].wasdirty&=~(1<<hr);
8817 regs[i].dirty&=~(1<<hr);
8818 }
8819 }
8820 }
8821 // Preload target address for load instruction (non-constant)
8822 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8823 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8824 {
8825 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8826 {
8827 regs[i].regmap[hr]=dops[i+1].rs1;
8828 regmap_pre[i+1][hr]=dops[i+1].rs1;
8829 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8830 regs[i].isconst&=~(1<<hr);
8831 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8832 constmap[i][hr]=constmap[i+1][hr];
8833 regs[i+1].wasdirty&=~(1<<hr);
8834 regs[i].dirty&=~(1<<hr);
8835 }
8836 }
8837 }
8838 // Load source into target register
8839 if(dops[i+1].lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8840 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8841 {
8842 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8843 {
8844 regs[i].regmap[hr]=dops[i+1].rs1;
8845 regmap_pre[i+1][hr]=dops[i+1].rs1;
8846 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8847 regs[i].isconst&=~(1<<hr);
8848 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8849 constmap[i][hr]=constmap[i+1][hr];
8850 regs[i+1].wasdirty&=~(1<<hr);
8851 regs[i].dirty&=~(1<<hr);
8852 }
8853 }
8854 }
8855 // Address for store instruction (non-constant)
8856 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8857 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8858 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8859 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8860 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8861 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
8862 assert(hr>=0);
8863 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8864 {
8865 regs[i].regmap[hr]=dops[i+1].rs1;
8866 regmap_pre[i+1][hr]=dops[i+1].rs1;
8867 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8868 regs[i].isconst&=~(1<<hr);
8869 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8870 constmap[i][hr]=constmap[i+1][hr];
8871 regs[i+1].wasdirty&=~(1<<hr);
8872 regs[i].dirty&=~(1<<hr);
8873 }
8874 }
8875 }
8876 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8877 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8878 int nr;
8879 hr=get_reg(regs[i+1].regmap,FTEMP);
8880 assert(hr>=0);
8881 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
8882 {
8883 regs[i].regmap[hr]=dops[i+1].rs1;
8884 regmap_pre[i+1][hr]=dops[i+1].rs1;
8885 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8886 regs[i].isconst&=~(1<<hr);
8887 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8888 constmap[i][hr]=constmap[i+1][hr];
8889 regs[i+1].wasdirty&=~(1<<hr);
8890 regs[i].dirty&=~(1<<hr);
8891 }
8892 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8893 {
8894 // move it to another register
8895 regs[i+1].regmap[hr]=-1;
8896 regmap_pre[i+2][hr]=-1;
8897 regs[i+1].regmap[nr]=FTEMP;
8898 regmap_pre[i+2][nr]=FTEMP;
8899 regs[i].regmap[nr]=dops[i+1].rs1;
8900 regmap_pre[i+1][nr]=dops[i+1].rs1;
8901 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8902 regs[i].isconst&=~(1<<nr);
8903 regs[i+1].isconst&=~(1<<nr);
8904 regs[i].dirty&=~(1<<nr);
8905 regs[i+1].wasdirty&=~(1<<nr);
8906 regs[i+1].dirty&=~(1<<nr);
8907 regs[i+2].wasdirty&=~(1<<nr);
8908 }
8909 }
8910 }
8911 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8912 if(dops[i+1].itype==LOAD)
8913 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8914 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8915 hr=get_reg(regs[i+1].regmap,FTEMP);
8916 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8917 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8918 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
8919 }
8920 if(hr>=0&&regs[i].regmap[hr]<0) {
8921 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8922 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8923 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8924 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8925 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8926 regs[i].isconst&=~(1<<hr);
8927 regs[i+1].wasdirty&=~(1<<hr);
8928 regs[i].dirty&=~(1<<hr);
8929 }
8930 }
8931 }
8932 }
8933 }
8934 }
8935 }
8936
8937 /* Pass 6 - Optimize clean/dirty state */
8938 clean_registers(0,slen-1,1);
8939
8940 /* Pass 7 - Identify 32-bit registers */
8941 for (i=slen-1;i>=0;i--)
8942 {
8943 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8944 {
8945 // Conditional branch
8946 if((source[i]>>16)!=0x1000&&i<slen-2) {
8947 // Mark this address as a branch target since it may be called
8948 // upon return from interrupt
8949 dops[i+2].bt=1;
8950 }
8951 }
8952 }
8953
8954 if(dops[slen-1].itype==SPAN) {
8955 dops[slen-1].bt=1; // Mark as a branch target so instruction can restart after exception
8956 }
8957
8958#ifdef DISASM
8959 /* Debug/disassembly */
8960 for(i=0;i<slen;i++)
8961 {
8962 printf("U:");
8963 int r;
8964 for(r=1;r<=CCREG;r++) {
8965 if((unneeded_reg[i]>>r)&1) {
8966 if(r==HIREG) printf(" HI");
8967 else if(r==LOREG) printf(" LO");
8968 else printf(" r%d",r);
8969 }
8970 }
8971 printf("\n");
8972 #if defined(__i386__) || defined(__x86_64__)
8973 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
8974 #endif
8975 #ifdef __arm__
8976 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
8977 #endif
8978 #if defined(__i386__) || defined(__x86_64__)
8979 printf("needs: ");
8980 if(needed_reg[i]&1) printf("eax ");
8981 if((needed_reg[i]>>1)&1) printf("ecx ");
8982 if((needed_reg[i]>>2)&1) printf("edx ");
8983 if((needed_reg[i]>>3)&1) printf("ebx ");
8984 if((needed_reg[i]>>5)&1) printf("ebp ");
8985 if((needed_reg[i]>>6)&1) printf("esi ");
8986 if((needed_reg[i]>>7)&1) printf("edi ");
8987 printf("\n");
8988 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
8989 printf("dirty: ");
8990 if(regs[i].wasdirty&1) printf("eax ");
8991 if((regs[i].wasdirty>>1)&1) printf("ecx ");
8992 if((regs[i].wasdirty>>2)&1) printf("edx ");
8993 if((regs[i].wasdirty>>3)&1) printf("ebx ");
8994 if((regs[i].wasdirty>>5)&1) printf("ebp ");
8995 if((regs[i].wasdirty>>6)&1) printf("esi ");
8996 if((regs[i].wasdirty>>7)&1) printf("edi ");
8997 #endif
8998 #ifdef __arm__
8999 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9000 printf("dirty: ");
9001 if(regs[i].wasdirty&1) printf("r0 ");
9002 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9003 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9004 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9005 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9006 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9007 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9008 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9009 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9010 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9011 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9012 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9013 #endif
9014 printf("\n");
9015 disassemble_inst(i);
9016 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9017 #if defined(__i386__) || defined(__x86_64__)
9018 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9019 if(regs[i].dirty&1) printf("eax ");
9020 if((regs[i].dirty>>1)&1) printf("ecx ");
9021 if((regs[i].dirty>>2)&1) printf("edx ");
9022 if((regs[i].dirty>>3)&1) printf("ebx ");
9023 if((regs[i].dirty>>5)&1) printf("ebp ");
9024 if((regs[i].dirty>>6)&1) printf("esi ");
9025 if((regs[i].dirty>>7)&1) printf("edi ");
9026 #endif
9027 #ifdef __arm__
9028 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9029 if(regs[i].dirty&1) printf("r0 ");
9030 if((regs[i].dirty>>1)&1) printf("r1 ");
9031 if((regs[i].dirty>>2)&1) printf("r2 ");
9032 if((regs[i].dirty>>3)&1) printf("r3 ");
9033 if((regs[i].dirty>>4)&1) printf("r4 ");
9034 if((regs[i].dirty>>5)&1) printf("r5 ");
9035 if((regs[i].dirty>>6)&1) printf("r6 ");
9036 if((regs[i].dirty>>7)&1) printf("r7 ");
9037 if((regs[i].dirty>>8)&1) printf("r8 ");
9038 if((regs[i].dirty>>9)&1) printf("r9 ");
9039 if((regs[i].dirty>>10)&1) printf("r10 ");
9040 if((regs[i].dirty>>12)&1) printf("r12 ");
9041 #endif
9042 printf("\n");
9043 if(regs[i].isconst) {
9044 printf("constants: ");
9045 #if defined(__i386__) || defined(__x86_64__)
9046 if(regs[i].isconst&1) printf("eax=%x ",(u_int)constmap[i][0]);
9047 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(u_int)constmap[i][1]);
9048 if((regs[i].isconst>>2)&1) printf("edx=%x ",(u_int)constmap[i][2]);
9049 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(u_int)constmap[i][3]);
9050 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(u_int)constmap[i][5]);
9051 if((regs[i].isconst>>6)&1) printf("esi=%x ",(u_int)constmap[i][6]);
9052 if((regs[i].isconst>>7)&1) printf("edi=%x ",(u_int)constmap[i][7]);
9053 #endif
9054 #if defined(__arm__) || defined(__aarch64__)
9055 int r;
9056 for (r = 0; r < ARRAY_SIZE(constmap[i]); r++)
9057 if ((regs[i].isconst >> r) & 1)
9058 printf(" r%d=%x", r, (u_int)constmap[i][r]);
9059 #endif
9060 printf("\n");
9061 }
9062 if(dops[i].is_jump) {
9063 #if defined(__i386__) || defined(__x86_64__)
9064 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9065 if(branch_regs[i].dirty&1) printf("eax ");
9066 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9067 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9068 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9069 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9070 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9071 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9072 #endif
9073 #ifdef __arm__
9074 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9075 if(branch_regs[i].dirty&1) printf("r0 ");
9076 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9077 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9078 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9079 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9080 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9081 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9082 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9083 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9084 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9085 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9086 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9087 #endif
9088 }
9089 }
9090#endif // DISASM
9091
9092 /* Pass 8 - Assembly */
9093 linkcount=0;stubcount=0;
9094 ds=0;is_delayslot=0;
9095 u_int dirty_pre=0;
9096 void *beginning=start_block();
9097 if((u_int)addr&1) {
9098 ds=1;
9099 pagespan_ds();
9100 }
9101 void *instr_addr0_override = NULL;
9102
9103 if (start == 0x80030000) {
9104 // nasty hack for the fastbios thing
9105 // override block entry to this code
9106 instr_addr0_override = out;
9107 emit_movimm(start,0);
9108 // abuse io address var as a flag that we
9109 // have already returned here once
9110 emit_readword(&address,1);
9111 emit_writeword(0,&pcaddr);
9112 emit_writeword(0,&address);
9113 emit_cmp(0,1);
9114 #ifdef __aarch64__
9115 emit_jeq(out + 4*2);
9116 emit_far_jump(new_dyna_leave);
9117 #else
9118 emit_jne(new_dyna_leave);
9119 #endif
9120 }
9121 for(i=0;i<slen;i++)
9122 {
9123 //if(ds) printf("ds: ");
9124 disassemble_inst(i);
9125 if(ds) {
9126 ds=0; // Skip delay slot
9127 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9128 instr_addr[i] = NULL;
9129 } else {
9130 speculate_register_values(i);
9131 #ifndef DESTRUCTIVE_WRITEBACK
9132 if (i < 2 || !dops[i-2].is_ujump)
9133 {
9134 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9135 }
9136 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9137 dirty_pre=branch_regs[i].dirty;
9138 }else{
9139 dirty_pre=regs[i].dirty;
9140 }
9141 #endif
9142 // write back
9143 if (i < 2 || !dops[i-2].is_ujump)
9144 {
9145 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9146 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9147 }
9148 // branch target entry point
9149 instr_addr[i] = out;
9150 assem_debug("<->\n");
9151 drc_dbg_emit_do_cmp(i);
9152
9153 // load regs
9154 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
9155 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9156 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9157 address_generation(i,&regs[i],regs[i].regmap_entry);
9158 load_consts(regmap_pre[i],regs[i].regmap,i);
9159 if(dops[i].is_jump)
9160 {
9161 // Load the delay slot registers if necessary
9162 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9163 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9164 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9165 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9166 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9167 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9168 if (dops[i+1].is_store)
9169 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9170 }
9171 else if(i+1<slen)
9172 {
9173 // Preload registers for following instruction
9174 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9175 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9176 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9177 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9178 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9179 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9180 }
9181 // TODO: if(is_ooo(i)) address_generation(i+1);
9182 if (dops[i].itype == CJUMP)
9183 load_regs(regs[i].regmap_entry,regs[i].regmap,CCREG,CCREG);
9184 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9185 load_regs(regs[i].regmap_entry,regs[i].regmap,ROREG,ROREG);
9186 if (dops[i].is_store)
9187 load_regs(regs[i].regmap_entry,regs[i].regmap,INVCP,INVCP);
9188 // assemble
9189 switch(dops[i].itype) {
9190 case ALU:
9191 alu_assemble(i,&regs[i]);break;
9192 case IMM16:
9193 imm16_assemble(i,&regs[i]);break;
9194 case SHIFT:
9195 shift_assemble(i,&regs[i]);break;
9196 case SHIFTIMM:
9197 shiftimm_assemble(i,&regs[i]);break;
9198 case LOAD:
9199 load_assemble(i,&regs[i]);break;
9200 case LOADLR:
9201 loadlr_assemble(i,&regs[i]);break;
9202 case STORE:
9203 store_assemble(i,&regs[i]);break;
9204 case STORELR:
9205 storelr_assemble(i,&regs[i]);break;
9206 case COP0:
9207 cop0_assemble(i,&regs[i]);break;
9208 case COP1:
9209 cop1_assemble(i,&regs[i]);break;
9210 case C1LS:
9211 c1ls_assemble(i,&regs[i]);break;
9212 case COP2:
9213 cop2_assemble(i,&regs[i]);break;
9214 case C2LS:
9215 c2ls_assemble(i,&regs[i]);break;
9216 case C2OP:
9217 c2op_assemble(i,&regs[i]);break;
9218 case MULTDIV:
9219 multdiv_assemble(i,&regs[i]);
9220 multdiv_prepare_stall(i,&regs[i]);
9221 break;
9222 case MOV:
9223 mov_assemble(i,&regs[i]);break;
9224 case SYSCALL:
9225 syscall_assemble(i,&regs[i]);break;
9226 case HLECALL:
9227 hlecall_assemble(i,&regs[i]);break;
9228 case INTCALL:
9229 intcall_assemble(i,&regs[i]);break;
9230 case UJUMP:
9231 ujump_assemble(i,&regs[i]);ds=1;break;
9232 case RJUMP:
9233 rjump_assemble(i,&regs[i]);ds=1;break;
9234 case CJUMP:
9235 cjump_assemble(i,&regs[i]);ds=1;break;
9236 case SJUMP:
9237 sjump_assemble(i,&regs[i]);ds=1;break;
9238 case SPAN:
9239 pagespan_assemble(i,&regs[i]);break;
9240 }
9241 if (dops[i].is_ujump)
9242 literal_pool(1024);
9243 else
9244 literal_pool_jumpover(256);
9245 }
9246 }
9247
9248 assert(slen > 0);
9249 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9250 // no ending needed for this block since INTCALL never returns
9251 }
9252 // If the block did not end with an unconditional branch,
9253 // add a jump to the next instruction.
9254 else if (i > 1) {
9255 if (!dops[i-2].is_ujump && dops[i-1].itype != SPAN) {
9256 assert(!dops[i-1].is_jump);
9257 assert(i==slen);
9258 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9259 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9260 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9261 emit_loadreg(CCREG,HOST_CCREG);
9262 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
9263 }
9264 else
9265 {
9266 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9267 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9268 }
9269 add_to_linker(out,start+i*4,0);
9270 emit_jmp(0);
9271 }
9272 }
9273 else
9274 {
9275 assert(i>0);
9276 assert(!dops[i-1].is_jump);
9277 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9278 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9279 emit_loadreg(CCREG,HOST_CCREG);
9280 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
9281 add_to_linker(out,start+i*4,0);
9282 emit_jmp(0);
9283 }
9284
9285 // TODO: delay slot stubs?
9286 // Stubs
9287 for(i=0;i<stubcount;i++)
9288 {
9289 switch(stubs[i].type)
9290 {
9291 case LOADB_STUB:
9292 case LOADH_STUB:
9293 case LOADW_STUB:
9294 case LOADD_STUB:
9295 case LOADBU_STUB:
9296 case LOADHU_STUB:
9297 do_readstub(i);break;
9298 case STOREB_STUB:
9299 case STOREH_STUB:
9300 case STOREW_STUB:
9301 case STORED_STUB:
9302 do_writestub(i);break;
9303 case CC_STUB:
9304 do_ccstub(i);break;
9305 case INVCODE_STUB:
9306 do_invstub(i);break;
9307 case FP_STUB:
9308 do_cop1stub(i);break;
9309 case STORELR_STUB:
9310 do_unalignedwritestub(i);break;
9311 }
9312 }
9313
9314 if (instr_addr0_override)
9315 instr_addr[0] = instr_addr0_override;
9316
9317 /* Pass 9 - Linker */
9318 for(i=0;i<linkcount;i++)
9319 {
9320 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9321 literal_pool(64);
9322 if (!link_addr[i].ext)
9323 {
9324 void *stub = out;
9325 void *addr = check_addr(link_addr[i].target);
9326 emit_extjump(link_addr[i].addr, link_addr[i].target);
9327 if (addr) {
9328 set_jump_target(link_addr[i].addr, addr);
9329 add_jump_out(link_addr[i].target,stub);
9330 }
9331 else
9332 set_jump_target(link_addr[i].addr, stub);
9333 }
9334 else
9335 {
9336 // Internal branch
9337 int target=(link_addr[i].target-start)>>2;
9338 assert(target>=0&&target<slen);
9339 assert(instr_addr[target]);
9340 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9341 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9342 //#else
9343 set_jump_target(link_addr[i].addr, instr_addr[target]);
9344 //#endif
9345 }
9346 }
9347
9348 u_int source_len = slen*4;
9349 if (dops[slen-1].itype == INTCALL && source_len > 4)
9350 // no need to treat the last instruction as compiled
9351 // as interpreter fully handles it
9352 source_len -= 4;
9353
9354 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9355 copy = shadow;
9356
9357 // External Branch Targets (jump_in)
9358 for(i=0;i<slen;i++)
9359 {
9360 if(dops[i].bt||i==0)
9361 {
9362 if(instr_addr[i]) // TODO - delay slots (=null)
9363 {
9364 u_int vaddr=start+i*4;
9365 u_int page=get_page(vaddr);
9366 u_int vpage=get_vpage(vaddr);
9367 literal_pool(256);
9368 {
9369 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
9370 assem_debug("jump_in: %x\n",start+i*4);
9371 ll_add(jump_dirty+vpage,vaddr,out);
9372 void *entry_point = do_dirty_stub(i, source_len);
9373 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
9374 // If there was an existing entry in the hash table,
9375 // replace it with the new address.
9376 // Don't add new entries. We'll insert the
9377 // ones that actually get used in check_addr().
9378 struct ht_entry *ht_bin = hash_table_get(vaddr);
9379 if (ht_bin->vaddr[0] == vaddr)
9380 ht_bin->tcaddr[0] = entry_point;
9381 if (ht_bin->vaddr[1] == vaddr)
9382 ht_bin->tcaddr[1] = entry_point;
9383 }
9384 }
9385 }
9386 }
9387 // Write out the literal pool if necessary
9388 literal_pool(0);
9389 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9390 // Align code
9391 if(((u_int)out)&7) emit_addnop(13);
9392 #endif
9393 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9394 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9395 memcpy(copy, source, source_len);
9396 copy += source_len;
9397
9398 end_block(beginning);
9399
9400 // If we're within 256K of the end of the buffer,
9401 // start over from the beginning. (Is 256K enough?)
9402 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9403 out = ndrc->translation_cache;
9404
9405 // Trap writes to any of the pages we compiled
9406 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
9407 invalid_code[i]=0;
9408 }
9409 inv_code_start=inv_code_end=~0;
9410
9411 // for PCSX we need to mark all mirrors too
9412 if(get_page(start)<(RAM_SIZE>>12))
9413 for(i=start>>12;i<=(start+slen*4)>>12;i++)
9414 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
9415 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
9416 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
9417
9418 /* Pass 10 - Free memory by expiring oldest blocks */
9419
9420 int end=(((out-ndrc->translation_cache)>>(TARGET_SIZE_2-16))+16384)&65535;
9421 while(expirep!=end)
9422 {
9423 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
9424 uintptr_t base_offs = ((uintptr_t)(expirep >> 13) << shift); // Base offset of this block
9425 uintptr_t base_offs_s = base_offs >> shift;
9426 inv_debug("EXP: Phase %d\n",expirep);
9427 switch((expirep>>11)&3)
9428 {
9429 case 0:
9430 // Clear jump_in and jump_dirty
9431 ll_remove_matching_addrs(jump_in+(expirep&2047),base_offs_s,shift);
9432 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base_offs_s,shift);
9433 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base_offs_s,shift);
9434 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base_offs_s,shift);
9435 break;
9436 case 1:
9437 // Clear pointers
9438 ll_kill_pointers(jump_out[expirep&2047],base_offs_s,shift);
9439 ll_kill_pointers(jump_out[(expirep&2047)+2048],base_offs_s,shift);
9440 break;
9441 case 2:
9442 // Clear hash table
9443 for(i=0;i<32;i++) {
9444 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
9445 uintptr_t o1 = (u_char *)ht_bin->tcaddr[1] - ndrc->translation_cache;
9446 uintptr_t o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9447 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9448 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
9449 ht_bin->vaddr[1] = -1;
9450 ht_bin->tcaddr[1] = NULL;
9451 }
9452 o1 = (u_char *)ht_bin->tcaddr[0] - ndrc->translation_cache;
9453 o2 = o1 - MAX_OUTPUT_BLOCK_SIZE;
9454 if ((o1 >> shift) == base_offs_s || (o2 >> shift) == base_offs_s) {
9455 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
9456 ht_bin->vaddr[0] = ht_bin->vaddr[1];
9457 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
9458 ht_bin->vaddr[1] = -1;
9459 ht_bin->tcaddr[1] = NULL;
9460 }
9461 }
9462 break;
9463 case 3:
9464 // Clear jump_out
9465 if((expirep&2047)==0)
9466 do_clear_cache();
9467 ll_remove_matching_addrs(jump_out+(expirep&2047),base_offs_s,shift);
9468 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base_offs_s,shift);
9469 break;
9470 }
9471 expirep=(expirep+1)&65535;
9472 }
9473#ifdef ASSEM_PRINT
9474 fflush(stdout);
9475#endif
9476 return 0;
9477}
9478
9479// vim:shiftwidth=2:expandtab
ARM optimized PCSX fork