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drc: get rid of RAM_FIXED, revive ROREG
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_drc_chk
... / ...
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1diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
2index 1d8cefa..528929f 100644
3--- a/libpcsxcore/new_dynarec/linkage_arm.S
4+++ b/libpcsxcore/new_dynarec/linkage_arm.S
5@@ -438,7 +438,7 @@ FUNCTION(cc_interrupt):
6 str r1, [fp, #LO_pending_exception]
7 and r2, r2, r10, lsr #17
8 add r3, fp, #LO_restore_candidate
9- str r10, [fp, #LO_cycle] /* PCSX cycles */
10+@@@ str r10, [fp, #LO_cycle] /* PCSX cycles */
11 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
12 ldr r4, [r2, r3]
13 mov r10, lr
14@@ -528,7 +528,7 @@ FUNCTION(new_dyna_leave):
15 ldr r0, [fp, #LO_last_count]
16 add r12, fp, #28
17 add r10, r0, r10
18- str r10, [fp, #LO_cycle]
19+@@@ str r10, [fp, #LO_cycle]
20 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
21 .size new_dyna_leave, .-new_dyna_leave
22
23@@ -645,7 +645,7 @@ FUNCTION(new_dyna_start):
24 \readop r0, [r1, r3, lsl #\tab_shift]
25 .endif
26 movcc pc, lr
27- str r2, [fp, #LO_cycle]
28+@@@ str r2, [fp, #LO_cycle]
29 bx r1
30 .endm
31
32@@ -680,7 +680,7 @@ FUNCTION(jump_handler_read32):
33 mov r0, r1
34 add r2, r2, r12
35 push {r2, lr}
36- str r2, [fp, #LO_cycle]
37+@@@ str r2, [fp, #LO_cycle]
38 blx r3
39
40 ldr r0, [fp, #LO_next_interupt]
41@@ -708,7 +708,7 @@ FUNCTION(jump_handler_write_h):
42 add r2, r2, r12
43 mov r0, r1
44 push {r2, lr}
45- str r2, [fp, #LO_cycle]
46+@@@ str r2, [fp, #LO_cycle]
47 blx r3
48
49 ldr r0, [fp, #LO_next_interupt]
50diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S
51index 7df82b4..79298e4 100644
52--- a/libpcsxcore/new_dynarec/linkage_arm64.S
53+++ b/libpcsxcore/new_dynarec/linkage_arm64.S
54@@ -123,7 +123,7 @@ FUNCTION(cc_interrupt):
55 str wzr, [rFP, #LO_pending_exception]
56 and w2, w2, rCC, lsr #17
57 add x3, rFP, #LO_restore_candidate
58- str rCC, [rFP, #LO_cycle] /* PCSX cycles */
59+## str rCC, [rFP, #LO_cycle] /* PCSX cycles */
60 # str rCC, [rFP, #LO_reg_cop0+36] /* Count */
61 ldr w19, [x3, w2, uxtw]
62 mov x21, lr
63@@ -231,7 +231,7 @@ FUNCTION(new_dyna_start):
64 FUNCTION(new_dyna_leave):
65 ldr w0, [rFP, #LO_last_count]
66 add rCC, rCC, w0
67- str rCC, [rFP, #LO_cycle]
68+## str rCC, [rFP, #LO_cycle]
69 ldp x19, x20, [sp, #16*1]
70 ldp x21, x22, [sp, #16*2]
71 ldp x23, x24, [sp, #16*3]
72@@ -249,7 +249,7 @@ FUNCTION(new_dyna_leave):
73 /* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
74 ldr w4, [rFP, #LO_last_count]
75 add w4, w4, w2
76- str w4, [rFP, #LO_cycle]
77+## str w4, [rFP, #LO_cycle]
78 .endm
79
80 .macro memhandler_post
81diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
82index 2f77516..21481bc 100644
83--- a/libpcsxcore/new_dynarec/new_dynarec.c
84+++ b/libpcsxcore/new_dynarec/new_dynarec.c
85@@ -521,6 +521,9 @@ static int doesnt_expire_soon(void *tcaddr)
86 // This is called from the recompiled JR/JALR instructions
87 void noinline *get_addr(u_int vaddr)
88 {
89+#ifdef DRC_DBG
90+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
91+#endif
92 u_int page=get_page(vaddr);
93 u_int vpage=get_vpage(vaddr);
94 struct ll_entry *head;
95@@ -4790,13 +4793,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
96 #endif
97 emit_addimm_and_set_flags(cycles,HOST_CCREG);
98 jaddr=out;
99- emit_jns(0);
100+ //emit_jns(0);
101+ emit_jmp(0);
102 }
103 else
104 {
105 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
106 jaddr=out;
107- emit_jns(0);
108+ //emit_jns(0);
109+ emit_jmp(0);
110 }
111 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
112 }
113@@ -5204,7 +5209,8 @@ static void rjump_assemble(int i,struct regstat *i_regs)
114 // special case for RFE
115 emit_jmp(0);
116 else
117- emit_jns(0);
118+ //emit_jns(0);
119+ emit_jmp(0);
120 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
121 #ifdef USE_MINI_HT
122 if(dops[i].rs1==31) {
123@@ -5309,7 +5315,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
124 else if(nop) {
125 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
126 void *jaddr=out;
127- emit_jns(0);
128+ //emit_jns(0);
129+ emit_jmp(0);
130 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
131 }
132 else {
133@@ -5496,7 +5503,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
134 emit_loadreg(CCREG,HOST_CCREG);
135 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
136 void *jaddr=out;
137- emit_jns(0);
138+ //emit_jns(0);
139+ emit_jmp(0);
140 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
141 emit_storereg(CCREG,HOST_CCREG);
142 }
143@@ -5505,7 +5513,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
144 assert(cc==HOST_CCREG);
145 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
146 void *jaddr=out;
147- emit_jns(0);
148+ //emit_jns(0);
149+ emit_jmp(0);
150 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
151 }
152 }
153@@ -5607,7 +5616,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
154 else if(nevertaken) {
155 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
156 void *jaddr=out;
157- emit_jns(0);
158+ //emit_jns(0);
159+ emit_jmp(0);
160 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
161 }
162 else {
163@@ -5763,7 +5773,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
164 emit_loadreg(CCREG,HOST_CCREG);
165 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
166 void *jaddr=out;
167- emit_jns(0);
168+ //emit_jns(0);
169+ emit_jmp(0);
170 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
171 emit_storereg(CCREG,HOST_CCREG);
172 }
173@@ -5772,7 +5783,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
174 assert(cc==HOST_CCREG);
175 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
176 void *jaddr=out;
177- emit_jns(0);
178+ //emit_jns(0);
179+ emit_jmp(0);
180 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
181 }
182 }
183@@ -6211,7 +6223,7 @@ void unneeded_registers(int istart,int iend,int r)
184 // R0 is always unneeded
185 u|=1;
186 // Save it
187- unneeded_reg[i]=u;
188+ unneeded_reg[i]=1;//u;
189 gte_unneeded[i]=gte_u;
190 /*
191 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
192@@ -8756,6 +8768,7 @@ int new_recompile_block(u_int addr)
193
194 // This allocates registers (if possible) one instruction prior
195 // to use, which can avoid a load-use penalty on certain CPUs.
196+#if 0
197 for(i=0;i<slen-1;i++)
198 {
199 if (!i || !dops[i-1].is_jump)
200@@ -8912,6 +8925,7 @@ int new_recompile_block(u_int addr)
201 }
202 }
203 }
204+#endif
205
206 /* Pass 6 - Optimize clean/dirty state */
207 clean_registers(0,slen-1,1);
208@@ -9217,6 +9231,11 @@ int new_recompile_block(u_int addr)
209 case SPAN:
210 pagespan_assemble(i,&regs[i]);break;
211 }
212+#ifdef DRC_DBG
213+ // write-out non-consts, consts are likely different because of get_final_value()
214+ if (!dops[i].is_jump)
215+ wb_dirtys(regs[i].regmap,regs[i].dirty&~regs[i].loadedconst);
216+#endif
217 if (dops[i].is_ujump)
218 literal_pool(1024);
219 else
220@@ -9451,6 +9470,10 @@ int new_recompile_block(u_int addr)
221 }
222 #ifdef ASSEM_PRINT
223 fflush(stdout);
224+#endif
225+#ifdef DRC_DBG
226+printf("new_recompile_block done\n");
227+fflush(stdout);
228 #endif
229 return 0;
230 }
ARM optimized PCSX fork