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drc: adjust constants, 32bit is enough
[pcsx_rearmed.git] / libpcsxcore / new_dynarec / patches / trace_drc_chk
... / ...
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1diff --git a/libpcsxcore/new_dynarec/linkage_arm.S b/libpcsxcore/new_dynarec/linkage_arm.S
2index bbc52c3..83c5b08 100644
3--- a/libpcsxcore/new_dynarec/linkage_arm.S
4+++ b/libpcsxcore/new_dynarec/linkage_arm.S
5@@ -437,7 +437,7 @@ FUNCTION(cc_interrupt):
6 str r1, [fp, #LO_pending_exception]
7 and r2, r2, r10, lsr #17
8 add r3, fp, #LO_restore_candidate
9- str r10, [fp, #LO_cycle] /* PCSX cycles */
10+@@@ str r10, [fp, #LO_cycle] /* PCSX cycles */
11 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
12 ldr r4, [r2, r3]
13 mov r10, lr
14@@ -527,7 +527,7 @@ FUNCTION(new_dyna_leave):
15 ldr r0, [fp, #LO_last_count]
16 add r12, fp, #28
17 add r10, r0, r10
18- str r10, [fp, #LO_cycle]
19+@@@ str r10, [fp, #LO_cycle]
20 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
21 .size new_dyna_leave, .-new_dyna_leave
22
23@@ -644,7 +644,7 @@ FUNCTION(new_dyna_start):
24 \readop r0, [r1, r3, lsl #\tab_shift]
25 .endif
26 movcc pc, lr
27- str r2, [fp, #LO_cycle]
28+@@@ str r2, [fp, #LO_cycle]
29 bx r1
30 .endm
31
32@@ -679,7 +679,7 @@ FUNCTION(jump_handler_read32):
33 mov r0, r1
34 add r2, r2, r12
35 push {r2, lr}
36- str r2, [fp, #LO_cycle]
37+@@@ str r2, [fp, #LO_cycle]
38 blx r3
39
40 ldr r0, [fp, #LO_next_interupt]
41@@ -707,7 +707,7 @@ FUNCTION(jump_handler_write_h):
42 add r2, r2, r12
43 mov r0, r1
44 push {r2, lr}
45- str r2, [fp, #LO_cycle]
46+@@@ str r2, [fp, #LO_cycle]
47 blx r3
48
49 ldr r0, [fp, #LO_next_interupt]
50diff --git a/libpcsxcore/new_dynarec/linkage_arm64.S b/libpcsxcore/new_dynarec/linkage_arm64.S
51index 444545c..031cee2 100644
52--- a/libpcsxcore/new_dynarec/linkage_arm64.S
53+++ b/libpcsxcore/new_dynarec/linkage_arm64.S
54@@ -119,7 +119,7 @@ FUNCTION(cc_interrupt):
55 str wzr, [rFP, #LO_pending_exception]
56 and w2, w2, rCC, lsr #17
57 add x3, rFP, #LO_restore_candidate
58- str rCC, [rFP, #LO_cycle] /* PCSX cycles */
59+## str rCC, [rFP, #LO_cycle] /* PCSX cycles */
60 # str rCC, [rFP, #LO_reg_cop0+36] /* Count */
61 ldr w19, [x3, w2, uxtw]
62 mov x21, lr
63@@ -227,7 +227,7 @@ FUNCTION(new_dyna_start):
64 FUNCTION(new_dyna_leave):
65 ldr w0, [rFP, #LO_last_count]
66 add rCC, rCC, w0
67- str rCC, [rFP, #LO_cycle]
68+## str rCC, [rFP, #LO_cycle]
69 ldp x19, x20, [sp, #16*1]
70 ldp x21, x22, [sp, #16*2]
71 ldp x23, x24, [sp, #16*3]
72@@ -245,7 +245,7 @@ FUNCTION(new_dyna_leave):
73 /* w0 = adddr/data, x1 = rhandler, w2 = cycles, x3 = whandler */
74 ldr w4, [rFP, #LO_last_count]
75 add w4, w4, w2
76- str w4, [rFP, #LO_cycle]
77+## str w4, [rFP, #LO_cycle]
78 .endm
79
80 .macro memhandler_post
81diff --git a/libpcsxcore/new_dynarec/new_dynarec.c b/libpcsxcore/new_dynarec/new_dynarec.c
82index a1d7f6a..3960f3b 100644
83--- a/libpcsxcore/new_dynarec/new_dynarec.c
84+++ b/libpcsxcore/new_dynarec/new_dynarec.c
85@@ -44,10 +44,10 @@ static int sceBlock;
86 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
87 #endif
88
89-//#define DISASM
90-//#define assem_debug printf
91+#define DISASM
92+#define assem_debug printf
93 //#define inv_debug printf
94-#define assem_debug(...)
95+//#define assem_debug(...)
96 #define inv_debug(...)
97
98 #ifdef __i386__
99@@ -489,6 +489,9 @@ static int doesnt_expire_soon(void *tcaddr)
100 // This is called from the recompiled JR/JALR instructions
101 void noinline *get_addr(u_int vaddr)
102 {
103+#ifdef DRC_DBG
104+printf("get_addr %08x, pc=%08x\n", vaddr, psxRegs.pc);
105+#endif
106 u_int page=get_page(vaddr);
107 u_int vpage=get_vpage(vaddr);
108 struct ll_entry *head;
109@@ -4485,13 +4492,15 @@ void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
110 }
111 emit_addimm_and_set_flags(cycles,HOST_CCREG);
112 jaddr=out;
113- emit_jns(0);
114+ //emit_jns(0);
115+ emit_jmp(0);
116 }
117 else
118 {
119 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
120 jaddr=out;
121- emit_jns(0);
122+ //emit_jns(0);
123+ emit_jmp(0);
124 }
125 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
126 }
127@@ -4899,7 +4908,8 @@ static void rjump_assemble(int i,struct regstat *i_regs)
128 // special case for RFE
129 emit_jmp(0);
130 else
131- emit_jns(0);
132+ //emit_jns(0);
133+ emit_jmp(0);
134 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
135 #ifdef USE_MINI_HT
136 if(rs1[i]==31) {
137@@ -5004,7 +5014,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
138 else if(nop) {
139 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
140 void *jaddr=out;
141- emit_jns(0);
142+ //emit_jns(0);
143+ emit_jmp(0);
144 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
145 }
146 else {
147@@ -5191,7 +5202,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
148 emit_loadreg(CCREG,HOST_CCREG);
149 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
150 void *jaddr=out;
151- emit_jns(0);
152+ //emit_jns(0);
153+ emit_jmp(0);
154 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
155 emit_storereg(CCREG,HOST_CCREG);
156 }
157@@ -5200,7 +5212,8 @@ static void cjump_assemble(int i,struct regstat *i_regs)
158 assert(cc==HOST_CCREG);
159 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
160 void *jaddr=out;
161- emit_jns(0);
162+ //emit_jns(0);
163+ emit_jmp(0);
164 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
165 }
166 }
167@@ -5302,7 +5315,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
168 else if(nevertaken) {
169 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
170 void *jaddr=out;
171- emit_jns(0);
172+ //emit_jns(0);
173+ emit_jmp(0);
174 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
175 }
176 else {
177@@ -5458,7 +5472,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
178 emit_loadreg(CCREG,HOST_CCREG);
179 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
180 void *jaddr=out;
181- emit_jns(0);
182+ //emit_jns(0);
183+ emit_jmp(0);
184 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
185 emit_storereg(CCREG,HOST_CCREG);
186 }
187@@ -5467,7 +5482,8 @@ static void sjump_assemble(int i,struct regstat *i_regs)
188 assert(cc==HOST_CCREG);
189 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
190 void *jaddr=out;
191- emit_jns(0);
192+ //emit_jns(0);
193+ emit_jmp(0);
194 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
195 }
196 }
197@@ -5955,7 +5971,7 @@ void unneeded_registers(int istart,int iend,int r)
198 // R0 is always unneeded
199 u|=1;
200 // Save it
201- unneeded_reg[i]=u;
202+ unneeded_reg[i]=1;//u;
203 gte_unneeded[i]=gte_u;
204 /*
205 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
206@@ -8474,6 +8491,7 @@ int new_recompile_block(u_int addr)
207
208 // This allocates registers (if possible) one instruction prior
209 // to use, which can avoid a load-use penalty on certain CPUs.
210+#if 0
211 for(i=0;i<slen-1;i++)
212 {
213 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP))
214@@ -8630,6 +8648,7 @@ int new_recompile_block(u_int addr)
215 }
216 }
217 }
218+#endif
219
220 /* Pass 6 - Optimize clean/dirty state */
221 clean_registers(0,slen-1,1);
222@@ -8929,6 +8948,12 @@ int new_recompile_block(u_int addr)
223 case SPAN:
224 pagespan_assemble(i,&regs[i]);break;
225 }
226+
227+#ifdef DRC_DBG
228+ // write-out non-consts, consts are likely different because of get_final_value()
229+ if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP)
230+ wb_dirtys(regs[i].regmap,regs[i].dirty&~regs[i].loadedconst);
231+#endif
232 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
233 literal_pool(1024);
234 else
235@@ -9037,7 +9062,7 @@ int new_recompile_block(u_int addr)
236 }
237 }
238 // External Branch Targets (jump_in)
239- if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
240+ if(copy+slen*4>(void *)shadow+sizeof(shadow)) {copy=shadow;printf("shadow overflow\n");}
241 for(i=0;i<slen;i++)
242 {
243 if(bt[i]||i==0)
244@@ -9150,6 +9175,10 @@ int new_recompile_block(u_int addr)
245 }
246 expirep=(expirep+1)&65535;
247 }
248+#ifdef DRC_DBG
249+printf("new_recompile_block done\n");
250+fflush(stdout);
251+#endif
252 return 0;
253 }
254
ARM optimized PCSX fork