drc: add a timing hack for Internal Section
[pcsx_rearmed.git] / libpcsxcore / psxdma.c
... / ...
CommitLineData
1/***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
19
20/*
21* Handles PSX DMA functions.
22*/
23
24#include "psxdma.h"
25#include "gpu.h"
26
27// Dma0/1 in Mdec.c
28// Dma3 in CdRom.c
29
30void spuInterrupt() {
31 if (HW_DMA4_CHCR & SWAP32(0x01000000))
32 {
33 HW_DMA4_CHCR &= SWAP32(~0x01000000);
34 DMA_INTERRUPT(4);
35 }
36}
37
38void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
39 u16 *ptr;
40 u32 words;
41
42 switch (chcr) {
43 case 0x01000201: //cpu to spu transfer
44#ifdef PSXDMA_LOG
45 PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %x addr = %x size = %x\n", chcr, madr, bcr);
46#endif
47 ptr = (u16 *)PSXM(madr);
48 if (ptr == NULL) {
49#ifdef CPU_LOG
50 CPU_LOG("*** DMA4 SPU - mem2spu *** NULL Pointer!!!\n");
51#endif
52 break;
53 }
54 words = (bcr >> 16) * (bcr & 0xffff);
55 SPU_writeDMAMem(ptr, words * 2, psxRegs.cycle);
56 HW_DMA4_MADR = SWAPu32(madr + words * 4);
57 SPUDMA_INT(words / 2);
58 return;
59
60 case 0x01000200: //spu to cpu transfer
61#ifdef PSXDMA_LOG
62 PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %x addr = %x size = %x\n", chcr, madr, bcr);
63#endif
64 ptr = (u16 *)PSXM(madr);
65 if (ptr == NULL) {
66#ifdef CPU_LOG
67 CPU_LOG("*** DMA4 SPU - spu2mem *** NULL Pointer!!!\n");
68#endif
69 break;
70 }
71 words = (bcr >> 16) * (bcr & 0xffff);
72 SPU_readDMAMem(ptr, words * 2, psxRegs.cycle);
73 psxCpu->Clear(madr, words);
74
75 HW_DMA4_MADR = SWAPu32(madr + words * 4);
76 SPUDMA_INT(words / 2);
77 return;
78
79#ifdef PSXDMA_LOG
80 default:
81 PSXDMA_LOG("*** DMA4 SPU - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
82 break;
83#endif
84 }
85
86 HW_DMA4_CHCR &= SWAP32(~0x01000000);
87 DMA_INTERRUPT(4);
88}
89
90// Taken from PEOPS SOFTGPU
91static inline boolean CheckForEndlessLoop(u32 laddr, u32 *lUsedAddr) {
92 if (laddr == lUsedAddr[1]) return TRUE;
93 if (laddr == lUsedAddr[2]) return TRUE;
94
95 if (laddr < lUsedAddr[0]) lUsedAddr[1] = laddr;
96 else lUsedAddr[2] = laddr;
97
98 lUsedAddr[0] = laddr;
99
100 return FALSE;
101}
102
103static u32 gpuDmaChainSize(u32 addr) {
104 u32 size;
105 u32 DMACommandCounter = 0;
106 u32 lUsedAddr[3];
107
108 lUsedAddr[0] = lUsedAddr[1] = lUsedAddr[2] = 0xffffff;
109
110 // initial linked list ptr (word)
111 size = 1;
112
113 do {
114 addr &= 0x1ffffc;
115
116 if (DMACommandCounter++ > 2000000) break;
117 if (CheckForEndlessLoop(addr, lUsedAddr)) break;
118
119 // # 32-bit blocks to transfer
120 size += psxMu8( addr + 3 );
121
122 // next 32-bit pointer
123 addr = psxMu32( addr & ~0x3 ) & 0xffffff;
124 size += 1;
125 } while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF
126 // any pointer with bit 23 set will do.
127
128 return size;
129}
130
131void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
132 u32 *ptr;
133 u32 words;
134 u32 size;
135
136 switch (chcr) {
137 case 0x01000200: // vram2mem
138#ifdef PSXDMA_LOG
139 PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
140#endif
141 ptr = (u32 *)PSXM(madr);
142 if (ptr == NULL) {
143#ifdef CPU_LOG
144 CPU_LOG("*** DMA2 GPU - vram2mem *** NULL Pointer!!!\n");
145#endif
146 break;
147 }
148 // BA blocks * BS words (word = 32-bits)
149 words = (bcr >> 16) * (bcr & 0xffff);
150 GPU_readDataMem(ptr, words);
151 psxCpu->Clear(madr, words);
152
153 HW_DMA2_MADR = SWAPu32(madr + words * 4);
154
155 // already 32-bit word size ((size * 4) / 4)
156 GPUDMA_INT(words / 4);
157 return;
158
159 case 0x01000201: // mem2vram
160#ifdef PSXDMA_LOG
161 PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
162#endif
163 ptr = (u32 *)PSXM(madr);
164 if (ptr == NULL) {
165#ifdef CPU_LOG
166 CPU_LOG("*** DMA2 GPU - mem2vram *** NULL Pointer!!!\n");
167#endif
168 break;
169 }
170 // BA blocks * BS words (word = 32-bits)
171 words = (bcr >> 16) * (bcr & 0xffff);
172 GPU_writeDataMem(ptr, words);
173
174 HW_DMA2_MADR = SWAPu32(madr + words * 4);
175
176 // already 32-bit word size ((size * 4) / 4)
177 GPUDMA_INT(words / 4);
178 return;
179
180 case 0x01000401: // dma chain
181#ifdef PSXDMA_LOG
182 PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
183#endif
184
185 size = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff);
186 if ((int)size <= 0)
187 size = gpuDmaChainSize(madr);
188 HW_GPU_STATUS &= ~PSXGPU_nBUSY;
189
190 // we don't emulate progress, just busy flag and end irq,
191 // so pretend we're already at the last block
192 HW_DMA2_MADR = SWAPu32(0xffffff);
193
194 // Tekken 3 = use 1.0 only (not 1.5x)
195
196 // Einhander = parse linked list in pieces (todo)
197 // Final Fantasy 4 = internal vram time (todo)
198 // Rebel Assault 2 = parse linked list in pieces (todo)
199 // Vampire Hunter D = allow edits to linked list (todo)
200 GPUDMA_INT(size);
201 return;
202
203#ifdef PSXDMA_LOG
204 default:
205 PSXDMA_LOG("*** DMA 2 - GPU unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
206 break;
207#endif
208 }
209
210 HW_DMA2_CHCR &= SWAP32(~0x01000000);
211 DMA_INTERRUPT(2);
212}
213
214void gpuInterrupt() {
215 if (HW_DMA2_CHCR & SWAP32(0x01000000))
216 {
217 HW_DMA2_CHCR &= SWAP32(~0x01000000);
218 DMA_INTERRUPT(2);
219 }
220 HW_GPU_STATUS |= PSXGPU_nBUSY; // GPU no longer busy
221}
222
223void psxDma6(u32 madr, u32 bcr, u32 chcr) {
224 u32 words;
225 u32 *mem = (u32 *)PSXM(madr);
226
227#ifdef PSXDMA_LOG
228 PSXDMA_LOG("*** DMA6 OT *** %x addr = %x size = %x\n", chcr, madr, bcr);
229#endif
230
231 if (chcr == 0x11000002) {
232 if (mem == NULL) {
233#ifdef CPU_LOG
234 CPU_LOG("*** DMA6 OT *** NULL Pointer!!!\n");
235#endif
236 HW_DMA6_CHCR &= SWAP32(~0x01000000);
237 DMA_INTERRUPT(6);
238 return;
239 }
240
241 // already 32-bit size
242 words = bcr;
243
244 while (bcr--) {
245 *mem-- = SWAP32((madr - 4) & 0xffffff);
246 madr -= 4;
247 }
248 mem++; *mem = 0xffffff;
249
250 //GPUOTCDMA_INT(size);
251 // halted
252 psxRegs.cycle += words;
253 GPUOTCDMA_INT(16);
254 return;
255 }
256#ifdef PSXDMA_LOG
257 else {
258 // Unknown option
259 PSXDMA_LOG("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
260 }
261#endif
262
263 HW_DMA6_CHCR &= SWAP32(~0x01000000);
264 DMA_INTERRUPT(6);
265}
266
267void gpuotcInterrupt()
268{
269 if (HW_DMA6_CHCR & SWAP32(0x01000000))
270 {
271 HW_DMA6_CHCR &= SWAP32(~0x01000000);
272 DMA_INTERRUPT(6);
273 }
274}