psxinterpreter: use cycle_multiplier also
[pcsx_rearmed.git] / libpcsxcore / r3000a.h
... / ...
CommitLineData
1/***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
3 * *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
8 * *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
13 * *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
19
20#ifndef __R3000A_H__
21#define __R3000A_H__
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include "psxcommon.h"
28#include "psxmem.h"
29#include "psxcounters.h"
30#include "psxbios.h"
31
32enum {
33 R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
34 R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
35 R3000ACPU_NOTIFY_DMA3_EXE_LOAD = 2
36};
37
38typedef struct {
39 int (*Init)();
40 void (*Reset)();
41 void (*Execute)(); /* executes up to a break */
42 void (*ExecuteBlock)(); /* executes up to a jump */
43 void (*Clear)(u32 Addr, u32 Size);
44 void (*Notify)(int note, void *data);
45 void (*ApplyConfig)();
46 void (*Shutdown)();
47} R3000Acpu;
48
49extern R3000Acpu *psxCpu;
50extern R3000Acpu psxInt;
51extern R3000Acpu psxRec;
52
53typedef union {
54#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
55 struct { u8 h3, h2, h, l; } b;
56 struct { s8 h3, h2, h, l; } sb;
57 struct { u16 h, l; } w;
58 struct { s16 h, l; } sw;
59#else
60 struct { u8 l, h, h2, h3; } b;
61 struct { u16 l, h; } w;
62 struct { s8 l, h, h2, h3; } sb;
63 struct { s16 l, h; } sw;
64#endif
65} PAIR;
66
67typedef union {
68 struct {
69 u32 r0, at, v0, v1, a0, a1, a2, a3,
70 t0, t1, t2, t3, t4, t5, t6, t7,
71 s0, s1, s2, s3, s4, s5, s6, s7,
72 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
73 } n;
74 u32 r[34]; /* Lo, Hi in r[32] and r[33] */
75 PAIR p[34];
76} psxGPRRegs;
77
78typedef union {
79 struct {
80 u32 Index, Random, EntryLo0, EntryLo1,
81 Context, PageMask, Wired, Reserved0,
82 BadVAddr, Count, EntryHi, Compare,
83 Status, Cause, EPC, PRid,
84 Config, LLAddr, WatchLO, WatchHI,
85 XContext, Reserved1, Reserved2, Reserved3,
86 Reserved4, Reserved5, ECC, CacheErr,
87 TagLo, TagHi, ErrorEPC, Reserved6;
88 } n;
89 u32 r[32];
90 PAIR p[32];
91} psxCP0Regs;
92
93typedef struct {
94 short x, y;
95} SVector2D;
96
97typedef struct {
98 short z, pad;
99} SVector2Dz;
100
101typedef struct {
102 short x, y, z, pad;
103} SVector3D;
104
105typedef struct {
106 short x, y, z, pad;
107} LVector3D;
108
109typedef struct {
110 unsigned char r, g, b, c;
111} CBGR;
112
113typedef struct {
114 short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
115} SMatrix3D;
116
117typedef union {
118 struct {
119 SVector3D v0, v1, v2;
120 CBGR rgb;
121 s32 otz;
122 s32 ir0, ir1, ir2, ir3;
123 SVector2D sxy0, sxy1, sxy2, sxyp;
124 SVector2Dz sz0, sz1, sz2, sz3;
125 CBGR rgb0, rgb1, rgb2;
126 s32 reserved;
127 s32 mac0, mac1, mac2, mac3;
128 u32 irgb, orgb;
129 s32 lzcs, lzcr;
130 } n;
131 u32 r[32];
132 PAIR p[32];
133} psxCP2Data;
134
135typedef union {
136 struct {
137 SMatrix3D rMatrix;
138 s32 trX, trY, trZ;
139 SMatrix3D lMatrix;
140 s32 rbk, gbk, bbk;
141 SMatrix3D cMatrix;
142 s32 rfc, gfc, bfc;
143 s32 ofx, ofy;
144 s32 h;
145 s32 dqa, dqb;
146 s32 zsf3, zsf4;
147 s32 flag;
148 } n;
149 u32 r[32];
150 PAIR p[32];
151} psxCP2Ctrl;
152
153enum {
154 PSXINT_SIO = 0,
155 PSXINT_CDR,
156 PSXINT_CDREAD,
157 PSXINT_GPUDMA,
158 PSXINT_MDECOUTDMA,
159 PSXINT_SPUDMA,
160 PSXINT_GPUBUSY,
161 PSXINT_MDECINDMA,
162 PSXINT_GPUOTCDMA,
163 PSXINT_CDRDMA,
164 PSXINT_NEWDRC_CHECK,
165 PSXINT_RCNT,
166 PSXINT_CDRLID,
167 PSXINT_CDRPLAY_OLD, /* unused */
168 PSXINT_SPU_UPDATE,
169 PSXINT_COUNT
170};
171
172typedef struct psxCP2Regs {
173 psxCP2Data CP2D; /* Cop2 data registers */
174 psxCP2Ctrl CP2C; /* Cop2 control registers */
175} psxCP2Regs;
176
177typedef struct {
178 psxGPRRegs GPR; /* General Purpose Registers */
179 psxCP0Regs CP0; /* Coprocessor0 Registers */
180 union {
181 struct {
182 psxCP2Data CP2D; /* Cop2 data registers */
183 psxCP2Ctrl CP2C; /* Cop2 control registers */
184 };
185 psxCP2Regs CP2;
186 };
187 u32 pc; /* Program counter */
188 u32 code; /* The instruction */
189 u32 cycle;
190 u32 interrupt;
191 struct { u32 sCycle, cycle; } intCycle[32];
192 u32 gteBusyCycle;
193 u32 muldivBusyCycle;
194 u32 subCycle; /* interpreter cycle counting */
195 u32 subCycleStep;
196 // warning: changing anything in psxRegisters requires update of all
197 // asm in libpcsxcore/new_dynarec/
198} psxRegisters;
199
200extern psxRegisters psxRegs;
201
202/* new_dynarec stuff */
203extern u32 event_cycles[PSXINT_COUNT];
204extern u32 next_interupt;
205
206void new_dyna_before_save(void);
207void new_dyna_after_save(void);
208void new_dyna_freeze(void *f, int mode);
209
210#define new_dyna_set_event_abs(e, abs) { \
211 u32 abs_ = abs; \
212 s32 di_ = next_interupt - abs_; \
213 event_cycles[e] = abs_; \
214 if (di_ > 0) { \
215 /*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \
216 next_interupt = abs_; \
217 } \
218}
219
220#define new_dyna_set_event(e, c) \
221 new_dyna_set_event_abs(e, psxRegs.cycle + (c))
222
223int psxInit();
224void psxReset();
225void psxShutdown();
226void psxException(u32 code, u32 bd);
227void psxBranchTest();
228void psxExecuteBios();
229void psxJumpTest();
230
231#ifdef __cplusplus
232}
233#endif
234#endif