[pcsx_rearmed.git] / libpcsxcore / r3000a.h

/***************************************************************************
 *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.,                                       *
 *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
 ***************************************************************************/

#ifndef __R3000A_H__
#define __R3000A_H__

#ifdef __cplusplus
extern "C" {
#endif

#include "psxcommon.h"
#include "psxmem.h"
#include "psxcounters.h"
#include "psxbios.h"

enum R3000Aexception {
	R3000E_Int = 0,      // Interrupt
	R3000E_AdEL = 4,     // Address error (on load/I-fetch)
	R3000E_AdES = 5,     // Address error (on store)
	R3000E_IBE = 6,      // Bus error (instruction fetch)
	R3000E_DBE = 7,      // Bus error (data load/store)
	R3000E_Syscall = 8,  // syscall instruction
	R3000E_Bp = 9,       // Breakpoint - a break instruction
	R3000E_RI = 10,      // reserved instruction
	R3000E_CpU = 11,     // Co-Processor unusable
	R3000E_Ov = 12       // arithmetic overflow
};

enum R3000Anote {
	R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
	R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
	R3000ACPU_NOTIFY_BEFORE_SAVE,
	R3000ACPU_NOTIFY_AFTER_LOAD,
};

enum blockExecCaller {
	EXEC_CALLER_BOOT,
	EXEC_CALLER_HLE,
};

typedef struct {
	int  (*Init)();
	void (*Reset)();
	void (*Execute)();
	void (*ExecuteBlock)(enum blockExecCaller caller); /* executes up to a jump */
	void (*Clear)(u32 Addr, u32 Size);
	void (*Notify)(enum R3000Anote note, void *data);
	void (*ApplyConfig)();
	void (*Shutdown)();
} R3000Acpu;

extern R3000Acpu *psxCpu;
extern R3000Acpu psxInt;
extern R3000Acpu psxRec;

typedef union {
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	struct { u8 h3, h2, h, l; } b;
	struct { s8 h3, h2, h, l; } sb;
	struct { u16 h, l; } w;
	struct { s16 h, l; } sw;
#else
	struct { u8 l, h, h2, h3; } b;
	struct { u16 l, h; } w;
	struct { s8 l, h, h2, h3; } sb;
	struct { s16 l, h; } sw;
#endif
} PAIR;

typedef union {
	struct {
		u32   r0, at, v0, v1, a0, a1, a2, a3,
						t0, t1, t2, t3, t4, t5, t6, t7,
						s0, s1, s2, s3, s4, s5, s6, s7,
						t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	} n;
	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	PAIR p[34];
} psxGPRRegs;

typedef union psxCP0Regs_ {
	struct {
		u32 Reserved0, Reserved1, Reserved2,  BPC,
		    Reserved4, BDA,       Target,     DCIC,
		    BadVAddr,  BDAM,      Reserved10, BPCM,
		    SR,        Cause,     EPC,        PRid,
		    Reserved16[16];
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP0Regs;

typedef struct {
	short x, y;
} SVector2D;

typedef struct {
	short z, pad;
} SVector2Dz;

typedef struct {
	short x, y, z, pad;
} SVector3D;

typedef struct {
	short x, y, z, pad;
} LVector3D;

typedef struct {
	unsigned char r, g, b, c;
} CBGR;

typedef struct {
	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
} SMatrix3D;

typedef union {
	struct {
		SVector3D     v0, v1, v2;
		CBGR          rgb;
		s32          otz;
		s32          ir0, ir1, ir2, ir3;
		SVector2D     sxy0, sxy1, sxy2, sxyp;
		SVector2Dz    sz0, sz1, sz2, sz3;
		CBGR          rgb0, rgb1, rgb2;
		s32          reserved;
		s32          mac0, mac1, mac2, mac3;
		u32 irgb, orgb;
		s32          lzcs, lzcr;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Data;

typedef union {
	struct {
		SMatrix3D rMatrix;
		s32      trX, trY, trZ;
		SMatrix3D lMatrix;
		s32      rbk, gbk, bbk;
		SMatrix3D cMatrix;
		s32      rfc, gfc, bfc;
		s32      ofx, ofy;
		s32      h;
		s32      dqa, dqb;
		s32      zsf3, zsf4;
		s32      flag;
	} n;
	u32 r[32];
	PAIR p[32];
} psxCP2Ctrl;

enum {
	PSXINT_SIO = 0,
	PSXINT_CDR,
	PSXINT_CDREAD,
	PSXINT_GPUDMA,
	PSXINT_MDECOUTDMA,
	PSXINT_SPUDMA,
	PSXINT_GPUBUSY,
	PSXINT_MDECINDMA,
	PSXINT_GPUOTCDMA,
	PSXINT_CDRDMA,
	PSXINT_NEWDRC_CHECK,
	PSXINT_RCNT,
	PSXINT_CDRLID,
	PSXINT_CDRPLAY_OLD,	/* unused */
	PSXINT_SPU_UPDATE,
	PSXINT_COUNT
};

enum R3000Abdt {
	// corresponds to bits 31,30 of Cause reg
	R3000A_BRANCH_TAKEN = 3,
	R3000A_BRANCH_NOT_TAKEN = 2,
	// none or tells that there was an exception in DS back to doBranch
	R3000A_BRANCH_NONE_OR_EXCEPTION = 0,
};

typedef struct psxCP2Regs {
	psxCP2Data CP2D; 	/* Cop2 data registers */
	psxCP2Ctrl CP2C; 	/* Cop2 control registers */
} psxCP2Regs;

typedef struct {
	// note: some cores like lightrec don't keep their data here,
	// so use R3000ACPU_NOTIFY_BEFORE_SAVE to sync
	psxGPRRegs GPR;		/* General Purpose Registers */
	psxCP0Regs CP0;		/* Coprocessor0 Registers */
	union {
		struct {
			psxCP2Data CP2D; 	/* Cop2 data registers */
			psxCP2Ctrl CP2C; 	/* Cop2 control registers */
		};
		psxCP2Regs CP2;
	};
	u32 pc;				/* Program counter */
	u32 code;			/* The instruction */
	u32 cycle;
	u32 interrupt;
	struct { u32 sCycle, cycle; } intCycle[32];
	u32 gteBusyCycle;
	u32 muldivBusyCycle;
	u32 subCycle;       /* interpreter cycle counting */
	u32 subCycleStep;
	u32 biuReg;
	u8  branching;      /* interp. R3000A_BRANCH_TAKEN / not, 0 if not branch */
	u8  dloadSel;       /* interp. delay load state */
	u8  dloadReg[2];
	u32 dloadVal[2];
	// warning: changing anything in psxRegisters requires update of all
	// asm in libpcsxcore/new_dynarec/
} psxRegisters;

extern psxRegisters psxRegs;

/* new_dynarec stuff */
extern u32 event_cycles[PSXINT_COUNT];
extern u32 next_interupt;

void new_dyna_freeze(void *f, int mode);

#define new_dyna_set_event_abs(e, abs) { \
	u32 abs_ = abs; \
	s32 di_ = next_interupt - abs_; \
	event_cycles[e] = abs_; \
	if (di_ > 0) { \
		/*printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);*/ \
		next_interupt = abs_; \
	} \
}

#define new_dyna_set_event(e, c) \
	new_dyna_set_event_abs(e, psxRegs.cycle + (c))

int  psxInit();
void psxReset();
void psxShutdown();
void psxException(u32 code, enum R3000Abdt bdt, psxCP0Regs *cp0);
void psxBranchTest();
void psxExecuteBios();
void psxJumpTest();

#ifdef __cplusplus
}
#endif
#endif
Commit	Line	Data
	1	/***************************************************************************
	2	* Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
	3	* *
	4	* This program is free software; you can redistribute it and/or modify *
	5	* it under the terms of the GNU General Public License as published by *
	6	* the Free Software Foundation; either version 2 of the License, or *
	7	* (at your option) any later version. *
	8	* *
	9	* This program is distributed in the hope that it will be useful, *
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
	12	* GNU General Public License for more details. *
	13	* *
	14	* You should have received a copy of the GNU General Public License *
	15	* along with this program; if not, write to the *
	16	* Free Software Foundation, Inc., *
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
	18	***************************************************************************/
	19
	20	#ifndef __R3000A_H__
	21	#define __R3000A_H__
	22
	23	#ifdef __cplusplus
	24	extern "C" {
	25	#endif
	26
	27	#include "psxcommon.h"
	28	#include "psxmem.h"
	29	#include "psxcounters.h"
	30	#include "psxbios.h"
	31
	32	enum R3000Aexception {
	33	R3000E_Int = 0, // Interrupt
	34	R3000E_AdEL = 4, // Address error (on load/I-fetch)
	35	R3000E_AdES = 5, // Address error (on store)
	36	R3000E_IBE = 6, // Bus error (instruction fetch)
	37	R3000E_DBE = 7, // Bus error (data load/store)
	38	R3000E_Syscall = 8, // syscall instruction
	39	R3000E_Bp = 9, // Breakpoint - a break instruction
	40	R3000E_RI = 10, // reserved instruction
	41	R3000E_CpU = 11, // Co-Processor unusable
	42	R3000E_Ov = 12 // arithmetic overflow
	43	};
	44
	45	enum R3000Anote {
	46	R3000ACPU_NOTIFY_CACHE_ISOLATED = 0,
	47	R3000ACPU_NOTIFY_CACHE_UNISOLATED = 1,
	48	R3000ACPU_NOTIFY_BEFORE_SAVE,
	49	R3000ACPU_NOTIFY_AFTER_LOAD,
	50	};
	51
	52	enum blockExecCaller {
	53	EXEC_CALLER_BOOT,
	54	EXEC_CALLER_HLE,
	55	};
	56
	57	typedef struct {
	58	int (*Init)();
	59	void (*Reset)();
	60	void (*Execute)();
	61	void (ExecuteBlock)(enum blockExecCaller caller); / executes up to a jump */
	62	void (*Clear)(u32 Addr, u32 Size);
	63	void (Notify)(enum R3000Anote note, void data);
	64	void (*ApplyConfig)();
	65	void (*Shutdown)();
	66	} R3000Acpu;
	67
	68	extern R3000Acpu *psxCpu;
	69	extern R3000Acpu psxInt;
	70	extern R3000Acpu psxRec;
	71
	72	typedef union {
	73	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
	74	struct { u8 h3, h2, h, l; } b;
	75	struct { s8 h3, h2, h, l; } sb;
	76	struct { u16 h, l; } w;
	77	struct { s16 h, l; } sw;
	78	#else
	79	struct { u8 l, h, h2, h3; } b;
	80	struct { u16 l, h; } w;
	81	struct { s8 l, h, h2, h3; } sb;
	82	struct { s16 l, h; } sw;
	83	#endif
	84	} PAIR;
	85
	86	typedef union {
	87	struct {
	88	u32 r0, at, v0, v1, a0, a1, a2, a3,
	89	t0, t1, t2, t3, t4, t5, t6, t7,
	90	s0, s1, s2, s3, s4, s5, s6, s7,
	91	t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
	92	} n;
	93	u32 r[34]; /* Lo, Hi in r[32] and r[33] */
	94	PAIR p[34];
	95	} psxGPRRegs;
	96
	97	typedef union psxCP0Regs_ {
	98	struct {
	99	u32 Reserved0, Reserved1, Reserved2, BPC,
	100	Reserved4, BDA, Target, DCIC,
	101	BadVAddr, BDAM, Reserved10, BPCM,
	102	SR, Cause, EPC, PRid,
	103	Reserved16[16];
	104	} n;
	105	u32 r[32];
	106	PAIR p[32];
	107	} psxCP0Regs;
	108
	109	typedef struct {
	110	short x, y;
	111	} SVector2D;
	112
	113	typedef struct {
	114	short z, pad;
	115	} SVector2Dz;
	116
	117	typedef struct {
	118	short x, y, z, pad;
	119	} SVector3D;
	120
	121	typedef struct {
	122	short x, y, z, pad;
	123	} LVector3D;
	124
	125	typedef struct {
	126	unsigned char r, g, b, c;
	127	} CBGR;
	128
	129	typedef struct {
	130	short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
	131	} SMatrix3D;
	132
	133	typedef union {
	134	struct {
	135	SVector3D v0, v1, v2;
	136	CBGR rgb;
	137	s32 otz;
	138	s32 ir0, ir1, ir2, ir3;
	139	SVector2D sxy0, sxy1, sxy2, sxyp;
	140	SVector2Dz sz0, sz1, sz2, sz3;
	141	CBGR rgb0, rgb1, rgb2;
	142	s32 reserved;
	143	s32 mac0, mac1, mac2, mac3;
	144	u32 irgb, orgb;
	145	s32 lzcs, lzcr;
	146	} n;
	147	u32 r[32];
	148	PAIR p[32];
	149	} psxCP2Data;
	150
	151	typedef union {
	152	struct {
	153	SMatrix3D rMatrix;
	154	s32 trX, trY, trZ;
	155	SMatrix3D lMatrix;
	156	s32 rbk, gbk, bbk;
	157	SMatrix3D cMatrix;
	158	s32 rfc, gfc, bfc;
	159	s32 ofx, ofy;
	160	s32 h;
	161	s32 dqa, dqb;
	162	s32 zsf3, zsf4;
	163	s32 flag;
	164	} n;
	165	u32 r[32];
	166	PAIR p[32];
	167	} psxCP2Ctrl;
	168
	169	enum {
	170	PSXINT_SIO = 0,
	171	PSXINT_CDR,
	172	PSXINT_CDREAD,
	173	PSXINT_GPUDMA,
	174	PSXINT_MDECOUTDMA,
	175	PSXINT_SPUDMA,
	176	PSXINT_GPUBUSY,
	177	PSXINT_MDECINDMA,
	178	PSXINT_GPUOTCDMA,
	179	PSXINT_CDRDMA,
	180	PSXINT_NEWDRC_CHECK,
	181	PSXINT_RCNT,
	182	PSXINT_CDRLID,
	183	PSXINT_CDRPLAY_OLD, /* unused */
	184	PSXINT_SPU_UPDATE,
	185	PSXINT_COUNT
	186	};
	187
	188	enum R3000Abdt {
	189	// corresponds to bits 31,30 of Cause reg
	190	R3000A_BRANCH_TAKEN = 3,
	191	R3000A_BRANCH_NOT_TAKEN = 2,
	192	// none or tells that there was an exception in DS back to doBranch
	193	R3000A_BRANCH_NONE_OR_EXCEPTION = 0,
	194	};
	195
	196	typedef struct psxCP2Regs {
	197	psxCP2Data CP2D; /* Cop2 data registers */
	198	psxCP2Ctrl CP2C; /* Cop2 control registers */
	199	} psxCP2Regs;
	200
	201	typedef struct {
	202	// note: some cores like lightrec don't keep their data here,
	203	// so use R3000ACPU_NOTIFY_BEFORE_SAVE to sync
	204	psxGPRRegs GPR; /* General Purpose Registers */
	205	psxCP0Regs CP0; /* Coprocessor0 Registers */
	206	union {
	207	struct {
	208	psxCP2Data CP2D; /* Cop2 data registers */
	209	psxCP2Ctrl CP2C; /* Cop2 control registers */
	210	};
	211	psxCP2Regs CP2;
	212	};
	213	u32 pc; /* Program counter */
	214	u32 code; /* The instruction */
	215	u32 cycle;
	216	u32 interrupt;
	217	struct { u32 sCycle, cycle; } intCycle[32];
	218	u32 gteBusyCycle;
	219	u32 muldivBusyCycle;
	220	u32 subCycle; /* interpreter cycle counting */
	221	u32 subCycleStep;
	222	u32 biuReg;
	223	u8 branching; /* interp. R3000A_BRANCH_TAKEN / not, 0 if not branch */
	224	u8 dloadSel; /* interp. delay load state */
	225	u8 dloadReg[2];
	226	u32 dloadVal[2];
	227	// warning: changing anything in psxRegisters requires update of all
	228	// asm in libpcsxcore/new_dynarec/
	229	} psxRegisters;
	230
	231	extern psxRegisters psxRegs;
	232
	233	/* new_dynarec stuff */
	234	extern u32 event_cycles[PSXINT_COUNT];
	235	extern u32 next_interupt;
	236
	237	void new_dyna_freeze(void *f, int mode);
	238
	239	#define new_dyna_set_event_abs(e, abs) { \
	240	u32 abs_ = abs; \
	241	s32 di_ = next_interupt - abs_; \
	242	event_cycles[e] = abs_; \
	243	if (di_ > 0) { \
	244	/printf("%u: next_interupt %u -> %u\n", psxRegs.cycle, next_interupt, abs_);/ \
	245	next_interupt = abs_; \
	246	} \
	247	}
	248
	249	#define new_dyna_set_event(e, c) \
	250	new_dyna_set_event_abs(e, psxRegs.cycle + (c))
	251
	252	int psxInit();
	253	void psxReset();
	254	void psxShutdown();
	255	void psxException(u32 code, enum R3000Abdt bdt, psxCP0Regs *cp0);
	256	void psxBranchTest();
	257	void psxExecuteBios();
	258	void psxJumpTest();
	259
	260	#ifdef __cplusplus
	261	}
	262	#endif
	263	#endif